Voltage compensation method and device for cascaded multi-level inverter

Abstract

The present application belongs to the field of power electronics technology, and specifically discloses a voltage compensation method and device for a cascaded multi-level inverter. In the present application, the predicted value of the output current of each H-bridge inverter module in the cascaded multi-level inverter is used to compensate the turn-on angle and turn-off angle of each H-bridge inverter module respectively, and the phase shift control signal of each switching device in the H-bridge inverter module is distributed according to the compensated turn-on angle and turn-off angle, thereby effectively compensating for the PWM voltage distortion caused by the dead zone effect and the switch parasitic capacitance effect. In addition, the present application does not need to detect the output current of the H-bridge inverter module, eliminating the current detection hardware and optical fiber communication delay time. In the high-frequency cascade topology, the low-order harmonics introduced by the dead zone effect and the switch parasitic capacitance effect can be effectively suppressed, significantly improving the waveform quality.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and more specifically, relates to a voltage compensation method and device for a cascaded multi-level inverter. Background Art

[0002] Very low frequency (3-30kHz) electromagnetic waves have the advantages of low propagation loss and strong penetration, making them widely used in underwater communications, positioning navigation, and geological exploration. In very low frequency electromagnetic wave transmission systems, a cascaded multilevel inverter, which uses a transformer to superimpose the output voltage of an H-bridge inverter module, is a core device. To suppress harmonics and reduce switching losses, cascaded multilevel inverters typically employ Selective Harmonic Elimination Pulse Width Modulation (SHEPWM), where the switching frequency is equal to the fundamental frequency. Theoretically, using SHEPWM with N H-bridge inverter modules can eliminate all harmonics up to 2N-1. However, due to the non-ideal nature of switching devices, parasitic capacitance exists between the gate, source, and drain of the switch, resulting in turn-on and turn-off delays between control commands and switching actions. To prevent shoot-through in the bridge arms, dead time is artificially inserted into the pulse width modulation (PWM) control signals of the switching devices. Existing research has shown that the voltage dropout caused by dead-time effects and the slow turn-off transients caused by parasitic capacitance in switches significantly distort the output voltage (or PWM voltage) of the H-bridge inverter module, introducing a large number of low-order harmonics into the cascaded output voltage. These low-order harmonics can affect electromagnetic wave quality, increase line losses, and even damage loads connected to the output of the cascaded multilevel inverter. Therefore, compensation for PWM voltage distortion is necessary.

[0003] Research on PWM voltage compensation in cascaded multilevel inverters is limited. Furthermore, because cascaded multilevel inverters typically operate under high power and high voltage conditions, existing research has ignored switch parasitic capacitance and focused solely on compensating for dead-time effects. However, the PWM voltages of each H-bridge inverter module in a cascaded multilevel inverter are sequentially phase-shifted, while the current flowing through each H-bridge inverter module is nearly identical. Regardless of the load current, one H-bridge inverter module will always insert dead-time into the PWM control signal near the current zero crossing. In this case, the rising and falling edges of the H-bridge inverter module's output voltage become slow ramps, rather than step responses, due to the influence of the switch parasitic capacitance. When applied to very low frequency electromagnetic wave transmission systems, the low-order harmonics introduced by the switch parasitic capacitance effect can be significant due to the short fundamental period of the cascaded multilevel inverter.

[0004] Although some recent literature has studied the effects of dead time and switch parasitic capacitance in two-level voltage source inverters and proposed solutions, these methods require precise sampling of the bridge arm currents. Because cascaded multilevel inverters with numerous H-bridge inverter modules employ a distributed control structure, communication delays exist between the main controller and the H-bridge inverter modules. If current sampling-based compensation methods are employed, the compensation command will lag behind the dead time, resulting in overcompensation. While some scholars have proposed methods that do not rely on current sensing, these require additional hardware circuitry, significantly increasing the cost of the cascaded multilevel inverter.

[0005] In general, existing compensation methods for cascaded multilevel inverters fail to effectively suppress low-order harmonics because they ignore the effects of switch parasitic capacitance. Compensation methods for two-level voltage source inverters, which rely on current sampling, struggle to achieve effective compensation when applied to cascaded multilevel inverters. Accurate compensation of the PWM voltage in cascaded multilevel inverters operating at high frequencies remains to be studied. Summary of the Invention

[0006] In response to the shortcomings of the prior art, the purpose of this application is to provide a voltage compensation method and device for a cascaded multi-level inverter, aiming to solve the problem that the existing PWM voltage compensation method for a cascaded multi-level inverter ignores the parasitic capacitance effect of the switch and relies on current detection, making it difficult to meet the low harmonic requirements of the very low frequency transmission system.

[0007] To achieve the above objectives, in a first aspect, the present application provides a voltage compensation method for a cascaded multi-level inverter, comprising:

[0008] Determining a compensated turn-on angle and a compensated turn-off angle of each H-bridge inverter submodule according to a predicted value of an output current of each H-bridge inverter submodule in the cascaded multilevel inverter;

[0009] Determine the phase shift control signal of each switching device in the H-bridge inverter module according to the compensated turn-on angle and the compensated turn-off angle;

[0010] The output voltage of each H-bridge inverter submodule is compensated according to the phase shift control signal of each switching device in each H-bridge inverter submodule.

[0011] In some embodiments, determining a compensated turn-on angle and a compensated turn-off angle of each H-bridge inverter submodule according to a predicted value of an output current of each H-bridge inverter submodule in a cascaded multilevel inverter includes:

[0012] For any H-bridge inverter module, at ωt = θ s +δ off In case of:

[0013] If the predicted value of the output current is less than or equal to 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula:

[0014]

[0015] If the predicted value of the output current is greater than 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula:

[0016] θ s,com =θ s -(δ d +δ on -δ off );

[0017] Among them, θ s,com is the opening angle of the H-bridge inverter module after compensation, θ s is the opening angle of the H-bridge inverter module, V DC is the DC bus voltage, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, δ on is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, δ d is the angle corresponding to the dead time, u c is the voltage error of the parasitic capacitance of the switching device of the H-bridge inverter module, ω is the fundamental angular frequency, and t is the current time;

[0018] At ωt = θ e +δ off In the case of , if the output of the cascaded multilevel inverter is connected to a resistive-inductive load, the compensated turn-off angle of the H-bridge inverter module is calculated by the following formula:

[0019]

[0020] Among them, θ e is the turn-off angle of the H-bridge inverter module, θ e,com is the compensated turn-off angle of the H-bridge inverter module.

[0021] In some embodiments, a method for obtaining a predicted value of the output current of each H-bridge inverter sub-module includes:

[0022] Calculate the ideal cascade voltage of the cascaded multilevel inverter based on the turn-on and turn-off angles of each H-bridge inverter module;

[0023] Calculate the cascade voltage taking into account the dead-time effect based on the dead-time voltage error and ideal cascade voltage of each H-bridge inverter module;

[0024] According to the cascade voltage, calculate the load current value considering the dead zone effect;

[0025] Calculate the voltage error of the parasitic capacitance of the switching devices of each H-bridge inverter module according to the load current value;

[0026] Based on the voltage error, calculate the equivalent cascade voltage on the primary side of the transformer connected to each H-bridge inverter module;

[0027] Based on the equivalent cascade voltage, calculate the actual load current on the primary side of the transformer taking into account the parasitic capacitance effect of the switch;

[0028] The predicted value of the output current of each H-bridge inverter submodule is calculated based on the transformer excitation current and the actual load current.

[0029] In some embodiments, calculating an ideal cascade voltage of a cascaded multilevel inverter based on a turn-on angle and a turn-off angle of each H-bridge inverter submodule includes:

[0030] The ideal cascode voltage is calculated using the following formula:

[0031]

[0032] Where u m,idl is the ideal cascade voltage, N is the number of H-bridge inverter modules, u idl,j is the ideal output voltage of the jth H-bridge inverter module, which is calculated by the following formula:

[0033] u idl,j =S j ·V DC ;

[0034] Where V DC is the DC bus voltage, S j Calculated by the following formula:

[0035]

[0036] Where ω is the fundamental angular frequency, t is the current time, and θ s,j is the opening angle of the jth H-bridge inverter module, θ e,j is the turn-off angle of the jth H-bridge inverter module, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module.

[0037] In some embodiments, calculating the cascade voltage taking into account the dead-zone effect based on the dead-zone voltage errors of the H-bridge inverter sub-modules and the ideal cascade voltage includes:

[0038] The cascade voltage is calculated using the following formula:

[0039]

[0040] Where um,d is the cascade voltage, N is the number of H-bridge inverter modules, u d,j is the dead-zone voltage error of the jth H-bridge inverter module;

[0041] When the output of the cascaded multilevel inverter is connected to a resistive-inductive load, u d,j Calculated by the following formula:

[0042] when When ωt∈[0,2π], then u d,j =0;

[0043] when When, if Then u d,j =-V DC ,like Then u d,j =V DC Otherwise, u d,j =0;

[0044] when When ωt∈[θ s,j +δ off ,θ s,j +δ d +δ on ], then u d,j =-V DC , if ωt∈[θ s,j +δ off +π,θ s,j +δ d +δ on +π], then u d,j =V DC Otherwise, u d,j =0;

[0045] Where, is the current phase angle of the H-bridge inverter module, θ s,j is the turn-on angle of the jth H-bridge inverter module, δ d is the angle corresponding to the dead time, δ on is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, V DC is the DC bus voltage.

[0046] In some embodiments, calculating a load current value taking into account a dead zone effect based on the cascade voltage includes:

[0047] The load current value is calculated using the following formula:

[0048]

[0049] Where u m,d is the cascade voltage, t is the current time, i′ g,d is the load current value, L c is the inductance value of the parasitic inductance of the transmission line, R c is the parasitic resistance of the transmission line, L g is the inductance of the load inductor, R g is the resistance of the load resistor, k is the transformer winding coefficient in the cascaded multilevel inverter, L eq is the inductance of the equivalent leakage inductance of the cascaded multilevel inverter, R eq is the equivalent winding resistance of the cascaded multilevel inverter.

[0050] In some embodiments, calculating the equivalent cascade voltage on the primary side of the transformer connected to each H-bridge inverter sub-module based on the voltage error includes:

[0051] The equivalent cascade voltage is calculated using the following formula:

[0052]

[0053] Where u m is the equivalent cascade voltage, N is the number of H-bridge inverter modules, u c,j is the voltage error of the parasitic capacitance of the switching device of the jth H-bridge inverter module, including the voltage error u′ of each H-bridge module inverter in the positive half cycle c,j And the voltage error u″ in the negative half cycle c,j ;

[0054] When a resistive-inductive load is connected to the output of the cascaded multilevel inverter, the voltage error of each H-bridge module inverter in the positive half cycle is calculated as follows:

[0055] At ωt = θ s,j +δ off When the output current of the H-bridge inverter module is less than or equal to 0, then according to i r,j with I th The voltage error in the positive half cycle is calculated as follows:

[0056]

[0057] Where ω is the fundamental angular frequency, t is the current time, and θ s,j is the turn-on angle of the jth H-bridge inverter module, V DC is the DC bus voltage, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, δ onis the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, δ d is the angle corresponding to the dead time, Δt r,j is the first voltage rise time of the jth H-bridge inverter module, C oss is the parasitic capacitance of the switching devices in the H-bridge inverter module, i r,j is the output current i of the jth H-bridge inverter module s,j In [θ s,j +δ off ,θ s,j +δ d +δ on ] within the linear average, I th is the current threshold;

[0058] At ωt = θ s,j +δ off When the output current of the H-bridge inverter module is greater than 0, then when ωt∈[θ s,j +δ off ,θ s,j +δ d ], u′ c,j =0;

[0059] At ωt = θ e,j +δ off When, according to i r,j with I th The voltage error in the positive half cycle is calculated as follows:

[0060]

[0061] Where θ e,j is the turn-off angle of the jth H-bridge inverter module, i f,j is the output current i of the jth H-bridge inverter module s,j In [θ e,j +δ off ,θ e,j +δ d +δ on ] linear average value, Δt f,j is the second voltage rise time of the jth H-bridge inverter module, which is calculated by the following formula:

[0062]

[0063] Voltage error u″ of each H-bridge module inverter in the negative half cycle c,j =-u′ c,j .

[0064] In some embodiments, calculating the actual load current on the primary side of the transformer taking into account the parasitic capacitance effect of the switching device based on the equivalent cascade voltage includes:

[0065] The actual load current is calculated using the following formula:

[0066]

[0067] Where u m is the equivalent cascade voltage, i′ g is the actual load current, t is the current time, L c is the inductance value of the parasitic inductance of the transmission line, R c is the parasitic resistance of the transmission line, L g is the inductance of the load inductor, R g is the resistance of the load resistor, k is the transformer winding coefficient in the cascaded multilevel inverter, L eq is the inductance of the equivalent leakage inductance of the cascaded multilevel inverter, R eq is the equivalent winding resistance of the cascaded multilevel inverter.

[0068] In some embodiments, the predicted value of the output current of each H-bridge inverter submodule is calculated based on the excitation current of the transformer and the actual load current, including:

[0069] The predicted output current is calculated using the following formula:

[0070] i′ s,j =i′ g +i 0,j ,j=1,2,3,...,N;

[0071] Where i′ s,j is the predicted value of the output current of the jth H-bridge inverter module, N is the number of H-bridge inverter modules, i′ g is the actual load current, i 0,j is the excitation current of the jth H-bridge inverter module, which is calculated by the following formula:

[0072]

[0073] Where t is the current time, u s,j is the output voltage of the jth H-bridge inverter module, L m is the inductance of the excitation inductance of a single transformer, R m is the equivalent excitation resistance of a single transformer.

[0074] In a second aspect, the present application provides a voltage compensation device for a cascaded multi-level inverter, comprising:

[0075] A first acquisition module is used to predict the output current of each H-bridge inverter submodule in the cascade multilevel inverter and determine the compensated turn-on angle and the compensated turn-off angle of each H-bridge inverter submodule;

[0076] A second acquisition module is used to determine the phase shift control signal of each switching device in the H-bridge inverter submodule according to the compensated turn-on angle and the compensated turn-off angle;

[0077] The compensation module is used to compensate the output voltage of each H-bridge inverter submodule according to the phase shift control signal of each switching device in each H-bridge inverter submodule.

[0078] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the programs stored in the memory are executed, the processor is used to execute the voltage compensation method for the cascaded multi-level inverter described in the first aspect or any embodiments of the first aspect.

[0079] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the voltage compensation method for the cascaded multi-level inverter described in the first aspect or any embodiments of the first aspect.

[0080] In a fifth aspect, the present application provides a computer program product. When the computer program product runs on a processor, it enables the processor to execute the voltage compensation method for the cascaded multi-level inverter described in the first aspect or any embodiments of the first aspect.

[0081] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0082] The voltage compensation method and device for the cascaded multi-level inverter provided in the embodiment of the present application utilizes the predicted value of the output current of each H-bridge inverter module in the cascaded multi-level inverter to compensate the turn-on angle and turn-off angle of each H-bridge inverter module separately, and distributes the phase shift control signal of each switching device in the H-bridge inverter module according to the compensated turn-on angle and turn-off angle, thereby effectively compensating for the PWM voltage distortion caused by the dead zone effect and the switch parasitic capacitance effect. In addition, the present application does not need to detect the output current of the H-bridge inverter module, eliminating the current detection hardware and optical fiber communication delay time. In the high-frequency cascade topology, the low-order harmonics introduced by the dead zone effect and the switch parasitic capacitance effect can be effectively suppressed, significantly improving the waveform quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 1 is a flow chart of a voltage compensation method for a cascaded multi-level inverter provided in an embodiment of the present application;

[0084] Figure 2 1 is a topology diagram of a cascaded multi-level inverter provided in an embodiment of the present application;

[0085] Figure 3 This is a schematic diagram of obtaining a multi-level inverter switching angle using the SHEPWM technology provided in an embodiment of the present application;

[0086] Figure 4 1 is a schematic diagram summarizing the dead zone effect that occurs in the H-bridge inverter submodule during actual operation of the cascaded multilevel inverter provided by an embodiment of the present application, wherein (a) shows the case where the current crosses zero after the dead zone time ends, (b) shows the case where the current crosses zero during the dead zone time, and (c) shows the case where the current crosses zero before the dead zone time begins;

[0087] Figure 5 is a schematic diagram of the parasitic capacitance between electrodes of a switching device provided in an embodiment of the present application;

[0088] Figure 6 Schematic diagram of voltage error caused by parasitic capacitance of switching devices at different current values ​​provided by an embodiment of the present application, wherein (a) is a voltage rising transient state and (b) is a voltage falling transient state;

[0089] Figure 7 1 is a schematic diagram of an equivalent system model of a multi-level inverter after decoupling of cascaded transformers provided in an embodiment of the present application;

[0090] Figure 8 1 is a flow chart of a current prediction method for a cascaded multi-level inverter provided in an embodiment of the present application;

[0091] Figure 9 2 is a schematic diagram comparing the output voltage harmonic content under different compensation methods in the simulation provided by the embodiment of the present application;

[0092] Figure 10 1 is a schematic structural diagram of a voltage compensation device for a cascaded multi-level inverter provided in an embodiment of the present application;

[0093] Figure 11 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0094] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0095] The term "and / or" as used herein describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. The symbol " / " as used herein indicates that the related objects are in an "or" relationship, for example, A / B means either A or B.

[0096] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0097] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0098] See also Figure 1 , an embodiment of the present application provides a voltage compensation method for a cascaded multi-level inverter, which may include: step 110, step 120 and step 130.

[0099] Step 110 determines a compensated turn-on angle and a compensated turn-off angle of each H-bridge inverter submodule according to a predicted value of the output current of each H-bridge inverter submodule in the cascaded multilevel inverter;

[0100] Step 120 determines the phase shift control signal of each switching device in the H-bridge inverter module according to the compensated turn-on angle and the compensated turn-off angle;

[0101] Step 130 compensates the output voltage of each H-bridge inverter submodule according to the phase shift control signal of each switch device in each H-bridge inverter submodule.

[0102] In a specific implementation, the output current of each H-bridge inverter submodule in the cascaded multilevel inverter is predicted to obtain a predicted value of the output current of each H-bridge inverter submodule, and based on the predicted value of the output current of each H-bridge inverter submodule, the compensated turn-on angle and turn-off angle of each H-bridge inverter submodule are calculated.

[0103] In the embodiment of the present application, the output currents of the H-bridge inverter modules are equal.

[0104] According to the predicted value of the output current of the H-bridge inverter submodule, a phase shift control signal is allocated to each switching device in the H-bridge inverter submodule.

[0105] Similarly, phase-shift control signals may be allocated to the switching devices in the remaining H-bridge inverter sub-modules.

[0106] Based on the phase shift control signal of each switching device in each H-bridge inverter submodule, the output voltage of each H-bridge inverter submodule is compensated.

[0107] The voltage compensation method for the cascaded multi-level inverter provided in the embodiment of the present application utilizes the predicted value of the output current of each H-bridge inverter module in the cascaded multi-level inverter to compensate the turn-on angle and turn-off angle of each H-bridge inverter module separately, and distributes the phase shift control signal of each switching device in the H-bridge inverter module according to the compensated turn-on angle and turn-off angle, thereby effectively compensating for the PWM voltage distortion caused by the dead zone effect and the switch parasitic capacitance effect. In addition, the present application does not need to detect the output current of the H-bridge inverter module, eliminating the current detection hardware and optical fiber communication delay time. In the high-frequency cascade topology, the low-order harmonics introduced by the dead zone effect and the switch parasitic capacitance effect can be effectively suppressed, significantly improving the waveform quality.

[0108] Furthermore, in some embodiments, in step 110, determining the compensated turn-on angle and the compensated turn-off angle of each H-bridge inverter submodule according to the predicted value of the output current of each H-bridge inverter submodule in the cascaded multilevel inverter may include:

[0109] For any H-bridge inverter module, at ωt = θ s +δ off In case of:

[0110] If the predicted value of the output current is less than or equal to 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula:

[0111]

[0112] If the predicted value of the output current is greater than 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula:

[0113] θ s,com =θ s -(δ d +δ on -δ off );

[0114] Among them, θ s,com is the opening angle of the H-bridge inverter module after compensation, θ s is the opening angle of the H-bridge inverter module, V DC is the DC bus voltage, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, δ on is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, δ d is the angle corresponding to the dead time, u cis the voltage error of the parasitic capacitance of the switching device of the H-bridge inverter module, ω is the fundamental angular frequency, and t is the current time;

[0115] At ωt = θ e +δ off In the case of , if the output of the cascaded multilevel inverter is connected to a resistive-inductive load, the compensated turn-off angle of the H-bridge inverter module is calculated by the following formula:

[0116]

[0117] Among them, θ e is the turn-off angle of the H-bridge inverter module, θ e,com is the compensated turn-off angle of the H-bridge inverter module.

[0118] In a specific implementation, for any H-bridge inverter submodule, assuming it is the j-th H-bridge inverter submodule, its corresponding compensated turn-on angle and compensated turn-off angle can be calculated as follows:

[0119] At ωt = θ s +δ off time:

[0120] If the predicted value of the output current of the jth H-bridge inverter module is i s ' ,j , satisfy i s ' ,j ≤0, the compensation opening angle θ of the H-bridge inverter module s,com Calculated by the following formula:

[0121]

[0122] If the predicted value i′ of the output current of the jth H-bridge inverter module s,j , satisfying i′ s,j >0, the compensated opening angle θ of the H-bridge inverter module s,com Calculated by the following formula:

[0123] θ s,com =θ s -(δ d +δ on -δ off );

[0124] Among them, ω is the fundamental angular frequency, ω=2πf0, f0 is the fundamental frequency, t is the current time, δ off is the turn-off delay time t of the switching device in the H-bridge inverter module off The corresponding angle, δ off =ωt off , δ onis the turn-on delay time t of the switching device in the H-bridge inverter module off The corresponding angle, δ on =ωt on ,θ s is the opening angle of the H-bridge inverter module, V DC is the DC bus voltage, δ d is the dead time t d The corresponding angle, δ d =ωt d ,u c is the voltage error of the parasitic capacitance of the switching devices of the H-bridge inverter module, C oss is the parasitic capacitance value, i r is i′ s,j In the interval [θ s +δ off ,θ s +δ d +δ on ] within the linear average, i′ s,j (θ s +δ off ) and i′ s,j (θ s +δ d +δ on ) are i′ s,j In θ s +δ off and θ s +δ d +δ on The current value at th is the current threshold, which can be calculated as follows:

[0125]

[0126] At ωt = θ e +δ off At this moment, if the output end of the cascaded multilevel inverter is connected to a resistive-inductive load, the predicted value of the output current of each H-bridge inverter module in the cascaded multilevel inverter is greater than 0, and the compensated turn-off angle θ of the H-bridge inverter module is e,com It can be calculated by the following formula:

[0127]

[0128] Where θ e is the turn-off angle of the H-bridge inverter module, i f is i′ s,j In the interval [θ e +δ off ,θ e +δ d +δon ] within the linear average, i′ s,j (θ e +δ off ) and i′ s,j (θ e +δ d +δ on ) are i′ s,j In θ e +δ off and θ e +δ d +δ on The current value at .

[0129] Furthermore, in some embodiments, in the above steps, the method for obtaining the predicted value of the output current of each H-bridge inverter sub-module may include:

[0130] Calculate the ideal cascade voltage of the cascaded multilevel inverter based on the turn-on and turn-off angles of each H-bridge inverter module;

[0131] Calculate the cascade voltage taking into account the dead-time effect based on the dead-time voltage error and ideal cascade voltage of each H-bridge inverter module;

[0132] According to the cascade voltage, calculate the load current value considering the dead zone effect;

[0133] Calculate the voltage error of the parasitic capacitance of the switching devices of each H-bridge inverter module according to the load current value;

[0134] Based on the voltage error, calculate the equivalent cascade voltage on the primary side of the transformer connected to each H-bridge inverter module;

[0135] Based on the equivalent cascade voltage, calculate the actual load current on the primary side of the transformer taking into account the parasitic capacitance effect of the switch;

[0136] The predicted value of the output current of each H-bridge inverter submodule is calculated based on the transformer excitation current and the actual load current.

[0137] In the embodiment of the present application, the ideal cascade voltage u of the cascaded multi-level inverter composed of N H-bridge inverter modules is calculated based on the turn-on angle and turn-off angle of each H-bridge inverter module. m,idl .

[0138] Estimating the current phase angle of the H-bridge inverter module And calculate the dead zone voltage error u of N H-bridge inverter modules d ,u d ={u1,...,u j}, j = 1, 2, ..., N, where u1 is the dead zone voltage error of the first H-bridge inverter module, u j is the dead zone voltage error of the jth H-bridge inverter module, and then the cascade voltage u considering the dead zone effect is calculated m,d , and using the cascade voltage u m,d Calculate the load current value i′ converted to the primary side of the transformer connected to N H-bridge inverter modules, considering only the dead zone effect g,d .

[0139] It is approximately assumed that the load current value i′ g,d =Equal to the output current of N H-bridge inverter modules, and according to the output current of N H-bridge inverter modules, calculate the voltage error u of the parasitic capacitance of the switching devices of N H-bridge inverter modules c ,u c ={u c,1 ,...,u c,j},j=1,2,...,N, where u c,1 is the voltage error of the parasitic capacitance of the switching device of the first H-bridge inverter module, u c,j is the voltage error of the parasitic capacitance of the switching device of the jth H-bridge inverter module, and then u c Calculate the equivalent cascade voltage u on the primary side of the transformer m , based on u m Calculate the actual load current i′ converted to the primary side of the transformer considering the parasitic capacitance effect of the switch g .

[0140] Based on the transformer excitation current and actual load current i′ g , calculate the predicted value of the output current of N H-bridge inverter modules.

[0141] Furthermore, in some embodiments, in the above steps, calculating the ideal cascade voltage of the cascaded multi-level inverter according to the turn-on angle and turn-off angle of each H-bridge inverter sub-module may include:

[0142] The ideal cascode voltage is calculated using the following formula:

[0143]

[0144] Where u m,idl is the ideal cascade voltage, N is the number of H-bridge inverter modules, u idl,j is the ideal output voltage of the jth H-bridge inverter module, which is calculated by the following formula:

[0145] u idl,j =S j ·V DC ;

[0146] Where V DC is the DC bus voltage, S j Calculated by the following formula:

[0147]

[0148] Where ω is the fundamental angular frequency, t is the current time, and θ s,j is the opening angle of the jth H-bridge inverter module, θ e,j is the turn-off angle of the jth H-bridge inverter module, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module.

[0149] In the embodiment of the present application, the ideal cascade voltage u can be calculated by the following formula m,idl :

[0150]

[0151] Among them, u idl,j is the ideal output voltage of the jth H-bridge inverter module, which can be calculated as follows:

[0152] u idl,j =S j ·V DC ;

[0153] in, θ s,j is the opening angle of the jth H-bridge inverter module, θ e,j is the turn-off angle of the jth H-bridge inverter module.

[0154] Furthermore, in some embodiments, in the above steps, calculating the cascade voltage considering the dead-zone effect based on the dead-zone voltage error and the ideal cascade voltage of each H-bridge inverter sub-module may include:

[0155] The cascade voltage is calculated using the following formula:

[0156]

[0157] Where u m,d is the cascade voltage, N is the number of H-bridge inverter modules, u d,j is the dead-zone voltage error of the jth H-bridge inverter module;

[0158] When the output of the cascaded multilevel inverter is connected to a resistive-inductive load, u d,j Calculated by the following formula:

[0159] when When ωt∈[0,2π], then u d,j =0;

[0160] when When, if Then u d,j =-V DC ,like Then u d,j =V DC Otherwise, u d,j =0;

[0161] when When ωt∈[θ s,j +δ off ,θ s,j +δ d +δ on ], then u d,j =-V DC , if ωt∈[θ s,j +δ off +π,θ s,j +δ d +δ on +π], then u d,j =V DC Otherwise, u d,j =0;

[0162] Where, is the current phase angle of the H-bridge inverter module, θ s,j is the turn-on angle of the jth H-bridge inverter module, δ d is the angle corresponding to the dead time, δ on is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, V DC is the DC bus voltage.

[0163] In the embodiment of the present application, the cascade voltage u is calculated by the following formula: m,d :

[0164]

[0165] Among them, u d,j is the dead-zone voltage error of the j-th H-bridge inverter module.

[0166] When a resistive-inductive load is connected to the output of a cascaded multilevel inverter, three dead-zone voltage errors occur in each H-bridge inverter module:

[0167] 1. When When ωt∈[0,2π], then u d,j =0;

[0168] 2. When When , there are:

[0169]

[0170] 3. When When , there are:

[0171]

[0172] in, is the current phase angle of the H-bridge inverter module, The specific estimation method of can be estimated by existing methods, θ s,j is the turn-on angle of the jth H-bridge inverter module.

[0173] Furthermore, in some embodiments, in the above steps, calculating the load current value taking into account the dead zone effect according to the cascade voltage includes:

[0174] The load current value is calculated using the following formula:

[0175]

[0176] Where u m,d is the cascade voltage, t is the current time, i′ g,d is the load current value, L c is the inductance value of the parasitic inductance of the transmission line, R c is the parasitic resistance of the transmission line, L g is the inductance of the load inductor, R g is the resistance of the load resistor, k is the transformer winding coefficient in the cascaded multilevel inverter, L eq is the inductance of the equivalent leakage inductance of the cascaded multilevel inverter, R eq is the equivalent winding resistance of the cascaded multilevel inverter.

[0177] In the embodiment of the present application, the load current value i′ can be solved by numerical iteration after discretization by the following formula g,d :

[0178]

[0179] Where, L c is the inductance value of the parasitic inductance of the transmission line, R c is the parasitic resistance of the transmission line, L g is the inductance of the load inductor, R g is the resistance of the load resistor, k is the transformer winding coefficient in the cascaded multilevel inverter, L eq is the inductance of the equivalent leakage inductance of the cascaded multilevel inverter, R eqL is the equivalent winding resistance of the cascaded multi-level inverter. eq and R eq It can be calculated by the following formula:

[0180] L eq =N(L1+k 2 L2);

[0181] R eq =N(R1+k 2 R2);

[0182] Among them, L1 and L2 are the leakage inductance of the primary and secondary sides of the transformer respectively, and R1 and R2 are the winding resistance of the primary and secondary sides of the transformer respectively.

[0183] Furthermore, in some embodiments, in the above steps, calculating the equivalent cascade voltage on the primary side of the transformer connected to each H-bridge inverter sub-module based on the voltage error may include:

[0184] The equivalent cascade voltage is calculated using the following formula:

[0185]

[0186] Where u m is the equivalent cascade voltage, N is the number of H-bridge inverter modules, u c,j is the voltage error of the parasitic capacitance of the switching device of the jth H-bridge inverter module, including the voltage error u′ of each H-bridge module inverter in the positive half cycle c,j And the voltage error u′ in the negative half cycle c,j ;

[0187] When a resistive-inductive load is connected to the output of the cascaded multilevel inverter, the voltage error of each H-bridge module inverter in the positive half cycle is calculated as follows:

[0188] At ωt = θ s,j +δ off When the output current i of the H-bridge inverter module is s Less than or equal to 0, i s ={i s,1 ,...,i s,j}, i s,1 is the output current of the first H-bridge inverter module, i s,j is the output current of the jth H-bridge inverter module, then according to i r,j with I th The voltage error in the positive half cycle is calculated as follows:

[0189]

[0190] Where ω is the fundamental angular frequency, t is the current time, and θ s,j is the turn-on angle of the jth H-bridge inverter module, V DC is the DC bus voltage, δ off is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, δ on is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, δ d is the angle corresponding to the dead time, Δt r,j is the first voltage rise time of the jth H-bridge inverter module, C oss is the parasitic capacitance of the switching devices in the H-bridge inverter module, i r,j is the output current i of the jth H-bridge inverter module s,j In [θ s,j +δ off ,θ s,j +δ d +δ on ] within the linear average, I th is the current threshold;

[0191] At ωt = θ s,j +δ off When the output current of the H-bridge inverter module is greater than 0, then when ωt∈[θ s,j +δ off ,θ s,j +δ d ], u′ c,j =0;

[0192] At ωt = θ e,j +δ off When, according to i r,j with I th The voltage error in the positive half cycle is calculated as follows:

[0193]

[0194] Where θ e,j is the turn-off angle of the jth H-bridge inverter module, i f,j is the output current i of the jth H-bridge inverter module s,j In [θ e,j +δ off ,θ e,j +δ d +δ on ] linear average value, Δt f,j is the second voltage rise time of the jth H-bridge inverter module, which is calculated by the following formula:

[0195]

[0196] Voltage error u″ of each H-bridge module inverter in the negative half cycle c,j =-u′ c,j .

[0197] In the embodiment of the present application, the equivalent cascade voltage u can be calculated by the following formula: m :

[0198]

[0199] Among them, u c,j is the voltage error of the parasitic capacitance of the switching device of the jth H-bridge inverter module, which may include the voltage error u′ of the N H-bridge module inverters in the positive half cycle c,j And the voltage error u″ in the negative half cycle c,j .

[0200] When a resistive-inductive load is connected to the output of the cascaded multilevel inverter, three types of switching parasitic capacitance voltage errors exist in each H-bridge inverter module during the positive half cycle, namely:

[0201] 1. When ωt = θ s,j +δ off If the output current of the H-bridge inverter module is less than or equal to 0, then the r,j with I th The voltage error in the positive half cycle is calculated as follows:

[0202]

[0203] Where Δt r,j is the first voltage rise time of the jth H-bridge inverter module, C oss is the parasitic capacitance of the switching devices in the H-bridge inverter module, i r,j is the output current i of the jth H-bridge inverter module s,j In [θ s,j +δ off ,θ s,j +δ d +δ on ] is the linear average within , and

[0204] i s,j (θ s,j +δ off ) and i s,j (θ s,j +δ d +δ on ) are i s,j In θ s,j +δoff and θ s,j +δ d +δ on The current value at th is the current threshold.

[0205] 2. When ωt = θ s,j +δ off When the output current of the H-bridge inverter module is greater than 0, the switch parasitic capacitance will not introduce voltage error, then when ωt∈[θ s,j +δ off ,θ s,j +δ d ], there is u′ c,j =0;

[0206] 3. When ωt = θ e,j +δ off When, according to i r,j with I th The voltage error in the positive half cycle is calculated as follows:

[0207]

[0208] Where θ e,j is the turn-off angle of the jth H-bridge inverter module, i f,j is the output current i of the jth H-bridge inverter module s,j In [θ e,j +δ off ,θ e,j +δ d +δ on ] within the linear average,

[0209] i s,j (θ e,j +δ off ) and i s,j (θ e,j +δ d +δ on ) are i s,j In θ e,j +δ off and θ e,j +δ d +δ on The current value at Δt f,j is the second voltage rise time of the jth H-bridge inverter module, which can be calculated by the following formula:

[0210]

[0211] The voltage error of the switching parasitic capacitance of each H-bridge inverter module in the negative half cycle can be obtained based on the waveform symmetry:

[0212] ″′

[0213] u c,j =-u c,j .

[0214] Furthermore, in some embodiments, in the above steps, calculating the actual load current on the primary side of the transformer taking into account the parasitic capacitance effect of the switching device according to the equivalent cascade voltage may include:

[0215] The actual load current is calculated using the following formula:

[0216]

[0217] Where u m is the equivalent cascade voltage, i′ g is the actual load current, t is the current time, L c is the inductance value of the parasitic inductance of the transmission line, R c is the parasitic resistance of the transmission line, L g is the inductance of the load inductor, R g is the resistance of the load resistor, k is the transformer winding coefficient in the cascaded multilevel inverter, L eq is the inductance of the equivalent leakage inductance of the cascaded multilevel inverter, R eq is the equivalent winding resistance of the cascaded multilevel inverter.

[0218] In the embodiment of the present application, the actual load current i′ g It can be discretized by the following formula and solved by numerical iteration:

[0219]

[0220] Where, L c is the inductance value of the parasitic inductance of the transmission line, R c is the parasitic resistance of the transmission line, L g is the inductance of the load inductor, R g is the resistance of the load resistor, k is the transformer winding coefficient in the cascaded multilevel inverter, L eq is the inductance of the equivalent leakage inductance of the cascaded multilevel inverter, R eq is the equivalent winding resistance of the cascaded multilevel inverter.

[0221] Furthermore, in some embodiments, in the above steps, calculating the predicted value of the output current of each H-bridge inverter submodule according to the excitation current and the actual load current of the transformer may include:

[0222] The predicted output current is calculated using the following formula:

[0223] i s ' ,j =i g ′+i 0,j ,j=1,2,3,...,N;

[0224] Where i s ' ,j is the predicted value of the output current of the jth H-bridge inverter module, N is the number of H-bridge inverter modules, i′ g is the actual load current, i 0,j is the excitation current of the jth H-bridge inverter module, which is calculated by the following formula:

[0225]

[0226] Where t is the current time, u s,j is the output voltage of the jth H-bridge inverter module, L m is the inductance of the excitation inductance of a single transformer, R m is the equivalent excitation resistance of a single transformer.

[0227] In the embodiment of the present application, the excitation current i0 of the transformer connected to each H-bridge inverter module is calculated respectively, i0={i 0,1 ,...,i 0,j}, where i 0,1 is the excitation current of the transformer connected to the first H-bridge inverter module, i 0,j is the excitation current of the transformer connected to the jth H-bridge inverter module, and is compared with the actual load current i′ g Add together to get the predicted value i of the output current of each H-bridge inverter module s ' ,j , as follows:

[0228] i s ' ,j =i g ′+i 0,j ,j=1,2,3,...,N;

[0229] Where i s ' ,j is the predicted value of the output current of the jth H-bridge inverter module, N is the number of H-bridge inverter modules, i′ g is the actual load current, i 0,j is the excitation current of the transformer connected to the jth H-bridge inverter module, which is calculated by the following formula:

[0230]

[0231] Where u s,jis the output voltage of the jth H-bridge inverter module, L m is the inductance of the excitation inductance of a single transformer, R m is the equivalent excitation resistance of a single transformer.

[0232] For example, Figure 2 As shown in the figure, the single-phase cascaded H-bridge multi-level inverter using high-frequency transformers is a commonly used inverter circuit for very low frequency (VLF) transmission systems. Unlike the traditional cascaded H-bridge converter, the H-bridge inverter module is composed of N high-frequency transformers with independent magnetic cores connected in cascade. Figure 2 Medium, T1~T N Represent N transformers respectively. The inputs of the N submodules are connected in parallel to the same DC source, and the outputs are connected to the primary side of the transformer, and the secondary sides of the transformers are connected in series. This topology using cascaded transformers avoids the requirement for multiple independent DC sources and is suitable for multi-level converters with a large number of submodules. Each submodule is an H-bridge structure. The same bridge arm includes two upper and lower switching tubes. The switching tubes are all SiC MOSFETs. According to the current direction, the bridge arm where the current flows out is defined as the left bridge arm, and the bridge arm where the current flows out is defined as the right bridge arm. The upper and lower switching tubes of the left bridge arm, and the upper and lower switching tubes of the right bridge arm are respectively recorded as S1, S2, S3, and S4. Each submodule can generate -V DC , 0 and +V DC Three levels.

[0233] Since the fundamental frequency is usually greater than 17kHz, in order to suppress voltage harmonics and reduce switching losses, the cascaded multilevel converter adopts Figure 3 The fundamental frequency shown is equal to 1 / 4 of the switching frequency in the symmetrical SHEPWM. j is the switching angle of the jth H-bridge inverter module, satisfying 0<θ1<...<θ N <π / 2, θ1 is the switching angle of the first H-bridge inverter module, θ N is the switching angle of the Nth H-bridge inverter module. A cascaded multilevel converter with N H-bridge inverter modules can generate 2N+1 voltage levels, theoretically eliminating all harmonics below 2N-1. However, due to the non-ideal nature of switching devices, parasitic capacitance exists between their gates, sources, and drains. This results in turn-on and turn-off delays between control commands and switching actions. To prevent shoot-through in the bridge arms, dead time is artificially inserted into the PWM control signals of the switching devices. The missing voltage levels caused by the dead time and the slow turn-off transients caused by the parasitic capacitance of the switches cause significant distortion in the PWM voltage output by the H-bridge inverter modules and introduce a large number of low-order harmonics into the cascaded output voltage. Low-order harmonics can affect electromagnetic wave quality, increase line losses, and even damage downstream loads. Therefore, compensation for PWM voltage distortion is necessary.

[0234] It should be noted that, since the inverter of the VLF transmission system is composed of a plurality of H-bridge inverter submodules in cascade and the fundamental frequency is greater than 17 kHz, the cascade multilevel inverter involved in the present invention is a high-frequency cascade multilevel inverter.

[0235] The output voltage of the H-bridge inverter module can be regarded as an ideal voltage u idl , dead zone voltage error u d and the voltage error u of the switch parasitic capacitance c Since SHEPWM is a carrier-free pre-programmed modulation method, the key to PWM voltage compensation is to accurately adjust the output voltage pulse width of each inverter H-bridge inverter sub-module to compensate for the voltage error introduced by the dead zone effect and the switch parasitic capacitance effect, that is, u d and u c .

[0236] First of all, d Since each H-bridge inverter module is cascaded through a transformer, the current flowing through it is a similar sine wave, and the output voltage is a square wave with sequential phase shifts. Figure 4 This is a summary of the dead-zone voltage errors that occur in the H-bridge inverter module during actual operation of the high-frequency cascade multi-level inverter provided by the embodiment of the present application. S1 to S4 respectively represent the drive signals of the H-bridge inverter module switches S1 to S4 using a delayed-on dead-zone insertion method. Figure 4 (a) represents the module output current i of the H-bridge inverter s After the dead time ends, it crosses zero. Figure 4 (b) represents i s Zero crossing during the dead time, Figure 4 (c) represents i s Before the dead time starts, u s is the output voltage of the H-bridge inverter module, u d When the output of the cascade multilevel inverter is connected to a resistive-inductive load, the following error will appear in the cascade multilevel inverter under steady-state conditions: Figure 4 The three dead-zone voltage errors shown are:

[0237] 1. In When, ωt∈[0,2π], u d,j =0, corresponding to Figure 4 (a)

[0238] 2. In When, if Then u d,j =-V DC ,like Then u d,j =V DC Otherwise, ud,j =0, corresponding to Figure 4 (b)

[0239] 3. In When ωt∈[θ s,j +δ off ,θ s,j +δ d +δ on ], then u d,j =-V DC , if ωt∈[θ s,j +δ off +π,θ s,j +δ d +δ on +π], then u d,j =V DC Otherwise, u d,j =0, corresponding to Figure 4 Middle (c).

[0240] Among them, θ s and θ e They are the turn-on angle and turn-off angle of the H-bridge inverter module, respectively. Figure 3 The relationship between the SHEPWM switching angle and the s =θ j ,θ e =π-θ N+1-j ; is the current phase angle, i.e. the output current i of the H-bridge inverter module s The phase angle can be defined as the ideal output voltage phase of the cascaded multilevel inverter is 0. For resistive and inductive loads, the output current lags behind the output voltage. The range is 0~π / 2.

[0241] Further to u c Since the switching device is non-ideal, there are parasitic capacitances between its source, drain, and gate, such as Figure 5 As shown. The gate-drain capacitance C gd and drain-source capacitance C ds Under the charge and discharge action of the switch, the rise and fall of the drain-source voltage is not infinitely fast. s The voltage error caused by switch parasitic capacitance is a trapezoidal waveform, rather than a square wave. Due to the complex mechanism of voltage error caused by switch parasitic capacitance, existing research on PWM voltage compensation for multilevel inverters often ignores the effects of switch parasitic capacitance. However, due to the large number of H-bridge inverter modules and the high fundamental frequency (over 17kHz), the low-order harmonics introduced by switch parasitic capacitance are very significant. To meet the requirements for low harmonics in very low frequency electromagnetic waves, it is necessary to analyze and model the voltage error caused by switch parasitic capacitance.

[0242] Voltage error u caused by parasitic capacitance of switching devices c (including u′ c and u″ c ) appears only in u s For the convenience of explanation, C gd and C ds The sum is defined as the switching device output capacitance C oss When the subsequent stage is connected to a resistive-inductive load, each H-bridge inverter module of the cascaded multi-level inverter has three types of u′ in the positive half cycle: c ,like Figure 6 As shown, the time domain models are:

[0243] 1. When ωt = θ s +δ off At this moment, when the output current i s ≤0, corresponding to Figure 4 The transient state 1 in (a) is shown in Figure 1. r with I th The voltage error in the positive half cycle is calculated as follows:

[0244]

[0245] Where i r for i s In [θ s +δ off ,θ s +δ d +δ on ], defined as the linear average within

[0246] 2. When ωt = θ s +δ off When the output current of the H-bridge inverter module is greater than 0, the corresponding Figure 4 In the transient state 2 of (c), when ωt∈[θ s,j +δ off ,θ s,j +δ d ], u c =0;

[0247] 3. When ωt = θ e +δ off When the output current i of each H-bridge inverter module in the cascade multi-level inverter is s are greater than 0, corresponding to Figure 4 The transient state 3 and Figure 4 In the transient state 4 of (c), according to i r with I th The voltage error in the positive half cycle is calculated as follows:

[0248]

[0249] Among them, i f for i s In [θ e +δ off ,θ e +δ d +δ on ], defined as the linear average within i s (θ e +δ off ) and i s (θ e +δ d +δ on ) are i s In θ e +δ off and θ e +δ d +δ on The current value at

[0250] Voltage error u″ of each H-bridge module inverter in the negative half cycle c =-u′ c .

[0251] From the above analysis, we can see that PWM voltage compensation requires accurate calculation of u d and u c .u d The modeling only requires However, u c Modeling of the switching transient requires the s . In previous literature, the voltage error was calculated using the current sampling value. However, the cascaded multi-level inverter with multiple H-bridge inverter modules adopts a distributed control structure, and each H-bridge inverter module is controlled by the main controller through optical fiber communication. There is a communication delay in the optical fiber transmission from the sampling hardware to the main controller and the H-bridge inverter module. If the current sampling value is used for error modeling and compensation, the compensation command will lag behind the switching transient, resulting in incomplete PWM voltage compensation. Therefore, in order to improve the compensation accuracy, it is necessary to calculate the output current i of the H-bridge inverter module of the cascaded multi-level inverter. s Make predictions.

[0252] Different from the traditional cascade multi-level inverter in which H-bridge inverter modules are directly cascaded, the H-bridge inverter module output current i s is i′ g and the transformer excitation current i0, where i′ gis the actual load current converted to the primary side of the transformer, i′ g =i g / k, k is the transformer winding coefficient, i g is the actual load current on the secondary side of the transformer.

[0253] i s =i′ g +i0;

[0254] First, we derive the mathematical expression for i0. Since the excitation impedance in a high-frequency transformer is much larger than the leakage impedance, we can assume that all the primary voltage is used for excitation. Then the excitation current in a single transformer is:

[0255]

[0256] Among them, u s is the output voltage of the H-bridge inverter module, u s =u idl +u d +u c ,u idl ={u idl,1 ,...,u idl,j},u idl,1 is the ideal output voltage of the first H-bridge inverter module, u idl,j is the ideal output voltage of the jth H-bridge inverter module.

[0257] Then derive i′ g The mathematical expression of cascade transformer decoupling method mentioned in the related art is used, and the parasitic parameters in the transformer and transmission cable are considered. The equivalent circuit of the cascade multilevel inverter is as follows: Figure 7 As shown, we have:

[0258] R eq =N(R1+k 2 R2), L eq =N(L1+k 2 L2);

[0259] The cascade transformer is reconstructed into a two-port network to form a new equivalent transformer. After decoupling and equivalence, the H-bridge inverter module can be regarded as directly cascaded on the primary side of the transformer and then output through the equivalent transformer. According to this equivalent circuit, i′ g The mathematical expression of is shown below.

[0260]

[0261] The above formula can be discretized and solved by numerical iteration. It is worth mentioning that u m is to calculate i′ g But according to the above analysis, um The calculation should take into account u d and u c , as shown below:

[0262]

[0263] Wherein, the subscript j represents the physical quantity of the jth H-bridge inverter module. d The current phase angle of the H-bridge inverter module can be estimated by However, in obtaining i s Before, it was not possible to c Therefore, the embodiment of the present application needs to predict the output current of the H-bridge inverter submodule in the cascade multi-level inverter.

[0264] Example 1:

[0265] like Figure 8 As shown, predicting the output current of the H-bridge inverter module may include steps S1 to S4.

[0266] S1 is based on the opening angle θ of each H-bridge inverter module s and the turn-off angle θ e , calculate the ideal cascade voltage u of the cascaded multilevel inverter m,idl ;

[0267]

[0268] Among them, u idl,j is the ideal output voltage of the jth H-bridge inverter module, which is calculated by the following formula:

[0269] u idl,j =S j ·V DC

[0270]

[0271] S2 estimates the current phase angle of the H-bridge inverter module Calculate the dead zone voltage error u of each H-bridge inverter module d , and then calculate the cascade voltage u considering the dead zone effect m,d ; It is approximately believed that u m,d =u d , based on u m,d Calculate the load current i′ converted to the primary side of the transformer considering only the dead zone effect g,d ;

[0272]

[0273] Among them, u d,jis the dead-zone voltage error of the j-th H-bridge inverter module.

[0274] S3 approximates that i′ g,d Equal to the output current i of each H-bridge inverter module s , using i′ g,d Calculate the voltage error u of the switching parasitic capacitance of each H-bridge inverter module c , and then calculate the equivalent cascade voltage u on the primary side of the transformer m ; Based on u m Calculate the actual load current i′ converted to the primary side of the transformer considering the parasitic capacitance effect of the switch g ;

[0275]

[0276] Among them, u c,j is the voltage error of the switch parasitic capacitance of the jth H-bridge inverter module.

[0277] S4 calculates the excitation current of the transformer connected to each H-bridge inverter module and compares it with i′ g The predicted values ​​of the output currents of the H-bridge inverter modules are obtained by adding them together.

[0278] i s ' ,j =i g ′+i 0,j ,j=1,2,3,...,N;

[0279] Among them, i s ' ,j is the predicted value of the output current of the jth H-bridge inverter module, i 0,j is the excitation current of the transformer connected to the jth H-bridge inverter module. s,j =u idl,j +u d,j +u c,j , where u s,j is the output voltage of the jth H-bridge inverter module, u idl,j 、u d,j and u c,j All of them have been calculated in the previous steps.

[0280] By accounting for voltage errors caused by dead time, parasitic switch capacitance (the turn-on and turn-off delays of the switching devices are also included in the dead time), and the transformer magnetizing current, the proposed four-step current prediction method can accurately predict the output current of each H-bridge inverter module. The predicted current values ​​are used for PWM voltage compensation, improving the accuracy of voltage compensation near the current zero crossing without the need for current sampling.

[0281] Example 2:

[0282] Calculating the compensated turn-on angle and the compensated turn-off angle of each H-bridge inverter module according to the predicted value of the output current of each H-bridge inverter module;

[0283] The phase shift control signal of each switch device in the H-bridge inverter submodule is distributed according to the compensated turn-on angle and the compensated turn-off angle to achieve PWM voltage compensation.

[0284] Considering that the parasitic capacitance effect of the switching device will further reduce the narrow pulse width, Figure 4 (b) and (c) can be combined into one category in PWM voltage compensation. For any H-bridge inverter module, s,com and θ e,com They represent the compensated turn-on angle and the compensated turn-off angle respectively, then:

[0285] At ωt = θ s +δ off hour:

[0286] When the predicted value of the output current is less than or equal to 0, the compensated opening angle of the H-bridge inverter module is calculated by the following formula:

[0287]

[0288] When the predicted value of the output current is greater than 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula:

[0289] θ s,com =θ s -(δ d +δ on -δ off );

[0290] At ωt = θ e +δ off When the output end of the cascaded multilevel inverter is connected to a resistive-inductive load, the predicted output current of each H-bridge inverter module in the cascaded multilevel inverter is greater than 0, and the compensated turn-off angle θ of the H-bridge inverter module is e,com It can be calculated by the following formula:

[0291]

[0292] It is understandable that the turn-on angle and turn-off angle of each H-bridge inverter module can be based on Figure 3 The SHEPWM modulation method shown is determined and pre-recorded in the storage unit. For any H-bridge inverter module, after compensating its opening angle according to the above method, after allocating the phase shift control signal to the switch tube of the H-bridge inverter module, the trigger signal of the left bridge arm tube S1 is θ s,com +δd to θ s,com +π period is high level, the trigger signal of the left bridge arm lower tube S2 is between 0 and θ s,com and θ s,com +π+δ d The trigger signal of the right bridge arm upper tube S3 is high during θ e,com +δ d to θ e,com +π period is high level, the trigger signal of the right bridge arm lower tube S4 is between 0 and θ e,com and θ e,com +π+δ d It is high level during the period from 0 to 2π.

[0293] In this embodiment, after calculating the predicted output current of each H-bridge inverter module, the corresponding dead-zone voltage error and switch parasitic capacitance voltage error are calculated. The turn-on and turn-off angles of each H-bridge inverter module are compensated accordingly, and the phase-shift control signals of each switching device in the H-bridge inverter module are distributed according to the compensated turn-on and turn-off angles. This effectively compensates for PWM voltage distortion caused by the dead-zone effect and the parasitic capacitance of the switching devices. Because the predicted output current of each H-bridge inverter module is obtained through predictive calculation, current detection and optical fiber communication delay time are eliminated. Low-order harmonics introduced by the dead-zone effect can be effectively suppressed in a high-frequency cascade topology, significantly improving waveform quality.

[0294] The beneficial effects that can be achieved by the embodiments of the present application are further explained below with reference to specific simulation examples.

[0295] The simulation verification was carried out using MATLAB / Simulink software to verify the compensation effect of the high-frequency cascade multi-level inverter dead zone compensation method based on current phase estimation provided by the embodiment of the present application. The simulation model uses a single-phase 17-level high-frequency cascade multi-level converter and adopts SHEPWM to eliminate harmonics of 15 times the fundamental frequency and below. Set the DC bus voltage V DC =200V, fundamental frequency f0 = 30kHz, dead time t d =500ns, and the rest of the system parameters and load parameters are shown in Table 1.

[0296] Table 1

[0297]

[0298]

[0299] Among them, the transformer parameters and transmission line parameters are related to the fundamental frequency. The table only lists the system parameters when f0 = 30kHz. DC =200V, the parasitic capacitance of the switching device Coss Set to 605pF.

[0300] First, the dead time and the switching device delay time are converted into radians, i.e., δ d =2πf0t d , δ on =2πf0t on and δ off =2πf0t off The system model of the cascaded multilevel inverter is established by the above modeling method to calculate the equivalent leakage resistance R of the cascaded transformer. eq and equivalent leakage inductance L eq , using the load parameter R g and L g The output current of the H-bridge inverter module is calculated in advance, and the current prediction value is used to compensate the turn-on angle and turn-off angle of each H-bridge inverter module in the multi-level inverter to achieve PWM voltage compensation.

[0301] Figure 9 A comparison of the load voltage harmonic content under four conditions is provided: no compensation method in the simulation, a traditional compensation method that only compensates for the dead time error voltage (traditional method 1), a traditional compensation method that compensates for the dead time error voltage and the switch parasitic capacitance error voltage based on current detection (traditional method 2), and a voltage compensation method of the cascaded multi-level inverter provided by the embodiment of the present application. Under the influence of the dead time effect and the switch parasitic capacitance effect, the third and fifth harmonics in the load voltage increase significantly and become the main harmonic components. Traditional method 1 ignores the voltage error introduced by the switch parasitic capacitance and only compensates for the dead time error voltage, resulting in incorrect switching angle compensation. Only the 3rd and 15th harmonics are reduced, while all other harmonics are significantly increased. Traditional method 2 compensates for the voltage errors introduced by the dead time and the switch parasitic capacitance, where the switch parasitic capacitance voltage error is calculated based on the current sampling value at the beginning of the dead time. The 3rd and 5th harmonics are reduced, but are still much larger than 0.10% of the fundamental. The reason is that traditional method 2 relies on current detection. Due to the fiber optic communication delay introduced by the distributed structure of the multi-level inverter, the PWM voltage compensation instruction lags behind the ideal compensation moment, causing the turn-on angle and turn-off angle of the H-bridge inverter module to be overcompensated. In contrast, the method provided by the present invention compensates for the voltage error introduced by the dead time and the parasitic capacitance of the switch based on the accurate prediction of the current value of the H-bridge inverter module. Both current prediction and PWM voltage compensation are completed in the main controller, eliminating current detection and avoiding communication delays. When using the voltage compensation method for the cascaded multi-level inverter provided in the embodiment of the present application, the 3rd to 7th harmonics are suppressed to less than 0.10% of the fundamental wave. Compared with the traditional method, low-order harmonics are better suppressed.

[0302] The harmonics introduced by the dead zone effect and the parasitic capacitance effect of the switch are vector-added with the ideal voltage harmonics. Some higher-order harmonics will decrease after the dead zone time is inserted. In order to more comprehensively reflect the harmonic suppression capability of the voltage compensation method for the cascaded multi-level inverter provided by the embodiment of the present application, the total harmonic distortion (THD) indicator is introduced. The THD of the output voltage under the four simulation conditions is 3.08%, 2.50%, 1.32% and 1.16% respectively. It can be seen that the voltage compensation method for the cascaded multi-level inverter provided by the embodiment of the present application effectively suppresses the harmonics introduced by the PWM voltage distortion in the high-frequency cascaded multi-level inverter.

[0303] The voltage compensation method for a cascaded multilevel inverter provided in an embodiment of the present application takes into account all factors that affect PWM voltage edges, including dead time, switch parasitic capacitance, and switch turn-on and turn-off delays. It also incorporates the transformer's excitation current in the calculation, enabling accurate prediction of the output current of each H-bridge inverter submodule in a cascaded multilevel inverter employing a transformer. The method then compensates the PWM voltage of each H-bridge inverter submodule based on the predicted output current, eliminating the need for current sensors and eliminating communication delays.

[0304] The voltage compensation device for a cascaded multilevel inverter provided by the present invention is described below. The voltage compensation device for a cascaded multilevel inverter described below and the voltage compensation method for a cascaded multilevel inverter described above can be referred to in correspondence with each other.

[0305] See also Figure 10 An embodiment of the present application provides a voltage compensation device for a cascaded multi-level inverter, including: a first acquisition module 1010 , a second acquisition module 1020 and a compensation module 1030 .

[0306] A first acquisition module 1010 is configured to obtain a predicted value of an output current of each H-bridge inverter submodule in a cascaded multilevel inverter, and determine a compensated turn-on angle and a compensated turn-off angle of each H-bridge inverter submodule;

[0307] A second acquisition module 1020 is configured to determine a phase shift control signal for each switching device in the H-bridge inverter submodule according to the compensated turn-on angle and the compensated turn-off angle;

[0308] The compensation module 1030 is configured to compensate the output voltage of each H-bridge inverter submodule according to the phase shift control signal of each switching device in each H-bridge inverter submodule.

[0309] The voltage compensation device for the cascaded multi-level inverter provided in the embodiment of the present application utilizes the predicted value of the output current of each H-bridge inverter module in the cascaded multi-level inverter to compensate the turn-on angle and turn-off angle of each H-bridge inverter module respectively, and distributes the phase shift control signal of each switching device in the H-bridge inverter module according to the compensated turn-on angle and turn-off angle, thereby effectively compensating for the PWM voltage distortion caused by the dead zone effect and the switch parasitic capacitance effect. In addition, the present application does not need to detect the output current of the H-bridge inverter module, eliminating the current detection hardware and optical fiber communication delay time. In the high-frequency cascade topology, the low-order harmonics introduced by the dead zone effect and the switch parasitic capacitance effect can be effectively suppressed, significantly improving the waveform quality. It is understandable that the detailed functional implementation of each of the above-mentioned units / modules can be found in the introduction of the aforementioned method embodiment, and will not be repeated here.

[0310] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method and will not be repeated here.

[0311] Based on the method in the above embodiment, the embodiment of the present application provides an electronic device, see Figure 11 The electronic device may include: a processor 1110, a communications interface 1120, a memory 1130, and a communication bus 1140. The processor 1110, the communications interface 1120, and the memory 1130 communicate with each other via the communication bus 1140. The processor 1110 may call logic instructions in the memory 1130 to execute the method in the above embodiment.

[0312] In addition, the logic instructions in the above-mentioned memory 1130 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0313] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0314] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0315] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0316] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0317] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0318] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0319] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A voltage compensation method for a cascaded multi-level inverter, characterized in that: include: Determining a compensated turn-on angle and a compensated turn-off angle of each H-bridge inverter submodule according to a predicted value of an output current of each H-bridge inverter submodule in the cascaded multilevel inverter; Determining a phase shift control signal of each switching device in the H-bridge inverter submodule according to the compensated turn-on angle and the compensated turn-off angle; Compensating the output voltage of each H-bridge inverter module according to a phase shift control signal of each switching device in each H-bridge inverter module; determining the compensated turn-on angle and the compensated turn-off angle of each H-bridge inverter module according to the predicted value of the output current of each H-bridge inverter module in the cascaded multi-level inverter, including: For any H-bridge inverter module, In case of: If the predicted value of the output current is less than or equal to 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula: ； If the predicted value of the output current is greater than 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula: ； in, is the opening angle of the H-bridge inverter module after compensation, is the turn-on angle of the H-bridge inverter module, is the DC bus voltage, is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, is the angle corresponding to the dead time, is the voltage error of the parasitic capacitance of the switching device of the H-bridge inverter module, is the fundamental angular frequency, is the current time; exist In the case of , if the output end of the cascaded multilevel inverter is connected to a resistive-inductive load, the compensated turn-off angle of the H-bridge inverter submodule is calculated by the following formula: ； in, is the turn-off angle of the H-bridge inverter module, is the compensated turn-off angle of the H-bridge inverter module; The method for obtaining the predicted value of the output current of each H-bridge inverter sub-module includes: Calculating an ideal cascade voltage of the cascaded multi-level inverter according to the turn-on angle and turn-off angle of each H-bridge inverter submodule; Calculating a cascade voltage taking into account a dead-zone effect based on the dead-zone voltage errors of the H-bridge inverter submodules and the ideal cascade voltage; Calculating a load current value taking into account a dead zone effect according to the cascade voltage; Calculating the voltage error of the parasitic capacitance of the switching device of each H-bridge inverter module according to the load current value; Calculating the equivalent cascade voltage of the primary side of the transformer connected to each H-bridge inverter sub-module according to the voltage error; Calculating the actual load current of the primary side of the transformer taking into account the parasitic capacitance effect of the switch according to the equivalent cascade voltage; The predicted value of the output current of each H-bridge inverter submodule is calculated according to the excitation current of the transformer and the actual load current.

2. The voltage compensation method for a cascaded multi-level inverter according to claim 1, wherein: Calculating the ideal cascade voltage of the cascade multi-level inverter according to the turn-on angle and turn-off angle of each H-bridge inverter sub-module includes: The ideal cascade voltage is calculated by the following formula: ； Where, is the ideal cascade voltage, is the number of H-bridge inverter modules, For the The ideal output voltage of each H-bridge inverter module is calculated as follows: ； Where, is the DC bus voltage, Calculated by the following formula: ； Where, is the fundamental angular frequency, is the current time, For the The turn-on angle of each H-bridge inverter module, For the The turn-off angle of each H-bridge inverter module, is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module.

3. The voltage compensation method for a cascaded multi-level inverter according to claim 1, wherein: The calculating of the cascade voltage taking into account the dead-zone effect according to the dead-zone voltage errors of the H-bridge inverter sub-modules and the ideal cascade voltage includes: The cascade voltage is calculated by the following formula: ； Where, is the cascade voltage, is the ideal cascade voltage, is the number of H-bridge inverter modules, For the Dead-zone voltage error of each H-bridge inverter module; When the output of the cascaded multilevel inverter is connected to a resistive-inductive load, Calculated by the following formula: when When, if ,but ; when When, if ,but ,like ,but ,otherwise, ; when When, if ,but ,like ,but ,otherwise, ; Where, is the current phase angle of the H-bridge inverter module, For the The turn-on angle of each H-bridge inverter module, is the angle corresponding to the dead time, is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, is the DC bus voltage.

4. The voltage compensation method for a cascaded multi-level inverter according to claim 1, wherein: The calculating, based on the cascade voltage, a load current value taking into account a dead zone effect, includes: The load current value is calculated by the following formula: ； Where, is the cascade voltage, is the current time, is the load current value, is the inductance value of the parasitic inductance of the transmission line, is the parasitic resistance of the transmission line, is the inductance value of the load inductor, is the resistance of the load resistor, is the transformer winding coefficient in the cascaded multilevel inverter, is the inductance value of the equivalent leakage inductance of the cascaded multilevel inverter, is the resistance of the equivalent winding resistance of the cascaded multi-level inverter.

5. The voltage compensation method for a cascaded multi-level inverter according to claim 1, wherein: Calculating the equivalent cascade voltage on the primary side of the transformer connected to each H-bridge inverter sub-module based on the voltage error includes: The equivalent cascade voltage is calculated by the following formula: ； Where, is the equivalent cascade voltage, is the cascade voltage, is the number of H-bridge inverter modules, For the The voltage error of the parasitic capacitance of the switching devices of the H-bridge inverter submodule, including the voltage error of each H-bridge module inverter in the positive half cycle and the voltage error in the negative half cycle ; When the output end of the cascaded multi-level inverter is connected to a resistive-inductive load, the voltage error of each H-bridge module inverter in the positive half cycle is calculated by the following formula: exist When the output current of the H-bridge inverter module is less than or equal to 0, and The voltage error in the positive half cycle is calculated as follows: Where, is the fundamental angular frequency, is the current time, For the The turn-on angle of each H-bridge inverter module, is the DC bus voltage, is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, is the angle corresponding to the dead time, For the The first voltage rise time of each H-bridge inverter module, , is the parasitic capacitance of the switching devices in the H-bridge inverter module, For the Output current of each H-bridge inverter module exist The linear average within is the current threshold; exist If the output current of the H-bridge inverter module is greater than 0, then when hour, ; exist When, according to and The voltage error in the positive half cycle is calculated as follows: ； Where, For the The turn-off angle of each H-bridge inverter module, For the Output current of each H-bridge inverter module exist The linear average within For the The second voltage rise time of each H-bridge inverter module is calculated by the following formula: ； Voltage error of each H-bridge module inverter in the negative half cycle .

6. The voltage compensation method for a cascaded multi-level inverter according to claim 1, wherein: Calculating the actual load current of the primary side of the transformer taking into account the parasitic capacitance effect of the switching device according to the equivalent cascade voltage includes: The actual load current is calculated by the following formula: ； Where, is the equivalent cascade voltage, is the actual load current, is the current time, is the inductance value of the parasitic inductance of the transmission line, is the parasitic resistance of the transmission line, is the inductance value of the load inductor, is the resistance of the load resistor, is the transformer winding coefficient in the cascaded multilevel inverter, is the inductance value of the equivalent leakage inductance of the cascaded multilevel inverter, is the resistance of the equivalent winding resistance of the cascaded multi-level inverter.

7. The voltage compensation method for a cascaded multi-level inverter according to claim 1, wherein: The step of calculating the predicted value of the output current of each H-bridge inverter submodule according to the excitation current of the transformer and the actual load current includes: The predicted value of the output current is calculated by the following formula: ； Where, For the The predicted value of the output current of each H-bridge inverter module, is the number of H-bridge inverter modules, is the actual load current, For the said The excitation current of each H-bridge inverter module is calculated by the following formula: ； Where, is the current time, For the The output voltage of each H-bridge inverter module, is the inductance of the excitation inductance of a single transformer, is the equivalent excitation resistance of a single transformer.

8. A voltage compensation device for a cascaded multi-level inverter, characterized in that: include: A first acquisition module is configured to determine a compensated turn-on angle and a compensated turn-off angle of each H-bridge inverter submodule according to a predicted value of an output current of each H-bridge inverter submodule in the cascaded multilevel inverter; A second acquisition module is used to determine the phase shift control signal of each switching device in the H-bridge inverter submodule according to the compensated turn-on angle and the compensated turn-off angle; a compensation module, configured to compensate the output voltage of each H-bridge inverter submodule according to a phase shift control signal of each switching device in each H-bridge inverter submodule; The step of determining the compensated turn-on angle and the compensated turn-off angle of each H-bridge inverter submodule according to the predicted value of the output current of each H-bridge inverter submodule in the cascaded multilevel inverter includes: For any H-bridge inverter module, In case of: If the predicted value of the output current is less than or equal to 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula: ； If the predicted value of the output current is greater than 0, the compensated opening angle of the H-bridge inverter module is calculated using the following formula: ； in, is the opening angle of the H-bridge inverter module after compensation, is the turn-on angle of the H-bridge inverter module, is the DC bus voltage, is the angle corresponding to the turn-off delay time of the switching device in the H-bridge inverter module, is the angle corresponding to the turn-on delay time of the switching device in the H-bridge inverter module, is the angle corresponding to the dead time, is the voltage error of the parasitic capacitance of the switching device of the H-bridge inverter module, is the fundamental angular frequency, is the current time; exist In the case of , if the output end of the cascaded multilevel inverter is connected to a resistive-inductive load, the compensated turn-off angle of the H-bridge inverter submodule is calculated by the following formula: ； in, is the turn-off angle of the H-bridge inverter module, is the compensated turn-off angle of the H-bridge inverter module; The method for obtaining the predicted value of the output current of each H-bridge inverter sub-module includes: Calculating an ideal cascade voltage of the cascaded multi-level inverter according to the turn-on angle and turn-off angle of each H-bridge inverter submodule; Calculating a cascade voltage taking into account a dead-zone effect based on the dead-zone voltage errors of the H-bridge inverter submodules and the ideal cascade voltage; Calculating a load current value taking into account a dead zone effect according to the cascade voltage; Calculating the voltage error of the parasitic capacitance of the switching device of each H-bridge inverter module according to the load current value; Calculating the equivalent cascade voltage of the primary side of the transformer connected to each H-bridge inverter sub-module according to the voltage error; Calculating the actual load current of the primary side of the transformer taking into account the parasitic capacitance effect of the switch according to the equivalent cascade voltage; The predicted value of the output current of each H-bridge inverter submodule is calculated according to the excitation current of the transformer and the actual load current.

Images