Microprocessor-based nmos transistor driver circuit, system, and apparatus

Abstract

The application discloses a kind of NMOS tube driving circuit, system and device based on microprocessor, it is related to electronic circuit technical field, the driving circuit includes the voltage regulating circuit, pulse generating circuit, boost circuit connected in turn;Pulse generating circuit includes second PNP triode, third NPN triode, third resistance, fourth resistance, fifth resistance, sixth resistance, seventh resistance and microprocessor;The output end of voltage regulating circuit is connected with the one end of third resistance and the emitter of second PNP triode;The collector of second PNP triode is as the output end of pulse generating circuit;The other end of third resistance is connected with the base of second PNP triode and the one end of fourth resistance.This application generates pulse signal by the pulse generating circuit of design cooperation microprocessor, provides foundation for subsequent driving work, meets actual demand under the premise of effectively controlling cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuit, in particular to a NMOS tube driving circuit, system and device based on microprocessor. BACKGROUND

[0002] When the NMOS tube is in high-side output, the gate voltage of the NMOS tube needs to be higher than the drain voltage, and the NMOS tube can be turned on only when the gate voltage is higher than the turn-on threshold voltage. In order to make the NMOS tube fully conduct, the turn-on threshold voltage is generally about 10V, that is, the gate voltage is about 10V higher than the drain voltage. The MOS tube only has a fully conductive state, and the internal resistance is small so as not to heat up. Only when the MOS tube is fully conductive, the damage to the tube can be reduced.

[0003] At present, the body control mostly uses high-side output intelligent MOS tubes. The intelligent MOS integrates the driving circuit of the tube, and the user of the tube only needs to provide a level signal for driving. However, the intelligent MOS tube is expensive and has poor selectivity. If a common MOS tube is used, an external MOS tube high-side driving circuit is designed separately, which can effectively reduce the cost and enrich the diversity. However, there is no technology that can meet the above requirements at present.

[0004] Therefore, in order to meet the actual needs, the present application provides a NMOS tube driving technology based on microprocessor. SUMMARY

[0005] In view of the defects in the prior art, the purpose of the present application is to provide a NMOS tube driving circuit, system and device based on microprocessor. The pulse signal is generated by the designed pulse generating circuit cooperating with the microprocessor, which provides the basis for subsequent driving work. Under the premise of effectively controlling the cost, the actual needs are met.

[0006] In order to achieve the above purpose, the technical scheme adopted by the present application is:

[0007] In a first aspect, the present application provides a NMOS tube driving circuit based on microprocessor, which comprises a regulating voltage circuit, a pulse generating circuit and a voltage boosting circuit connected in sequence.

[0008] The pulse generating circuit comprises a second PNP transistor, a third NPN transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a microprocessor.

[0009] The output end of the regulating voltage circuit is connected with one end of the third resistor and the emitter of the second PNP transistor.

[0010] The collector of the second PNP triode is connected with one end of the seventh resistor, and the other end of the seventh resistor is grounded, and the seventh resistor serves as an output terminal of the pulse generating circuit;

[0011] The other end of the third resistor is connected with the base of the second PNP triode and one end of the fourth resistor;

[0012] The collector of the third NPN triode is connected with the other end of the fourth resistor;

[0013] The output terminal of the microprocessor is connected with one end of the fifth resistor, and the other end of the fifth resistor is connected with one end of the sixth resistor and the base of the third NPN triode;

[0014] The other end of the sixth resistor and the emitter of the third NPN triode are both grounded.

[0015] On the basis of the above technical solution, the voltage regulating circuit comprises a first resistor, a second resistor, a third diode and a first NPN triode;

[0016] One end of the first resistor is connected with the collector of the first NPN triode and a power supply terminal;

[0017] The other end of the first resistor is connected with the base of the first NPN triode, one end of the second resistor and the negative electrode of the third diode;

[0018] The positive electrode of the third diode and the other end of the second resistor are both grounded;

[0019] The emitter of the first NPN triode serves as an output terminal of the voltage regulating circuit.

[0020] On the basis of the above technical solution, the voltage regulating circuit comprises a first resistor, a second resistor, a third diode and a first NPN triode;

[0021] One end of the first resistor is connected with the collector of the first NPN triode and a power supply terminal;

[0022] The other end of the first resistor is connected with the base of the first NPN triode, one end of the second resistor and the negative electrode of the third diode;

[0023] The positive electrode of the third diode and the other end of the second resistor are both grounded;

[0024] The emitter of the first NPN triode serves as an output terminal of the voltage regulating circuit.

[0025] On the basis of the above technical solution, the circuit further comprises:

[0026] The gate drive switch circuit is connected with the output terminal of the voltage boosting circuit.

[0027] On the basis of the above technical solution, the gate drive switch circuit comprises a plurality of parallel switch circuits.

[0028] On the basis of the above technical solution, the third diode is a voltage stabilizing diode.

[0029] On the basis of the above technical solution, the voltage of the power supply terminal is 12V or 24V or 48V.

[0030] In a second aspect, the application provides a microprocessor-based NMOS tube driving system, which comprises a housing with a receiving cavity formed therein, and the microprocessor-based NMOS tube driving circuit mentioned in the first aspect arranged in the housing.

[0031] In a third aspect, the application provides a microprocessor-based NMOS tube driving device, which comprises the microprocessor-based NMOS tube driving system mentioned in the second aspect.

[0032] Compared with the prior art, the application has the following advantages:

[0033] The pulse signal generated by the designed pulse generating circuit in cooperation with the microprocessor provides a basis for subsequent driving work, and the actual demand is met under the premise of effectively controlling the cost. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0035] Figure 1 The structure diagram of the microprocessor-based NMOS tube driving circuit in the embodiments of the application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the embodiments of the application clearer, the technical scheme in the embodiments of the application will be described clearly and completely in conjunction with the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor belong to the scope of protection of the application.

[0037] The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0038] The embodiment of the present application provides a microprocessor-based NMOS tube driving circuit, system and device, a pulse signal is generated through a designed pulse generating circuit cooperating with a microprocessor, a basis is provided for subsequent driving work, actual needs are met under the premise of effectively controlling cost.

[0039] To achieve the above technical effects, the general idea of the present application is as follows:

[0040] A microprocessor-based NMOS tube driving circuit, the driving circuit comprises a regulating voltage circuit, a pulse generating circuit, a voltage boosting circuit connected in sequence;

[0041] The pulse generating circuit comprises a second PNP transistor, a third NPN transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a microprocessor;

[0042] The output end of the regulating voltage circuit is connected with one end of the third resistor and the emitter of the second PNP transistor;

[0043] The collector of the second PNP transistor is connected with one end of the seventh resistor, and the output end of the pulse generating circuit, and the other end of the seventh resistor is grounded;

[0044] The other end of the third resistor is connected with the base of the second PNP transistor and one end of the fourth resistor;

[0045] The collector of the third NPN transistor at the other end of the fourth resistor is connected;

[0046] The output end of the microprocessor is connected with one end of the fifth resistor, and the other end of the fifth resistor is connected with one end of the sixth resistor and the base of the third NPN transistor;

[0047] The other end of the sixth resistor and the emitter of the third NPN transistor are both grounded.

[0048] The embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0049] In the first aspect, referring to Figure 1 The embodiment of the present application provides a microprocessor-based NMOS tube driving circuit, the driving circuit comprises a regulating voltage circuit, a pulse generating circuit, a voltage boosting circuit connected in sequence;

[0050] The pulse generating circuit comprises a second PNP transistor, a third NPN transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a microprocessor;

[0051] The output terminal of the voltage regulation circuit is connected to one end of the third resistor and the emitter of the second PNP transistor.

[0052] The collector of the second PNP transistor is connected to one end of the seventh resistor and serves as the output terminal of the pulse generation circuit, while the other end of the seventh resistor is grounded.

[0053] The other end of the third resistor is connected to the base of the second PNP transistor and one end of the fourth resistor.

[0054] The collector of the third NPN transistor is connected to the other end of the fourth resistor.

[0055] The output terminal of the microprocessor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to one end of the sixth resistor and the base of the third NPN transistor.

[0056] The other end of the sixth resistor and the emitter of the third NPN transistor are both grounded.

[0057] It should be noted that, in order to address the technical issues mentioned above and to reliably drive the NMOS transistor, the gate drive voltage and drain voltage must have a constant voltage. Regardless of changes in the input voltage, the gate drive voltage must be higher than the drain voltage by the full turn-on voltage, but cannot exceed the limit voltage of the full turn-on voltage, which is generally around 20V. Taking a 24V vehicle system as an example, it needs to be able to operate normally in environments with power supply voltages ranging from 18V to 32V. This requires the gate drive voltage to follow voltage changes and always be higher than, and only higher than, the full turn-on voltage.

[0058] In this embodiment, a pulse signal is generated by a designed pulse generation circuit in conjunction with a microprocessor, providing a foundation for subsequent driving operations and meeting practical needs while effectively controlling costs.

[0059] Furthermore, the voltage regulation circuit includes a first resistor, a second resistor, a third diode, and a first NPN transistor;

[0060] One end of the first resistor is connected to the collector and power supply terminal of the first NPN transistor;

[0061] The other end of the first resistor is connected to the base of the first NPN transistor, one end of the second resistor, and the negative terminal of the third diode;

[0062] The positive terminal of the third diode and the other end of the second resistor are both grounded;

[0063] The transmitter of the first NPN transistor serves as the output terminal of the voltage regulation circuit.

[0064] Furthermore, the boost circuit includes a second capacitor, a second diode, a first diode, and a third capacitor;

[0065] One end of the second capacitor is connected to the output terminal of the pulse generating circuit;

[0066] The other end of the second capacitor is connected to the negative terminal of the second diode and the positive terminal of the first diode;

[0067] The positive terminal of the second diode is connected to the power supply terminal;

[0068] The negative terminal of the first diode is connected to one end of the capacitor, forming the output terminal of the boost circuit.

[0069] Furthermore, the circuit also includes:

[0070] A gate drive switch circuit, the input of which is connected to the output of the boost circuit.

[0071] Furthermore, the gate drive switch circuit includes multiple switch circuits connected in parallel.

[0072] Furthermore, the third diode is a Zener diode.

[0073] Furthermore, the voltage (VC) at the power supply terminal is 12V, 24V, or 48V.

[0074] As shown in the attached diagram of the instruction manual. Figure 1 As shown, the voltage at the power supply terminal is denoted as VC, and the output voltage of the voltage regulating circuit is denoted as VTH.

[0075] The first resistor is denoted as R1, the second resistor as R2, the third diode as D3, and the first NPN transistor as Q1.

[0076] The second PNP transistor is denoted as Q2, the third NPN transistor as Q3, the third resistor as R3, the fourth resistor as R4, the fifth resistor as R5, the sixth resistor as R6, the seventh resistor as R7, and the microprocessor signal as MCU-PWM.

[0077] The second capacitor is denoted as C2, the second diode as D2, the first diode as D1, and the third capacitor as C3.

[0078] The gate drive switch circuit includes multiple parallel switch circuits, denoted as K1, K2, ..., Kn.

[0079] Based on the technical solutions of the embodiments of this application, and in conjunction with the accompanying drawings, Figure 1The explanation is as follows:

[0080] The first part of the accompanying diagram, namely the voltage regulation circuit, primarily functions to generate a stable voltage based on the VC voltage at the power supply terminal. Even if the VC voltage fluctuates, the output voltage VTH remains a fixed value. The voltage regulation circuit provides a boost voltage with a constant differential voltage; other forms of voltage regulator circuits can be used as substitutes if necessary.

[0081] The voltage value of VTH is less than the regulated voltage of the third diode, with a specific voltage difference of 0.7V. The first resistor R1 and the second resistor R2 are both used as voltage divider resistors.

[0082] The fourth part of the attached diagram in the manual, namely the pulse generation circuit, generates pulse signals. It is generated by the MCU, and the peak-to-peak value of the pulse voltage is VTH. It is generated by the microprocessor MCU_PWM control, and the frequency is determined by the microprocessor MCU_PWM signal.

[0083] The second part of the accompanying diagram, namely the boost circuit, is mainly intended to boost a constant voltage based on the VC voltage. This constant voltage is determined by the peak-to-peak value of the pulse voltage, VTH, and its frequency.

[0084] The working process of the boost circuit is as follows:

[0085] The pulse signal generated by the pulse generator circuit enters the negative terminal of the second diode D2 through the second capacitor C2. The VC voltage also enters the negative terminal of the second diode D2 through D2 (if the second diode D2 is made of silicon, the voltage drops by about 0.7V). When the pulse signal voltage is 0V (low level), the voltage at the positive terminal of D1 is approximately the VC voltage. When the pulse signal voltage is VTH (high level), the voltage at the positive terminal of D1 is approximately the VC+VTH voltage. Thus, the pulse signal at the negative terminal of the second diode D2 is superimposed on the VC voltage.

[0086] After being filtered by the first diode D1 and the third capacitor C3, the pulse signal is converted into a DC signal. At this time, the voltage is higher than the VC voltage, that is, a boost voltage has occurred.

[0087] The third part of the accompanying drawings describes the gate drive switch circuit, which may include multiple switch circuits connected in parallel, and the switch circuits may be various electronic switches.

[0088] It should be noted that the advantages of the technical solution in the embodiments of this application are as follows:

[0089] The pulse signal generation method of the above pulse generation circuit is relatively simple, but it requires a microprocessor (MCU) to complete the process. The MCU generates the PMW pulse, and the switching circuit (Q2, Q3, R3, R4, R5, R6) completes the amplitude amplification of the pulse (also known as the amplitude amplification circuit), amplifying the peak-to-peak value to VTH. The amplitude amplification circuit can also be completed by a device that integrates NPN transistors, PNP transistors, and resistors, which can form a smaller space and fewer components.

[0090] Furthermore, in practical use, the technical solution of this application embodiment can generate a voltage with a constant voltage difference relative to the power supply voltage VC, and change with the change of VC voltage;

[0091] In addition, multiple NMOS transistors can be powered and driven centrally.

[0092] Secondly, embodiments of this application provide a microprocessor-based NMOS transistor driving system, the system comprising: a housing having an internal cavity, and the microprocessor-based NMOS transistor driving circuit mentioned in the first aspect, disposed within the housing.

[0093] The NMOS transistor high-side drive system provided in this application embodiment is the same as the NMOS transistor high-side drive circuit mentioned in the first aspect in terms of technical solution, technical problem solved and technical effect obtained, and will not be repeated here.

[0094] Thirdly, embodiments of this application provide a microprocessor-based NMOS transistor driving device, which includes the microprocessor-based NMOS transistor driving system mentioned in the second aspect.

[0095] The NMOS transistor high-side driving device provided in this application embodiment is the same as the NMOS transistor high-side driving circuit mentioned in the first aspect and the NMOS transistor high-side driving system mentioned in the second aspect in terms of technical solution, technical problem solved and technical effect obtained, and will not be repeated here.

[0096] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0097] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0098] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A microprocessor-based NMOS transistor driving circuit, characterized in that, The driving circuit includes a voltage regulation circuit, a pulse generation circuit, and a boost circuit connected in sequence. The pulse generating circuit includes a second PNP transistor, a third NPN transistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a microprocessor; The output terminal of the voltage regulation circuit is connected to one end of the third resistor and the emitter of the second PNP transistor. The collector of the second PNP transistor is connected to one end of the seventh resistor and serves as the output terminal of the pulse generation circuit, while the other end of the seventh resistor is grounded. The other end of the third resistor is connected to the base of the second PNP transistor and one end of the fourth resistor. The collector of the third NPN transistor is connected to the other end of the fourth resistor. The output terminal of the microprocessor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to one end of the sixth resistor and the base of the third NPN transistor. The other end of the sixth resistor and the emitter of the third NPN transistor are both grounded; The boost circuit includes a second capacitor, a second diode, a first diode, and a third capacitor; One end of the second capacitor is connected to the output terminal of the pulse generating circuit; The other end of the second capacitor is connected to the negative terminal of the second diode and the positive terminal of the first diode; The positive terminal of the second diode is connected to the power supply terminal; The negative terminal of the first diode is connected to one end of the capacitor to form the output terminal of the boost circuit; The voltage regulation circuit includes a first resistor, a second resistor, a third diode, and a first NPN transistor; One end of the first resistor is connected to the collector and power supply terminal of the first NPN transistor; The other end of the first resistor is connected to the base of the first NPN transistor, one end of the second resistor, and the negative terminal of the third diode; The positive terminal of the third diode and the other end of the second resistor are both grounded; The transmitter of the first NPN transistor serves as the output terminal of the voltage regulation circuit; wherein, the third diode is a Zener diode, and the output voltage of the voltage regulation circuit is less than the Zener voltage of the third diode.

2. The microprocessor-based NMOS transistor driving circuit as described in claim 1, characterized in that, The circuit also includes: A gate drive switch circuit, the input of which is connected to the output of the boost circuit.

3. The microprocessor-based NMOS transistor driving circuit as described in claim 2, characterized in that: The gate drive switch circuit includes multiple switch circuits connected in parallel.

4. The microprocessor-based NMOS transistor driving circuit as described in claim 1, characterized in that: The voltage at the power supply terminal is 12V, 24V, or 48V.

5. A microprocessor-based NMOS transistor driving system, characterized in that, include: A housing with an internal receiving cavity, and a microprocessor-based NMOS transistor driving circuit as described in any one of claims 1-4, are disposed within the housing.

6. A microprocessor-based NMOS transistor driving device, characterized in that, The microprocessor-based NMOS transistor driving device includes the system described in claim 5.

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