Level-skipping pipelined analog-to-digital converter with triggered sampling and residual quantization

Abstract

The present invention discloses a level-spanning pipelined analog-to-digital converter with trigger sampling and residual quantization, including a level-spanning detection circuit, a residual voltage capture circuit, a residual amplification circuit, and a sub-analog-to-digital conversion circuit; the present invention monitors the input signal through a level-spanning detection circuit, and when the input signal crosses a preset level, a spanning signal and a first-level digital code are generated, and at the same time, a residual voltage capture circuit starts to work, and the residual voltage is accurately captured by the sampling operation triggered by the spanning signal and the direct feedback of the first-level digital code, and the captured residual voltage is amplified by a residual amplification circuit, and then further quantized by a second-level sub-analog-to-digital conversion circuit to generate a second-level digital code. The present invention converts the inevitable signal-related errors in the traditional level-spanning analog-to-digital converter into smaller non-signal-related errors by introducing trigger sampling and residual quantization, effectively solving the challenge of high-precision design of the level-spanning analog-to-digital converter.

Description

Technical Field

[0001] The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a level-spanning pipeline analog-to-digital converter with trigger sampling and residual quantization. Background Art

[0002] Analog-to-digital converter (ADC) is a bridge between the analog world and the digital world, and plays an indispensable role in modern electronic systems. In the real world, data and signals usually exist in analog form, such as sound, light signals, temperature, etc. However, digital systems can only process discrete digital signals, so analog-to-digital converters are needed to digitize continuously changing analog signals for storage, processing and transmission.

[0003] As people pay more and more attention to health, wearable medical devices are gradually becoming a hot topic; wearable medical devices provide doctors with more comprehensive data support by monitoring various physical indicators of patients in their daily lives, so as to customize more accurate treatment plans. Such devices usually rely on batteries for power supply. For such energy-constrained fields, analog-to-digital converters are key modules that affect device performance. Considering its high accuracy, wearable and sustainable recording characteristics, it not only requires low power consumption to extend the battery life and avoid overheating of the device causing damage to human tissue, but also requires sufficient accuracy to ensure the accurate acquisition of biopotential signals.

[0004] In order to achieve the performance requirements of low power consumption and high precision, many Nyquist analog-to-digital converters and oversampling analog-to-digital converters have been applied to the recording of biopotential signals. These analog-to-digital converters are driven by high-speed clocks at the MHz level to uniformly sample and process the signals. Although such clock-driven uniformly sampled analog-to-digital converters have high resolution and high energy efficiency, they often waste power due to the particularity of biopotential signals. Biopotential signals, especially electrocardiogram signals, are sparse signals. They usually show rapid changes in a short period of time, followed by a long period of inactivity. When recording such signals, the clock-driven analog-to-digital converter will generate a large number of sampling points during the inactive period of the signal, resulting in low information density and unnecessary power consumption.

[0005] In order to avoid wasting power during signal inactivity, a level-crossing ADC has been proposed and used for the acquisition of sparse signals. Unlike clock-driven uniform sampling ADCs, the level-crossing ADC is an event-driven non-uniform ADC that compares the amplitude of the input signal with a preset voltage. Whenever the input signal crosses a predefined voltage, the output is the voltage value and the time of crossing the voltage. The input signal is reconstructed by interpolating these two sets of data. The event-driven working mode makes full use of the sparsity of biopotential signals, and the output points are concentrated during the active period of the signal, which greatly reduces the power consumption during the inactive period.

[0006] However, level-skipping ADCs face challenges in achieving high precision. Traditional level-skipping ADCs use continuous-time comparators to monitor input signals, but since their propagation delay is related to the input signal, it varies with different input signals, introducing signal-dependent delays. When reconstructing the input signal, this signal-dependent delay can cause significant distortion, severely limiting the accuracy of the system. Among all reported level-skipping ADCs, the highest SNDR (Signal Noise Distortion Rate) achieved when the third harmonic is included is only 64dB. Summary of the invention

[0007] In view of the above, the present invention provides a level-skipping pipelined analog-to-digital converter with triggered sampling and residual quantization, which can accurately capture signal-related errors in traditional level-skipping analog-to-digital converters and convert the errors into smaller non-signal-related errors using a pipelined working mode, thereby improving the effective number of bits of the level-skipping analog-to-digital converter.

[0008] A level-spanning pipeline analog-to-digital converter with triggered sampling and residual quantization, comprising:

[0009] The level crossing detection circuit is used to monitor the input signal in real time, compare the input signal amplitude with the preset voltage threshold, generate a trigger signal indicating the level crossing when the input signal crosses the voltage threshold, and output a digital code of the crossed level value, i.e., the first-level digital code;

[0010] The residual voltage capture circuit samples the input signal when enabled by the trigger signal, and generates a residual voltage according to the first-level digital code, wherein the residual voltage is the difference between the amplitude of the input signal at the end of sampling and the crossed level value;

[0011] A residual amplifier circuit, used for amplifying the residual voltage;

[0012] The sub-analog-to-digital conversion circuit is used to further quantize the amplified residual voltage and generate a second-level digital code through sampling and successive approximation operations.

[0013] Furthermore, the level crossing detection circuit is a double-ended differential structure. For either end structure, it includes a capacitive AC coupling input network, two continuous time comparators CMP1-CMP2, a shift register and a level crossing monitoring logic circuit, wherein:

[0014] The capacitive AC coupling input network includes an input capacitor and N feedback capacitors. The lower plate of the input capacitor is connected to the input signal, the upper plate of the input capacitor is connected to the upper plate of the feedback capacitor, the positive input terminal of CMP1 and the positive input terminal of CMP2, and the lower plate of the feedback capacitor is connected to the reference voltage V REFN or V REFP , the inverting input of CMP2 is grounded, V REFN is low level, V REFP is high level, N is the number of digits of the first level digital code (manually set);

[0015] The level crossing monitoring logic circuit is used to monitor the outputs of CMP1 and CMP2, and controls the inverting input terminal of CMP1 to be connected to the reference voltage V according to the output level of CMP2. L or V H When the output level of CMP1 changes, the level crossing monitoring logic circuit generates a trigger signal to indicate the occurrence of a level crossing. At this time, if the output level of CMP2 is 1, the shift register is controlled to shift to the left; if the output level of CMP2 is 0, the shift register is controlled to shift to the right; V H One LSB (Least Significant Bit) higher than the common mode voltage, V L One LSB lower than the common mode voltage;

[0016] The shift register is composed of N D flip-flops, and the output of these D flip-flops is the first-level digital code D corresponding to N bits. 1 ~D N , where D 1 ~D N / 2 The initial value is set to 0, and the initial values ​​of the remaining digital codes are set to 1; when the shift register shifts left, D N Fill 1, shift right D 1 Fill 0; D 1 ~D N Control N feedback capacitors separately. When D i When it is 0, the lower plate of the corresponding feedback capacitor is connected to V REFP When D i When it is 1, the lower plate of the corresponding feedback capacitor is connected to VREFN , D 1 ~D N That is, the digital code representing the level value to be crossed, i is a natural number and 1≤i≤N.

[0017] Furthermore, the residual voltage capture circuit is a double-ended differential structure. For either end structure, it is composed of a capacitor array and a control circuit. The number of capacitors in the capacitor array is the number of bits of the first-level digital code. In the detection stage, the control circuit makes the upper and lower plates of the capacitor array suspended. In the sampling stage, the control circuit connects the upper plate of the capacitor array to the common mode voltage and the lower plate to the input signal. In the pre-switching stage, the control circuit connects the upper plate of the capacitor array to the input signal and the lower plate to the common mode voltage. In the residual voltage generation stage, the control circuit connects the lower plate of each capacitor in the capacitor array to the reference voltage V REFN or V REFP , the upper plate of the capacitor array generates a residual voltage.

[0018] Furthermore, the control circuit controls the capacitors in the capacitor array according to the first-level digital code. When the i-th digital code is 0, the corresponding capacitor lower plate is connected to V REFP ; When the i-th digital code is 1, the corresponding capacitor lower plate is connected to V REFN , i is a natural number and 1≤i≤N, N is the number of bits of the first-level digital code.

[0019] Furthermore, the magnitude of the residual voltage is equal to V IN +Σ(D 1,i ×V REFP -V CM ), where V IN is the input signal, V CM is the common mode voltage, D 1,i is the i-th digital code of the first level.

[0020] Furthermore, the residual amplifier circuit includes a two-stage FIA ​​(Floating Inverter Amplifier), six switches S 1 ~S 6 And four capacitors C F1 , C F2 , C L1 , C L2 , where S 1 One end of the negative residual voltage, S 1 The other end of S 5 One end of C F1 One end of the FIA ​​is connected to the inverting input terminal, S 2 One end of the positive phase residual voltage, S 2 The other end of S 3 One end of CF2 One end of the FIA ​​is connected to the positive input terminal, S 5 The other end of the F1 The other end, S 6 One end of C L1 One end of the FIA ​​is connected to the positive phase output terminal, S 3 The other end of the F2 The other end, S 4 One end of C L2 One end of the FIA ​​is connected to the inverting output terminal, S 4 The other end of S 6 The other end, C L1 The other end and C L2 The other end of the pin is connected to the common mode voltage.

[0021] Furthermore, the FIA ​​includes 12 switches T 1 ~T 12 , four PMOS tubes M 1 ~M 4 , four NMOS tubes M 5 ~M 8 And three capacitors C RES1 ~C RES3 , where T 1 One end of the 2 One end is connected to the power supply voltage VDD, T 1 The other end of T 3 One end and C RES3 One end of T 3 The other end of T 2 The other end of T 4 One end and C RES1 One end of C RES3 The other end of T 5 One end and T 6 One end of T 5 The other end of the RES1 The other end of T 7 One end and T 8 One end of T 6 The other end of T 7 The other end of T 4 The other end of M 1 The source and M 2 The source of M 1 The gate and M 5 The gate of the FIA ​​is connected to the positive input terminal, M 2 The gate and M 6 The gate of the FIA ​​is connected to the inverting input terminal, M 1The drain and M 5 The drain, M 3 The gate and M 7 The gate of M 2 The drain and M 6 The drain, M 4 The gate and M 8 The gate of M 5 The source and M 6 The source and T 8 The other end is connected to T 9 One end is connected to the power supply voltage VDD, T 9 The other end of T 10 One end and C RES2 One end of C RES2 The other end of T 11 One end and T 12 One end of T 11 The other end of T 10 The other end of M 3 The source and M 4 The source of M 3 The drain and M 7 The drain of M is connected to the positive output terminal of FIA. 4 The drain and M 8 The drain of M is connected to the inverting output terminal of FIA. 7 The source and M 8 The source and T 12 The other end is connected to T 4 , T 8 , T 10 and T 12 The switching clock is Φ amp1 , T 3 and T 5 The switching clock is Φ amp2 , T 2 , T 7 , T 9 and T 11 The switching clock is Φ amp1 The inverted clock, T 1 and T 6 The switching clock is Φ amp2 The inverted clock.

[0022] Furthermore, the switching clock Φ amp2 The falling edge of Φ amp1 Synchronous, and Φ amp2 The pulse width is Φ amp1 1 / 2 of.

[0023] Furthermore, the sub-analog-to-digital conversion circuit adopts an M-bit successive approximation analog-to-digital converter, where M is the number of bits of the second-level digital code (artificially set).

[0024] Furthermore, the final digital output result of the level-spanning pipeline analog-to-digital converter is:

[0025]

[0026] Where: D out D is the final digital output result of the level-crossing pipeline analog-to-digital converter. 1,i is the i-th digital code of the first level, D 2,j is the jth digital code of the second level, N is the number of bits of the first level digital code, M is the number of bits of the second level digital code, and G is the amplification factor of the residual amplifier circuit (i.e., the total capacitance of the capacitor array at one end in the residual voltage capture circuit divided by C F1 capacitance value).

[0027] The present invention monitors the input signal through a level cross-domain detection circuit. When the input signal crosses a preset level, a cross-domain signal and a first-level digital code are generated. At the same time, a residual voltage capture circuit starts working, and the residual voltage is accurately captured by using a sampling operation triggered by the cross-domain signal and direct feedback of the first-level digital code. The captured residual voltage is amplified by a residual amplifier circuit, and then further quantized by a second-level sub-analog-to-digital conversion circuit to generate a second-level digital code.

[0028] The level-spanning pipelined analog-to-digital converter of the present invention converts the inevitable signal-related errors in the traditional level-spanning analog-to-digital converter into smaller non-signal-related errors by introducing trigger sampling and further residual quantization, and achieves a maximum SNDR of 72.5dB when including the third harmonic under a 1V power supply voltage and a 20kHz bandwidth, which effectively solves the challenge of high-precision design of the level-spanning analog-to-digital converter; under full-band input, the power consumption of the present invention is 1.2μW~11.8μW, retaining the event-driven characteristics. Therefore, the level-spanning pipelined analog-to-digital converter of the present invention can provide a low-power analog-to-digital converter for wearable medical devices, increase battery life, and ensure the accuracy of biopotential signal acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a system structure block diagram of the level-spanning pipeline analog-to-digital converter of the present invention.

[0030] Figure 2 Schematic diagram of the structure of the level crossing detection circuit in an embodiment of the present invention.

[0031] Figure 3Schematic diagram of capacitor array connection at different stages of the residual voltage capture circuit in an embodiment of the present invention.

[0032] Figure 4 Schematic diagram of the structure of a residual amplifier circuit based on switched capacitors in an embodiment of the present invention.

[0033] Figure 5 Schematic diagram of the circuit structure of a floating inverting amplifier in an embodiment of the present invention.

[0034] Figure 6 4 is a timing diagram of the analog-to-digital converter in an embodiment of the present invention.

[0035] Figure 7 This is an output spectrum diagram of the analog-to-digital converter when the input frequency is 6.6 kHz in an embodiment of the present invention.

[0036] Figure 8 FIG. 4 is a graph showing the relationship between the power consumption of the analog-to-digital converter and different input frequencies in an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0038] like Figure 1 As shown, the level-spanning pipeline analog-to-digital converter of the present invention includes a level-spanning detection circuit, a residual voltage capture circuit, a residual amplification circuit, and a sub-analog-to-digital conversion circuit, wherein:

[0039] The level crossing detection circuit is used to monitor the input signal in real time, compare the input signal amplitude with the predefined voltage value in real time, and generate a trigger signal EN indicating the level crossing (this signal is used to generate the time data Tout used in the interpolation processing) when the input signal amplitude crosses the predefined voltage, and output the digital code D of the crossed level value. 1 The structure of the level crossing detection circuit in this embodiment is as follows: Figure 2 As shown (for simplicity, it is shown in single-ended form only, but it is actually a double-ended differential structure), it includes a capacitive AC coupling input network, continuous time comparators CMP1 and CMP2, a shift register, and a level crossing detection logic circuit.

[0040] The capacitive AC coupling input network consists of an input capacitor C IN and 16 feedback capacitors C u Composition, input capacitor C IN The lower plate is connected to the input signal, and the upper plate is connected to C IN / (C IN +16C u) produces a coupling voltage that tracks the input signal. The lower plate of the feedback capacitor is connected to the digital code D output by the shift register. 1,1 ~D 1,16 With reference voltage V REFN or V REFP Connected to the upper board with C u / (C IN +16C u ) coefficient to generate feedback voltage, and the upper plates of the input capacitor and feedback capacitor are connected to the positive terminal of the continuous time comparator input.

[0041] The shift register consists of 16 D flip-flops corresponding to D 1,1 ~D 1,16 , D 1,1 ~D 1,8 The initial value is set to 0, D 1,9 ~D 1,16 The initial value is set to 1. When the register is shifted left, D 1,16 When the register is shifted right, D 1,1 Fill 0, D 1,1 ~D 1,16 Control 16 feedback capacitors respectively. 1,i When the value is 0, the lower plate of the corresponding feedback capacitor is connected to V REFP , when D 1,i When the value is 1, the corresponding feedback capacitor lower plate is connected to V REFN , D 1,1 ~D 1,16 A digital code representing the level value that was crossed.

[0042] The level crossing monitoring logic circuit adopts fixed window detection logic and uses two continuous time comparators CMP1 and CMP2 to monitor the coupling voltage difference value V at the plate of the input network. o-diff , CMP2 compares V o-diff With GND, an UP / DN signal is generated. This signal is used to determine whether the level crossing occurs upward or downward. CMP1 compares V o-diff With V H or V L , V H Ratio common mode voltage V CM One LSB higher, V L Ratio common mode voltage V CM One LSB lower, LSB is the preset voltage window size, which means that the level crossing will be detected every time the coupled input signal changes by one LSB. In this implementation method, the LSB size is V REFP / 16. When the CMP1 output changes, it indicates that a level crossing occurs. The level crossing monitoring logic circuit generates a trigger signal EN indicating that a level crossing occurs. This signal triggers the switching of the lower plate of the feedback capacitor on the one hand, and wakes up the residual voltage capture circuit to start working on the other hand. The control logic circuit is composed of switches. The code word from the shift register determines the switch control feedback capacitor lower plate and V REFP Still V REFN When the i-th digital code is 0, the corresponding capacitor lower plate is connected to V REFP ; When the i-th digital code is 1, the corresponding capacitor lower plate is connected to V REFN At this time, the UP / DN signal determines the shift direction of the shift register. When UP / DN is 1, the shift register shifts to the left, making V o-diff Reduce LSB; otherwise, shift to the right to make V o-diff Increasing LSB, this detection logic makes the coupled voltage V o-diff Always keep between -LSB and +LSB.

[0043] After the level crossing is detected, the trigger signal EN controls the residual voltage capture circuit to start working. In this embodiment, the residual voltage capture circuit is composed of a group of capacitor arrays C 1 and control circuit to achieve that the capacitor array C 1 Similar to the capacitor array in the level crossing detection circuit, the 16 capacitors C 1,1 ~C 1,16 The weighted composition of the thermometer code facilitates direct use of the digital code D output by the level crossing detection circuit 1 Generate feedback voltage. In the process of residual capture, the capacitor connection relationship is as follows Figure 3 As shown, the process is as follows:

[0044] (1) Detection stage: When no level crossing is detected, only the continuous time comparator continues to work, and the capacitor array C 1 Both ends are floating and not connected to any power supply. Figure 3 (a) in .

[0045] (2) Sampling stage: After the level crossing is detected, the trigger signal arrives, the residual capture circuit samples the input signal, and the capacitor array C 1 The upper plate and the common mode voltage V CM connected, the lower plate is connected to the input signal V IN Connected, corresponding Figure 3 (b) in .

[0046] (3) Pre-switching stage: After sampling, the capacitor array C 1 Upper plate and V CM Disconnect the lower plate from VCM connected, the upper plate voltage V DAC V IN ,correspond Figure 3 (c) in .

[0047] (4) Residual voltage generation stage: Feedback is generated based on the digital code of the crossed level value output by the level crossing detection circuit. 1,i When the value is 0, the corresponding feedback capacitor C 1,i The lower plate is connected to V REFP , when D 1,i When the value is 1, the corresponding feedback capacitor lower plate is connected to V REFN , at this time the capacitor array C 1 Upper plate voltage V DAC V IN +Σ(D 1,i ×V REFP -V CM ), this voltage is the captured residual voltage, corresponding to Figure 3 (d) in.

[0048] The level crossing detection circuit and the residual voltage capture circuit together form the first stage of the pipeline.

[0049] After the residual voltage is captured, the Figure 4 The residual amplifier circuit composed of the switch capacitor shown in the figure amplifies the residual voltage, and the operational amplifier used is as follows Figure 5 The two-stage floating inverting amplifier FIA shown in the figure has a DC gain of 75dB. The first stage of the two-stage FIA ​​consists of two NMOS transistors M 5 、M 6 , two PMOS tubes M 1 、M 2 and two capacitors C RES1 , C RES3 The second stage consists of two NMOS tubes M 7 、M 8 , two PMOS tubes M 3 、M 4 and a capacitor C RES2 Composition, M 1 and M 5 , M 2 and M 6 , M 3 and M 7 , M 4 and M 8 They are all connected in an inverter connection. Unlike the traditional inverter where the source of the PMOS tube is connected to the power supply VDD and the source of the NMOS tube is grounded, the FIA ​​uses a capacitor pre-charged to VDD to power the MOS tube in the inverter connection; the 2-level FIA uses two power supply capacitors CRES1 and C RES2 In addition, a third power supply capacitor C is introduced RES3 , when the whole amplification process is halfway through, C RES3 With C RES1 Connected in parallel to power the first-stage MOS tube, the newly introduced capacitor C RES3 The noise of the amplifier can be greatly reduced. 4 , T 8 , T 10 and T 12 The switching clock is Φ amp1 , T 3 and T 5 The switching clock is Φ amp2 , T 2 , T 7 , T 9 and T 11 The switching clock is Φ amp1 The inverted clock, T 1 and T 6 The switching clock is Φ amp2 The inverted clock.

[0050] The amplified voltage is fed to the second stage of the pipeline for further quantization, and the process is as follows:

[0051] (1) Reset phase

[0052] Before the residual voltage stabilizes, switch S 1 , S 2 Disconnect, C 1 is the capacitor array of the residual capture circuit, in which case C 1 is being sampled and fed back to obtain the residual voltage, S 3 ~S 6 Closed, FIA input and output reset to V CM At this time, FIA C RES1 ~C RES3 Charged to VDD, the source of the PMOS tube connected with the inverter is disconnected, and the clock is in Φ amp1 or Φ amp2 The FIA ​​does not work if the clock is inverted.

[0053] (2) Amplification stage

[0054] Amplification stage 1: After the residual voltage stabilizes, switch S 1 , S 2 Close, C 1 The upper plate of the capacitor array is connected to the input of the FIA, and the switch S 3 ~S 6 Disconnect, and start closed-loop amplification of the residual voltage; in this embodiment, CF1 ~C F2 is set to C 1 The unit capacitance value of is the same, so the closed-loop gain G is 16. At this time, C RES1 , C RES2 The upper plate is disconnected from the power supply VDD and switched to the source of the PMOS tube. The lower plate is disconnected from GND and switched to the source of the NMOS tube. FIA enters the amplification phase. amp1 It is high level during this phase.

[0055] Amplification stage 2: Halfway through the amplification, C RES3 Disconnected from the power supply VDD and GND, the upper and lower plates are connected to the source of the PMOS tube and the NMOS tube respectively, and the amplifier enters the amplification stage 2. At this time, Φ amp2 becomes a high level, the first stage uses a larger current to produce a smaller equivalent resistance to reduce the noise at the output node.

[0056] Then the second-stage analog-to-digital conversion circuit starts working, sampling the output voltage of the amplifier and using successive approximation to quantize the residual voltage more finely to generate the second-stage digital code D 2 In this embodiment, the second-stage analog-to-digital conversion circuit adopts an 8-bit successive approximation analog-to-digital converter (SAR ADC).

[0057] Figure 6 is the timing of the analog-to-digital converter in this embodiment, ZOOM IN represents close-range zoom, where Φ 1S is the sampling clock of the capacitor array in the residual voltage capture circuit, Φ C1 is the capacitor switching clock in the residual voltage capture circuit, Φ amp is the amplification clock of the residual amplifier circuit, Φ S2 is the sampling clock of the capacitor array in the second-stage analog-to-digital conversion circuit, Φ C2 It is the clock for the successive approximation operation of the sub-analog-to-digital conversion circuit. When the input signal does not cross the preset level, the continuous time comparator continuously monitors the input signal, other module circuits do not work at this time, and the digital output remains unchanged. When the level crosses, the level cross detection circuit generates a time signal EN and a digital code D representing the crossed level value. 1 At the same time, the residual voltage capture circuit is awakened for sampling. After the sampling is completed, the digital code D of the level crossing detection circuit is used 1 The capacitor array is switched to generate a residual, and then the sampling and residual amplifier circuits of the second-stage sub-analog-to-digital conversion circuit start working respectively. The amplified residual voltage is sampled in the sub-analog-to-digital conversion circuit, and then further quantized by the sub-analog-to-digital conversion circuit to obtain the second-stage output codeword D 2 .

[0058] The output 24-digit code D 1,1 ~D 1,16 is the first-level output and is the thermometer code weight, D 2,1 ~D 2,8 is the output of the second stage, which is a binary weight. Due to the existence of the residual amplifier, the final digital output is:

[0059]

[0060] like Figure 7 As shown, in this embodiment, when the analog-to-digital converter is under a power supply voltage of 1V and a bandwidth of 20kHz and the input signal frequency Fin is 6.6kHz, the signal-to-noise distortion ratio SNDR is 72.5dB, which proves the effectiveness of the level-skipping pipeline analog-to-digital converter of the present invention in enhancing the SNDR and provides an effective solution for achieving high resolution of the level-skipping analog-to-digital converter.

[0061] The relationship between the power consumption and input frequency of the analog-to-digital converter in this embodiment is as follows: Figure 8 As shown, under the full-band input, the power consumption varies from 1.2 μW to 11.8 μW, which shows the full dynamic characteristics of the level-crossing analog-to-digital converter of the present invention, which still maintains the event-triggered driving mode.

[0062] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments, and improvements and modifications made by those skilled in the art based on the disclosure of the present invention should be within the scope of protection of the present invention.

Claims

1. A level-skipping pipelined analog-to-digital converter with triggered sampling and residual quantization, characterized in that: include: The level crossing detection circuit is used to monitor the input signal in real time, compare the input signal amplitude with the preset voltage threshold, generate a trigger signal indicating the level crossing when the input signal crosses the voltage threshold, and output a digital code of the crossed level value, i.e., the first-level digital code; The residual voltage capture circuit samples the input signal when enabled by the trigger signal, and generates a residual voltage according to the first-level digital code, wherein the residual voltage is the difference between the amplitude of the input signal at the end of sampling and the crossed level value; A residual amplifier circuit, used for amplifying the residual voltage; A sub-analog-to-digital conversion circuit is used to further quantize the amplified residual voltage and generate a second-level digital code through sampling and successive approximation operations; The level crossing detection circuit is a double-ended differential structure. For either end structure, it includes a capacitive AC coupling input network, two continuous time comparators CMP1-CMP2, a shift register and a level crossing monitoring logic circuit, wherein: The capacitive AC coupling input network includes an input capacitor and N feedback capacitors. The lower plate of the input capacitor is connected to the input signal, the upper plate of the input capacitor is connected to the upper plate of the feedback capacitor, the positive input terminal of CMP1 and the positive input terminal of CMP2, and the lower plate of the feedback capacitor is connected to the reference voltage V REFN or V REFP , the inverting input of CMP2 is grounded, V REFN is low level, V REFP is high level, N is the number of bits of the first level digital code; The level crossing monitoring logic circuit is used to monitor the outputs of CMP1 and CMP2, and controls the inverting input terminal of CMP1 to be connected to the reference voltage V according to the output level of CMP2. L or V H When the output level of CMP1 changes, the level crossing monitoring logic circuit generates a trigger signal to indicate the occurrence of a level crossing. At this time, if the output level of CMP2 is 1, the shift register is controlled to shift to the left; if the output level of CMP2 is 0, the shift register is controlled to shift to the right; V H One LSB higher than the common-mode voltage, V L One LSB lower than the common mode voltage; The shift register is composed of N D flip-flops, and the output of these D flip-flops corresponds to the first-level digital code D1~D N , where D1~D N / 2 The initial value is set to 0, and the initial values ​​of the remaining digital codes are set to 1; when the shift register shifts left, D N Fill 1, D1 fills 0 when shifting right; D1~D N Control N feedback capacitors separately. When D i When it is 0, the lower plate of the corresponding feedback capacitor is connected to V REFP When D i When it is 1, the lower plate of the corresponding feedback capacitor is connected to V REFN , D1~D N That is, the digital code representing the level value to be crossed, i is a natural number and 1≤i≤N.

2. A level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 1, characterized in that: The residual voltage capture circuit is a double-terminal differential structure. For either end structure, it is composed of a capacitor array and a control circuit. The number of capacitors in the capacitor array is the number of bits of the first-level digital code. During the detection phase, the control circuit causes the upper and lower plates of the capacitor array to be suspended; In the sampling stage, the control circuit connects the upper plate of the capacitor array to the common mode voltage and the lower plate to the input signal; in the pre-switching stage, the control circuit connects the upper plate of the capacitor array to the input signal and the lower plate to the common mode voltage; in the residual voltage generation stage, the control circuit connects the lower plate of each capacitor in the capacitor array to the reference voltage V REFN or V REFP , the upper plate of the capacitor array generates a residual voltage.

3. A level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 2, characterized in that: The control circuit controls the capacitors in the capacitor array according to the first-level digital code. When the i-th digital code is 0, the corresponding capacitor lower plate is connected to V REFP ; When the i-th digital code is 1, the corresponding capacitor lower plate is connected to V REFN , i is a natural number and 1≤i≤N, N is the number of bits of the first-level digital code.

4. The level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 2, characterized in that: The magnitude of the residual voltage is equal to V IN +Σ(D 1,i ×V REFP -V CM ), where V IN is the input signal, V CM is the common mode voltage, D 1,i is the i-th digital code of the first level, i is a natural number and 1≤i≤N, N is the number of bits of the first level digital code.

5. The level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 1, characterized in that: The residual amplifier circuit includes two-stage FIA, six switches S1-S6 and four capacitors C F1 , C F2 , C L1 , C L2 , where one end of S1 is connected to the negative residual voltage, and the other end of S1 is connected to one end of S5 and C F1 One end of S2 is connected to the inverting input of FIA, one end of S2 is connected to the positive residual voltage, and the other end of S2 is connected to one end of S3 and C F2 One end of S5 is connected to the positive input of FIA, and the other end of S5 is connected to C F1 The other end of S6, one end of C L1 One end of S3 is connected to the positive phase output of FIA, and the other end of S3 is connected to C F2 The other end of S4, one end of C L2 One end of S4 is connected to the inverting output end of FIA, and the other end of S6 is connected to the other end of C L1 The other end and C L2 The other end is connected to the common mode voltage.

6. A level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 5, characterized in that: The FIA ​​includes 12 switches T1~T 12 , four PMOS tubes M1~M4, four NMOS tubes M5~M8 and three capacitors C RES1 ~C RES3 One end of T1 is connected to one end of T2 and connected to the power supply voltage VDD, and the other end of T1 is connected to one end of T3 and C RES3 The other end of T3 is connected to the other end of T2, one end of T4 and C RES1 One end of C RES3 The other end of T5 is connected to one end of T6, and the other end of T5 is connected to C RES1 The other end of T4 is connected to the source of M1 and the source of M2, the gate of M1 is connected to the gate of M5 and serves as the positive input terminal of FIA, the gate of M2 is connected to the gate of M6 and serves as the negative input terminal of FIA, the drain of M1 is connected to the drain of M5, the gate of M3 and the gate of M7, the drain of M2 is connected to the drain of M6, the gate of M4 and the gate of M8, the source of M5 is connected to the source of M6 and the other end of T8, one end of T9 is connected to the power supply voltage VDD, and the other end of T9 is connected to T 10 One end and C RES2 One end of C RES2 The other end of T 11 One end and T 12 One end of T 11 The other end of T 10 The other end is connected to the source of M3 and the source of M4, the drain of M3 is connected to the drain of M7 and serves as the positive output of FIA, the drain of M4 is connected to the drain of M8 and serves as the negative output of FIA, the source of M7 is connected to the source of M8 and T 12 The other end is connected to T4, T8, T 10 and T 12 The switching clock is Φ amp1 , the switching clock of T3 and T5 is Φ amp2 , T2, T7, T9 and T 11 The switching clock is Φ amp1 The inverted clock of T1 and T6 is Φ amp2 The inverted clock.

7. A level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 6, characterized in that: The switching clock Φ amp2 The falling edge of Φ amp1 Synchronous, and Φ amp2 The pulse width is Φ amp1 1 / 2 of.

8. The level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 1, characterized in that: The sub-analog-to-digital conversion circuit adopts an M-bit successive approximation analog-to-digital converter, where M is the number of bits of the second-level digital code.

9. The level-skipping pipeline analog-to-digital converter with triggered sampling and residual quantization according to claim 1, characterized in that: The final digital output result of the level-crossing pipeline analog-to-digital converter is: ; Where: D out D is the final digital output result of the level-crossing pipeline analog-to-digital converter. 1,i is the i-th digital code of the first level, D 2,j is the j-th digital code of the second stage, N is the number of bits of the first stage digital code, M is the number of bits of the second stage digital code, and G is the amplification factor of the residual amplifier circuit.

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