Analog-to-digital converter with high bridge capacitance matching and analog-to-digital converter circuit

Abstract

The application relates to the technical field of integrated circuits, in particular to an analog-digital converter with high bridge capacitance matching degree and an analog-digital converter circuit, wherein the analog-digital converter circuit comprises a high-bit capacitance array, a low-bit capacitance array, a bridge unit, a comparison and latching unit and a digital unit; the high-bit capacitance array is used for quantizing high-bit data in the analog-digital converter; the low-bit capacitance array is used for quantizing low-bit data in the analog-digital converter; the bridge unit is used for bridging between the high-bit capacitance array and the low-bit capacitance array; the comparison and latching unit is used for comparing and latching the voltages quantized by the high-bit capacitance array and the low-bit capacitance array with an external common-mode voltage; and the digital unit is used for converting an analog signal output by the comparison and latching unit into a digital signal through successive approximation logic. According to the scheme, the ratio between the bridge capacitance and the unit capacitance can be an integer multiple, so that the matching degree of the bridge capacitance is improved, and more accurate charge redistribution is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to an analog-to-digital converter with high bridge capacitor matching degree and an analog-to-digital converter circuit. BACKGROUND

[0002] Analog-to-digital converters (ADCs) are indispensable components in modern electronic systems, responsible for converting continuous analog signals into discrete digital form. This process is crucial for data acquisition, control systems, and communication technologies, making ADCs a key interface between analog and digital circuits. Among the many types of ADCs, successive approximation register (SAR) ADCs are widely favored for their simple circuit design and low power consumption, finding extensive applications in communication, medical, and sensor fields.

[0003] The core working principle of SAR ADCs is to gradually approximate the value of the input analog signal by comparing it with internally generated reference voltages, and finally output the corresponding digital code. To achieve this process, SAR ADCs rely on a capacitor array called DAC (digital-to-analog converter), which is responsible for generating the required reference voltages. However, with the continuous advancement of integrated circuit technology, higher requirements are placed on the size, speed, and power consumption of ADCs.

[0004] To address these issues, modern SAR ADC designs typically employ a segmented capacitor array, which divides the capacitor array into two parts: the MSB (most significant bit) capacitor array and the LSB (least significant bit) capacitor array. These two parts are connected through a bridge capacitor, aiming to reduce the chip area occupied by the overall DAC capacitor array. The advantage of this structure lies in its ability to significantly reduce the physical size of the ADC while maintaining high conversion speed and low power consumption.

[0005] However, the traditional SAR ADC bridge solution has a major problem: the ratio between the bridge capacitor and the unit capacitor is often not an integer multiple. This non-integer multiple relationship leads to a loss of conversion accuracy, forcing designers to adopt additional trimming schemes to compensate for this error. Such trimming not only takes time and effort, but the trimming results are also difficult to guarantee. Therefore, there is an urgent need to provide an analog-to-digital converter circuit with high bridge capacitor matching degree, which can make the ratio between the bridge capacitor and the unit capacitor an integer multiple, thereby improving the matching degree of the bridge capacitor and achieving more accurate charge redistribution. SUMMARY

[0006] The present application provides an analog-to-digital converter with high bridge capacitor matching degree and an analog-to-digital converter circuit, which can make the ratio between the bridge capacitor and the unit capacitor an integer multiple, thereby improving the matching degree of the bridge capacitor and achieving more accurate charge redistribution.

[0007] The application provides a basic scheme I:

[0008] An analog-to-digital converter circuit with high bridge capacitance matching degree, comprising a high-bit capacitance array, a low-bit capacitance array, a bridge unit, a comparison and latching unit and a digital unit;

[0009] The input ports INO, IN1, IN2 and IN3 in the high-bit capacitance array are connected with an external common-mode voltage port Vcom, a reference ground port GND, a reference voltage port VREF and an analog input signal port Vin respectively, and the output port OUT0 in the high-bit capacitance array is connected with the output port OUT0 in the bridge unit and the input port IP in the comparison and latching unit;

[0010] The input ports IN1 and IN2 in the low-bit capacitance array are connected with the reference ground port GND and the reference voltage port VREF respectively, and the output port OUT0 in the low-bit capacitance array is connected with the input port IN0 in the bridge unit;

[0011] The bridge unit comprises a bridge capacitance C6, a bridge capacitance C7, a switch SW1 and a common-source operational amplifier A0; the input end of the common-source operational amplifier A0 is connected with the input port IN0 in the bridge unit, and the output end is connected with one end of the bridge capacitance C7; the other end of the bridge capacitance C7 is connected with the output port OUT0 in the bridge unit, and the output port OUT0 in the bridge unit is connected with the input port IP in the comparison and latching unit; the bridge capacitance C6 and the switch SW1 are connected with the common-source operational amplifier A0 in parallel;

[0012] The input port IN in the comparison and latching unit is connected with the external common-mode voltage port Vcom; the output port Vout in the comparison and latching unit is connected with the input port IN0 in the digital unit; and the input port IN0 in the comparison and latching unit is connected with the output port OUT0 in the digital unit;

[0013] The digital unit is used for converting the analog signal output by the comparison and latching unit into a digital signal through successive approximation logic.

[0014] Further, the high-bit capacitance array comprises one high-bit redundant capacitance with a unit capacitance value and a plurality of high-bit sampling capacitances arranged in a weighted capacitance array in a manner of increasing according to binary weights based on the unit capacitance;

[0015] The upper plates of the high-redundancy capacitor and the high-sampling capacitors are connected and connected with the external common-mode voltage port Vcom through the switch SWT; the lower plates of the high-redundancy capacitor and the high-sampling capacitors are connected with the analog input signal port Vin through a single-pole single-throw switch respectively; the lower plate of the high-redundancy capacitor is further connected with the reference ground port GND through a normally closed switch; the lower plates of the high-sampling capacitors are further connected with the reference voltage port VREF through a high-voltage on-off switch respectively, and are further connected with the reference ground port GND through a high-reference ground on-off switch respectively.

[0016] Further, the low-capacitance array includes two low-redundancy capacitors with a unit capacitance value and a plurality of low-sampling capacitors arranged in a manner of increasing binary weight based on the unit capacitance to form a weighted capacitance array;

[0017] The upper plates of the low-redundancy capacitor and the low-sampling capacitors are connected and connected with the input port IN0 in the bridge unit; the lower plates of the low-redundancy capacitor and the low-sampling capacitors are connected with the reference voltage port VREF through a low-voltage on-off switch respectively, and are further connected with the reference voltage port VREF through a low-reference ground on-off switch respectively.

[0018] Further, the digital unit is connected with the high-capacitance array and the low-capacitance array, and controls the conduction and non-conduction of the single-pole single-throw switch, the normally closed switch, the high-voltage on-off switch, the high-reference ground on-off switch, the switch SWT in the high-capacitance array, and the low-voltage on-off switch and the low-reference ground on-off switch in the low-capacitance array through the multi-bit bus output.

[0019] Further, the common-source operational amplifier A0 includes a current source, a PMOS tube PM0, a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an NMOS tube NM0, an NMOS tube NM1, and an NMOS tube NM2.

[0020] The sources of the PMOS tube PM0, the PMOS tube PM2, and the PMOS tube PM4 are connected; the gates of the PMOS tube PM0, the PMOS tube PM2, and the PMOS tube PM4 are connected, and the drain is connected with the source of the PMOS tube PM1; the drain of the PMOS tube PM2 is connected with the source of the PMOS tube PM3; the gate of the PMOS tube PM1 is connected with the gate of the PMOS tube PM3 and the gate of the PMOS tube PM5; the drain of the PMOS tube PM4 is connected with the source of the PMOS tube PM5;

[0021] The drain of the PMOS tube PM1 is connected with a current source; the drain of the PMOS tube PM3 is connected with the drain of the NMOS tube NM0; the drain of the PMOS tube PM5 is connected with the drain of the NMOS tube NM1 and the output terminal of the common-source operational amplifier A0; the gate of the NMOS tube NM0 is connected with the gate of the NMOS tube NM1; the source of the NMOS tube NM1 is connected with the drain of the NMOS tube NM2; the gate of the NMOS tube NM2 is connected with the input terminal of the common-source operational amplifier A0; the current source, the source of the NMOS tube NM0 and the source of the NMOS tube NM2 are connected with each other and grounded.

[0022] Further, the input tube of the common-source operational amplifier A0 works in a sub-threshold region.

[0023] Further, the comparison and latching unit comprises a first-stage comparator, a second-stage comparator, a third-stage comparator, a latch, an SR flip-flop, a switch SCOO, a switch SCO1, a switch SCO2, a switch SCO3, a switch SCO4, a switch SCO5 and a switch SCO6.

[0024] The input port +IP in the first-stage comparator is connected with the input port IP of the comparison and latching unit, the input port -IN is connected with the input port IN of the comparison and latching unit, and the input port +IP and the input port -IN are connected with each other through the switch SCOO; the output port +OUTP in the first-stage comparator is connected with the input port +IP in the second-stage comparator through a calibration capacitor CO1, and the calibration capacitor CO1 and the input port +IP in the second-stage comparator are connected with each other through the switch SCO1; the output port -OUTN in the first-stage comparator is connected with the input port -IN in the second-stage comparator through a calibration capacitor CO2, and the calibration capacitor CO2 and the input port -IN in the second-stage comparator are connected with each other through the switch SCO2.

[0025] The output port +OUTP in the second-stage comparator is connected with the input port +IP in the third-stage comparator through a calibration capacitor CO3, and the calibration capacitor CO3 and the input port +IP in the third-stage comparator are connected with each other through the switch SCO3; the output port -OUTN in the second-stage comparator is connected with the input port -IN in the third-stage comparator through a calibration capacitor CO4, and the calibration capacitor CO4 and the input port -IN in the third-stage comparator are connected with each other through the switch SCO4.

[0026] The output port +OUTP in the third-stage comparator is connected with the input port +IP in the latch through a calibration capacitor CO5, the calibration capacitor CO5 and the input port +IP in the latch are connected with a switch SCO5; the output port -OUTN in the third-stage comparator is connected with the input port -IN in the latch through a calibration capacitor CO6, the calibration capacitor CO6 and the input port -IN in the latch are connected with a switch SCO6;

[0027] The other end of the switch SCO1, the switch SCO2, the switch SCO3, the switch SCO4, the switch SCO5 and the switch SCO6 is connected with an external common-mode voltage port Vcom;

[0028] The comparator is connected with the input port INO in the comparison latch unit, and is also connected with the input end of the SR flip-flop; the output end of the SR flip-flop is connected with the output port Vout in the comparison latch unit.

[0029] Further, the SR flip-flop comprises an NAND gate X13 and an NAND gate X14;

[0030] One input of the NAND gate X14 is connected with the output port +OUTP in the latch, and the other input is connected with the output of the NAND gate X13; one input of the NAND gate 13 is connected with the output port -OUTN in the latch, and the other input is connected with the output of the NAND gate X14; the output of the NAND gate 13 is also connected with the output port Vout in the comparison latch unit.

[0031] The application provides a basic scheme two:

[0032] Analog-to-digital converter with high bridge capacitance matching degree, which adopts the above-mentioned analog-to-digital converter circuit with high bridge capacitance matching degree.

[0033] The principle and advantages of the application are:

[0034] 1. A common-source operational amplifier working in sub-threshold is connected in the bridge unit between the high-bit capacitor array and the low-bit capacitor array. Firstly, sub-threshold operation enables the input tube of the common-source operational amplifier to work at a very low current level, which is conducive to reducing power consumption while maintaining high gain. Secondly, the high gain characteristic of the common-source operational amplifier can ensure that the input port of the common-source operational amplifier is approximately constant in potential when each switch in the low-bit capacitor array is on, so that the ratio of the bridge capacitance of the bridge unit between the high-bit capacitor array and the low-bit capacitor array to the unit capacitance is an integer multiple, thereby improving the matching degree of the bridge capacitance and realizing more accurate charge redistribution.

[0035] 2. In the common-source op-amp A0, PMOS transistors PM0, PM1, PM2, and PM3 form a current mirror, and PMOS transistors PM0, PM1, PM4, and PM5 form another current mirror. Assuming the current source provides a reference current Ibisa, the two current mirrors provide bias currents of Ibisa and 10 times Ibisa to NMOS transistors NM0 and NM2, respectively. NMOS transistor NM2 acts as a diode load, providing a bias voltage to NMOS transistor NM1. When the input and output terminals of the common-source op-amp are shorted, the input and output voltages are equal. By adjusting the dimensions of NMOS transistor NM2, its threshold voltage can be made equal to the input and output voltages of the common-source op-amp. In this case, NMOS transistor NM2 operates in the subthreshold region, and the overall gain of the common-source op-amp A0 can reach over 58dB. When the input and output terminals of the common-source op-amp are disconnected, the input and output terminals will remain unchanged due to the combined effect of the high gain of the common-source op-amp A0 and the bridging capacitor C6 inside the bridging unit.

[0036] 3. The digital unit provides successive approximation logic for the high-order capacitor array and the low-order capacitor array. It converts the analog signal output by the comparison latch unit into a digital signal through the successive approximation logic, and then controls the conduction and cutoff of each single-pole single-throw switch, each normally closed switch, each high-order voltage on / off switch, each high-order reference ground on / off switch, and switch SWT in the high-order capacitor array, as well as each low-order voltage on / off switch and each low-order reference ground on / off switch in the low-order capacitor array, to achieve the purpose of analog-to-digital conversion. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the overall circuit structure of an analog-to-digital converter circuit embodiment with high bridging capacitor matching degree according to the present invention.

[0038] Figure 2 This is a schematic diagram of the circuit structure of a common-source operational amplifier in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention.

[0039] Figure 3 This is a schematic diagram of the circuit structure of the comparison latch unit in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention.

[0040] Figure 4 This is a schematic diagram of the circuit structure of the first-stage comparator in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention.

[0041] Figure 5 This is a schematic diagram of the circuit structure of the second-stage comparator in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention.

[0042] Figure 6 This is a schematic diagram of the circuit structure of the latch in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention.

[0043] Figure 7 This is a schematic diagram of the NAND gate circuit structure in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention.

[0044] Figure 8 This is a schematic diagram of the circuit structure of each switch in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention.

[0045] Figure 9 This is a schematic diagram of the digital unit structure in an embodiment of an analog-to-digital converter circuit with high bridging capacitor matching degree according to the present invention. Detailed Implementation

[0046] The following detailed description illustrates the specific implementation method:

[0047] Example 1:

[0048] Example 1 is basically as shown in the appendix. Figure 1 As shown:

[0049] An analog-to-digital converter circuit with high bridging capacitor matching, such as... Figure 1 As shown, it includes a high-order capacitor array, a low-order capacitor array, a bridging unit, a comparison latch unit, and a digital unit.

[0050] The high-order capacitor array is used to quantize the high-order data in the analog-to-digital converter. For example... Figure 1 As shown, the input ports INO, IN1, IN2, and IN3 in the high-level capacitor array are connected to the external common-mode voltage port Vcom, the reference ground port GND, the reference voltage port VREF, and the analog input signal port Vin, respectively. The output port OUT0 in the high-level capacitor array is connected to both the output port OUT0 in the bridging unit and the input port IP in the comparator latch unit. The analog input signal port Vin has a voltage input range of 0V to VREF.

[0051] Specifically, the sampling method of the high-order capacitor array is lower plate sampling, including a high-order redundant capacitor CO0 with a unit capacitance value and several high-order sampling capacitors (corresponding to the high M-bit data conversion capacitors of the digital-to-analog converter) arranged in an increasing binary weight manner based on the unit capacitance. In this embodiment, there are M high-order sampling capacitors, namely CO1, CO2, CO3...CO M-1 CO M The capacitance value of the high-order redundant capacitor CO0 is C; the capacitance value of the high-order sampling capacitor CO1 is 2. 0C. The capacitance value of the high sampling capacitor CO2 is 2 1 C. The capacitance value of the high sampling capacitor CO3 is 2 2 C. The capacitance value of the high sampling capacitor CO M-1 is 2 M-2 C. The capacitance value of the high sampling capacitor CO M is 2 M-1 C. The total capacitance value of the high redundancy capacitor and each high sampling capacitor is 2 M C.

[0052] The upper plate of the high redundancy capacitor and each high sampling capacitor is connected and connected with the external common mode voltage port Vcom through the switch SWT; the lower plate of the high redundancy capacitor and each high sampling capacitor is connected with the analog input signal port Vin through a single-pole single-throw switch respectively; the lower plate of the high redundancy capacitor is also connected with the reference ground port GND through a normally closed switch; the lower plate of each high sampling capacitor is also connected with the reference voltage port VREF through a high voltage on-off switch respectively, and is also connected with the reference ground port GND through a high reference ground on-off switch respectively.

[0053] Specifically, the lower plate of the high redundancy capacitor CO0 is connected with the single-pole single-throw switch SP and the normally closed switch SN; the lower plate of the high sampling capacitor CO1, CO2, CO3…CO M-1 , CO M is connected with the single-pole single-throw switch SP1, SP2, SP3…SP M-1 , SP M is connected with the high voltage on-off switch SWP0<1>, SWP0<2>, SWP0<3>…SWP0 <m-1>SWP0 <m>Connects with high-level reference ground on-off switch SWN0<1>, SWN0<2>, SWN0<3>...SWN0 <m-1>SWN0 <m>connect.

[0054] The low-order capacitor array is used to quantize the low-order data in the analog-to-digital converter. For example... Figure 1 As shown, the input ports IN1 and IN2 of the low-side capacitor array are connected to the reference ground port GND and the reference voltage port VREF, respectively, and the output port OUT0 of the low-side capacitor array is connected to the input port IN0 of the bridging unit. In this embodiment, the voltage of the reference voltage port VREF is 2.5V.

[0055] Specifically, the low-order capacitor array includes two low-order redundant capacitors with unit capacitance values ​​and several low-order sampling capacitors arranged in an increasing binary weighting manner based on the unit capacitance to form a weighted capacitor array. In this embodiment, N low-order sampling capacitors are included, namely C11, C12, C13…C1 N-1 C1 N Low-level redundant capacitor C1 N0 and C1 N1 The capacitance value of all capacitors is C; the capacitance value of the low-order sampling capacitor C11 is 2. 0 C. The capacitance value of the low-order sampling capacitor C12 is 2. 1 C. The capacitance value of the low-order sampling capacitor C13 is 2. 2 C…Low-order sampling capacitor C1 N-1 The capacitance value is 2 N-2 C. Low-order sampling capacitor C1 N The capacitance value is 2 N-1 C.

[0056] The upper plates of the low-level redundant capacitors and each low-level sampling capacitor are connected to each other and connected to the input port IN0 in the bridging unit; the lower plates of each low-level redundant capacitor and each low-level sampling capacitor are respectively connected to the reference voltage port VREF through a low-level voltage on / off switch, and are also respectively connected to the reference voltage port VREF through a low-level reference ground on / off switch.

[0057] Specifically, the low-level redundant capacitor C1 N0 C1 N1 The lower plates are respectively connected to the low-voltage on / off switch SCP1 <0> SCP1 <1> Connect to the low-level reference ground on / off switch SCN1 <0> SCN1 <1> Connections; Low-order sampling capacitors C11, C12, C13…C1 N-1 C1 N The lower plates are respectively connected to the low-voltage on / off switch SWP1 <1> SWP1 <2> SWP1 <3> …SWP1 <n-1>SWP1 <n>Connects with low bit reference ground on-off switch SWN1<1>, SWN1<2>, SWN1<3>...SWN1 <n-1>SWN1 <n>connect.

[0058] The bridging unit is used to bridge the high-order capacitor array and the low-order capacitor array, and includes bridging capacitor C6, bridging capacitor C7, switch SW1, and common-source operational amplifier A0. The input terminal of the common-source operational amplifier A0 is connected to the input port IN0 of the bridging unit, and the output terminal is connected to one end of bridging capacitor C7. The other end of bridging capacitor C7 is connected to the output port OUT0 of the bridging unit, and the output port OUT0 of the bridging unit is connected to the input port IP of the comparator latch unit. Both bridging capacitor C6 and switch SW1 are connected in parallel with common-source operational amplifier A0. In this embodiment, the capacitance values ​​of bridging capacitor C6 and bridging capacitor C7 are TC and IC, respectively, where T and I are constants.

[0059] The input transistor of the common-source op-amp A0 operates in the subthreshold region. For example... Figure 2 As shown, the common-source operational amplifier A0 includes a current source, PMOS transistors PM0, PM1, PM2, PM3, PM4, PM5, NMOS transistors NM0, NM1, and NM2; Ibisa is the reference current provided by an external current reference. NM2 is the input transistor, PM4 and PM5 are current source loads, and NM1 is the bias transistor. During operation, the input and output potentials of the common-source operational amplifier A0 are equal, and it performs operational functions.

[0060] The sources of PMOS transistors PM0, PM2, and PM4 are all connected together; the gate of PMOS transistor PM0 is connected to the gates of PMOS transistors PM2 and PM4, and its drain is connected to the source of PMOS transistor PM1; the drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM3; the gate of PMOS transistor PM1 is connected to the gates of PMOS transistors PM3 and PM5; and the drain of PMOS transistor PM4 is connected to the source of PMOS transistor PM5.

[0061] The drain of PMOS transistor PM1 is connected to a current source; the drain of PMOS transistor PM3 is connected to the drain of NMOS transistor NM0; the drain of PMOS transistor PM5 is connected to the drain of NMOS transistor NM1 and the output of common-source operational amplifier A0; the gate of NMOS transistor NM0 is connected to the gate of NMOS transistor NM1; the source of NMOS transistor NM1 is connected to the drain of NMOS transistor NM2; the gate of NMOS transistor NM2 is connected to the input of common-source operational amplifier A0; the current source, the source of NMOS transistor NM0, and the source of NMOS transistor NM2 are all connected and grounded.

[0062] Among them, PMOS transistors PM0, PM1, PM2 and PM3 form a current mirror, and PMOS transistors PM0, PM1, PM4 and PM5 form a current mirror. Since the current source provides a reference current of Ibisa, the two current mirrors provide bias currents of Ibisa and 10 times Ibisa to NMOS transistors NM0 and NM2, respectively.

[0063] NMOS transistor NM2 acts as a diode load, providing a bias voltage for NMOS transistor NM1. When the input and output terminals of the common-source op-amp are shorted, the input and output voltages are equal. By adjusting the dimensions of NMOS transistor NM2, its threshold voltage can be made equal to the input and output voltages of the common-source op-amp. In this state, NMOS transistor NM2 operates in the subthreshold region, and the overall gain of common-source op-amp A0 can reach over 58dB. When the input and output terminals of the common-source op-amp are disconnected, the input and output terminals remain unchanged due to the high gain of common-source op-amp A0 and the bridging capacitor C6 inside the bridging unit.

[0064] The offset-calibrated comparator latch unit is used to compare and latch the voltages quantized from the high-order and low-order capacitor arrays with the common-mode voltage Vcom. In this embodiment, the Vcom port voltage is 1.25V. The input port IN of the comparator latch unit is connected to the external common-mode voltage port Vcom; the output port Vout of the comparator latch unit is connected to the input port INO of the digital unit; and the input port INO of the comparator latch unit is connected to the output port OUT0 of the digital unit.

[0065] The comparison latch unit includes a first-stage comparator, a second-stage comparator, a third-stage comparator, a latch, an SR flip-flop, switches SCO0, SCO1, SCO2, SCO3, SCO4, SCO5, and SCO6. Wherein, as... Figure 4 As shown, the first-stage comparator uses an NMOS cross-coupled pair as the load structure. Figure 5 The circuit structure of the second-stage comparator is shown. In this embodiment, the second-stage comparator and the third-stage comparator use the same circuit structure, employing PMOS cross-coupled pairs as loads; the specific circuit structure of the latch is as follows. Figure 6 As shown, the specific circuit structure of the SR flip-flop is as follows: Figure 7 As shown.

[0066] like Figure 3 As shown, the input port +IP in the first-stage comparator is connected with the input port IP of the comparison latch unit, the input port -IN is connected with the input port IN of the comparison latch unit, and the input port +IP and the input port -IN are connected with the switch SCO0; the output port +OUTP in the first-stage comparator is connected with the input port +IP in the second-stage comparator through the calibration capacitor CO1, and the calibration capacitor CO1 and the input port +IP in the second-stage comparator are connected with the switch SCO1; the output port -OUTN in the first-stage comparator is connected with the input port -IN in the second-stage comparator through the calibration capacitor CO2, and the calibration capacitor CO2 and the input port -IN in the second-stage comparator are connected with the switch SCO2.

[0067] The output port +OUTP in the second-stage comparator is connected with the input port +IP in the third-stage comparator through the calibration capacitor CO3, and the calibration capacitor CO3 and the input port +IP in the third-stage comparator are connected with the switch SCO3; the output port -OUTN in the second-stage comparator is connected with the input port -IN in the third-stage comparator through the calibration capacitor CO4, and the calibration capacitor CO4 and the input port -IN in the third-stage comparator are connected with the switch SCO4.

[0068] The output port +OUTP in the third-stage comparator is connected with the input port +IP in the latch through the calibration capacitor CO5, and the calibration capacitor CO5 and the input port +IP in the latch are connected with the switch SCO5; the output port -OUTN in the third-stage comparator is connected with the input port -IN in the latch through the calibration capacitor CO6, and the calibration capacitor CO6 and the input port -IN in the latch are connected with the switch SCO6.

[0069] The other end of the switch SCO1, the switch SCO2, the switch SCO3, the switch SCO4, the switch SCO5 and the switch SCO6 are connected with the external common-mode voltage port Vcom.

[0070] In the working state, the first, second and third comparators compare the input data of the input ports +IP and-IN, and the final result is transmitted to the latch for latching and sent to the digital unit for successive approximation logic, so as to obtain the M+N-bit data output of the analog-to-digital converter. The three comparators are calibrated by the output offset calibration method to calibrate the offset voltage of the comparator. When the digital unit controls the IN0 input to be low, the switches SCOO, SCO1, SCO2, SCO3, SCO4, SCO5 and SCO6 are closed, the input ports +IP and-IN of the three comparators are shorted together through the external Vcom voltage, and the offset voltage of each comparator will exist on the capacitors CO1, CO2, CO3, CO4, CO5 and CO6; when the digital unit controls the IN0 input to be high, the output of each comparator will be reduced by the offset voltage of the capacitor, so as to obtain the correct comparison result for latching by the latch.

[0071] The comparator is connected with the input port INO in the comparison and latch unit, and also connected with the input end of the SR flip-flop; the output end of the SR flip-flop is connected with the output port Vout in the comparison and latch unit.

[0072] The SR flip-flop comprises NAND gate X13 and NAND gate X14; one input of the NAND gate X14 is connected with the output port +OUTP in the latch, and the other input is connected with the output of the NAND gate X13; one input of the NAND gate 13 is connected with the output port-OUTN in the latch, and the other input is connected with the output of the NAND gate X14; the output of the NAND gate 13 is also connected with the output port Vout in the comparison and latch unit. After the differential output end of the latch latches the output of the comparator, the output Vout of the SR flip-flop will send the output to the digital unit for successive approximation logic.

[0073] As shown in Figure 9 , the digital unit is used to convert the analog signal output by the comparison and latch unit into a digital signal through successive approximation logic. The digital unit is connected with the high-bit capacitor array and the low-bit capacitor array, and controls the on and off of each single-pole single-throw switch, each normally closed switch, each high-bit voltage on-off switch, each high-bit reference ground on-off switch, the switch SWT in the high-bit capacitor array, and each low-bit voltage on-off switch and each low-bit reference ground on-off switch in the low-bit capacitor array through the multi-bit bus output mode. Figure 8

[0074] ​Specifically, the digital unit is designed at a behavior level using Verilog, then a gate level net list is synthesized based on the Verilog, and finally the gate level net list is used for layout and wiring to form a final layout, all gate circuits in the layout are designed using standard cells, and a successive approximation algorithm is embedded, the digital unit sends a signal to lock the output Vout of the comparison and latching module with the misadjustment calibration through an internal output terminal OUT0 to control the on and off of each switch, thereby realizing the successive approximation algorithm.

[0075] In the sampling phase, the digital unit controls the low voltage on-off switches SCP1<0>, SCP1<1>, the low voltage on-off switches SWP1<1>, SWP1<2>, SWP1<3>…SWP1 <n-1>SWP1 <n>The lower plate of the low-bit redundant capacitor C1 N0 , C1 N1 , the low-bit sampling capacitor C11, C12, C13... C1 N-1 , C1 N is connected to the reference voltage port VREF; by controlling the low-bit reference ground on-off switch SCN1<0>, SCN1<1>, the low-bit reference ground on-off switch SWN1<1>, SWN1<2>, SWN1<3>... SWN1 <n-1>SWN1 <n>is disconnected, switch SW1 is closed, so that Figure 1 The potential of midpoint VX is equal to the potential of point VY and VX=VY=Vt (Vt is the static bias point voltage of common-source operational amplifier A0); by controlling switch SWT to be closed, so that VP=Vcom, the digital unit controls single-pole single-throw switches SP1, SP2, SP3...SP M-1 , SP M , the lower plate of high-bit redundant capacitor CO0, high-bit sampling capacitors CO1, CO2, CO3...CO M-1 , CO M is connected to analog input signal port Vin, high-bit voltage on-off switches SWP0<1>, SWP0<2>, SWP0<3>...SWP0 <m-1>SWP0 <m>high-level reference ground on-off switches SWN0<1>, SWN0<2>, SWN0<3>...SWN0 <m-1>SWN0 <m>When disconnected, the high bit redundant capacitor COO, the high bit sampling capacitors COI, CO2, CO3...CO M-1 , CO M The charge amount of the upper plate is:

[0076] Ql = (Vcom - VY)I*C + (Vcom - Vin)2 M C

[0077] In the formula, I (I is an integer) represents that the capacitance value of the bridging capacitor C7 is I times of the unit capacitance value (C), Vcom is the common mode voltage input from outside, VY is the voltage at point VY, C is the unit capacitance value, Vin is the voltage input from outside and needed to be sampled, and 2 M C is COO~CO M The sum of all the capacitance values (wherein M is an integer, and is the capacitor number of the high bit capacitor array).

[0078] After the sampling stage is finished, the switch conversion of the high bit capacitor array is performed, and when the first time successive approximation is performed in the high bit capacitor array, the switches SW1, SWT, the single-pole single-throw switches SP1, SP2, SP3...SP M-1 , SP M are all disconnected, the lower plate of the high bit sampling capacitor CO M passes through the high bit voltage on-off switch SWPO <m>The reference voltage port VREF remains unchanged, and the rest of the switch states remain unchanged in the sampling phase. At this time, the high-bit redundant capacitor CO0, the high-bit sampling capacitors CO1, CO2, CO3, and CO m-1 , CO M The charge amount of the upper plate is:

[0079] Q2 = (VP-VY)I*C + (VP-VREF)2 M-1 C + VP*2 M-1 C

[0080] Due to charge conservation, we have:

[0081] Q1 = Q2

[0082] Thus we have:

[0083]

[0084] Since the input port IN of the comparison latch unit with offset calibration is connected to the external common-mode voltage port Vcom, then if:

[0085]

[0086] At this time, we have:

[0087]

[0088] At this time, the Vout value latched by the comparison latch unit is 1, and the digital unit will discharge the high-bit sampling capacitors CO M The corresponding high-bit voltage on-off switch SWP0 <m>turn off, turn off high-side reference ground switch SWN0 <m>The digital unit writes "0" on the output register of the M+Nth bit of the D / A converter, which completes the quantization of the most significant bit (i.e. the M+Nth bit) of the D / A converter; on the contrary, if the value of Vout latched by the comparison latching unit is 0, the digital unit will write "1" on the output register of the M+Nth bit of the D / A converter, which completes the quantization of the M+Nth bit of the D / A converter. M The corresponding high voltage on-off switch SWP0 <m>Keep the current open state, turn off the high-level reference ground switch SWN0 <m>The current off state is maintained while the digital unit writes a "1" on the M+Nth bit output register of the digital to analog converter, completing the quantization of the most significant bit of the digital to analog converter (i.e. the M+Nth bit). Similarly, the other switches of the high bit capacitor array (high bit voltage pass switch SWP0<1>, SWP0<2>, SWP0<3>...SWP0 <m-1>and SWN0<1>, SWN0<2>, SWN0<3>...SWN0 <m-1>) are also analyzed by the above method. VIN is converted by M times of switching and compared with Vcom, and the voltage at point VP is compared with Figure 1 as shown in the figure, and M times of comparison is completed to complete the quantization of the high M-bit data of the digital-to-analog converter.

[0089] After the switching conversion of the high-bit capacitor array is completed, the switching conversion of the low-bit capacitor array is performed. The capacitances of the low-bit capacitor array are N+2 bits, and the last two bits are redundant bits. During the quantization of the digital-to-analog converter, the last two bits are not used as data latches, and only the first N bits are latched. To simplify the analysis, it is assumed that the high-bit redundant capacitor COO and the lower plates of the high-bit sampling capacitors (CO1, CO2, CO3…CO M-1 , CO M ) in the high-bit capacitor array are connected to the reference ground port GND through the high-bit reference ground switch (the high-bit capacitor array has completed the quantization of the high M-bit data, and in fact, the high-bit redundant capacitor and the high-bit sampling capacitor can be connected to the reference ground port GND and the reference voltage port VREF, which will not affect the analysis).

[0090] The lower plate of the low-bit sampling capacitor C1 N is switched from VREF to 0 through a switch (the low-bit voltage on-off switch SWP1 <n>off, SWN1 <n>opening), due to the input tube working in the sub-threshold common-source operational amplifier A0 (the gain of A0 is greater than 58dB) high-gain characteristics, so that the input port of the common-source operational amplifier VX = Vt still holds during the low-bit capacitor array switching process, during which the low-bit redundant capacitor C1 N0 , C1 N1 , the upper plate of the low-bit sampling capacitor C11, C12, C13…C1 N-1 , C1 N The amount of charge does not involve exchange, so the amount of charge is conserved. By analyzing the amount of charge of the upper plate of the low-bit redundant capacitor C1 N0 , C1 N1 , the low-bit sampling capacitor C11, C12, C13…c1 N-1 , c1 N , we get:

[0091] Q VX0 = (VX-VREF) (2 N+1 )C + (VX-VY)T*C

[0092] In the formula, Q VX0 is the amount of charge on the upper plate of the low-bit redundant capacitor C1 N0 , C1 N1 , the low-bit sampling capacitor C11, C12, C13…C1 N-1 , C1 N , and VX and VY during the sampling stage are shorted to the static operating point of the common-source operational amplifier A0 by SW1, so VX = VY, and the above formula is combined to get:

[0093] Q VX0 = (VX-VREF) (2 N +1)C

[0094] When the low-bit sampling capacitor C1 N of the low-bit capacitor array is switched from VREF to GND (low-bit voltage on-off switch SWP1 <n>open, low reference ground switch SWN1 <n>When closed, the low-level redundant capacitor C1 N0 C1 N1 Low-order sampling capacitors C11, C12, C13…C1 N-1 C1 N The charge on the upper plate is:

[0095] Q VX1 =(VX′-VREF)(2 N-1 +1)C+VX′*(2 N-1 )C+(VX′-VY′)T*C

[0096] In the formula, VX′ and VY′ represent the low-order sampling capacitor C1 during the low-order capacitor array conversion, respectively. N The potentials of VX and VY during the switching transition need to be distinguished from those during sampling. As mentioned earlier, due to the high gain of the common-source op-amp A0, VX = VX′ = VY = Vt. Combining this with the above equation, we can obtain:

[0097] Q VX1 =(VX-VREF)(2) N-1 +1)C+VX*(2 N-1 )C+(VY-VY′)T*C

[0098] During this process, the low-level redundant capacitor C1 N0 C1 N1 Low-order sampling capacitors C11, C12, C13…C1 N-1 C1 N The charge on the upper plate does not involve exchange, therefore the charge is conserved, i.e., Q. VX0 =Q VX1 We can obtain:

[0099]

[0100] That is:

[0101]

[0102] It can be seen that during the low-order capacitor array conversion, the low-order sampling capacitor C1 N During the conversion process, the low-order sampling capacitor C1 N Before and after the corresponding switch transitions from VREF to GND, the potential of VY increases compared to the sampling phase. The potential change at point VP is analyzed below. As described in the sampling phase, during the sampling phase, the high-order redundant capacitor CO0 and the high-order sampling capacitors CO1, CO2, CO3…CO M-1 CO M The charge on the upper plate is:

[0103] Q1 = (Vcom-VY)I*C + (Vcom-Vin)2 M C

[0104] During low bit capacitor array conversion, low bit sampling capacitor C1 N Corresponding switch by VREF to GND in the process, high bit redundant capacitor CO0 and high bit sampling capacitor CO1, CO2, CO3… CO M-1 , CO M The charge amount of the upper plate is:

[0105] Q2 = (VP-VY')I*C + (VP)2 M C

[0106] According to the charge conservation Q1 = Q2, we have:

[0107]

[0108] Since the input port IN in the comparison latch unit connects to the external common mode voltage port Vcom, if:

[0109]

[0110] Then:

[0111]

[0112] That is:

[0113]

[0114] Let:

[0115]

[0116] Then:

[0117]

[0118] At this time, the Vout value latched by the comparison latch unit is 1, and the digital unit will convert the low bit sampling capacitor C1 N Corresponding low bit voltage on-off switch SWP1 <n>Maintain current off state, low side reference to ground on-off switch SWN1 <n>The current open state is maintained (the existence of the common-source operational amplifier A0 causes the phases of VX and VY to be opposite). At the same time, the digital unit writes "0" on the M+1 bit output register of the digital-to-analog converter to complete the quantization of the M+1 bit data of the digital-to-analog converter; on the contrary, if the Vout value latched by the comparison latching unit is 0, the digital unit will write "1" on the M+1 bit output register of the digital-to-analog converter to complete the quantization of the M+1 bit data of the digital-to-analog converter. N The corresponding low-bit voltage on-off switch SWP1 <n>Open, turn off low-side reference ground switch SWN1 <n>turn-off. At the same time, the digital unit writes "1" on the (M+1)th bit output register of the digital-to-analog converter to complete the quantization of the (M+1)th bit data of the digital-to-analog converter. In the same way, other switches of the low-bit capacitor array (low-bit voltage on-off switch SCP1<0>, SCP1<1>, low-bit reference ground on-off switch SCN1<0>, SCN1<1>, low-bit voltage on-off switch SWP1<1>, SWP1<2>, SWP1<3>…SWP1 <n-1>, low-level reference ground on-off switch SWN1<1>, SWN1<2>, SWN1<3>...SWN1 <n-1>The transformation is also analyzed using the method described above. However, due to C1 N0 and C1 N1 For low-level redundant capacitors, low-level voltage on / off switch SCP1 <0> SCP1 <1> Low-level reference ground on / off switch SCN1 <0> SCN1 <1> The state will not be written to the register by the digital unit. After VIN undergoes N+2 switching transformations and is compared with Vcom, as shown... Figure 1 The voltage at point VP shown is After N+2 comparisons, the digital unit will only use the low-order sampling capacitors C11, C12, C13...C1 N-1 C1 N The states of each switch connected to the lower plate are written to the register as N bits of low-order LSB data, thus completing the quantization of the low N bits of data in the digital-to-analog converter. Therefore, utilizing the high-gain characteristic of the common-source op-amp A0 (with a gain greater than 58dB) operating in subthreshold mode, the input port potential of the common-source op-amp remains approximately constant during the switching of the low-order capacitor array. This ensures that the number of bridging capacitors C6 and C7 is an integer multiple of the unit capacitance (T times and I times respectively, and satisfies...). This eliminates the need for additional adjustment schemes, making it easier to match during layout design.

[0119] like Figure 2 As shown, in the common-source op-amp A0, PMOS transistors PM0, PM1, PM2, and PM3 form a current mirror, and PMOS transistors PM0, PM1, PM4, and PM5 form another current mirror. Assuming the current source provides a reference current Ibisa, the two current mirrors provide bias currents of Ibisa and 10 times Ibisa to NMOS transistors NM0 and NM2, respectively. NMOS transistor NM2 acts as a diode load, providing a bias voltage to NMOS transistor NM1. When the input and output terminals of the common-source op-amp are shorted, the input and output voltages are equal. By adjusting the dimensions of NMOS transistor NM2, its threshold voltage can be made equal to the input and output voltages of the common-source op-amp. In this case, NMOS transistor NM2 operates in the subthreshold region, and the overall gain of the common-source op-amp A0 can reach over 58dB. When the input and output terminals of the common-source op-amp are disconnected, the input and output terminals will remain unchanged due to the combined effect of the high gain of the common-source op-amp A0 and the bridging capacitor C6 inside the bridging unit.

[0120] like Figure 3 As shown, in the working state, the first, second and third comparators compare the input data of the input ports +IP and -IN, and the final results are transmitted to the latch for latching and sent to the digital unit for successive approximation logic, so as to obtain the M+N-bit data output of the analog-to-digital converter. The above three comparators are calibrated by the output offset calibration method. When the digital unit controls the IN0 input to be low, the switches SCOO, SCO1, SCO2, SCO3, SCO4, SCO5 and SCO6 are closed, the input ports +IP and -IN of the three comparators are shorted together through the external Vcom voltage, and the offset voltages of the comparators are respectively stored on the capacitors CO1, CO2, CO3, CO4, CO5 and CO6; when the digital unit controls the IN0 input to be high, the output of each comparator will be reduced by the offset voltage of the capacitor, so as to obtain the correct comparison result for the latch. The latch is followed by an SR flip-flop composed of NAND gate X13 and NAND gate X14, and when the differential output end of the latch latches the output of the comparator, the output Vout of the SR flip-flop will send the output to the digital unit for successive approximation logic.

[0121] Specifically, Figure 4 As shown, the circuit structure of the first comparator, Ibias is the reference bias current provided by the external current reference, PM0' to PM3' are the current mirror structure composed of PMOS tubes, which provide long-tail bias current for the first comparator, IP and IN in the first comparator are the same direction input end and reverse input end of the first comparator, OUTP and OUTP in the first comparator are the same direction output end and reverse output end of the first comparator, PM4' and PM5' are the differential pair composed of PMSO tubes, NM0' to NM3' are the load composed of NMOS tubes, wherein NM1' and NM2' are cross-coupled structure, and NM0' and NM3' are diode structure.

[0122] Figure 5 As shown, the circuit structure of the second comparator is similar to that of the first comparator, but the load is PMSO tube. Wherein Ibias is the reference bias current provided by the external current reference, NM2'" to NM5'" are the current mirror structure composed of NMOS tubes, which provide long-tail bias current for the comparator, IP and IN in the second comparator are the same direction input end and reverse input end of the second comparator, OUTP and OUTP in the second comparator are the same direction output end and reverse output end of the second comparator, NM0'" and NM1'" are the differential pair composed of NMSO tubes, PM0'" to PM3'" are the load composed of PMOS tubes, wherein PM1'" and PM2'" are cross-coupled structure, and PM0'" and PM3'" are diode structure.

[0123] Figure 6 The circuit structure of the latch with offset calibration is shown, wherein Ibias is the reference bias current provided by an external current reference, NM'0 to NM'3 are the current mirror bias structure composed of NMOS tubes, and provide the long tail bias current for the NM'4 and NM'5 tubes of the latch; PM'0 to PM'1 are the current mirror bias structure composed of PMOS tubes, and provide the load bias current for the PM'2 to PM'5 tubes of the latch; NM'8 and NM'9 are the input differential pair tubes of the latch, NM'6, NM'7, PM'7 and PM'8 are the cross-coupled load composed of NMOS and PMOS tubes respectively, IP and IN in the latch are the same direction input terminal and reverse input terminal of the latch, and OUTP and OUTP in the latch are the same direction output terminal and reverse output terminal of the latch.

[0124] Figure 7 The circuit structure of the NAND gate in the flip-flop SR is shown, wherein PM<0> and PM<1> are PMOS tubes, NM<0> and NM<1> are NMOS tubes, A and B are the inputs of the NAND gate, and OUT is the output of the NAND gate.

[0125] Figure 8 The circuit structure of all mode switches in the scheme is shown, wherein PM[0] and NM[0] constitute the inverter structure, NM[1] and PM[1] constitute the transmission gate structure, CT is the control pin of the switch, IN is the input pin of the switch, and OUT is the output pin of the switch; when the digital unit controls CT to be high level, CTN is low level, the NM[1] tube and the PM[1] tube are both turned on, the whole switch will be opened to transmit the signal from the IN end to the OUT end, otherwise, when the digital unit CT is low level, CTN is high level, the NM[1] tube and the PM[1] tube are both turned off, the whole switch will be closed and cannot transmit the signal from the IN end to the OUT end, and presents high resistance state.

[0126] Figure 9 It is the module schematic diagram of the digital unit, the digital unit adopts Verilog to carry out behavior level design, then forms the gate level netlist on the basis of Verilog, and finally utilizes the gate level netlist to carry out layout and wiring to form the final layout, all gate level circuits in the layout are designed by using the standard unit, and the successive approximation algorithm is embedded, the digital unit sends the signal Vout of the comparison latch module with offset calibration through the internal output end OUT0 to control the turn-on and turn-off of each switch, so that the successive approximation algorithm is realized.

[0127] Analog-to-digital converter with high bridge capacitance matching degree, which adopts the above-mentioned analog-to-digital converter circuit with high bridge capacitance matching degree.

[0128] The above is only an embodiment of the present application, and the common knowledge of specific structures and characteristics in the scheme is not described in detail, and the ordinary skilled person in the art knows all the ordinary technical knowledge in the technical field of the present application before the application date or the priority date, can know all the prior art in the field, and has the ability to apply conventional experimental means before that date, and the ordinary skilled person in the art can improve and implement the present scheme under the guidance of the present application, and some typical known structures or known methods should not be an obstacle for the ordinary skilled person in the art to implement the present application. It should be pointed out that for those skilled in the art, without departing from the structure of the present application, a number of modifications and improvements can be made, which should also be considered as the protection scope of the present application, which will not affect the effect and practicality of the patent. The protection scope of the present application should be subject to the content of its claims, and the specific implementation mode and the like in the specification can be used to explain the content of the claims. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / m> < / m> < / m> < / m> < / m> < / m> < / m> < / n> < / n> < / n> < / n> < / m> < / m>

Claims

1. An analog-to-digital converter circuit with high bridging capacitor matching, characterized in that: It includes a high-order capacitor array, a low-order capacitor array, a bridging unit, a comparison latch unit, and a digital unit; The input ports INO, IN1, IN2 and IN3 in the high-level capacitor array are connected to the external common-mode voltage port Vcom, the reference ground port GND, the reference voltage port VREF and the analog input signal port Vin, respectively. The output port OUT0 in the high-level capacitor array is connected to the output port OUT0 in the bridging unit and the input port IP in the comparison latch unit. The input ports IN1 and IN2 of the low-position capacitor array are connected to the reference ground port GND and the reference voltage port VREF, respectively, and the output port OUT0 of the low-position capacitor array is connected to the input port IN0 of the bridging unit. The bridging unit includes bridging capacitor C6, bridging capacitor C7, switch SW1, and common-source operational amplifier A0; The input terminal of the common-source operational amplifier A0 is connected to the input port IN0 of the bridging unit, and the output terminal is connected to one end of the bridging capacitor C7. The other end of the bridging capacitor C7 is connected to the output port OUT0 of the bridging unit. The output port OUT0 of the bridging unit is connected to the input port IP of the comparator latch unit. The bridging capacitor C6 and the switch SW1 are both connected in parallel with the common-source operational amplifier A0. The input port IN of the comparison latch unit is connected to the external common-mode voltage port Vcom; the output port Vout of the comparison latch unit is connected to the input port INO of the digital unit; the input port INO of the comparison latch unit is connected to the output port OUT0 of the digital unit. The digital unit is used to convert the analog signal output by the comparison latch unit into a digital signal through successive approximation logic; The common-source operational amplifier A0 includes a current source, PMOS transistors PM0, PM1, PM2, PM3, PM4, PM5, NMOS transistors NM0, NMOS transistors NM1, and NMOS transistors NM2. The sources of PMOS transistors PM0, PM2, and PM4 are all connected together; the gate of PMOS transistor PM0 is connected to the gates of PMOS transistors PM2 and PM4, and its drain is connected to the source of PMOS transistor PM1; the drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM3; the gate of PMOS transistor PM1 is connected to the gates of PMOS transistors PM3 and PM5; and the drain of PMOS transistor PM4 is connected to the source of PMOS transistor PM5. The drain of PMOS transistor PM1 is connected to a current source; the drain of PMOS transistor PM3 is connected to the drain of NMOS transistor NM0; the drain of PMOS transistor PM5 is connected to the drain of NMOS transistor NM1 and the output of common-source operational amplifier A0; the gate of NMOS transistor NM0 is connected to the gate of NMOS transistor NM1; the source of NMOS transistor NM1 is connected to the drain of NMOS transistor NM2; the gate of NMOS transistor NM2 is connected to the input of common-source operational amplifier A0; the current source, the source of NMOS transistor NM0, and the source of NMOS transistor NM2 are all connected and grounded.

2. The analog-to-digital converter circuit with high bridging capacitor matching degree according to claim 1, characterized in that: The high-order capacitor array includes a high-order redundant capacitor with a unit capacitance value and several high-order sampling capacitors arranged in a weighted capacitor array based on the unit capacitance and according to the binary weight increment. The upper plates of the high-level redundant capacitor and each high-level sampling capacitor are connected together and connected to the external common-mode voltage port Vcom via a switch SWT; the lower plates of the high-level redundant capacitor and each high-level sampling capacitor are respectively connected to the analog input signal port Vin via a single-pole single-throw switch; the lower plate of the high-level redundant capacitor is also connected to the reference ground port GND via a normally closed switch; the lower plates of each high-level sampling capacitor are also respectively connected to the reference voltage port VREF via a high-level voltage on / off switch, and are also respectively connected to the reference ground port GND via a high-level reference ground on / off switch.

3. The analog-to-digital converter circuit with high bridging capacitor matching degree according to claim 2, characterized in that: The low-order capacitor array includes two low-order redundant capacitors with unit capacitance values ​​and several low-order sampling capacitors arranged in a weighted capacitor array based on unit capacitance and according to binary weight increments. The upper plates of the low-level redundant capacitors and each low-level sampling capacitor are connected to each other and connected to the input port IN0 in the bridging unit; the lower plates of each low-level redundant capacitor and each low-level sampling capacitor are respectively connected to the reference voltage port VREF through a low-level voltage on / off switch, and are also respectively connected to the reference voltage port VREF through a low-level reference ground on / off switch.

4. The analog-to-digital converter circuit with high bridging capacitor matching degree according to claim 3, characterized in that: The digital unit is connected to both the high-level capacitor array and the low-level capacitor array, and controls the conduction and cutoff of each single-pole single-throw switch, each normally closed switch, each high-level voltage on / off switch, each high-level reference ground on / off switch, and switch SWT in the high-level capacitor array, as well as each low-level voltage on / off switch and each low-level reference ground on / off switch in the low-level capacitor array, through a multi-bit bus output.

5. The analog-to-digital converter circuit with high bridging capacitor matching degree according to claim 1, characterized in that: The input transistor of the common-source op-amp A0 operates in the subthreshold region.

6. The analog-to-digital converter circuit with high bridging capacitor matching degree according to claim 1, characterized in that: The comparison latch unit includes a first-stage comparator, a second-stage comparator, a third-stage comparator, a latch, an SR flip-flop, a switch SCO0, a switch SCO1, a switch SCO2, a switch SCO3, a switch SCO4, a switch SCO5, and a switch SCO6. The input port +IP of the first-stage comparator is connected to the input port IP of the comparator latch unit, and the input port -IN is connected to the input port IN of the comparator latch unit. A switch SCO0 connects the input ports +IP and -IN. The output port +OUTP of the first-stage comparator is connected to the input port +IP of the second-stage comparator through a calibration capacitor CO1. Both the calibration capacitor CO1 and the input port +IP of the second-stage comparator are connected to the switch SCO1. The output port -OUTN of the first-stage comparator is connected to the input port -IN of the second-stage comparator through a calibration capacitor CO2. Both the calibration capacitor CO2 and the input port -IN of the second-stage comparator are connected to the switch SCO2. The output port +OUTP of the second-stage comparator and the input port +IP of the third-stage comparator are connected through calibration capacitor CO3. Both calibration capacitor CO3 and the input port +IP of the third-stage comparator are connected to switch SCO3. The output port -OUTN of the second-stage comparator and the input port -IN of the third-stage comparator are connected through calibration capacitor CO4. Both calibration capacitor CO4 and the input port -IN of the third-stage comparator are connected to switch SCO4. The output port +OUTP of the third-stage comparator and the input port +IP of the latch are connected through calibration capacitor CO5. Both calibration capacitor CO5 and the input port +IP of the latch are connected to switch SCO5. The output port -OUTN of the third-stage comparator and the input port -IN of the latch are connected through calibration capacitor CO6. Both calibration capacitor CO6 and the input port -IN of the latch are connected to switch SCO6. The other ends of switches SCO1, SCO2, SCO3, SCO4, SCO5, and SCO6 are all connected to the external common-mode voltage port Vcom. The comparator is connected to the input port INO in the comparator latch unit and also to the input of the SR flip-flop; the output of the SR flip-flop is connected to the output port Vout of the comparator latch unit.

7. The analog-to-digital converter circuit with high bridging capacitor matching degree according to claim 6, characterized in that: The SR trigger includes NAND gate X13 and NAND gate X14; One input of NAND gate X14 is connected to the output port +OUTP of the latch, and the other input is connected to the output of NAND gate X13; one input of NAND gate X13 is connected to the output port -OUTN of the latch, and the other input is connected to the output of NAND gate X14; the output of NAND gate X13 is also connected to the output port Vout of the comparison latch unit.

8. An analog-to-digital converter with high bridging capacitor matching, characterized in that: An analog-to-digital converter circuit employing any one of claims 1 to 7 is described above.

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