Crc checking method and apparatus, communication device, and storage medium

Abstract

The present disclosure provides a CRC checking method and device, communication equipment and storage medium, which can divide the to-be-checked data into multiple parallel block data, and the to-be-checked data is interleaving coded data; the column elements in each parallel block data are subjected to data rearrangement processing, so that the multiple parallel block data are arranged in ascending order according to the multiple column elements in the same row, and the incremental step of the multiple column elements is equal to the number of column elements in each parallel block data; the CRC checking unit is used to determine the first CRC result of each parallel block data in parallel, and the first CRC result is the CRC result obtained by checking each parallel block data by using the preset initial value; the first CRC result of each parallel block data is subjected to merging processing by time division multiplexing the CRC checking unit, and the CRC result of the to-be-checked data is obtained. The present disclosure can reduce the CRC checking cost and complexity.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a CRC verification method, apparatus, communication device, and storage medium. Background Technology

[0002] Mobile communication refers to communication between mobile entities, or between a mobile entity and a fixed entity. A mobile entity can be a person, or an object in motion such as a car, train, ship, or radio. In real-world network environments, the presence of various obstacles makes the signals received by terminals more complex, including multipath fading due to multipath propagation, shadowing fading caused by obstacles blocking or obstructing radio waves, and path loss in free space. In such situations, interleaving coding can discrete signal errors and improve the fading of mobile communication signals. However, interleaving also alters the order of data transmission, making it difficult for the receiving end to perform Cyclic Redundancy Check (CRC) verification. Summary of the Invention

[0003] This disclosure provides a CRC verification method, apparatus, communication device, and storage medium, which can solve the technical problems of high verification cost and complexity when performing CRC verification on interleaved encoded and decoded data.

[0004] The first aspect of this disclosure provides a CRC verification method, including:

[0005] The data to be verified is divided into multiple parallel blocks of data, and the data to be verified is interleaved encoded data;

[0006] The column elements in each parallel block of data are rearranged so that the column elements in the same row of the multiple parallel blocks of data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block of data.

[0007] The first CRC result of each parallel block of data is determined in parallel by the CRC check unit. The first CRC result is the CRC result obtained by the CRC check unit after checking each parallel block of data with a preset initial value.

[0008] By time-division multiplexing the CRC check unit, the first CRC results of each parallel block of data are merged to obtain the CRC result of the data to be checked.

[0009] A second aspect of this disclosure provides a CRC verification device, comprising:

[0010] The partitioning module is used to divide the data to be verified into multiple parallel blocks of data, wherein the data to be verified is interleaved encoded data;

[0011] The first processing module is used to perform data rearrangement processing on the column elements in each parallel block data, so that the multiple column elements in the same row of the multiple parallel block data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data.

[0012] The determination module is used to determine the first CRC result of each parallel block data in parallel using the CRC check unit. The first CRC result is the CRC result obtained by the CRC check unit after checking each parallel block data with a preset initial value.

[0013] The second processing module is used to merge the first CRC results of each parallel block of data by time-division multiplexing the CRC verification unit to obtain the CRC result of the data to be verified.

[0014] A third aspect of this disclosure provides a communication device comprising: a transceiver; a memory; and a processor connected to the transceiver and the memory, respectively, configured to control the transmission and reception of wireless signals of the transceiver by executing computer-executable instructions on the memory, and capable of implementing the method of the first aspect of this disclosure.

[0015] A fourth aspect of this disclosure provides a computer storage medium storing computer-executable instructions; when executed by a processor, the computer-executable instructions can implement the method of the first aspect of this disclosure.

[0016] The CRC verification method, apparatus, communication device, and storage medium provided in this disclosure can divide the data to be verified into multiple parallel blocks, and then rearrange the column elements in each parallel block so that the column elements in the same row of the multiple parallel blocks are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block. Then, a CRC verification unit is used to determine the first CRC result of each parallel block in parallel. The first CRC result is the CRC result obtained by the CRC verification unit after verifying each parallel block using a preset initial value. By time-division multiplexing the CRC verification unit, the first CRC results of each parallel block are merged to obtain the CRC result of the data to be verified. The technical solution in this disclosure, by rearranging multiple parallel blocks and using a single CRC verification unit to perform CRC verification on the rearranged parallel blocks in parallel, can reduce the complexity of CRC verification and improve verification efficiency. Furthermore, by time-division multiplexing the CRC verification unit, the number of CRC verification units can be reduced, thereby reducing the cost of CRC verification.

[0017] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a flowchart illustrating a CRC verification method according to an embodiment of the present disclosure;

[0020] Figure 2 This is a schematic diagram illustrating an example of multiple parallel blocks of data before interleaving encoding according to an embodiment of the present disclosure;

[0021] Figure 3 This is a schematic diagram illustrating an example of multiple parallel block data after interleaving encoding according to an embodiment of the present disclosure;

[0022] Figure 4 This is a schematic diagram illustrating an example of multiple parallel block data after data rearrangement processing according to an embodiment of the present disclosure;

[0023] Figure 5 This is a flowchart illustrating a CRC verification method according to an embodiment of the present disclosure;

[0024] Figure 6 This is a schematic diagram illustrating the principle of CRC verification according to an embodiment of the present disclosure;

[0025] Figure 7 This is a block diagram of a CRC verification device according to an embodiment of the present disclosure;

[0026] Figure 8 This is a schematic diagram of the structure of a communication device according to an embodiment of the present disclosure;

[0027] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of the present disclosure. Detailed Implementation

[0028] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0029] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments of this application and the features in the embodiments can be combined with each other.

[0030] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a” and “the” as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc., may be used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0032] Related technologies require the use of multiple CRC calculation units for collaborative verification of interleaved encoded and decoded data, which leads to high verification costs and complexity of CRC verification.

[0033] To address the aforementioned technical problems, this embodiment proposes a CRC verification method, apparatus, communication device, and storage medium, which can reduce the cost and complexity of CRC verification for interleaved encoded and decoded data.

[0034] The CRC verification method, apparatus, communication equipment, and storage medium provided in this application will be described in detail below with reference to the accompanying drawings.

[0035] Figure 1 A flowchart illustrating a CRC verification method according to an embodiment of this disclosure is shown. Figure 1 As shown, the embodiment may include the following steps.

[0036] Step 101: Divide the data to be verified into multiple parallel blocks of data. The data to be verified is interleaved coded data.

[0037] In embodiments of this disclosure, interleaving coding can be used to discrete signal errors and improve the fading of mobile communication signals. Figure 2 The communication data before interleaving coding shown can be obtained after interleaving coding as follows: Figure 3 The data transmission order is altered in the interleaved coded data shown. In this embodiment of the disclosure, after obtaining the data to be verified, it can be divided into multiple parallel blocks according to the parallelism and code length of the data to be verified. For example, assuming code length K = 40 and parallelism N = 8, as... Figure 3 As shown, each column (i.e., parallel block data) has S = K / N = 5 data (column elements), and each column represents the data processed by a parallel block.

[0038] In one embodiment of this disclosure, the decoding results corresponding to the eight data points in each row are generated at the same time.

[0039] Step 102: Perform data rearrangement on the column elements in each parallel block data so that the column elements in the same row of multiple parallel block data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data.

[0040] For embodiments of this disclosure, referring to the special characteristics of interleaved coding, the column elements in each parallel block of data are rearranged so that each data path belongs to a continuous data block, the data within the block is out of order, and the out-of-order pattern is consistent across the blocks of each sequence. That is, as follows... Figure 4 As shown, multiple parallel block data correspond to multiple column elements in the same row arranged in ascending order, and the increment step of multiple column elements is equal to the number of column elements in each parallel block data.

[0041] When the parallelism N is divisible by the code length K, the interleaved coding has the following special properties:

[0042] Contention-free and maximally-vectorizable: Elements from different columns remain in different columns after interleaving; elements in the same row remain in the same row after interleaving.

[0043] Parity remains unchanged: elements with odd ordinal numbers remain odd after interleaving; elements with even ordinal numbers remain even after interleaving.

[0044] For example, such as Figure 4 As shown, after the process of... Figure 3 After rearranging the column elements in the parallel block data shown, eight parallel block data sets are obtained: crc_in7, crc_in6, crc_in5, crc_in4, crc_in3, crc_in2, crc_in1, and crc_in0. These eight parallel block data sets are compared to... Figure 2The communication data shown is before interleaving encoding, with the data in the blocks arranged in random order. The eight parallel blocks correspond to multiple column elements within the same row compared to... Figure 3 The interleaved and encoded communication data shown are arranged in ascending order and follow a certain pattern. For example, the eight columns in the first row corresponding to the eight parallel blocks of data are arranged in ascending order as follows: 0, 5, 10, 15, 20, 25, 30, 35, and the increment step of the eight columns is equal to the number of columns in each parallel block of data, which is 5.

[0045] Step 103: Use the CRC check unit to determine the first CRC result of each parallel block data in parallel. The first CRC result is the CRC result obtained by the CRC check unit after checking each parallel block data with a preset initial value.

[0046] In one embodiment of this disclosure, since out-of-order CRC is used for calculation, the first CRC result of each parallel block of data is its contribution to the final CRC. When the input of the CRC check unit is 0, it does not contribute to the final CRC result. Therefore, the input of the CRC check unit can be fixed to 1, and the contribution to the CRC result can be determined by judging the parallel input of each parallel block of data. In this embodiment of the disclosure, after the column elements in each parallel block of data are rearranged, a CRC check unit can be used to check the first CRC result of each parallel block of data in parallel with a preset initial value.

[0047] Step 104: The first CRC result of each parallel block data is merged by the time-division multiplexing CRC check unit to obtain the CRC result of the data to be checked.

[0048] In the embodiments of this disclosure, the first CRC result of each parallel block data can be merged by time-division multiplexing CRC check units. Compared with the existing CRC check methods, the number of CRC check units used can be reduced. Only one CRC check unit is used to perform CRC check on the rearranged parallel block data in parallel, which can reduce the cost of CRC check.

[0049] For example, such as Figure 4As shown, for 8 parallel block data, after parallel processing of the first CRC results of each parallel block data in step 103 of the embodiment, 8 independent first CRC results corresponding to the 8 parallel block data can be obtained. In this embodiment, the CRC check unit can be time-division multiplexed according to the following order of the 8 parallel block data from front to back: crc_in7, crc_in6, crc_in5, crc_in4, crc_in3, crc_in2, crc_in1, crc_in0, to merge the first CRC results of the 8 parallel block data. When merging the first CRC results, since the first CRC results of the 8 parallel block data are check values ​​of different segments, CRC matrix compensation needs to be performed on the 8 parallel block data sequentially. The corresponding parallel matrix is ​​compensated according to its bit position in the parallel block data, and the compensated second CRC result is bit-XORed with the first CRC result of the next parallel block data until it is bit-XORed with the first CRC result of the last parallel block data, thus obtaining the final CRC result corresponding to the data to be checked.

[0050] In summary, the CRC verification method provided in this disclosure reduces the complexity of CRC verification and improves the verification efficiency by rearranging multiple parallel block data and using a single CRC verification unit to perform CRC verification on the rearranged parallel block data in parallel. Furthermore, by time-division multiplexing the CRC verification unit, the number of CRC verification units can be reduced, thereby reducing the cost of CRC verification.

[0051] Figure 5 A flowchart illustrating a CRC verification method according to an embodiment of this disclosure is shown. Figure 5 As shown, the embodiment may include the following steps.

[0052] Step 201: Divide the data to be verified into multiple parallel blocks of data. The data to be verified is interleaved coded data.

[0053] In this embodiment of the disclosure, after obtaining the data to be verified, the data to be verified can be divided into multiple parallel blocks according to the parallelism and code length of the data to be verified. Accordingly, the steps of the embodiment may include: determining the code length and parallelism of the data to be verified; dividing the data to be verified into multiple parallel blocks based on the code length and parallelism, wherein each parallel block corresponds to the same number of column elements, and the number of column elements in each parallel block is the ratio of the code length to the parallelism. For example, assuming the code length K = 40 and the parallelism N = 8, ... Figure 3 As shown, each column (i.e., parallel block data) has S = K / N = 5 data (column elements), and each column represents the data processed by a parallel block.

[0054] Step 202: Perform data rearrangement on the column elements in each parallel block data so that the column elements in the same row of multiple parallel block data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data.

[0055] For the specific implementation process of the embodiments disclosed herein, please refer to the relevant description in step 102 of the embodiment, which will not be repeated here.

[0056] Step 203: Configure a preset initial value for the CRC check unit. The preset initial value is that the input bit is 1 and the input data is the first parallel block data in the continuous data block.

[0057] In this embodiment of the disclosure, since out-of-order CRC is used for calculation, the first CRC result of each parallel block of data is its contribution to the final CRC. When the input of the CRC check unit is 0, it does not contribute to the final CRC result. Therefore, the input bit of the CRC check unit can be fixed to 1, and the contribution to the CRC result can be determined by judging the parallel input of each parallel block of data. Figure 4 As shown, given that multiple column elements in the same row of the eight parallel blocks correspond to the same increment step size, the first parallel block of data can reflect the disordered pattern of the other parallel blocks.

[0058] In this embodiment of the disclosure, to reduce the number of CRC check units and lower the cost of CRC verification, a single CRC check unit can be configured for multiple parallel data blocks based on their shared out-of-order characteristics. This is achieved by configuring a preset initial value for the CRC check unit: the input bit is 1, the input data is the first parallel block data in a continuous data block, and the CRC check unit with the preset initial value is used to simultaneously verify multiple parallel data blocks, thus obtaining the first CRC result for each parallel data block. Parallel verification of multiple parallel data blocks under the same preset initial value improves verification efficiency.

[0059] Step 204: Use the CRC check unit with the preset initial value to perform parallel check on each parallel block data to obtain the first CRC result of each parallel block data.

[0060] In the embodiments of this disclosure, corresponding verification circuits can be configured for each parallel block of data, such as... Figure 6 As shown, the verification circuit may include a multiplexer (MUX), an XOR gate, and a flip-flop (D). The input of the multiplexer is connected to the output of the CRC verification unit (serial out-of-order CRC768). In addition to the output value of the CRC verification unit, the multiplexer also inputs the column elements corresponding to different bit positions of the parallel block data. For example... Figure 6As shown, each parallel block of data contains 768 column elements. Taking the first parallel block of data as an example, the multiplexer corresponding to the first parallel block of data, in addition to inputting the output value of the CRC check unit under a preset initial value, also inputs the column elements at different bit positions of the parallel block of data: b0-b767. The multiplexer will input the output value and each column element in each parallel data block into an XOR gate in ascending order of bit position to perform bit XOR superposition operation until the bit XOR superposition operation of the last column element is completed. The trigger then outputs the first CRC result crc_out0 corresponding to the parallel block of data. Accordingly, the implementation steps may include: determining the output value of the CRC check unit under a preset initial value; performing bit XOR superposition operation on the output value and each column element in each parallel data block to obtain the first CRC result of each parallel block of data.

[0061] Step 205: The first CRC result of each parallel block data is merged by the time-division multiplexing CRC check unit to obtain the CRC result of the data to be checked.

[0062] For embodiments of this disclosure, such as Figure 6 As shown, for 8 parallel blocks of data, after parallel processing of the first CRC result of each parallel block of data in step 204 of the embodiment, 8 independent first CRC results corresponding to the 8 parallel blocks of data can be obtained. For the embodiments of this disclosure, as... Figure 6 Stage 2 in the code can time-division multiplex the CRC check unit according to the order of the eight parallel blocks of data from front to back, and merge the first CRC results of the eight parallel blocks of data: crc_out0, crc_out1, crc_out2, crc_out3, crc_out4, crc_out5, crc_out6, and crc_out7. When merging the first CRC results, since the first CRC results of the eight parallel blocks of data are check values ​​of different segments, CRC matrix compensation needs to be performed on the eight parallel blocks of data sequentially. The corresponding parallel matrix is ​​compensated according to its bit position in the parallel block of data, and the compensated second CRC result is bitwise XORed with the first CRC result of the next parallel block of data, until it is bitwise XORed with the first CRC result of the last parallel block of data, thus obtaining the final CRC result corresponding to the data to be checked.

[0063] The implementation steps may include: repeating the following process until the next parallel block data is determined to be the last parallel block data among multiple parallel block data; determining the initial value of the first CRC result of the next parallel block data as the CRC result of the data to be verified; sequentially determining each parallel block data as the current parallel block data according to the data block order from front to back among multiple parallel block data, and time-division multiplexing the CRC verification unit to perform CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, wherein the first parallel block data among multiple parallel block data directly determines the corresponding first CRC result as the initial value of the first CRC result; performing a bit XOR operation between the second CRC result of the current parallel block data and the first CRC result of the next parallel block data to obtain the initial value of the first CRC result of the next parallel block data.

[0064] For example, such as Figure 6 As shown, for 8 parallel block data, when merging the first CRC results of each parallel block data to obtain the CRC result of the data to be checked, the first parallel block data can be determined as the current parallel block data. The CRC check unit is reused, and the first CRC result corresponding to the first parallel block data is directly used as the initial value 'a' of the first CRC result for CRC matrix compensation, resulting in the second CRC result A of the first parallel block data. Then, the second CRC result A can be bitwise XORed with the first CRC result corresponding to the second parallel block data to obtain the initial value 'b' of the first CRC result of the second parallel block data. The second parallel block data is then determined as the current parallel block data, and the CRC check unit is reused to perform CRC matrix compensation on the initial value 'b' of the first CRC result of the second parallel block data, resulting in the second parallel block data. The second CRC result B of the block data; then, the second CRC result B can be bitwise XORed with the first CRC result corresponding to the third parallel block data to obtain the initial value C of the first CRC result of the third parallel block data. The third parallel block data is determined as the current parallel block data. The CRC check unit is reused to perform CRC matrix compensation on the initial value c of the first CRC result of the third parallel block data to obtain the second CRC result C of the third parallel block data; ...; repeat the above process until the current parallel block data is determined to be the second to last parallel block data among the 8 parallel block data, that is, the next parallel block data corresponding to the current parallel block data is the last parallel block data among the multiple parallel block data. At this time, the initial value h of the first CRC result of the last parallel block data can be determined as the final CRC result of the data to be checked.

[0065] In this embodiment of the disclosure, when the time-division multiplexing CRC check unit performs CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, the steps may include: determining the parallel matrix corresponding to the current parallel block data; the time-division multiplexing CRC check unit uses the parallel matrix to perform compensation processing on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

[0066] Accordingly, when using a parallel matrix to compensate the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, the implementation steps may include: inputting the initial value of the first CRC result of the current parallel block data into the corresponding parallel matrix to calculate the influence value of the current parallel block data; performing a bit XOR operation between the influence value of the current parallel block data and the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

[0067] In summary, the CRC verification method provided in this disclosure reduces the complexity of CRC verification and improves the verification efficiency by rearranging multiple parallel block data and using a single CRC verification unit to perform CRC verification on the rearranged parallel block data in parallel. Furthermore, by time-division multiplexing the CRC verification unit, the number of CRC verification units can be reduced, thereby reducing the cost of CRC verification.

[0068] Corresponding to the CRC verification methods provided in the above embodiments, this disclosure also provides a CRC verification device. Since the CRC verification device provided in this disclosure corresponds to the CRC verification methods provided in the above embodiments, the implementation methods of the CRC verification methods are also applicable to the CRC verification device provided in this embodiment, and will not be described in detail in this embodiment.

[0069] Figure 7 This is a schematic diagram of the structure of a CRC verification device 300 provided in an embodiment of this disclosure.

[0070] like Figure 7 The device 300 includes:

[0071] The partitioning module 310 can be used to divide the data to be verified into multiple parallel blocks of data, where the data to be verified is interleaved encoded data.

[0072] The first processing module 320 can be used to perform data rearrangement processing on the column elements in each parallel block data, so that the multiple column elements in the same row of multiple parallel block data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data.

[0073] The determination module 330 can be used to determine the first CRC result of each parallel block of data in parallel using the CRC check unit. The first CRC result is the CRC result obtained by the CRC check unit after checking each parallel block of data with a preset initial value.

[0074] The second processing module 340 can be used to merge the first CRC results of each parallel block of data through a time-division multiplexing CRC check unit to obtain the CRC result of the data to be checked.

[0075] In some embodiments of this disclosure, the partitioning module 310 can be used to determine the code length and parallelism of the data to be verified; the data to be verified is divided into multiple parallel block data based on the code length and parallelism, wherein each parallel block data corresponds to the same number of column elements, and the number of column elements in each parallel block data is the ratio of code length to parallelism.

[0076] In some embodiments of this disclosure, the determining module 330 can be used to configure a preset initial value for the CRC check unit, wherein the preset initial value is that the input bit is 1 and the input data is the first parallel block data in the continuous data block; the CRC check unit configured with the preset initial value is used to perform parallel check on each parallel block data to obtain the first CRC result of each parallel block data.

[0077] In some embodiments of this disclosure, the determining module 330 can be used to determine the output value of the CRC check unit under a preset initial value; and perform a bit XOR superposition operation between the output value and each column element in each parallel data block to obtain the first CRC result of each parallel block data.

[0078] In some embodiments of this disclosure, the second processing module 340 can be used to repeatedly execute the following process until it is determined that the next parallel block data is the last parallel block data among multiple parallel block data, and the initial value of the first CRC result of the next parallel block data is determined as the CRC result of the data to be verified: according to the data block order of multiple parallel block data from front to back, each parallel block data is determined as the current parallel block data in turn, and the CRC verification unit is time-division multiplexed to perform CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, wherein the first parallel block data among multiple parallel block data directly determines the corresponding first CRC result as the initial value of the first CRC result; the second CRC result of the current parallel block data is bit-XORed with the first CRC result of the next parallel block data to obtain the initial value of the first CRC result of the next parallel block data.

[0079] In some embodiments of this disclosure, the second processing module 340 can be used to determine the parallel matrix corresponding to the current parallel block data; the time-division multiplexing CRC check unit uses the parallel matrix to compensate the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

[0080] In some embodiments of this disclosure, the second processing module 340 can be used to input the initial value of the first CRC result of the current parallel block data into the corresponding parallel matrix to calculate the influence value of the current parallel block data; and to perform a bit XOR operation between the influence value of the current parallel block data and the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

[0081] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a communication device 1400 provided in an embodiment of this application. The communication device 1400 can be a network device, a user device, a chip, chip system, or processor that supports the network device in implementing the above methods, or a chip, chip system, or processor that supports the user device in implementing the above methods. This device can be used to implement the methods described in the above method embodiments; for details, please refer to the descriptions in the above method embodiments.

[0082] The communication device 1400 may include one or more processors 1401. The processor 1401 may be a general-purpose processor or a dedicated processor, such as a baseband processor or a central processing unit (CPU). The baseband processor can be used to process communication protocols and communication data, while the CPU can be used to control the communication device (e.g., base station, baseband chip, terminal equipment, terminal equipment chip, DU or CU, etc.), execute computer programs, and process data from the computer programs.

[0083] Optionally, the communication device 1400 may further include one or more memories 1402, on which a computer program 1404 may be stored. The processor 1401 executes the computer program 1404 to cause the communication device 1400 to perform the methods described in the above method embodiments. Optionally, the memory 1402 may also store data. The communication device 1400 and the memory 1402 may be provided separately or integrated together.

[0084] Optionally, the communication device 1400 may also include a transceiver 1405 and an antenna 1406. The transceiver 1405 may be referred to as a transceiver unit, transceiver, or transceiver circuit, etc., and is used to implement the transmission and reception functions. The transceiver 1405 may include a receiver and a transmitter. The receiver may be referred to as a receiver or receiving circuit, etc., and is used to implement the receiving function; the transmitter may be referred to as a transmitter or transmitting circuit, etc., and is used to implement the transmitting function.

[0085] Optionally, the communication device 1400 may further include one or more interface circuits 1407. The interface circuits 1407 are used to receive code instructions and transmit them to the processor 1401. The processor 1401 executes the code instructions to cause the communication device 1400 to perform the methods described in the above method embodiments.

[0086] In one implementation, the processor 1401 may include a transceiver for implementing receive and transmit functions. For example, the transceiver may be a transceiver circuit, an interface, or an interface circuit. The transceiver circuit, interface, or interface circuit for implementing receive and transmit functions may be separate or integrated. The aforementioned transceiver circuit, interface, or interface circuit can be used for reading and writing code / data, or it can be used for transmitting or relaying signals.

[0087] In one implementation, processor 1401 may store computer program 1403, which runs on processor 1401 and causes communication device 1400 to perform the methods described in the above method embodiments. Computer program 1403 may be embedded in processor 1401, in which case processor 1401 may be implemented in hardware.

[0088] In one implementation, the communication device 1400 may include circuitry capable of performing the transmitting, receiving, or communication functions described in the foregoing method embodiments. The processor and transceiver described in this application can be implemented on integrated circuits (ICs), analog ICs, radio frequency integrated circuits (RFICs), mixed-signal ICs, application-specific integrated circuits (ASICs), printed circuit boards (PCBs), electronic devices, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), n-metal-oxide-semiconductor (NMOS), positive-channel metal-oxide-semiconductor (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), etc.

[0089] The communication device described in the above embodiments may be a network device or a user equipment, but the scope of the communication device described in this application is not limited thereto, and the structure of the communication device may vary. Figure 8 The communication device can be a standalone device or part of a larger device. For example, the communication device could be:

[0090] (1) Independent integrated circuit IC, or chip, or chip system or subsystem;

[0091] (2) A collection of one or more ICs, optionally including storage components for storing data and computer programs;

[0092] (3) ASIC, such as modem;

[0093] (4) Modules that can be embedded in other devices;

[0094] (5) Receivers, terminal equipment, smart terminal equipment, cellular phones, wireless equipment, handheld devices, mobile units, vehicle-mounted equipment, network equipment, cloud equipment, artificial intelligence equipment, etc.

[0095] (6) Others, etc.

[0096] For cases where the communication device can be a chip or a chip system, please refer to [link / reference]. Figure 9 The diagram shows the structure of the chip. Figure 9 The chip shown includes a processor 1501 and an interface 1502. There can be one or more processors 1501, and multiple interfaces 1502.

[0097] Optionally, the chip also includes a memory 1503, which is used to store necessary computer programs and data.

[0098] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented by electronic hardware, computer software, or a combination of both. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the functionality using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0099] This application also provides a readable storage medium having instructions stored thereon that, when executed by a computer, implement the functions of any of the above method embodiments.

[0100] This application also provides a computer program product that, when executed by a computer, implements the functions of any of the above method embodiments.

[0101] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer programs. When a computer program is loaded and executed on a computer, it generates, in whole or in part, the processes or functions according to the embodiments of this application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer program can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, a computer program can be transferred from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0102] The embodiments or examples disclosed herein are not exhaustive, but merely illustrative of some embodiments or examples, and are not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment or example can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment or example can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment or example can be arbitrarily interchanged. Furthermore, optional methods or examples in a particular embodiment or example can be arbitrarily combined; moreover, embodiments or examples can be arbitrarily combined. For example, some or all steps of different embodiments or examples can be arbitrarily combined, and a particular embodiment or example can be arbitrarily combined with optional methods or examples of other embodiments or examples.

[0103] In some implementations or embodiments, terms such as “in response to…”, “in the case of…”, “when…”, “when…”, “if…”, etc. in this disclosure can be replaced with each other.

[0104] In some implementations or embodiments, the notation "A or B", "A and / or B", "at least one of A and B", "A in one case, B in another case", "in response to one case A, in response to another case B", etc., may include at least one of the following technical solutions depending on the circumstances: executing A regardless of B, that is, A in some implementations or embodiments; executing B regardless of A, that is, B in some implementations or embodiments; selectively executing A and B, that is, selecting to execute from A and B in some implementations or embodiments; executing both A and B, that is, A and B in some implementations or embodiments.

[0105] In some implementations or embodiments, the terms "including A", "containing A", "for indicating A", and "carrying A" in this disclosure can be interpreted as directly carrying A or indirectly indicating A.

[0106] Furthermore, each element, each row, or each column in the tables involved in this disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0107] Those skilled in the art will understand that the various numerical designations such as "first," "second," etc., involved in this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application, nor do they indicate the order of sequence.

[0108] At least one in this application can also be described as one or more, and multiple can be two, three, four or more, and this application does not impose any limitation. In the embodiments of this application, for a technical feature, the technical features in that technical feature are distinguished by "first", "second", "third", "A", "B", "C" and "D", and there is no order or size among the technical features described by "first", "second", "third", "A", "B", "C" and "D".

[0109] As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (e.g., disk, optical disk, memory, programmable logic device (PLD)) used to provide machine instructions and / or data to a programmable processor, including machine-readable media that receive machine instructions as machine-readable signals. The term "machine-readable signal" refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0110] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0111] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other.

[0112] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0113] In some embodiments, the terms "terminal", "terminal device", "user equipment (UE)", "user terminal", "mobile station (MS)", "mobile terminal (MT)", subscriber station, mobile unit, subscriber unit, wireless unit, remote unit, mobile device, wireless device, wireless communication device, remote device, mobile subscriberstation, access terminal, mobile terminal, wireless terminal, remote terminal, handset, user agent, mobile client, and client can be used interchangeably.

[0114] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0115] Furthermore, it should be understood that the various embodiments of this application can be implemented individually or in combination with other embodiments, where the scheme allows.

[0116] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0118] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A CRC check method, characterized in that, include: The data to be verified is divided into multiple parallel blocks of data, and the data to be verified is interleaved encoded data; The column elements in each parallel block of data are rearranged so that the column elements in the same row of the multiple parallel blocks of data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block of data. The first CRC result of each parallel block of data is determined in parallel using a CRC check unit. The first CRC result is the CRC result obtained by the CRC check unit after checking each parallel block of data using a preset initial value. By time-division multiplexing the CRC check unit, the first CRC results of each parallel block of data are merged to obtain the CRC result of the data to be checked.

2. The method according to claim 1, characterized in that, The process of dividing the data to be verified into multiple parallel blocks includes: Determine the code length and parallelism of the data to be verified; The data to be verified is divided into multiple parallel blocks based on the code length and the parallelism. Each parallel block corresponds to the same number of column elements, and the number of column elements in each parallel block is the ratio of the code length to the parallelism.

3. The method according to claim 1, characterized in that, The method of using a CRC check unit to determine the first CRC result of each parallel block of data in parallel includes: Configure a preset initial value for the CRC check unit. The preset initial value is that the input bit is 1 and the input data is the first parallel block data in the continuous data block. The CRC check unit configured with the preset initial value is used to perform parallel check on each parallel block of data to obtain the first CRC result of each parallel block of data.

4. The method according to claim 3, characterized in that, The step of using a CRC check unit configured with the preset initial value to perform parallel check on each parallel block of data to obtain the first CRC result of each parallel block of data includes: Determine the output value of the CRC check unit under the preset initial value; The output value is then superimposed by performing a bit XOR operation with each column element in each parallel data block to obtain the first CRC result of each parallel block data.

5. The method according to claim 1, characterized in that, The step of merging the first CRC results of each parallel block of data by time-division multiplexing the CRC check unit to obtain the CRC result of the data to be checked includes: Repeat the following process until the next parallel block of data is determined to be the last parallel block of data among the plurality of parallel blocks of data, and determine the initial value of the first CRC result of the next parallel block of data as the CRC result of the data to be verified: According to the data block order of the multiple parallel block data from front to back, each parallel block data is determined as the current parallel block data in turn, and the CRC check unit is time-division multiplexed to perform CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data. In this case, the first parallel block data in the multiple parallel block data directly determines the corresponding first CRC result as the initial value of the first CRC result. Perform a bitwise XOR operation between the second CRC result of the current parallel block data and the first CRC result of the next parallel block data to obtain the initial value of the first CRC result of the next parallel block data.

6. The method according to claim 5, characterized in that, The time-division multiplexing of the CRC check unit performs CRC matrix compensation on the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data, including: Determine the parallel matrix corresponding to the current parallel block data; The CRC check unit is time-division multiplexed, and the initial value of the first CRC result of the current parallel block data is compensated using the parallel matrix to obtain the second CRC result of the current parallel block data.

7. The method according to claim 6, characterized in that, The step of compensating the initial value of the first CRC result of the current parallel block data using the parallel matrix to obtain the second CRC result of the current parallel block data includes: The initial value of the first CRC result of the current parallel block data is input into the corresponding parallel matrix to calculate the influence value of the current parallel block data. The influence value of the current parallel block data is bitwise XORed with the initial value of the first CRC result of the current parallel block data to obtain the second CRC result of the current parallel block data.

8. A CRC verification device, characterized in that, include: The partitioning module is used to divide the data to be verified into multiple parallel blocks of data, wherein the data to be verified is interleaved encoded data; The first processing module is used to perform data rearrangement processing on the column elements in each parallel block data, so that the multiple column elements in the same row of the multiple parallel block data are arranged in ascending order, and the increment step of the multiple column elements is equal to the number of column elements in each parallel block data. The determination module is used to determine the first CRC result of each parallel block data in parallel using the CRC check unit. The first CRC result is the CRC result obtained by the CRC check unit after checking each parallel block data with a preset initial value. The second processing module is used to merge the first CRC results of each parallel block of data by time-division multiplexing the CRC verification unit to obtain the CRC result of the data to be verified.

9. A communication device, wherein, include: transceiver; Memory; The processor, connected to both the transceiver and the memory, is configured to control the wireless signal transmission and reception of the transceiver by executing computer-executable instructions on the memory, and to implement the method of any one of claims 1-7.

10. A computer storage medium, wherein, The computer storage medium stores computer-executable instructions; when executed by a processor, the computer-executable instructions can implement the method of any one of claims 1-7.

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