Flow table unloading system, method, device and cluster

Abstract

The present application provides a flow table unloading system, method, device and cluster. The system includes: the unloading hardware includes multiple storage repositories, each storage repositories includes a storage unit, each storage unit is used to store flow table items; the host includes an index bitmap, the index bitmap includes multiple index groups, there is a one-to-one correspondence between the multiple index groups and the multiple storage repositories, the index group includes multiple index bits, there is a one-to-one correspondence between the multiple index bits and the multiple storage units, the first index bit is selected according to the indication value of each index bit in each index group in the index bitmap, the first storage unit is determined to be used to store the first flow table item, so that the flow table item is evenly distributed in the multiple storage repositories, and the address of the first storage unit and the first flow table item are sent to the unloading hardware; the unloading hardware receives the address of the first storage unit and the first flow table item, and stores the first flow table item in the first storage unit according to the address of the first storage unit.

Description

Technical Field

[0001] The present application relates to the field of data communications, and in particular to a flow table unloading system, method, device and cluster. Background Art

[0002] With the development of cloud computing networks, the amount of data that needs to be forwarded is increasing. In order to reduce the burden on the host, data forwarding can be offloaded to the offload hardware. After data forwarding is offloaded to the offload hardware, the data packets are directly forwarded according to the flow table items stored in the offload hardware without the participation of the host, thereby effectively saving the host's resources. When a large number of data packets need to be processed quickly in the network, being able to quickly and accurately read the flow table items to determine how the data packets are processed is the key to reducing network pressure. If the reading efficiency of the flow table items is inefficient, it will cause delays and packet loss during the processing of data packets, affecting the real-time, throughput and overall performance of the network, and may even cause network congestion and performance bottlenecks. Summary of the invention

[0003] The present application provides a flow table unloading system, method, device and cluster, which can effectively improve the reading efficiency of flow table entries.

[0004] In a first aspect, a flow table unloading system is provided, including:

[0005] The offloading hardware includes a plurality of storage libraries, each storage library includes one or more storage units, and each storage unit is used to store flow table entries;

[0006] A host, comprising an index bitmap, the index bitmap comprising a plurality of index groups, a one-to-one correspondence between the plurality of index groups and the plurality of storage repositories, the index group comprising a plurality of index bits, a one-to-one correspondence between the plurality of index bits and the plurality of storage units, each index bit being used to indicate that a flow table entry is stored in a corresponding storage unit when the indication value is a first value, and indicating that a flow table entry is not stored in the corresponding storage unit when the indication value is a second value, the host being used to select a first index bit according to the indication value of each index bit in each index group in the index bitmap, thereby determining that a first storage unit corresponding to the first index bit is used to store a first flow table entry, so that the flow table entries are evenly distributed in the plurality of storage repositories, and sending the address of the first storage unit and the first flow table entry to the offloading hardware;

[0007] The offloading hardware is further used to receive the address of the first storage unit and the first flow table entry, and store the first flow table entry in the first storage unit according to the address of the first storage unit.

[0008] In the above scheme, the host finds the appropriate location in the offload hardware through the index bitmap, so that the flow table entries can be evenly distributed in different storage repositories of the offload hardware. Since the flow table entries can be read, written, searched, and other operations can be performed simultaneously in different storage repositories, the more evenly the flow table entries are distributed, the more effectively the reading efficiency of the flow table entries can be improved.

[0009] In some possible designs, the host is further configured to store the index value of the first flow table entry in the first index bit, and when the first flow table entry needs to be deleted, determine the address of the first storage unit according to the index value of the first flow table entry and the index bitmap, and send the address of the first storage unit to the offload hardware;

[0010] The uninstallation hardware is further used to delete the first flow table entry in the first storage unit according to the address of the first storage unit.

[0011] In some possible designs, the host is further configured to determine an address of a second storage unit in a second storage repository according to an index value of the second flow table entry and the index bitmap when the second flow table entry needs to be deleted, and send the address of the second storage unit to the offloading hardware;

[0012] The uninstallation hardware is further configured to delete the second flow table entry in the second storage unit according to the address of the second storage unit while deleting the first flow table entry.

[0013] In the above solution, flow table entries in different storage repositories can be deleted at the same time, thereby improving the efficiency of flow table entry deletion.

[0014] In some possible designs, the offload hardware is also used to, when receiving a first data packet and a second data packet, simultaneously read a first flow table entry from a first storage unit of a first storage repository in the offload hardware and read a second flow table entry from a second storage unit of a second storage repository in the offload hardware, forward the first data packet according to the first flow table entry, and forward the second data packet according to the second flow table entry.

[0015] In the above solution, flow table entries can be read from different storage repositories at the same time, and data forwarding can be performed according to the flow table entries, thereby improving the efficiency of data forwarding.

[0016] In some possible designs, the first data packet is a first tunnel packet, and the second data packet is a second tunnel packet.

[0017] In some possible designs, the host is also used to select, based on the indicative values ​​of each index bit in each index group in the index bitmap, an index bit with an indicative value of a second value in the index group with the least number of indicative values ​​of the first value in each index group as the first index bit.

[0018] In some possible designs, the host is further configured to select, from the storage bins, an index bit indicating a second value in an index group corresponding to a storage bin with the largest remaining space as the first index bit.

[0019] In a second aspect, a flow table unloading method is provided, including:

[0020] Providing multiple storage repositories by offloading hardware, each storage repository includes one or more storage units, and each storage unit is used to store flow table entries;

[0021] An index bitmap is provided by a host, the index bitmap includes a plurality of index groups, there is a one-to-one correspondence between the plurality of index groups and the plurality of storage banks, the index group includes a plurality of index bits, there is a one-to-one correspondence between the plurality of index bits and the plurality of storage units, each index bit is used to indicate that a flow table entry is stored in a corresponding storage unit when the indication value is a first value, and indicates that no flow table entry is stored in the corresponding storage unit when the indication value is a second value,

[0022] The host selects a first index bit according to an indication value of each index bit in each index group in the index bitmap, thereby determining that a first storage unit corresponding to the first index bit is used to store a first flow table entry, so that the flow table entry is evenly distributed in a plurality of storage repositories, and sends an address of the first storage unit and the first flow table entry to the offloading hardware;

[0023] The address of the first storage unit and the first flow table entry are received through the offloading hardware, and the first flow table entry is stored in the first storage unit according to the address of the first storage unit.

[0024] In a third aspect, a computing device is provided, comprising a flow table unloading system and a storage unit, wherein the flow table unloading system and the storage unit are capable of communicating with each other, and the flow table unloading system is a system as described in any one of the first aspects.

[0025] In a fourth aspect, a computing device cluster is provided, including a flow table offloading system and a storage unit, wherein the flow table offloading system and the storage unit can communicate with each other, and the flow table offloading system is a system as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0027] Figure 1 It is a structural schematic diagram of a flow table unloading system provided by this application;

[0028] Figure 2 It is a schematic diagram of the structure of a memory provided by this application;

[0029] Figure 3 It is a schematic diagram of the structure of a random access memory provided by the present application;

[0030] Figure 4 It is a structural schematic diagram of a host provided by this application;

[0031] Figure 5 It is a structural schematic diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0032] The embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. The terms used in the implementation mode of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0033] See also Figure 1 , Figure 1 Schematic diagram of a flow table unloading system provided by this application. Figure 1 As shown, the flow table offloading system includes offloading hardware 110 and a host 120 .

[0034] The offload hardware 110 may be a memory. The memory performs data transmission via double data rate (DDR). DDR is a synchronous dynamic random access memory (SDRAM) technology, and mainly includes DDR1, DDR2, DDR3, DDR4 and DDR5. The main feature of DDR is its high data transmission rate, which is achieved by performing data transmission at the rising edge and falling edge of each clock cycle, thereby achieving a double data transmission rate.

[0035] Memory is usually used to store various running software in the operating system, input and output data, and information exchanged with external memory. In order to improve the access speed of the processor, the memory needs to have the advantage of fast access speed. In the traditional computer system architecture, dynamic random access memory (DRAM) is usually used as memory. The processor can access the memory at high speed through the memory controller and perform read and write operations on any storage unit in the memory.

[0036] like Figure 2 As shown, the memory may include one or more Dual-Inline-Memory-Modules (DIMMs) 10 . Figure 2 In the figure, the memory includes two DIMM10 as an example. Usually, a DIMM can be regarded as a memory bar entity. A memory bar has two sides. The high-end memory bar has memory chips on both sides. We call each side a Rank, which means that a memory bar has Rank0 and Rank1. Figure 2 As shown, a DIMM 10 may include one or more Ranks 111 . Each Rank 111 may include a plurality of Random Access Memory (RAM) 112 .

[0037] Data is stored in the memory, and data is stored in the storage unit in the random access memory 112. A storage unit refers to the smallest storage unit (cell) for storing data. Usually, a storage unit can store 1 bit of data. Of course, some storage units can also implement multi-value storage. When the random access memory is DRAM, the storage units in the DRAM (also referred to as DRAM cells) are arranged and distributed into a matrix, which we call a memory bank or a DRAM memory bank. In this way, the storage units in a memory chip can be logically divided into multiple banks, and each bank can be regarded as a storage array composed of multiple storage units. Each memory cell (memory cell) in the memory bank is identified by its row address and column address, and the memory controller can locate any storage unit in the memory bank through the corresponding row and column decoders. The memory bank can also be referred to as a bank.

[0038] like Figure 3As shown, a random access memory including 8 memory banks is used as an example for illustration. The random access memory may include a control and refresh circuit, a plurality of memory banks (memory banks) 1121, a row address buffer, a column address buffer, a row decoder, and a column decoder. Among them, the control and refresh circuit is used to control the refresh operation of the memory cell. Random access memory (for example, DRAM) uses the amount of electricity stored in a capacitor to represent data 0 and 1, and is a volatile memory. Due to the leakage of the capacitor, the charge can only be maintained for a very short time. The leakage of the capacitor causes charge drift, which will cause errors in the stored data. Therefore, in order to store data, the control and refresh circuit needs to automatically perform a refresh operation to refresh and charge the memory cell storing the data to prevent the memory from losing data.

[0039] During the memory access process, after receiving a memory access request, the memory controller generates an address signal and a control signal according to the received memory access request, and sends the generated address signal and control signal to the DIMM to perform memory access. Among them, the address signal may include a row address signal and a column address signal, and the control signal may include a chip select signal (CS), a write enable signal (WE), a column access select signal (CAS), and a row access select signal (RAS). These signals can be received by the control and refresh circuit, the row address signal is cached in the row address buffer, the column address signal is cached in the column address buffer, and the control signal is passed to the storage bank corresponding to the row address specified by the address signal.

[0040] The row address buffer is used to cache the row address signal sent by the memory controller. The column address buffer is used to cache the column address signal sent by the memory controller. The row decoder is connected to the row address buffer and the plurality of memory banks 1121, respectively, and the column decoder is connected to the column address buffer and the plurality of memory banks, respectively. The row decoder is used to decode the row address signal, and the column decoder is used to decode the column address signal, so that the corresponding storage unit in the memory bank 1121 can be located according to the decoded row address signal and column address signal.

[0041] When the memory controller accesses DRAM, the memory controller needs to first identify the storage row corresponding to the data to be accessed and determine the memory bank to which the storage row to be accessed belongs. Then the memory controller will "open" the corresponding memory bank and storage row. In some implementations, the storage row may also be referred to as a "page". A "page" is a logical concept. In this case, a page includes the memory cells of a storage row in DRAM. Typically, the size of a memory page can include 512, 1024 (1K), 2048 (2K), 4098 (4K), 8196 (8K), 16392 (16K), or 32,768 (32K) bits of data.

[0042] Generally, when performing memory access, the storage row to be accessed may be in one of the following three states: row hit, row idle, or row conflict. Row hit means that the storage row to be accessed has been opened, that is, the data of the storage row to be accessed has been loaded into the row buffer corresponding to the storage bank storing the data of the row, and data can be read from the storage unit of the row or written to the storage unit of the row by directly sending a column access command. Among them, the column access command may include a read command or a write command. Row idle is used to indicate that the storage bank corresponding to the storage row to be accessed is in an idle state, no storage row is opened, and the storage row to be accessed needs to be opened by an "activate" command before access. That is, the data of the storage row to be accessed needs to be loaded into the row buffer corresponding to the storage bank by an "activate" command before a column access command can be sent for access. Row conflict is used to indicate that the currently opened storage row is different from the storage row to be accessed. In the case of rowconflict, the currently opened storage row needs to be "closed" first, specifically including using the "precharge" command to write the data of the opened storage row back to the memory array, and then using the activate command to load the data of the row to be accessed into the corresponding row cache, and then send the column access command to access it. In an embodiment of the present invention, the above three states of the storage row to be accessed can be referred to as the row hit state of the storage row. The "storage row" can also be referred to as a "row", and the storage row to be accessed can also be referred to as a target row.

[0043] From the above description, it can be seen that in the process of memory access, different states of the row to be accessed will cause different delays in access. In the state of row hit, since the row to be accessed is already in the open state, the memory controller can directly send a column access command. After sending the column access command, data can be read from the memory or written to the memory. In the case where the column access command is a read command, the read data can be obtained after a delay. In the case of row idle, since no row is opened in the memory bank, the row to be accessed needs to be opened by the "activate" command before access. Therefore, the memory controller needs to send a row activation command first, wait for the delay, and then send a column access command to access the open row. In the case where the column access command is a read command, it is necessary to wait for a delay before obtaining the read data. In the case of row conflict, since the currently open row is not the row to be accessed, you need to first send a pre-charge command to close the currently open row, wait for a delay, then send a row activation command to open the row to be accessed, and then wait for a delay before sending a column access command to access the row to be accessed. If the column access command is a read command, after sending the column access command, you need to wait for a delay to obtain the read data.

[0044] Each storage repository of the offload hardware 110 includes one or more storage units, each of which can be used to store a flow table entry.

[0045] The host 120 may be a central processing unit (CPU) or a processing core of a CPU. Figure 4 As shown, the host includes a memory address register 201, a memory data register 202, a program counter 203, an instruction register 204, an instruction decoder 205, an operation controller 207, a calculation unit 208, a general register group 209, an accumulator 210, a program status word register 211, a timing circuit 212 and a processor bus 220. The processor bus 220 can also be a data bus, a power bus, a control bus or a status signal bus, etc. In addition, the host is connected to the memory 240 via a DDR bus 230.

[0046] The host is used to process instructions and data stored in the memory 240. In some embodiments, the instructions may include one or more instruction formats. The instruction format may indicate various fields (number of bits, position of bits, etc.) to specify the data processing operation to be performed and the operand on which the operation is to be performed. Some instruction formats may be further defined by instruction templates (or sub-formats).

[0047] In the host, the memory address register 201 is used to store the address of the memory 240 currently to be accessed by the host 120. The memory data register 202 is used to store the data and read or write instructions read or written from the address by the host 120 to make up for the difference in operating speed between the processor and the memory.

[0048] The timing circuit 212 provides a time reference for each component through a fixed clock. The time for the host 120 to execute an instruction is an instruction cycle. The program counter 203 is used to store the address of the next instruction. When the instructions are executed sequentially, the program counter 203 automatically adds the number of bytes of an instruction after each instruction is taken. When a transfer instruction is encountered, the program counter 203 specifies the address of the next instruction through the address code field in the transfer instruction. The instruction register 204 is used to save the instruction currently being executed. The instruction includes two fields, an operation code and an address code. The operation code part is decoded by the instruction decoder 205 to generate the control potential of the operation required by the instruction. The operation controller 207 can generate various operation control signals based on the control potential signal output by the instruction decoder and the timing signal generated by the timing circuit 212, and control the remaining components of the host to complete the operation of fetching and executing instructions.

[0049] A microinstruction is the smallest unit of instructions executed by a processor. An instruction can be a single microinstruction or composed of several microinstructions. An instruction composed of multiple microinstructions is called a complex instruction. Various mechanisms can be used to implement the decoding of complex instructions by the instruction decoder 205. Specific decoding mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), microcode read-only memories (ROMs), and the like. In one embodiment, the steps of the microinstructions corresponding to the complex instructions can be stored in the microcode read-only memory 206. During the decoding process, the instruction decoder 205 can query and obtain the operation code and address code of the microinstructions constituting the complex instructions from the microcode read-only memory 206, and decode the operation code part of the microinstructions in turn to generate the control potential required by the microinstructions.

[0050] The operation controller 207 has multiple buffers, and can send the decoded instructions to their respective reservation stations for storage according to the types of instructions. After analyzing the status of the hardware circuit of the computing unit and the specific situation of whether each instruction can be executed in advance, the instructions that can be executed in advance are scheduled to the corresponding computing unit 208 for execution. During this period, the instruction stream is reordered so that the instruction pipeline can proceed and be smoothly scheduled. Exemplarily, for instructions of integer calculation, the operation controller 207 can use the integer reservation station to save instructions and assign them to the integer computing unit for calculation; for instructions of floating-point calculation, the operation controller 207 can use the floating-point reservation station to save instructions and assign them to the floating-point computing unit for calculation.

[0051] The general register group 209 is used to store the data corresponding to the address code according to the address code of the instruction. The calculation unit 208 is used to receive the operation control signal of the operation controller 207 and perform calculations on the data stored in the general register group 209, including arithmetic operations (including basic operations such as addition, subtraction, multiplication and additional operations) and logical operations (including shifting, logical testing or comparison of two values). The temporary variables generated in the calculation are stored in the accumulator 210, and the information of the generated status is stored in the program status word register 211, such as the operation result carry / borrow flag (C), the operation result overflow flag (O), the operation result zero flag (Z), the operation result negative flag (N), the operation result sign flag (S), etc. The program status word register is also used to save information such as interrupts and the working status of the computing device, so that the host 120 can timely understand the machine operation status and program operation status.

[0052] The calculation unit 208 includes a variety of different circuit modules, which can be used to execute different instructions. For example, the integer calculation unit 2081 and the floating point calculation unit 2082 are used to perform arithmetic operations and logical operations on integers and floating point numbers, respectively.

[0053] Figure 1 In the example, only one offloading hardware is used. In actual applications, the number of offloading hardware may be one or more. When there are multiple offloading hardware, different types of offloading hardware may be of the same type or different types, which is not specifically limited here. Figure 1As shown, the host 120 includes an index bitmap. The index bitmap includes multiple index groups (for example, a first index group, a second index group, and a third index group). There is a one-to-one correspondence between multiple index groups and multiple storage libraries. For example, when the multiple index groups include the first index group, the second index group, and the third index group, and the storage library includes the first storage library, the second storage library, and the third storage library, there is a correspondence between the first index group and the first storage library, a correspondence between the second index group and the second storage library, and a correspondence between the third index group and the third storage library. The index group includes multiple index bits, and there is a one-to-one correspondence between multiple index bits and multiple storage units. For simplicity, the figure only illustrates the correspondence between the first index bit in the first index group and the first storage unit in the first storage library, and the correspondence between the second index bit in the second index group and the second storage unit in the second storage library. There is also a correspondence between other index bits and storage units. Each index bit includes an index value and an indication value. The index value of each index bit is used to store the index value of the flow table entry, and the indication value is used to indicate whether the index bit stores a flow table entry. Each index bit is used to indicate that a flow table entry is stored in the corresponding storage unit when the indication value is a first value, and to indicate that no flow table entry is stored in the corresponding storage unit when the indication value is a second value. For example, when the indication value of the index bit is "0", it indicates that a flow table entry is stored in the corresponding storage unit, and when the indication value of the index bit is "1", it indicates that no flow table entry is stored in the corresponding storage unit. Alternatively, when the indication value of the index bit is "1", it indicates that a flow table entry is stored in the corresponding storage unit, and when the indication value of the index bit is "0", it indicates that no flow table entry is stored in the corresponding storage unit.

[0054] The host is used to select the first index bit according to the indication value of each index bit in each index group in the index bitmap. For example, the first index group has 3 index bits, wherein the indication value of one index bit is the first value, the second index group has 3 index bits, wherein the indication value of two index bits is the first value, the third index group has 3 index bits, wherein the indication value of two index bits is the first value, and the indication value of the first index bit in the first index group is the second value, then the first index bit can be selected. For another example, the host selects the index bit with the second value indication value in the index group corresponding to the storage library with the most remaining space in the storage library as the first index bit. The host determines that the first storage unit corresponding to the first index bit is used to store the first flow table entry, so that the flow table entry is evenly distributed in multiple storage libraries. Since there is a corresponding relationship between the first index bit and the first storage unit, it can be determined that the first storage unit corresponding to the first index bit is used to store the first flow table entry, and the address of the first storage unit and the first flow table entry are sent to the unloading hardware. Specifically, the host can select, according to the indication value of each index bit in each index group in the index bitmap, the index bit with the second value in the index group with the least number of indication values ​​of the first value in each index group as the first index bit. The host is also used to store the index value of the first flow table entry in the first index bit.

[0055] The offloading hardware is further used to receive the address of the first storage unit and the first flow table entry, and store the first flow table entry in the first storage unit according to the address of the first storage unit.

[0056] When the host needs to delete the first flow table entry, the host determines the address of the first storage unit according to the index value and the index bitmap of the first flow table entry, and sends the address of the first storage unit to the unloading hardware. The host is also used to determine the address of the second storage unit in the second storage library according to the index value and the index bitmap of the second flow table entry when it needs to delete the second flow table entry, and send the address of the second storage unit to the unloading hardware. The unloading hardware is also used to delete the first flow table entry in the first storage unit according to the address of the first storage unit, and when deleting the first flow table entry, delete the second flow table entry in the second storage unit according to the address of the second storage unit.

[0057] Optionally, the offloading hardware is also used to read the first flow table entry from the first storage unit of the first storage library in the offloading hardware and the second flow table entry from the second storage unit of the second storage library in the offloading hardware when receiving the first data packet and the second data packet, forward the first data packet according to the first flow table entry, and forward the second data packet according to the second flow table entry. The first data packet is a first tunnel packet, and the second data packet is a second tunnel packet. Here, the first tunnel packet and the second tunnel packet are merely used as a specific example of the first data packet and the second data packet. In actual applications, the first data packet may also be other packets, and the second data packet may also be other packets, which are not specifically limited here.

[0058] See also Figure 5 , Figure 5 4 is a schematic diagram of a computing device provided by the present application. The computing device 400 includes: one or more processing units 410 , a communication interface 420 and a memory 430 .

[0059] The processing unit 410, the communication interface 420 and the memory 430 are interconnected via a bus 440. Optionally, the computing device 400 may also include an input / output interface 450, which is connected to an input / output device for receiving parameters set by a user, etc. The computing device 400 can be used to implement part or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processing unit 410 can also be used to implement part or all of the operation steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 400 can refer to the specific details in the above-mentioned embodiment, such as the processing unit 410 is used to perform part or all of the steps in the above-mentioned method embodiment or part or all of the operations in the above-mentioned method embodiment. For another example, in the embodiment of the present application, the computing device 400 can be used to implement part or all of the functions of one or more components in the above-mentioned device embodiment, and the communication interface 420 can be specifically used for the communication functions necessary to implement the functions of these devices and components, and the processing unit 410 can be specifically used for the processing functions necessary to implement the functions of these devices and components, etc.

[0060] Figure 5 The computing device 400 may include one or more processing units 410, and the multiple processing units 410 may provide processing capabilities in a coordinated manner in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the multiple processing units 410 may constitute a processor sequence or a processor array, or the multiple processing units 410 may be divided into a main processor and an auxiliary processor, or the multiple processing units 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 5 The computing device 400 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 5 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0061] The processing unit 410 may have a variety of specific implementation forms. For example, the processing unit 410 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processing unit 410 may also be a single-core processor or a multi-core processor. The processing unit 410 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processing unit 410 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices, the wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., the wireless interface may be a cellular network interface or a wireless local area network interface, etc. The processing unit 410 may also be equipped with one or more random access memories, and the one or more random access memories are used to store flow table entries.

[0062] The memory 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The memory 430 may also be used to store program codes and data, so that the processing unit 410 calls the program codes stored in the memory 430 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 5 Show more or fewer components, or have different component configurations.

[0063] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0064] The present application also provides a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0065] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one network site, computer, server or data center to another network site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or it can be a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape, etc.), an optical medium (e.g., a DVD, etc.), or a semiconductor medium (e.g., a solid-state hard disk), etc. In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A flow table unloading system, characterized in that: include: The offloading hardware includes a plurality of storage repositories, each storage repositories includes a plurality of storage units, each storage unit can be used to store flow table entries; A host, comprising an index bitmap, the index bitmap comprising a plurality of index groups, a one-to-one correspondence between the plurality of index groups and the plurality of storage repositories, the index group comprising a plurality of index bits, a one-to-one correspondence between the plurality of index bits and the plurality of storage units, each index bit being used to indicate that a flow table entry is stored in a corresponding storage unit when the indication value is a first value, and indicating that a flow table entry is not stored in the corresponding storage unit when the indication value is a second value, the host being used to select a first index bit according to the indication value of each index bit in each index group in the index bitmap, thereby determining that a first storage unit corresponding to the first index bit is used to store a first flow table entry, so that the flow table entries are evenly distributed in the plurality of storage repositories, and sending the address of the first storage unit and the first flow table entry to the offloading hardware; The offloading hardware is further used to receive the address of the first storage unit and the first flow table entry, and store the first flow table entry in the first storage unit according to the address of the first storage unit.

2. The system according to claim 1, characterized in that The host is further configured to store the index value of the first flow table entry in the first index bit, determine the address of the first storage unit according to the index value of the first flow table entry and the index bitmap when the first flow table entry needs to be deleted, and send the address of the first storage unit to the offloading hardware; The uninstallation hardware is further used to delete the first flow table entry in the first storage unit according to the address of the first storage unit.

3. The system according to claim 2, characterized in that The host is further configured to determine the address of the second storage unit in the second storage repository according to the index value of the second flow table entry and the index bitmap when the second flow table entry needs to be deleted, and send the address of the second storage unit to the offloading hardware; The uninstallation hardware is further configured to delete the second flow table entry in the second storage unit according to the address of the second storage unit while deleting the first flow table entry.

4. The system according to claim 1, characterized in that The offloading hardware is also used to, when receiving a first data packet and a second data packet, simultaneously read a first flow table entry from a first storage unit of a first storage repository in the offloading hardware and read a second flow table entry from a second storage unit of a second storage repository in the offloading hardware, forward the first data packet according to the first flow table entry, and forward the second data packet according to the second flow table entry.

5. The system according to claim 4, characterized in that The first data packet is a first tunnel packet, and the second data packet is a second tunnel packet.

6. The system according to claim 1, characterized in that The host is further configured to select, according to the indication value of each index bit in each index group in the index bitmap, an index bit having an indication value of the second value in the index group having the least number of indication values ​​of the first value in each index group as the first index bit.

7. The system according to claim 1, characterized in that The host is further configured to select, from the storage bins, an index bit whose indication value is the second value in the index group corresponding to the storage bin with the largest remaining space as the first index bit.

8. A flow table unloading method, characterized in that: include: Providing a plurality of storage repositories by offloading hardware, each storage repositories comprising a plurality of storage units, each storage unit being used to store flow table entries; An index bitmap is provided by a host, the index bitmap includes a plurality of index groups, there is a one-to-one correspondence between the plurality of index groups and the plurality of storage banks, the index group includes a plurality of index bits, there is a one-to-one correspondence between the plurality of index bits and the plurality of storage units, each index bit is used to indicate that a flow table entry is stored in a corresponding storage unit when the indication value is a first value, and indicates that no flow table entry is stored in the corresponding storage unit when the indication value is a second value, The host selects a first index bit according to an indication value of each index bit in each index group in the index bitmap, thereby determining that a first storage unit corresponding to the first index bit is used to store a first flow table entry, so that the flow table entry is evenly distributed in a plurality of storage repositories, and sends an address of the first storage unit and the first flow table entry to the offloading hardware; The address of the first storage unit and the first flow table entry are received through the offloading hardware, and the first flow table entry is stored in the first storage unit according to the address of the first storage unit.

9. A computing device, characterized in that It comprises a flow table unloading system and a storage unit, the flow table unloading system and the storage unit can communicate with each other, and the flow table unloading system is a system as described in any one of claims 1-7.

10. A computing device cluster, characterized in that: It comprises a flow table unloading system and a storage unit, the flow table unloading system and the storage unit can communicate with each other, and the flow table unloading system is a system as described in any one of claims 1-7.

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