A method for addressing equipment in a battery management system

Abstract

The present application discloses an addressing method for devices in a battery management system, including: a master device sends an address clearing instruction to a first slave device through a differential signal line; the first slave device sends a first response message to the master device through a differential signal line to indicate whether the first slave device has a first preset address, and if the first preset address exists, it is cleared and the address valid state bit of the first slave device is set to a first value; the master device outputs a first PWM signal carrying the first address to the first slave device through an addressing signal line; the first slave device uses the parsed first address as the address of the first slave device, modifies the address valid state bit of the first slave device to a second value, and sends the first indication to the master device through a differential interface; if the master device confirms that the address of the first slave device carried in the first indication is the same as the address carried in the first PWM signal, the master device stops sending the first PWM signal to the first slave device. By adopting the present application, the operation process is simple and no manual operation is required.

Description

Technical Field

[0001] The present application relates to the technical field of battery management system equipment, and in particular to an addressing method for equipment in a battery management system. Background Art

[0002] As we all know, in commercial storage BMS (Battery Management System), the DC side voltage is usually increased by connecting battery modules in series. Each battery module in series requires a BMU (Battery Management Unit) for management. In order to achieve the positioning management and precise maintenance of each battery module, the associated BMU needs to set a unique address ID as an identity.

[0003] In the prior art, the method of setting a unique address ID for a BMU is usually:

[0004] 1> The scheme of using multi-position DIP switches is adopted. The DIP switches are manually adjusted before installation. The corresponding high and low levels are generated in the circuit and transmitted to the detection unit in the BMU. The detection unit parses the address ID according to the level signal to complete the addressing. The defects of this scheme are: 1. The DIP switches need to be exposed on the outer layer to facilitate manual adjustment during maintenance, but the exposure increases the risk of human error, which can easily lead to address ID errors; 2. The versatility is poor and there are many limitations. The number of BMUs varies in actual application. Especially when encountering a scenario with an increase in BMUs, more holes need to be expanded to add multi-position DIP switches, and the hardware needs to add detection circuits to adapt. In the long run, it takes too much space and cost, and it is impossible to expand indefinitely; 3. The overall efficiency is low. It takes more than 5 seconds to address a single BMU during application;

[0005] 2> Use software to reserve empty addresses. Before installation, manually set the address command to BMU through special equipment. BMU parses the address ID according to the command content to complete the addressing. The defects of this solution are: 1. The development cycle and cost increase, and additional special equipment components need to be developed for address ID setting; 2. On-site management is difficult. BMUs with address IDs need to be classified and managed according to address IDs, and they need to be reset after confusion and errors; 3. The overall efficiency is low, and single BMU addressing takes a long time when applied. Summary of the invention

[0006] In order to solve the above technical problems, the present application provides an addressing method for a device in a battery management system, wherein the battery management system comprises: a master device and a first slave device, wherein the addressing method comprises:

[0007] The master device sends an address clear instruction to the first slave device through a differential signal line;

[0008] In response to the received address clearing instruction, the first slave device sends a first response message indicating whether the first slave device has a first preset address to the master device through a differential signal line; if the first slave device has the first preset address, the first preset address is cleared, and the address valid state bit of the first slave device is set to a first value; and the first slave device sets its differential interface for connecting the differential signal line to a silent mode;

[0009] In response to receiving the first response information, the master device outputs a first PWM signal carrying a first address to the first slave device through an addressing signal line;

[0010] After receiving the first PWM signal, the first slave device uses the parsed first address as the address of the first slave device, modifies the address valid status bit of the first slave device to a second value, and sends a first indication carrying the address of the first slave device and the modified address valid status bit of the first slave device to the master device through the differential interface of which the silent mode has been released;

[0011] In response to receiving the first indication, if the master device confirms that the address of the first slave device carried in the first indication is the same as the address carried in the first PWM signal, the master device stops sending the first PWM signal to the first slave device, and addressing of the first slave device is completed.

[0012] In an optional implementation manner, the battery management system further includes: a second slave device; and the addressing method further includes:

[0013] The master device sends an address clear instruction to the second slave device through a differential signal line;

[0014] In response to receiving the address clearing instruction, the second slave device sends a second response message indicating whether the second slave device has a second preset address to the master device through a differential signal line, and if the second slave device has a second preset address, clears the second preset address and sets the address valid status bit of the second slave device to a first value; and sets the differential interface used to connect the differential signal line to a silent mode;

[0015] When the first slave device detects that the master device stops sending the first PWM signal to the first slave device, the first slave device increases its own address by a preset value to obtain a second address, and outputs a second PWM signal carrying the second address to the second slave device through the addressing signal line;

[0016] After receiving the second PWM signal, the second slave device uses the parsed second address as the address of the second slave device, modifies the address valid status bit of the second slave device to a second value, and sends a second indication carrying the address of the second slave device and the modified address valid status bit of the second slave device to the first device and the master device through the differential interface of which the silent mode has been released;

[0017] In response to receiving the second indication, if the first slave device confirms that the address of the first device in the second indication is the same as the address in the second PWM signal, the first slave device stops sending the second PWM signal to the second slave device, and addressing of the second slave device is completed;

[0018] When the second slave device detects that the first slave device stops sending the second PWM signal to the second slave device, the second slave device increases its own address by a preset value to obtain a third address, and outputs a third PWM signal carrying the third address to the master device through the addressing signal line;

[0019] In response to receiving the third PWM signal, if the master device confirms that the address valid status bits of the first slave device and the second slave device carried in the first indication and the second indication are both the second value, the master device confirms that the addresses of the first slave device and the second slave device are both successfully addressed.

[0020] In an optional implementation manner, after the master device confirms that the addresses of the first slave device and the second slave device are both successful, the addressing method further includes:

[0021] In response to receiving an addressing success indication sent by the master device through the differential signal line; the second slave device stops sending the third PWM signal to the master device;

[0022] In an optional implementation manner, the first address includes: an address commonly corresponding to the frequency of the first PWM signal and the duty cycle of the first PWM signal;

[0023] The second address includes: an address commonly corresponding to the frequency of the second PWM signal and the duty cycle of the second PWM signal;

[0024] The third address includes: an address commonly corresponding to the frequency of the third PWM signal and the duty cycle of the third PWM signal.

[0025] In an optional implementation manner, the first address includes: an address corresponding to the frequency of the first PWM signal;

[0026] The second address includes: an address corresponding to the frequency of the second PWM signal;

[0027] The third address includes: an address corresponding to the frequency of the third PWM signal.

[0028] In an optional implementation manner, the first address includes: an address corresponding to a duty cycle of the first PWM signal;

[0029] The second address includes: an address corresponding to the duty cycle of the second PWM signal;

[0030] The third address includes: an address corresponding to the duty cycle of the third PWM signal.

[0031] In an optional implementation manner, the differential interface includes any one of the following:

[0032] CAN communication network interface, RS-485 communication interface, RS232 communication interface;

[0033] The differential signal lines include: CAN communication lines, RS-485 communication lines or RS232 communication lines.

[0034] In an optional implementation manner, the preset value is any positive integer;

[0035] When the first value is 0, the second value is 1; when the first value is 1, the second value is 0.

[0036] In an optional implementation manner, after the master device confirms that the addresses of the first slave device and the second slave device are both successfully addressed, the method further includes:

[0037] The master device receives first target information sent by the first device through the differential signal line and second target information sent by the second device through the differential signal line, respectively; wherein the first target information carries the address valid status bit of the first slave device, and the second target information carries the address valid status bit of the second slave device;

[0038] The master device determines in real time whether the address of the first slave device is wrong by judging the valid state bit of the address of the first slave device in the first target information, and determines in real time whether the address of the second slave device is wrong by judging the valid state bit of the address of the second slave device in the second target information;

[0039] If it is confirmed that the valid state bit of the address of the first slave device in the first target information is the second value, the address of the first slave device is correct; if it is confirmed that the valid state bit of the address of the first slave device in the second target information is the second value, the address of the second slave device is correct.

[0040] In an optional implementation manner, the second slave device detects that the first slave device stops sending the second PWM signal to the second slave device, including:

[0041] When the second slave device does not receive the second PWM signal sent by the first slave device within a preset time, the second slave device determines that the first slave device stops sending the second PWM signal to the second slave device.

[0042] In an optional implementation manner, the second slave device detects that the first slave device stops sending the second PWM signal to the second slave device, specifically including:

[0043] If the second slave device does not receive the second PWM signal sent again by the first slave device within a preset time starting from the moment the second slave device receives the second PWM signal, the second slave device determines that the first slave device stops sending the second PWM signal to the second slave device.

[0044] The present application provides an addressing method for devices in a battery management system, wherein the battery management system includes: a master device and a first slave device; the addressing method includes: the master device sends an address clearing instruction to the first slave device through a differential signal line; in response to the received address clearing instruction, the first slave device sends a first response information indicating whether the first slave device has a first preset address to the master device through the differential signal line, if the first slave device has the first preset address, the first preset address is cleared, and the address valid status bit of the first slave device is set to a first value; and the first slave device sets its own differential interface for connecting the differential signal line to a silent mode. In response to receiving the first response information, the master device outputs a first PWM signal carrying the first address to the first slave device through the addressing signal line. After receiving the first PWM signal, the first slave device uses the parsed first address as the address of the first slave device, sets the address valid status bit of the first slave device to a second value, and sends the first indication carrying the address of the first slave device and the address valid status bit of the first slave device to the master device through the differential interface that has been released from the silent mode. In response to receiving the first indication, if the master device confirms that the address of the first slave device carried in the first indication is the same as the address carried in the first PWM signal, the master device stops sending the first PWM signal to the first slave device, and the addressing of the first slave device is completed. With the present application, the operation process is simple, the degree of automation is high, and no special equipment is required for manual operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1is a schematic flow chart of a method for addressing devices in a battery management system provided by the present application;

[0047] Figure 2 is a schematic flow chart of another method for addressing devices in a battery management system provided by the present application;

[0048] Figure 3 It is a schematic diagram of the connection between devices in a battery management system provided by the present application;

[0049] Figure 4 It is a connection diagram between devices in another battery management system provided by the present application;

[0050] Figure 5 This is another schematic diagram of connections between devices in a battery management system provided by the present application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in this application to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] It should be noted that the first, second, and third in this application are only used to distinguish different devices, different preset addresses, different addresses, different PWM signals, different values, etc., and have no other meanings and should not limit the scope of protection of this application.

[0053] See also Figure 1 , is a flow chart of a method for addressing a device in a battery management system provided by the present application, such as Figure 1 Specifically, the addressing method may include but is not limited to the following steps:

[0054] S101. A master device sends an address clear instruction to a first slave device via a differential signal line.

[0055] In the embodiment of the present application, the battery management system includes but is not limited to: a master device, a first slave device;

[0056] The above differential signal lines may include but are not limited to: CAN communication lines, RS485 communication lines, RS232 communication lines or other twisted pairs. Among them, the above differential signal lines use twisted pairs to transmit signals such as address clearing instructions, and the transmitted instructions or signals have strong anti-interference performance. Among them,

[0057] The differential signal line may include but is not limited to: a communication line H and a communication line L, that is, the communication line H and the communication line L are a pair of twisted pairs;

[0058] The CAN communication line includes: a communication line CANH and a communication line CANL, that is, the communication line CANH and the communication line CANL are a pair of twisted pairs;

[0059] The RS485 communication line includes: a communication line 485A and a communication line 485B, that is, the communication line 485A and the communication line 485B are a pair of twisted pairs.

[0060] The RS232 communication line includes: a communication line 232A and a communication line 232B, that is, the communication line 232A and the communication line 232B are a pair of twisted pairs.

[0061] S102 . In response to the received address clearing instruction, the first slave device sends first response information indicating whether the first slave device has a first preset address to the master device through a differential signal line.

[0062] In an embodiment of the present application, the first preset address may be a physical address; optionally, the first preset address is: 2.

[0063] S103: If the first slave device has a first preset address, clear the first preset address and set the address valid status bit of the first slave device to a first value; and the first slave device sets its differential interface for connecting the differential signal line to a silent mode.

[0064] In the embodiment of the present application, the first value can be 0 or 1.

[0065] The differential interface includes any one of the following:

[0066] CAN communication network interface, RS485 communication interface, RS232 communication.

[0067] The first slave device sets its differential interface for connecting the differential signal line to silent mode, specifically:

[0068] The first slave device sets its differential interface for connecting the differential signal line to a mode capable of receiving information but not capable of sending information.

[0069] S104 , in response to receiving the first response information, the master device outputs a first PWM (Pulse Width Modulation) signal carrying a first address to the first slave device through an addressing signal line.

[0070] In the embodiment of the present application, the first address may include but is not limited to any of the following:

[0071] The first type: an address commonly corresponding to the frequency of the first PWM signal and the duty cycle of the first PWM signal; for example, the address commonly corresponding to the frequency of the first PWM signal and the duty cycle of the first PWM signal can take the value of: any positive integer within the number range of devices in the battery management system, that is, the address commonly corresponding to the frequency of the first PWM signal and the duty cycle of the first PWM signal can take the value of 1;

[0072] The second type: the address corresponding to the frequency of the first PWM signal; for example, the address corresponding to the frequency of the first PWM signal and the duty cycle of the first PWM signal may take the value of: any positive integer within the number of devices in the battery management system, that is, the address corresponding to the frequency of the first PWM signal may take the value of 1;

[0073] The third type: the address corresponding to the duty cycle of the first PWM signal; for example, the address corresponding to the frequency of the first PWM signal and the duty cycle of the first PWM signal can take the value of: any positive integer within the range of the number of devices in the battery management system, that is, the address corresponding to the duty cycle of the first PWM signal can take the value of 1.

[0074] Table 1 shows an example of a corresponding table of addresses corresponding to a frequency and a duty cycle. As shown in Table 1,

[0075] Table 1

[0076]

[0077] S105 . After receiving the first PWM signal, the first slave device uses the parsed first address as the address of the first slave device, and modifies the valid state bit of the address of the first slave device to a second value.

[0078] In the embodiment of the present application, the second value may be 0 or 1;

[0079] It should be noted that when the first value is 0, the second value is 1; when the first value is 1, the second value is 0.

[0080] S106: The first device sends a first indication carrying the address of the first slave device and the modified valid status bit of the address of the first slave device to the master device through the differential interface of the first device which has been released from silent mode.

[0081] S107. In response to receiving the first indication, if the master device confirms that the address of the first slave device carried in the first indication is the same as the address carried in the first PWM signal, the master device stops sending the first PWM signal to the first slave device, and addressing of the first slave device is completed.

[0082] In an embodiment of the present application, in response to receiving the first indication, if the master device confirms that the address of the first slave device carried in the first indication is the same as the address carried in the first PWM signal, the master device stops sending the first PWM signal to the first slave device through the addressing signal line, and the address of the first slave device has been addressed.

[0083] Figure 1 It is only used to illustrate the embodiments of the present application and should not limit the scope of protection of the present application.

[0084] See also Figure 2 , is another flow chart of a method for addressing a device in a battery management system provided by the present application, such as Figure 2 As shown,

[0085] Specifically, the addressing method may include but is not limited to the following steps:

[0086] S201. The master device sends an address clear instruction to the first slave device through a differential signal line, and sends an address clear instruction to the second slave device through a differential signal line.

[0087] The differential signal lines in the embodiment of the present application can refer to the above description and will not be repeated here.

[0088] S202. In response to a received address clear instruction, the first slave device sends, via a differential signal line, first response information for indicating whether the first slave device has a first preset address; in response to a received address clear instruction, the second slave device sends, via a differential signal line, second response information for indicating whether the second slave device has a second preset address.

[0089] In an embodiment of the present application, the first preset address may be a physical address; optionally, the first preset address is: 3.

[0090] S203. If the first slave device has a first preset address, the first preset address is cleared, and the address valid status bit of the first slave device is set to a first value; and the first slave device sets its own differential interface for connecting the differential signal line to silent mode; if the second slave device has a second preset address, the second preset address is cleared, and the address valid status bit of the second slave device is set to the first value; and the second slave device sets its own differential interface for connecting the differential signal line to silent mode.

[0091] In the embodiment of the present application, the second slave device sets its differential interface for connecting the differential signal line to a silent mode, specifically:

[0092] The second slave device sets its differential interface for connecting the differential signal line to a mode capable of receiving information but not capable of sending information.

[0093] S204 , in response to receiving the first response information, the master device outputs a first PWM signal carrying a first address to the first slave device through an addressing signal line.

[0094] S205 . After receiving the first PWM signal, the first slave device uses the parsed first address as the address of the first slave device, and modifies the valid state bit of the address of the first slave device to a second value.

[0095] S206: The first slave device sends a first indication carrying the address of the first slave device and the modified valid status bit of the address of the first slave device to the master device through the differential interface of which the silent mode has been released.

[0096] S207 . In response to receiving the first indication, if the master device confirms that the address of the first slave device carried in the first indication is the same as the address carried in the first PWM signal, the master device stops sending the first PWM signal to the first slave device.

[0097] S208 . When the first slave device detects that the master device stops sending the first PWM signal to the first slave device, the first slave device increases its own address by a preset value to obtain a second address.

[0098] In the embodiment of the present application, the second address may include but is not limited to any of the following:

[0099] The first type: an address commonly corresponding to the frequency of the second PWM signal and the duty cycle of the second PWM signal; for example, the address commonly corresponding to the frequency of the second PWM signal and the duty cycle of the second PWM signal can take the value of: any positive integer within the number range of devices in the battery management system, that is, the address commonly corresponding to the frequency of the second PWM signal and the duty cycle of the second PWM signal can take the value of 1;

[0100] The second type: the address corresponding to the frequency of the second PWM signal; for example, the address corresponding to the frequency of the second PWM signal and the duty cycle of the second PWM signal may take the value of: any positive integer within the number of devices in the battery management system, that is, the address corresponding to the frequency of the second PWM signal may take the value of 1;

[0101] The third type: the address corresponding to the duty cycle of the second PWM signal; for example, the address corresponding to the frequency of the second PWM signal and the duty cycle of the second PWM signal can take the value of: any positive integer within the range of the number of devices in the battery management system, that is, the address corresponding to the duty cycle of the second PWM signal can take the value of 1.

[0102] S209: The first slave device outputs a second PWM signal carrying a second address to the second slave device through the addressing signal line.

[0103] S210: After receiving the second PWM signal, the second slave device uses the parsed second address as the address of the second slave device, and modifies the valid state bit of the address of the second slave device to a second value.

[0104] S211, the second slave device sends a second indication carrying the address of the second slave device and the valid status bit of the address of the second slave device to the master device through its differential interface which has been released from the silent mode, and the second slave device sends a second indication carrying the address of the second slave device and the modified valid status bit of the address of the second slave device to the first slave device through its differential interface which has been released from the silent mode.

[0105] S212: In response to receiving the second indication, if the first slave device confirms that the address of the second slave device carried in the second indication is the same as the address carried in the second PWM signal, the first device stops sending the second PWM signal to the second slave device.

[0106] S213: When the second slave device detects that the first slave device stops sending the second PWM signal to the second slave device, the second slave device increases its own address by a preset value to obtain a third address.

[0107] In the embodiment of the present application, the second slave device detects that the first slave device stops sending the second PWM signal to the second slave device, which may include but is not limited to:

[0108] If the second slave device does not receive the second PWM signal sent again by the first slave device within a preset time starting from the moment the second slave device receives the second PWM signal, the second slave device determines that the first slave device stops sending the second PWM signal to the second slave device. The preset time can be 2s.

[0109] S214: The second slave device outputs a third PWM signal carrying a third address to the master device through the addressing signal line.

[0110] In the embodiment of the present application, the third address may include but is not limited to any of the following:

[0111] The first type: an address commonly corresponding to the frequency of the third PWM signal and the duty cycle of the third PWM signal; for example, the address commonly corresponding to the frequency of the third PWM signal and the duty cycle of the third PWM signal can take the value of: any positive integer within the number range of devices in the battery management system, that is, the address commonly corresponding to the frequency of the third PWM signal and the duty cycle of the third PWM signal can take the value of 1;

[0112] The second type: an address corresponding to the frequency of the third PWM signal; for example, the address corresponding to the frequency of the third PWM signal and the duty cycle of the third PWM signal may take the value of: any positive integer within the number of devices in the battery management system, that is, the address corresponding to the frequency of the third PWM signal may take the value of 1;

[0113] The third type: the address corresponding to the duty cycle of the third PWM signal; for example, the address corresponding to the frequency of the third PWM signal and the duty cycle of the third PWM signal can take the value of: any positive integer within the range of the number of devices in the battery management system, that is, the address corresponding to the duty cycle of the third PWM signal can take the value of 1.

[0114] S215. In response to receiving the third PWM signal, if the master device confirms that the address valid status bits of the first slave device and the second slave device carried in the first indication and the second indication are both the second value, it is confirmed that the addresses of the first slave device and the second slave device are both successfully addressed.

[0115] In the embodiment of the present application, after the master device confirms that the addresses of the first slave device and the second slave device are both successful, the addressing method further includes but is not limited to the following steps:

[0116] In response to receiving an addressing success indication sent by the master device through the differential signal line; the second slave device stops sending the third PWM signal to the master device.

[0117] It should be noted that after the master device confirms that the addresses of the first slave device and the second slave device are successfully addressed, the following steps are also included but not limited to:

[0118] The master device receives first target information sent by the first device through the differential signal line and second target information sent by the second device through the differential signal line, respectively; wherein the first target information carries the address valid status bit of the first slave device, and the second target information carries the address valid status bit of the second slave device;

[0119] The master device determines in real time whether the address of the first slave device is wrong by judging the valid state bit of the address of the first slave device in the first target information, and determines in real time whether the address of the second slave device is wrong by judging the valid state bit of the address of the second slave device in the second target information;

[0120] If it is confirmed that the valid state bit of the address of the first slave device in the first target information is the second value, the address of the first slave device is correct; if it is confirmed that the valid state bit of the address of the first slave device in the second target information is the second value, the address of the second slave device is correct.

[0121] It should be noted that when the battery management system includes but is not limited to: a master device, a first slave device, a second slave device, ..., an Nth slave device, wherein N is a positive integer greater than 2, that is, the master device is a BMS master device, the first slave device is a BMS slave device 1, the second slave device is a BMS slave device 2, ..., the Nth slave device is a BMS slave device N, and the differential signal lines are communication lines H and L. For details, please refer to Figure 3 .

[0122] Figure 3 An exemplary method of transmitting directly through differential signal lines in a battery management system is shown. For details, see Figure 3 As shown,

[0123] The data clearing instruction, the first response information, the first indication, the second response information, and the second indication are transmitted between the BMS slave device 1, the BMS slave device 2, ..., and the BMS slave device N through the communication line H and the communication line L.

[0124] It should be noted that the BMS slave device 1, the BMS slave device 2, ..., the BMS slave device N transmit the first PWM signal, the second PWM signal, and the third PWM signal through the addressing signal line.

[0125] Optionally, the master device is a BMS master device, the first slave device is a BMS slave device 1, the second slave device is a BMS slave device 2, ..., the Nth slave device is a BMS slave device N, and the differential signal line is a CAN communication line, and the CAN communication line includes a communication line CANH and a communication line CANL. For details, please refer to Figure 4 .

[0126] Figure 4 This example shows a method in which a device in a battery management system transmits directly through a CAN communication line. For details, see Figure 4 As shown,

[0127] The data clearing instruction, the first response information, the first indication, the second response information, and the second indication are transmitted between the BMS slave device 1, the BMS slave device 2, ..., and the BMS slave device N through the communication line CANH and the communication line CANL.

[0128] Optionally, the master device is a BMS master device, the first slave device is a BMS slave device 1, the second slave device is a BMS slave device 2, ..., the Nth slave device is a BMS slave device N, the differential signal line is an RS485 communication line, and the RS485 communication line includes: communication line 485A and communication line 485B as an example, for details, please refer to Figure 5 .

[0129] Figure 5This example shows a method in which a device in a battery management system transmits directly through an RS485 communication line. For details, see Figure 5 As shown,

[0130] The data clearing instruction, the first response information, the first indication, the second response information, and the second indication are transmitted between the BMS slave device 1, the BMS slave device 2, ..., and the BMS slave device N through the communication line CANH and the communication line CANL.

[0131] Figure 2-Figure 5 It is only used to explain the embodiments of the present application and should not limit the scope of protection of the present application.

[0132] Those of ordinary skill in the art will appreciate that the devices and algorithm steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0133] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and systems can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the composition and steps of each example are described. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0135] The embodiments of the systems and devices described above are merely illustrative. For example, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, systems or units, or may be electrical, mechanical or other forms of connection.

[0136] Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0137] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for addressing equipment in a battery management system, characterized in that: The battery management system includes: a master device and a first slave device; the addressing method includes: The master device sends an address clear instruction to the first slave device through a differential signal line; In response to the received address clearing instruction, the first slave device sends a first response message indicating whether the first slave device has a first preset address to the master device through a differential signal line; if the first slave device has the first preset address, the first preset address is cleared, and the address valid state bit of the first slave device is set to a first value; and the first slave device sets its differential interface for connecting the differential signal line to a silent mode; In response to receiving the first response information, the master device outputs a first PWM signal carrying a first address to the first slave device through an addressing signal line; After receiving the first PWM signal, the first slave device uses the parsed first address as the address of the first slave device, modifies the address valid status bit of the first slave device to a second value, and sends a first indication carrying the address of the first slave device and the modified address valid status bit of the first slave device to the master device through the differential interface of which the silent mode has been released; In response to receiving the first indication, if the master device confirms that the address of the first slave device carried in the first indication is the same as the address carried in the first PWM signal, the master device stops sending the first PWM signal to the first slave device, and addressing of the first slave device is completed.

2. The method for addressing a device in a battery management system according to claim 1, characterized in that: The battery management system further includes: a second slave device; the addressing method further includes: The master device sends an address clear instruction to the second slave device through a differential signal line; In response to receiving the address clearing instruction, the second slave device sends a second response message indicating whether the second slave device has a second preset address to the master device through a differential signal line; if the second slave device has a second preset address, the second preset address is cleared, and the address valid status bit of the second slave device is set to a first value; and the differential interface used to connect the differential signal line is set to a silent mode; When the first slave device detects that the master device stops sending the first PWM signal to the first slave device, the first slave device increases its own address by a preset value to obtain a second address, and outputs a second PWM signal carrying the second address to the second slave device through the addressing signal line; After receiving the second PWM signal, the second slave device uses the parsed second address as the address of the second slave device, modifies the address valid status bit of the second slave device to a second value, and sends a second indication carrying the address of the second slave device and the modified address valid status bit of the second slave device to the first device and the master device through the differential interface of which the silent mode has been released; In response to receiving the second indication, if the first slave device confirms that the address of the first device in the second indication is the same as the address in the second PWM signal, the first slave device stops sending the second PWM signal to the second slave device, and addressing of the second slave device is completed; When the second slave device detects that the first slave device stops sending the second PWM signal to the second slave device, the second slave device increases its own address by a preset value to obtain a third address, and outputs a third PWM signal carrying the third address to the master device through the addressing signal line; In response to receiving the third PWM signal, if the master device confirms that the address valid status bits of the first slave device and the second slave device carried in the first indication and the second indication are both the second value, the master device confirms that the addresses of the first slave device and the second slave device are both successfully addressed.

3. The method for addressing a device in a battery management system according to claim 2, characterized in that: After the master device confirms that the addresses of the first slave device and the second slave device are both successful, the addressing method further includes: In response to receiving an addressing success indication sent by the master device through the differential signal line; the second slave device stops sending the third PWM signal to the master device.

4. The method for addressing a device in a battery management system according to claim 3, characterized in that: The first address includes: an address commonly corresponding to the frequency of the first PWM signal and the duty cycle of the first PWM signal; The second address includes: an address commonly corresponding to the frequency of the second PWM signal and the duty cycle of the second PWM signal; The third address includes: an address commonly corresponding to the frequency of the third PWM signal and the duty cycle of the third PWM signal.

5. The method for addressing a device in a battery management system according to claim 3, characterized in that: The first address includes: an address corresponding to the frequency of the first PWM signal; The second address includes: an address corresponding to the frequency of the second PWM signal; The third address includes: an address corresponding to the frequency of the third PWM signal.

6. The method for addressing a device in a battery management system according to claim 3, characterized in that: The first address includes: an address corresponding to the duty cycle of the first PWM signal; The second address includes: an address corresponding to the duty cycle of the second PWM signal; The third address includes: an address corresponding to the duty cycle of the third PWM signal.

7. The method for addressing a device in a battery management system according to claim 4, characterized in that: The differential interface includes any one of the following: CAN communication network interface, RS485 communication interface, RS232 communication interface; The differential signal lines include: CAN communication lines, RS485 communication lines or RS232 communication lines.

8. The method for addressing a device in a battery management system according to claim 2, characterized in that: The preset value is any positive integer; When the first value is 0, the second value is 1; when the first value is 1, the second value is 0.

9. The method for addressing a device in a battery management system according to claim 2, characterized in that: After the master device confirms that the addresses of the first slave device and the second slave device are both successfully addressed, the method further includes: The master device receives first target information sent by the first device through the differential signal line and second target information sent by the second device through the differential signal line, respectively; wherein the first target information carries the address valid status bit of the first slave device, and the second target information carries the address valid status bit of the second slave device; The master device determines in real time whether the address of the first slave device is wrong by judging the valid state bit of the address of the first slave device in the first target information, and determines in real time whether the address of the second slave device is wrong by judging the valid state bit of the address of the second slave device in the second target information; If it is confirmed that the valid state bit of the address of the first slave device in the first target information is the second value, the address of the first slave device is correct; if it is confirmed that the valid state bit of the address of the first slave device in the second target information is the second value, the address of the second slave device is correct.

10. The method for addressing a device in a battery management system according to claim 2, characterized in that: The second slave device detects that the first slave device stops sending the second PWM signal to the second slave device, specifically comprising: If the second slave device does not receive the second PWM signal sent again by the first slave device within a preset time starting from the moment the second slave device receives the second PWM signal, the second slave device determines that the first slave device stops sending the second PWM signal to the second slave device.

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