Clock control method and electronic device thereof

Abstract

A clock control method for a high definition multimedia interface (HDMI) receiving device operating in a power saving mode in the receiving device is provided. The HDMI receiving device has a first module, a second module, and a third module. The clock control method includes the following phases. A clock signal can be transmitted to the first module and the third module during a first region of received data. Transmission of the clock signal to the second module is inhibited during the first region of the received data. During a second region of the received data, the clock signal is enabled for transmission to the third module, and transmission of the clock signal to the first module and the second module is inhibited.

Description

Technical Field

[0001] The present invention relates to a clock control method, and in particular to a clock control method of a High Definition Multimedia Interface (HDMI) receiving device in a receiving device. Background Art

[0002] Fast switching between different HDMI ports is required in HDMI applications. Due to High-Bandwidth Digital Content Protection (HDCP) encryption, the sink device should be synchronized with the source HDCP state of the source device. The HDCP encryption state is based on the frame counter and AVMUTE control. The frame counter and AVMUTE control rely on the signal transmitted through the HDMI channel.

[0003] However, turning on all HDMI ports to synchronize all HDMI channel signals may result in high power consumption. Summary of the invention

[0004] One embodiment of the present invention provides a clock control method of a high-definition multimedia interface (HDMI) receiving device in a receiving device, the HDMI receiving device operates in a power saving mode and has a first module, a second module and a third module. The clock control method includes the following stages. In a first area of ​​received data, a clock signal is enabled to be sent to the first module and the third module. In the first area, a clock signal is disabled to be sent to the second module. In a second area of ​​received data, a clock signal is enabled to be sent to the third module, and a clock signal is disabled to be sent to the first module and the second module.

[0005] According to the clock control method, the first area receiving data is the power-on area of ​​the frame. The second area receiving data is the power-off area of ​​the frame. The power-on area is a group of queues containing HDCP information of the frame, and the power-off area is the remaining queues that do not contain HDCP information of the frame.

[0006] According to the above clock control method, the third module includes a power switch controller and a synchronization module.

[0007] According to the clock control method, the first module includes a decoder, a timing detector and a HDCP encryption detector.

[0008] According to the above clock control method, the second module includes an HDCP password related module and an audio related module.

[0009] According to the clock control method, the synchronization module maintains synchronization between the sink device and the source device.

[0010] According to the above clock control method, the HDCP information includes AVMUTE control information and HDCP control information.

[0011] According to the above clock control method, the clock signal is a fixed rate link (FRL) clock or a transition minimized differential signaling (TMDS) clock.

[0012] An embodiment of the present invention also provides an electronic device. The electronic device includes a group of first circuits, a group of second circuits, a plurality of clock switches and a controller. Each clock switch is electrically connected to the first module and the second module and receives a clock signal. The controller is electrically connected to the clock switch and sends an enable signal or a disable signal to the clock switch. The controller enables the clock switch to send the clock signal to the first group of circuits through the enable signal. The controller disables the clock switch through the disable signal, so that when the clock signal is enabled to be sent to the first group of circuits, the clock signal is not sent to the second group of circuits.

[0013] According to the electronic device, the controller receives data including a power-on region and a power-off region in a frame from the source device. The power-on region is a group of queues including HDCP information of the frame, and the power-off region is the remaining queues not including HDCP information of the frame.

[0014] According to the electronic device, when the first area of ​​each frame is received, the first group of circuits includes a power switch controller, a synchronization module, a decoder, a timing detector, an HDCP encryption detector module and a power switch controller. The second group of circuits includes an HDCP encryption related module and an audio related module.

[0015] According to the electronic device, when the second area of ​​each frame is received, the first group of circuits includes a power switch controller and a synchronization module. The second group of circuits includes a decoder, a timing detector, an HDCP encryption detector module, a power switch controller and a synchronization module.

[0016] According to the above electronic device, the synchronization module maintains synchronization between the electronic device and the source device.

[0017] According to the above electronic device, the HDCP information includes AVMUTE control information and HDCP control information.

[0018] According to the electronic device, the clock signal is a fixed rate link (FRL) clock or a transition minimized differential signaling (TMDS) clock.

[0019] According to the above-mentioned electronic device, the electronic device is an HDMI sink device among the sink devices.

[0020] According to the electronic device, the first area is a power-on area of ​​a frame in the source device, and the second area is a power-off area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention may be more fully understood by reading the following detailed description and by referring to the accompanying drawings, in which:

[0022] Figure 1 is a flow chart of a clock control method of a high-definition multimedia interface (HDMI) receiving device operating in a power saving mode according to some embodiments of the present invention.

[0023] Figure 2 is a schematic diagram of a frame structure according to some embodiments of the present invention.

[0024] Figure 3 is a schematic diagram of High-bandwidth Digital Content Protection (HDCP) encryption according to some embodiments of the present invention.

[0025] Figure 4 is a schematic diagram of an electronic device 400 according to some embodiments of the present invention. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objects, features and advantages of certain embodiments of the present invention easier to understand, the following is a detailed description with reference to the accompanying drawings.

[0027] Certain terms are used throughout the description and in subsequent claims to refer to specific components. As those skilled in the art will appreciate, electronic device manufacturers may refer to a component by different names. This document does not intend to distinguish between components that have different names but the same function. It should be understood that the words "include", "have" and "comprise" are used in an open-ended manner and should therefore be interpreted as "including but not limited to...". Therefore, when the terms "include", "have" and / or "comprise" are used in the present invention, they are used to indicate the presence of specific technical features, values, method steps, operations, units and / or components. However, this does not exclude the possibility of adding more technical features, values, method steps, working processes, units, components or any combination of the above.

[0028] Directional terms used throughout the description and subsequent claims, such as: "upper", "above", "above", "lower", "below", "front", "rear", "back", "left", "right", etc., refer only to directions in the drawings. Therefore, these directional terms are used to explain and not to limit the present invention. With respect to the drawings, the drawings illustrate the general characteristics of the methods, structures and / or materials used in particular embodiments. However, the drawings should not be interpreted as defining or limiting the scope or properties covered by these embodiments. For example, the relative size, thickness, and position of each layer, each region, and / or each structure may be reduced or exaggerated for clarity.

[0029] When a component such as a layer or a region is referred to as being “on another component”, it may be directly on the other component, or other components may exist between them. On the other hand, when a component is referred to as being “directly on another component (or a variation thereof)”, there are no components between them. In addition, when a corresponding component is referred to as being “on another component”, the corresponding component and the other component have an arrangement relationship along the top view / vertical direction, the corresponding component may be located below or above the other component, and the arrangement relationship along the top view / vertical direction is determined by the orientation of the device.

[0030] It should be understood that when a component or layer is referred to as being “connected to” another component or layer, it can be directly connected to the other component or layer, or intervening components or layers may exist between them. In contrast, when a component is referred to as being “directly connected to” another component or layer, there are no intervening components or layers.

[0031] The electrical connection or coupling described herein may refer to direct connection or indirect connection. In the case of direct connection, the component terminals on the two circuits are directly connected or connected to each other through conductor segments, and in the case of indirect connection, switches, diodes, capacitors, inductors, resistors, other appropriate components, or combinations of the above components exist between the component terminals on the two circuits, but the intermediate components are not limited to these.

[0032] The terms "first", "second", "third", "fourth", "fifth", and "sixth" are used to describe components. They are not used to indicate priority or advanced relationship, but are only used to distinguish components with the same name.

[0033] It should be noted that the technical features of different embodiments described below may be replaced, recombined or mixed with each other to constitute another embodiment without departing from the spirit of the present invention.

[0034] Figure 1 1 is a flow chart of a clock control method of an HDMI receiving device operating in a power saving mode according to some embodiments of the present invention. The HDMI receiving device comprises a first module, a second module and a third module. The HDMI receiving device is located in the receiving device. Figure 1As shown, the clock control method of the HDMI receiving device includes the following stages. In the first area of ​​the received data, the clock signal is enabled to be sent to the first module and the third module, and the clock signal is disabled to be sent to the second module (step S100). In the second area of ​​the received data, the clock signal is enabled to be sent to the third module, and the clock signal is disabled to be sent to the first module and the second module (step S102). In some embodiments, in step S100, the clock signal is enabled to be sent to the first module and the third module by an enable signal, and the clock signal is disabled to be sent to the second module by a disable signal, but the present invention is not limited thereto. In some embodiments, the enable signal and the disable signal are from a controller, but the present invention is not limited thereto.

[0035] In some embodiments, the clock control method of the present invention further receives data having a first area and a second area in a frame from a source device. In some embodiments, the data has an HDMI frame structure. The first area is a group of (data) queues containing HDCP information of the frame, and the second area is a remaining (data) queue that does not contain HDCP information of the frame.

[0036] When the sink device enters power-saving mode, the HDCP information in the first area is still required by the sink device for decrypting the encrypted data from the source device to achieve fast switching between different HDMI ports. Therefore, when receiving data in the first area from the source device, the HDMI sink device must be powered on. In other words, when in power-saving mode, the first area is the power-on area of ​​the HDMI sink device.

[0037] On the other hand, the second area of ​​the frame from the source device does not contain the HDCP information required for decryption. Therefore, when receiving data in the second area from the source device, the HDMI sink device must be powered off. That is, when in power saving mode, the first area is the power-on area and the second area is the power-off area of ​​the HDMI sink device.

[0038] HDCP information includes AVMUTE control information and HDCP control information. Detailed description of the power-on area and the power-off area may be described in the following Figure 2. In step S100, when the shutdown region of the frame is received, the first module includes a power switch controller and a synchronization module. In some embodiments, the power switch controller provides power to the first module and the second module. Even if the first module and the second module receive power from the power switch controller, they will not operate if the clock signal is not received. In some embodiments, the synchronization module maintains synchronization between the receiving device and the source device. In step S102, when the shutdown region of the frame is received, the second module includes the remaining modules except the power switch controller and the synchronization module.

[0039] In some embodiments, in step S100, when the power-on region of each frame is received, the first module includes a power switch controller, a synchronization module, a decoder, a timing detector, and an HDCP encryption detector module. In some embodiments, the decoder module and the HDCP encryption detector module decode the encrypted data stream from the source device so that the receiving device can obtain correct video data and audio data. In some embodiments, the timing detector detects the timing so that the clock signal can be sent to the first module in sequence according to the HDMI specification. In step S102, when the power-on region of each frame is received, the second module includes the remaining modules except the power switch controller, the synchronization module, the decoder, the timing detector, and the HDCP encryption detector module. In some embodiments, the clock signal in steps S100 and S102 is a fixed rate link (FRL) clock or a transition minimized differential signal (TMDS) clock, but the present invention is not limited to this.

[0040] Figure 2 Schematic diagram of the framework structure according to some embodiments of the present invention. Figure 2 As shown, the framework 200 includes a power-on region 202 located between the data queue L1 and the data queue L2, and a power-off region located between the data queues L0 and L1, and between the data queues L2 and L3. In some embodiments, Figure 2The frame 200 in is the frame when the receiving device is in the power saving mode. That is, when the receiving device is in the power saving mode, the power-on area 202 containing the HDCP information of the frame 200 is located between the data queue L1 and the data queue L2, and the power-off area is the remaining queues that do not contain the frame HDCP information, for example, between the data queues L0 and L1, and between the data queues L2 and L3. In some embodiments, the frame 200 also includes video data 210. However, when the receiving device is in the power saving mode, since the video data 210 is located in the power-off area, the video data 210 will be ignored. In some embodiments, the power-on area 202 includes sub-area 204, sub-area 206, and sub-area 208. Sub-area 204 includes a VSYNC active edge. In some embodiments, for clock synchronization, the power is turned on a few pixels before the VSYNC active edge of sub-area 204. Sub-area 206 and sub-area 208 contain the HDCP information of the frame 200. Sub-area 206 includes AVMUTE control information. Sub-region 208 includes HDCP control information. In some embodiments, the power is turned on within one queue period after the VSYNC active edge, such as the period when data queue L2 is turned on, to observe the HDCP information including AVMUTE control information and HDCP control information. In some embodiments, the power is turned off at other times for power saving mode. According to the HDMI specification, the AVMUTE control information in sub-region 206 is transmitted between the VSYNC active edge of sub-region 204 and 384 pixels after the VSYNC active edge.

[0041] According to the HDCP specification, HDCP control information is transmitted between 512 pixels and 528 pixels after the VSYNC active edge. In some embodiments, the data length of the AVMUTE control information is 32 pixels. The data length of the HDCP control information is 16 pixels. In some embodiments, when the receiving device is in normal mode, the framework 200 will include a power-on area but not a power-off area. That is, the power-on area in normal mode may be located between data queue L0 and data queue L3, but the present invention is not limited to this.

[0042] Figure 3 is a schematic diagram of high-bandwidth digital content protection (HDCP) encryption according to some embodiments of the present invention. Figure 3 As shown, when performing HDCP encryption, the source device or sink device of the present invention combines the parameter stream riv and the count number inputCtr to obtain a combined stream p. For example, the data size of the parameter stream riv is 64 bits, the data size of the count number inputCtr is 64 bits, and thus the data size of the combined stream p is 128 bits. Then, the source device or sink device of the present invention inputs the combined stream p to the Advanced Encryption Standard (AES) algorithm 300 operating in the CTR mode (in Figure 3 The present invention is not limited to the algorithm here. In addition, the source device or receiving device of the present invention also performs an XOR operation on the parameter stream Ks and the parameter stream lc128 to obtain a calculation result, and inputs the calculation result to the AES algorithm 300. Next, the source device or receiving device of the present invention encrypts the combined stream p and the calculation result to obtain the key stream 310. In some embodiments, the data size of the calculation result is 128 bits, and the data size of the key stream 310 is also 128 bits, but the present invention is not limited to this. Then, the clock control method of the present invention performs an XOR operation on the key stream 310 and the input data 330 to obtain the encrypted stream 320. In some embodiments, the input data 330 may be Figure 2 In some embodiments, the source device sends the encrypted stream 320 to the receiving device of the present invention via an HDMI cable. Afterwards, the receiving device performs the operation according to the video 210 in the normal mode and the power saving mode. Figure 2 The encrypted stream 320 is decoded by using the AVMUTE control information and the HDCP control information received in the frame 200 in the receiving device. In some embodiments, the parameter streams riv, Ks and lc128 are determined after the receiving device is started. Therefore, if the receiving device in the power saving mode can synchronize the input count inputCtr from the source device through the HDCP control information in the frame 200, the receiving device can decode the encrypted stream 320 to obtain the input data 330. In detail, the input count inputCtr is sensed by a 64-bit counter. The 64-bit counter includes a 38-bit frame number and a 26-bit data number. From the beginning of HDCP encryption, each time an HDCP encryption enable signal (such as an enable signal ENC_EN) is received, the frame number increases by one. After each 128-bit key stream 310 is generated, the data number increases by one. In some embodiments, the frame number shall not be reset at any other time. The data number should be reset each time the enable signal ENC_EN is received. In some embodiments, for unencrypted frames, the input count inputCtr should not change. For example, the input count inputCtr may not change when the SET_AVMUTE signal of the sub-region 206 in the power-on region 202 is received, but may change when the ENC_EN signal of the sub-region 208 in the power-on region 202 is received. According to the above rules, the source device can complete the HDCP encryption to output the encrypted stream 320, and the sink device can decode the encrypted stream 320 according to the AVMUTE control information and the HDCP control information to restore the input data 330.

[0043] Figure 4 4 is a schematic diagram of an electronic device 400 according to some embodiments of the present invention. In some embodiments, the electronic device 400 may be an HDMI receiving device in a receiving device, but the present invention is not limited thereto. Figure 4As shown, the electronic device 400 includes a physical layer (PHY) 402, a media access control layer (MAC) 404, a plurality of clock switches, such as clock switches 410-1, 410-2, ..., 410-K, clock switches 420-1, 420-2, ..., 420-M, a controller 412, and a clock selector 414. In some embodiments, the physical layer 402 includes a plurality of functional modules, such as modules 406-1, 406-2, ..., 406-K. K is an integer greater than two. The MAC layer 404 includes a plurality of functional modules, such as modules 408-1, 408-2, ..., 408-M. M is an integer greater than two. K and M may be the same or different. In some embodiments, modules 406-1, 406-2, ..., 406-K in the physical layer 402 are used to perform analog signal processing, and modules 408-1, 408-2, ..., 408-M in the MAC layer 404 are used to perform digital signal processing. In some embodiments, data 430 is input to the physical layer 402 for analog processing, and data 430 is input to the MAC layer 404 for digital processing.

[0044] like Figure 4 As shown, clock switch 410-1 is electrically connected to module 406-1. Clock switch 410-2 is electrically connected to module 406-2. Clock switch 410-K is electrically connected to module 406-K. Clock switch 420-1 is electrically connected to module 408-1. Clock switch 420-2 is electrically connected to module 408-2. Clock switch 420-M is electrically connected to module 408-M. Controller 412 is electrically connected to clock switches 410-1, 410-2, ..., 410-K and clock switches 420-1, 420-2, ..., 420-M. Clock selector 414 is also electrically connected to clock switches 410-1, 410-2, ..., 410-K and clock switches 420-1, 420-2, ..., 420-M. Clock selector 414 is electrically connected to FRL clock 440 and TMDS clock 450.

[0045] In some embodiments, the clock switches 410-1, 410-2, ..., 410-K and the clock switches 420-1, 420-2, ..., 420-M receive a clock signal from the clock selector 414 respectively. The clock signal can be an FRL clock 440 or a TMDS clock 450, based on the HDMI version, such as HDMI 1.4 or HDMI 2.0, but the present invention is not limited thereto. In some embodiments, the controller 412 sends an enable signal or a disable signal to the clock switches 410-1, 410-2, ..., 410-K and the clock switches 420-1, 420-2, ..., 420-M to enable or disable the corresponding clock switches. In some embodiments, the controller 412 receives data in a frame including a power-on region and a power-off region from the source device (such as Figure 2 ). The power-on region is a set of queues containing HDCP information for a frame, and the power-off region is the remaining queues for frames that do not contain HDCP information. In some embodiments, when the receiving device is in power saving mode and the power-on region of each frame is received, the controller 412 sends an enable signal to the clock switches 410-1, 410-2, ..., 410-K and the clock switches 420-1, 420-2, ..., 420-(M-1) so that the clock signal can be sent to the modules 406-1, 406-2, ..., 406-K and the modules 408-1, 408-2, ..., 408-(M-1). Conversely, the controller 412 sends a disable signal to the clock switch 420-M so that the clock signal cannot be sent to the module 408-M. In this embodiment, the modules 406-1, 406-2, ..., 406-K and the modules 408-1, 408-2, ..., 408-(M-1) receiving the clock signal in the power-on region in the power-saving mode may be a power switch controller, a synchronization module, a decoder, a timing detector, and an HDCP encryption detector module. Module 408-M may be an HDCP password-related module and an audio-related module. That is, when the receiving device is in the power-saving mode and the power-on region of each frame is received, the power switch controller, the synchronization module, the decoder, the timing detector, and the HDCP encryption detector module are enabled to receive the clock signal, while the HDCP password-related module and the audio-related module are disabled to receive the clock signal.

[0046] In other embodiments, when the receiving device is in the power saving mode and the power-down region of the frame is received, the controller 412 sends an enable signal to the clock switch 410-2 and the clock switch 420-2, so that the clock signal can be sent to the module 406-2 of the physical layer 402 and the module 408-2 of the MAC layer 404. Conversely, the controller 412 sends a disable signal to the modules 410-1, 410-3, ..., 410-K and the modules 420-1, 420-3, ..., 420-M, so that the clock signal cannot be sent to the modules 406-1, 406-3, ..., 406-K of the physical layer 402, and the clock signal cannot be sent to the modules 408-1, 408-3, ..., 408-M of the MAC layer 404. In this embodiment, the module 406-2 may be a power switch controller of the physical layer 402, and the module 408-2 may be a synchronization module of the MAC layer 404. That is, when the receiving device is in power saving mode and the shutdown region of the frame is received, most modules can be disabled except for the power switch controller and the synchronization module. The synchronization module maintains synchronization between the receiving device and the source device. In some embodiments, when the receiving device is in normal mode, all modules in the physical layer 402 and the MAC layer 404 are enabled.

[0047] For the sake of clarity, the power switch controller and synchronization module of the HDMI receiving device 400 are enabled to receive the clock signal to maintain the power switch function and the frame counting function. The power switch controller is configured to turn on and off the modules 406-1, 406-2, ... 406-K, 408-1, 408-2, ... 408-M in the physical layer 402 and the MAC layer 404. The synchronization module is a frame counter that continues the frame counting when receiving data from the source device input. The power switch function and the frame counting function are essential for the HDMI receiving device in the power saving mode. In addition, when the HDMI receiving device 400 is in the power saving mode, the HDCP password-related module and the audio-related module are disabled to receive the clock signal. When the HDMI receiving device 400 operates in the power saving mode, the clock gating state of the decoder, the timing detector, and the HDCP encryption detector depends on the received data. If the area of ​​the received data contains HDCP information, the decoder, the timing detector, and the HDCP encryption detector are enabled by the controller 412 to receive the clock signal. In contrast, if the area of ​​the received data does not contain the HDCP information, the decoder, the timing detector, and the HDCP encryption detector are disabled by the controller 412 to receive the clock signal.

[0048] Assume that a receiving device includes four HDMI ports, such as port #1, port #2, port #3, and port #4. In some embodiments, the four HDMI ports are electrically connected to respective source devices. The HDMI receiving device of port #1 is initially in normal mode. The HDMI receiving devices of ports #2, #3, and #4 are in power saving mode. When the HDMI receiving devices of ports #2, #3, and #4 are in power saving mode, each HDMI receiving device of ports #2, #3, and #4 still receives HDCP information including AVMUTE control information and HDCP control information in the power-on area of ​​each frame. When the HDMI receiving device of port #1 is transferred to power saving mode, the HDMI receiving device of port #2 is transferred to normal mode, while the HDMI receiving devices of ports #3 and #4 remain in power saving mode, and the HDMI receiving device of port #2 can immediately decode the encrypted stream according to the HDCP information received in the previous power saving mode to recover the video and audio data, so that the receiving device can display the video and audio from port #1 to port #2 accordingly.

[0049] Although the present invention has been described by way of examples and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (which are obvious to those skilled in the art). Therefore, the attached claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A clock control method for a high-definition multimedia interface (HDMI) receiving device operating in a power saving mode, wherein the receiving device comprises a first module, a second module and a third module, including: enabling a clock signal to be sent to the first module and the third module in a first region where data is received, and disabling the clock signal to be sent to the second module; and The clock signal is enabled to be sent to the third module in the second region of the received data, and the clock signal is disabled to be sent to the first module and the second module.

2. The clock control method according to claim 1, wherein the received data in the first area is a startup area of ​​a frame, the received data in the second area is a shutdown area of ​​the frame, the first area is a group of queues containing HDCP information of the frame, and the second area is the remaining queues of the frame that do not contain the HDCP information.

3. The clock control method according to claim 2, wherein the third module comprises a power switch controller and a synchronization module.

4. The clock control method according to claim 2, wherein the first module comprises a decoder, a timing detector and a HDCP encryption detector.

5. The clock control method according to claim 2, wherein the second module comprises an HDCP password related module and an audio related module. 6 . The clock control method as claimed in claim 3 , wherein the synchronization module maintains synchronization between the sink device and the source device.

7. The clock control method according to claim 2, wherein the HDCP information comprises AVMUTE control information and HDCP control information.

8. The clock control method according to claim 1, wherein the clock signal is a fixed rate link (FRL) clock or a transition minimized differential signaling (TMDS) clock.

9. An electronic device comprising: a first circuit; a set of second circuits; a plurality of clock switches, each electrically connected to the first module and the second module and configured to receive a clock signal; as well as a controller electrically connected to the clock switch and configured to send an enable signal or a disable signal to the clock switch; wherein the controller enables the clock switch through the enable signal to send the clock signal to the group of first circuits; The controller disables the clock switch through the disable signal, so that when the clock signal is enabled to be sent to the group of first circuits, the clock signal is not sent to the group of second circuits.

10. The electronic device according to claim 9, wherein The controller receives data including a first region and a second region in a frame from a source device; The first area is a group of queues containing HDCP information of the frame, and the second area is the remaining queues of the frame that do not contain the HDCP information.

11. The electronic device according to claim 10, wherein when the first area of ​​each frame is received, the group of first circuits includes a power switch controller, a synchronization module, a decoder, a timing detector, an HDCP encryption detector module, a power switch controller and a synchronization module, and the group of second circuits includes an HDCP encryption-related module and an audio-related module.

12. The electronic device according to claim 10, wherein when the second area of ​​each frame is received, the first group of circuits includes a power switch controller and a synchronization module, and the second group of circuits includes a decoder, a timing detector, an HDCP encryption detector module, a power switch controller and a synchronization module.

13. The electronic device according to claim 11, wherein The synchronization module maintains synchronization between the electronic device and the source device.

14. The electronic device according to claim 10, wherein the HDCP information comprises AVMUTE control information and HDCP control information.

15. The electronic device of claim 9, wherein the clock signal is a fixed rate link (FRL) clock or a transition minimized differential signaling (TMDS) clock.

16. The electronic device according to claim 9, wherein the electronic device is an HDMI sink in a sink.

17. The electronic device of claim 10, wherein the first region is a power-on region, and the second region is a power-off region of the frame from the source device.

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