A semiconductor structure and a method of forming the same

Abstract

The present disclosure provides a semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, the substrate comprising an array region, a peripheral region; forming a first mask layer on the substrate, and forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer; forming an array pattern in the array region based on the first mask pattern.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In order to meet the demand for high integration of memory devices, it has been proposed to form array patterns through a self-aligned double patterning (SADP) process and a self-aligned quadruple patterning (SAQP) process.

[0003] However, as the integration density of memory devices continues to increase, the cell pitch of the array pattern continues to shrink. In the process of forming the array pattern using the SADP process and the SAQP process, many problems still need to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate comprising an array region and a peripheral region;

[0008] forming a first mask layer on the substrate, and forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer;

[0009] An array pattern is formed in the array region based on the first mask pattern.

[0010] In an optional embodiment, the cell size of the first mask pattern directly above the array region is a first size, and the cell size of the first mask pattern directly above the peripheral region is a second size;

[0011] The first size is greater than or equal to the second size.

[0012] In an optional embodiment, the ratio of the first size to the second size is in the range of 1-1.2.

[0013] In an optional embodiment, the method further includes: forming a second mask layer on the first mask layer, and forming a second mask pattern in the second mask layer directly above the array area, and excluding the second mask pattern directly above the peripheral area.

[0014] In an optional embodiment, forming an array pattern in the array area based on the first mask pattern includes:

[0015] An array pattern is formed in the array region based on the first mask pattern and the second mask pattern, and the array pattern is not formed in the peripheral region.

[0016] In an optional embodiment, forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer includes:

[0017] forming a first mask layer, a third mask layer, a fourth mask layer, and a first photoresist layer on the substrate; wherein the first photoresist layer includes a third mask pattern located directly above the array region and directly above the peripheral region;

[0018] forming a fourth mask pattern in the fourth mask layer located directly above the array region and directly above the peripheral region based on the third mask pattern;

[0019] forming a first dielectric layer on the sidewalls of the fourth mask pattern, and removing the fourth mask pattern;

[0020] The third mask layer is etched using the first dielectric layer as a mask to form a fifth mask pattern directly above the array region and directly above the peripheral region.

[0021] In an optional embodiment, forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer further includes:

[0022] forming a second dielectric layer on the sidewalls of the fifth mask pattern;

[0023] The first mask layer is etched using the second dielectric layer as a mask to form the first mask pattern directly above the array region and directly above the peripheral region; and the remaining portion of the second dielectric layer is formed on the first mask pattern.

[0024] In an optional embodiment, the method further includes:

[0025] A first filling layer is formed at least between the gaps of the first mask pattern and the gaps of the second dielectric layer remaining on the first mask pattern; the first filling layer directly above the array area is flush with the first filling layer directly above the peripheral area.

[0026] In an optional embodiment, the method further includes:

[0027] etching the first filling layer and removing the second dielectric layer remaining on the first mask pattern to form a first groove;

[0028] forming a second filling layer in the first groove;

[0029] Parts of the first filling layer and the second filling layer are removed, so that the first filling layer directly above the array region is flush with the first filling layer directly above the peripheral region, and the first mask pattern is exposed.

[0030] In an optional embodiment, etching the first filling layer includes:

[0031] The first filling layer is etched using a dry etching process.

[0032] In an optional embodiment, the material of the second filling layer is the same as that of the first filling layer.

[0033] In an optional embodiment, the forming of a second mask layer on the first mask layer, and forming a second mask pattern in the second mask layer directly above the array region, wherein the second mask pattern is not included directly above the peripheral region, comprises:

[0034] forming a second mask layer and a fifth mask layer in sequence on the first mask layer directly above the array region and directly above the peripheral region, and forming a second photoresist layer on the fifth mask layer directly above the array region; the second photoresist layer includes a sixth mask pattern;

[0035] etching the fifth mask layer based on the sixth mask pattern to form a seventh mask pattern, and removing the fifth mask layer directly above the peripheral region;

[0036] A third dielectric layer is formed on the sidewalls and top surface of the seventh mask pattern, between two adjacent units of the seventh mask pattern, and on the second mask layer directly above the peripheral region.

[0037] In an optional embodiment, the array region comprises a boundary region adjacent to the peripheral region; the forming a second mask layer on the first mask layer and forming a second mask pattern on the second mask layer directly above the array region and not directly above the peripheral region further comprises:

[0038] forming a third photoresist layer on the third dielectric layer directly above the boundary region and the peripheral region;

[0039] etching the second mask layer based on the third photoresist layer, the third dielectric layer and the seventh mask pattern to form a second mask pattern in the second mask layer.

[0040] In an optional embodiment, before forming the first mask layer on the substrate, the forming method further comprises:

[0041] forming an amorphous carbon layer on the substrate;

[0042] the forming an array pattern in the array region and not forming the array pattern in the peripheral region based on the first mask pattern and the second mask pattern comprises:

[0043] etching the amorphous carbon layer with the first mask pattern and the second mask pattern as a mask, transferring the pattern formed by the overlapping of the first mask pattern and the second mask pattern to the amorphous carbon layer directly above the array region to form a patterned amorphous carbon layer;

[0044] etching the substrate with the patterned amorphous carbon layer as a mask and removing the remaining amorphous carbon layer to form an array pattern in the array region and not form the array pattern in the peripheral region.

[0045] In a second aspect, the embodiments of the present disclosure provide a semiconductor structure obtained by the forming method of the semiconductor structure in any of the preceding embodiments.

[0046] In the technical solutions provided by the present disclosure, by forming the first mask pattern directly above the array region and the peripheral region, the difference between the patterns directly above the array region and the peripheral region is reduced, thereby reducing the load effect of the peripheral region and the array region in the process of forming the array pattern, improving the uniformity of the array pattern in the array region, effectively reducing the possibility of abnormality of the array pattern, and avoiding the formation of redundant patterns in the peripheral region and the damage of the peripheral region, thereby improving the reliability of the finally formed semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figures 1 to 5 a structural schematic diagram of an array pattern forming process provided by the embodiments of the present disclosure;

[0048] Figure 6 A schematic diagram of a top view of an array pattern provided in an embodiment of the present disclosure;

[0049] Figure 7 A schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0050] Figures 8 to 23 A structural schematic diagram of the semiconductor structure formation process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0053] In the drawings, like reference numerals refer to like elements throughout.

[0054] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] Related technologies have proposed using SADP and SAQP processes to form capacitor hole arrays with small cell sizes and high aspect ratios (AR). However, as the integration density of memory devices continues to increase, the cell size of the array pattern continues to shrink. During the formation of the array pattern using SADP and SAQP processes, the loading effect becomes increasingly severe, leading to anomalies at the boundaries of the array pattern within the array region and causing certain damage to the peripheral region.

[0057] Figures 1 to 5 FIG. 1 is a schematic diagram of a semiconductor structure forming process according to an embodiment of the present disclosure. Figure 1 , providing a substrate 1, the substrate 1 includes an array area and a peripheral area, a mask layer 2 is formed on the substrate 1, and a mask pattern 3 is formed on the mask layer 2. Figure 2 , a filling layer 4 covering the mask pattern 3 is formed on the mask layer 2. Figure 3 , remove part of the filling layer 4 so that the top surface of the mask pattern 3 is exposed. Figure 4 , a mask layer 5 is formed on the filling layer 4, and a mask pattern 6 is formed on the mask layer 5. Figure 5 , the mask pattern 6 and the mask pattern 3 are transferred to the substrate 1 , thereby forming an array pattern 7 in the substrate 1 .

[0058] In the process of forming the above array pattern 7, since there is a mask pattern 3 directly above the array area, but no mask pattern 3 is formed directly above the peripheral area, there will be a large load effect during the spin coating process to form the filling layer 4, so that each unit in the mask pattern 3 formed directly above the array area has asymmetry, and finally the array pattern formed in the array area appears as follows: Figure 6 The distortion shown will further affect the formation of the capacitor hole array in subsequent steps. In addition, the pattern difference between the array area and the peripheral area will also cause the height of the filling layer 4 to be significantly different between the array area and the peripheral area. The height of the filling layer 4 near the peripheral area and the filling layer 4 far from the peripheral area above the array area also has a certain difference. Figure 2 As shown, the height of the filling layer 4 directly above the array area far from the peripheral area is higher, the height of the filling layer 4 directly above the array area close to the peripheral area is second, and the height of the filling layer 4 directly above the peripheral area is the lowest, so that Figure 3 After removing part of the filling layer 4 as shown, the height of the remaining filling layer 4 above the array area and the peripheral area will also be different, so that the following appears in the process of forming the array pattern 7: Figure 5 The peripheral area shown also forms an unnecessary pattern, causing some damage to the peripheral area.

[0059] Based on the above problems, how to optimize the formation process of the array pattern and reduce the loading effect has become an urgent problem to be solved. In this regard, the present disclosure proposes the following implementation methods.

[0060] The present disclosure provides a method for forming a semiconductor structure. Figure 7 Schematic diagram of the process of forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 7 As shown, the method for forming a semiconductor structure includes the following steps:

[0061] Step S101: providing a substrate, the substrate including an array region and a peripheral region;

[0062] Step S102: forming a first mask layer on the substrate, and forming a first mask pattern in the first mask layer directly above the array region and the peripheral region;

[0063] Step S103 : forming an array pattern in the array region based on the first mask pattern.

[0064] Figures 8 to 23 The schematic diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is shown below. Figure 7 、 Figures 8 to 23 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0065] Reference Figure 8 First, a substrate 101 is provided, and the substrate 101 includes an array area a and a peripheral area b.

[0066] In some embodiments, providing the substrate 101 includes: forming a metal layer; forming a stacked structure on the metal layer in which a sacrificial layer and a supporting layer are overlapped and arranged along the Z direction ( Figure 8 A polysilicon layer 134 and an oxide layer 125 are formed on the stack structure. The oxide layer 125 is a target etching layer for forming an array pattern.

[0067] In some specific examples, the material of the metal layer includes but is not limited to tungsten; the material of the support layer includes but is not limited to silicon oxide; the material of the sacrificial layer includes but is not limited to silicon nitride; the material of the oxide layer 125 includes but is not limited to doped silicon oxide, for example, phosphorus-doped silicon oxide, phosphorus-boron-doped silicon oxide.

[0068] The following will be combined Figures 8-17 The process of forming the first mask pattern is introduced in detail.

[0069] In some embodiments, reference Figure 8-Figure 9 , forming a first mask pattern located directly above the array region a and the peripheral region b in the first mask layer, comprising:

[0070] A first mask layer 102, a third mask layer 107, a fourth mask layer 108, and a first photoresist layer 109 are formed on a substrate 101; the first photoresist layer 109 includes a third mask pattern 110 located directly above the array region a and directly above the peripheral region b;

[0071] Based on the third mask pattern 110 , a fourth mask pattern 111 is formed in the fourth mask layer 108 directly above the array region a and the peripheral region b.

[0072] It can be understood that the first photoresist layer 109 in the embodiment of the present disclosure includes a third mask pattern 110 located directly above the array area a and directly above the peripheral area b. That is, the third mask pattern 110 is formed directly above the array area a and directly above the peripheral area b. In this way, the difference in pattern density directly above the peripheral area b and directly above the array area a is relatively reduced, thereby reducing the load effect in the process of forming the array pattern directly above the peripheral area b and directly above the array area a.

[0073] In the disclosed embodiment, the fourth mask layer 108 includes a first sub-mask layer 128 and a second sub-mask layer 129 arranged sequentially along the Z direction, and the third mask layer 107 includes a third sub-mask layer 126 and a fourth sub-mask layer 127 arranged sequentially along the Z direction. A first photoresist layer 109 including a third mask pattern 110 is first formed on the second sub-mask layer 129. The second sub-mask layer 129 and the first sub-mask layer 128 are then etched using the first photoresist layer 109 including the third mask pattern 110 as a mask to form a fourth mask pattern 111 in the first sub-mask layer 128 and the second sub-mask layer 129. During this process, the fourth sub-mask layer 127 serves as an etch stop layer, allowing the opening formed by etching the fourth mask layer 108 to stop on the fourth sub-mask layer 127.

[0074] In some specific examples, the material of the first mask layer 102 includes but is not limited to silicon-rich silicon oxynitride; the material of the third sub-mask layer 126 includes but is not limited to amorphous carbon; the material of the fourth sub-mask layer 127 includes but is not limited to silicon oxide; the material of the first sub-mask layer 128 includes but is not limited to spin-on hard mask (SOH) material (for example, silicon hard mask material, carbon hard mask material, organic hard mask material, etc.); the material of the second sub-mask layer 129 includes but is not limited to silicon oxynitride.

[0075] In some specific examples, the first mask layer 102, the first sub-mask layer 128, the second sub-mask layer 129, the third sub-mask layer 126 and the fourth sub-mask layer 127 can be formed by a deposition process or a spin coating process, and the first sub-mask layer 128 and the second sub-mask layer 129 can be etched by a dry etching process.

[0076] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD); the spin coating process includes but is not limited to spin-on dielectrics (SOD) process; the dry etching process includes but is not limited to plasma etching (PE), sputtering etching (SE), ion beam etching (IBE) and reactive ion etching (RIE).

[0077] Next, refer to Figure 10 、 Figure 11 , a first dielectric layer 112 is formed on the sidewall of the fourth mask pattern 111, and the fourth mask pattern 111 is removed; the third mask layer 107 is etched using the first dielectric layer 112 as a mask, and a fifth mask pattern 113 is formed directly above the array area a and directly above the peripheral area b.

[0078] In some specific examples, a first dielectric layer 112 can be first formed on the surface of the fourth sub-mask layer 127, the sidewalls of the fourth mask pattern 111, and the top surface of the fourth mask pattern 111, and the first dielectric layer 112 on the top surface of the fourth mask pattern 111, the first dielectric layer 112 on the surface of the fourth sub-mask layer 127, and the fourth mask pattern 111 are removed, and the first dielectric layer 112 on the sidewalls of the fourth mask pattern 111 is retained. The remaining first dielectric layer 112 constitutes a spacer, and the unit size of the spacer is half the unit size of the fourth mask pattern 111.

[0079] In some specific examples, the first dielectric layer 112 can be etched using an anisotropic etching process. The anisotropic etching process includes but is not limited to a plasma etching process with high selectivity. When etching away the first dielectric layer 112 on the top surface of the fourth mask pattern 111 and the first dielectric layer 112 on the surface of the fourth sub-mask layer 127, the first dielectric layer 112 on the side wall of the fourth mask pattern 111 may not be laterally etched.

[0080] In some embodiments, reference Figure 12 、 Figure 13 , forming a first mask pattern 103 located directly above the array area a and the peripheral area b in the first mask layer 102, further comprising: forming a second dielectric layer 114 on the sidewalls of the fifth mask pattern 113; etching the first mask layer 102 using the second dielectric layer 114 as a mask to form the first mask pattern 103 directly above the array area a and directly above the peripheral area b; and removing the remaining portion of the second dielectric layer 114 on the first mask pattern 103.

[0081] In some specific examples, a second dielectric layer 114 can be first formed on the surface of the first mask layer 102, the sidewalls of the fifth mask pattern 113, and the top surface of the fifth mask pattern 113, and the second dielectric layer 114 on the top surface of the fifth mask pattern 113, the second dielectric layer 114 on the surface of the first mask layer 102, and the fifth mask pattern 113 are removed, and the second dielectric layer 114 on the sidewalls of the fifth mask pattern 113 is retained. Then, the first mask layer 102 is etched using the remaining second dielectric layer 114 as a mask to obtain the first mask pattern 103.

[0082] In some specific examples, the first dielectric layer 112 and the second dielectric layer 114 may be formed by using an ALD process.

[0083] In some specific examples, the material of the first dielectric layer 112 and / or the second dielectric layer 114 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or boron nitride.

[0084] It can be understood that in the embodiment of the present disclosure, the first mask pattern 103 is formed directly above the peripheral area b and the array area a. In this way, when the array pattern 104 is formed directly above the array area a and the peripheral area b, the difference in pattern density directly above the peripheral area and directly above the array area is reduced, thereby reducing the load effect of the array area a and the peripheral area b.

[0085] In some embodiments, the cell size of the first mask pattern 103 directly above the array region a is a first size, and the cell size of the first mask pattern 103 directly above the peripheral region b is a second size.

[0086] Here, the unit size of the mask pattern can be understood as the pitch of the mask pattern, that is, the size of a periodic pattern. The smaller the unit size, the greater the density of the pattern.

[0087] It is understood that the cell size of the first mask pattern 103 directly above the array region a can be larger or smaller than the cell size of the first mask pattern 103 directly above the peripheral region b, or the two can be equal. However, the difference between the first and second sizes cannot be too large. A large difference means a significant difference in pattern density directly above the peripheral region b and directly above the array region a. When the first and second filling layers 115 and 116 are subsequently filled, the height difference between the first and second filling layers 115 and 116 formed in the peripheral region b and the array region a will be significant, which will increase the difficulty of subsequent processing.

[0088] In some embodiments, the first size is greater than or equal to the second size.

[0089] In some embodiments, the ratio of the first dimension to the second dimension is in the range of 1-1.2.

[0090] It should be noted that the ratio range of the first size to the second size given in the above embodiment is only for illustrative purposes and is not intended to limit the ratio range of the first size to the second size in the embodiments of the present disclosure.

[0091] Here, the second size cannot be too small, otherwise it will lead to high process requirements; the second size cannot be too large, otherwise it will lead to a large difference between the first size and the second size, resulting in a large height difference between the first filling layer 115 formed directly above the peripheral area b and directly above the array area a.

[0092] In some embodiments, the first size is equal to the second size.

[0093] It can be understood that when the first size is equal to the second size, the pattern density difference between the first mask pattern 103 directly above the peripheral region b and the array region a is minimal, which can achieve a better effect of reducing the loading effect.

[0094] In some embodiments, reference Figure 14 The method for forming a semiconductor structure further includes: forming a first filling layer 115 at least between the gaps in the first mask pattern 103 and the gaps in the second dielectric layer 114 remaining on the first mask pattern 103; the first filling layer 115 directly above the array area a is flush with the first filling layer 115 directly above the peripheral area b.

[0095] In some specific examples, the first filling layer 115 may be formed by using a spin coating process.

[0096] It can be understood that in the embodiment of the present disclosure, since the first mask pattern 103 is formed directly above the peripheral area b and directly above the array area a, the pattern density difference between the array area a and the peripheral area b is small. This makes it possible to form a highly consistent first filling layer 115 in the peripheral area b and directly above the array area a, thereby reducing the load effect directly above the array area a and directly above the peripheral area b in the subsequent formation of the array pattern.

[0097] In some specific examples, such as Figure 14 As shown, a portion of the first filling layer 115 is also formed on the second dielectric layer 114 .

[0098] In some embodiments, reference Figure 15-17 The method for forming the semiconductor structure further includes: etching the first filling layer 115 and removing the remaining second dielectric layer 114 on the first mask pattern 103 to form a first groove 117; forming a second filling layer 116 in the first groove 117; and removing a portion of the first filling layer 115 and the second filling layer 116 so that the first filling layer 115 directly above the array region a is flush with the first filling layer 115 directly above the peripheral region b, and the first mask pattern 103 is exposed.

[0099] In some embodiments, etching the first filling layer 115 includes etching the first filling layer 115 using a dry etching process.

[0100] In some specific examples, the first filling layer 115 may be etched using a dry etching process to expose the remaining second dielectric layer 114 , and then the remaining second dielectric layer 114 may be removed using an etching process.

[0101] In some specific examples, removing a portion of the first filling layer 115 and the second filling layer 116 includes: removing a portion of the first filling layer 115 and the second filling layer 116 by a dry etching process.

[0102] In some specific examples, the materials of the first filling layer 115 and the second filling layer 116 include, but are not limited to, spin-on hard mask materials (e.g., silicon hard mask materials, carbon hard mask materials, organic hard mask materials, etc.). The materials of the first filling layer 115 and the second filling layer 116 can be the same or different.

[0103] In some embodiments, the material of the first filling layer 115 is the same as the material of the second filling layer 116 .

[0104] It is understood that the spin-on hard mask material is a polymer material, and a first mask pattern 103 with a smaller size is formed in the first filling layer 115. If a chemical mechanical polishing (CMP) process is used, the spin-on hard mask material is directly Figure 14 On the basis of removing part of the first filling layer 115 and the remaining second dielectric layer 114 to obtain Figure 17 The structure shown will damage the first mask pattern 103 and cannot achieve the effect of making the first filling layer 115 directly above the array region a and the first filling layer 115 directly above the peripheral region b flush with each other.

[0105] It can be understood that in the embodiment of the present disclosure, a first filling layer 115 is first formed, and then the first filling layer 115 is etched using a dry etching process and the remaining second dielectric layer 114 is removed, and then a second filling layer 116 made of the same material as the first filling layer 115 is formed, and a portion of the first filling layer 115 and the second filling layer 116 are removed using a dry etching process, so that the height of the first filling layer 115 directly above the array area a is flush with the height of the first filling layer 115 directly above the peripheral area b, thereby reducing the pattern difference directly above the array area a and directly above the peripheral area a, and reducing the load effect directly above the array area a and directly above the peripheral area b in the subsequent formation of the array pattern.

[0106] In some specific examples, such as Figure 16 As shown, when the second filling layer 116 is formed in the first groove 117 , a portion of the second filling layer 116 is also formed on the top of the first filling layer 115 .

[0107] In some specific examples, an etching process may be used to remove a portion of the first filling layer 115 and the second filling layer 116. After removing a portion of the first filling layer 115 and the second filling layer 116, as shown in FIG. Figure 17 As shown, the height of the first filling layer 115 is flush with the height of the first mask layer, and the height of the first filling layer 115 directly above the array region a and the peripheral region b is flush with each other.

[0108] It can be understood that in the embodiment of the present disclosure, by reducing the difference in pattern density directly above the peripheral area b and directly above the array area a, the load effect during the corresponding etching and filling directly above the peripheral area b and directly above the array area a is reduced, so that the height difference of the first filling layer 115 directly above the peripheral area b and directly above the array area a is smaller, which is conducive to the subsequent formation of the array pattern.

[0109] In some embodiments, the method for forming a semiconductor structure further includes: forming a second mask layer on the first mask layer 102, and forming a second mask pattern in the second mask layer directly above the array region a, and not including the second mask pattern directly above the peripheral region b.

[0110] Next, combine Figures 18-22 The formation process of the second mask pattern is introduced in detail.

[0111] In some embodiments, reference Figures 18-20 , forming a second mask layer 105 on the first mask layer 102, and forming a second mask pattern 106 in the second mask layer 105 directly above the array region a, and excluding the second mask pattern 106 directly above the peripheral region b, including:

[0112] A second mask layer 105 and a fifth mask layer 118 are sequentially formed on the first mask layer 102 directly above the array area a and directly above the peripheral area b, and a second photoresist layer 119 is formed on the fifth mask layer 118 directly above the array area a; the second photoresist layer 119 includes a sixth mask pattern 120; based on the sixth mask pattern 120, the fifth mask layer 118 is etched to form a seventh mask pattern 121, and the fifth mask layer 118 directly above the peripheral area b is removed; a third dielectric layer 122 is formed on the sidewalls and top surface of the seventh mask pattern 121, between two adjacent units of the seventh mask pattern 121, and on the second mask layer 105 directly above the peripheral area b.

[0113] In some specific examples, the fifth mask layer 118 includes a fifth sub-mask layer 130, a sixth sub-mask layer 131, a seventh sub-mask layer 132, and an eighth sub-mask layer 133 arranged sequentially along the Z direction. The specific process of forming the seventh mask pattern 121 includes etching the fifth sub-mask layer 130, the sixth sub-mask layer 131, the seventh sub-mask layer 132, and the eighth sub-mask layer 133 using the patterned second photoresist layer 119 as a mask, thereby forming the seventh mask pattern 121. The seventh mask pattern 121 can be formed using a SADP process such that the cell size of the seventh mask pattern 121 is half the cell size of the sixth mask pattern 120.

[0114] Here, since the peripheral region b is not covered by the second photoresist 119 , the fifth sub-mask layer 130 , the sixth sub-mask layer 131 , the seventh sub-mask layer 132 , and the eighth sub-mask layer 133 in the peripheral region b are all removed.

[0115] In some specific examples, the fifth sub-mask layer 130, the sixth sub-mask layer 131, the seventh sub-mask layer 132, and the eighth sub-mask layer 133 can be formed by a deposition process or a spin coating process, and the fifth sub-mask layer 130, the sixth sub-mask layer 131, the seventh sub-mask layer 132, and the eighth sub-mask layer 133 can be etched by a dry etching process.

[0116] In some specific examples, the material of the second mask layer 105 includes but is not limited to silicon-rich silicon oxynitride; the material of the fifth sub-mask layer 130 includes but is not limited to amorphous carbon; the material of the sixth sub-mask layer 131 includes but is not limited to silicon oxide; the material of the seventh sub-mask layer 132 includes but is not limited to spin-on hard mask material (for example, silicon hard mask material, carbon hard mask material, organic hard mask material, etc.); the material of the eighth sub-mask layer 133 includes but is not limited to silicon oxynitride.

[0117] In some specific examples, the material of the third dielectric layer 122 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, or boron nitride. The material of the third dielectric layer 122 can be the same as or different from that of the first dielectric layer 112 and the second dielectric layer 114.

[0118] In some specific examples, the third dielectric layer 122 may be formed by using an ALD process.

[0119] In some embodiments, reference Figure 21-22 , the array area a includes an intersection area close to the peripheral area b; a second mask layer 105 is formed on the first mask layer 102, and a second mask pattern 106 is formed in the second mask layer 105 directly above the array area a, and the second mask pattern 106 is not included directly above the peripheral area b, and the method further includes: forming a third photoresist layer 123 on the third dielectric layer 122 in the intersection area and directly above the peripheral area b; based on the third photoresist layer 123, the third dielectric layer 122, and the seventh mask pattern 121, etching the second mask layer 105 to form a second mask pattern 106 in the second mask layer 105.

[0120] In some specific examples, the height of the third photoresist layer 123 directly above the boundary region and the height of the third photoresist layer 123 directly above the peripheral region b may be substantially flush.

[0121] In some embodiments, reference Figure 22-23, forming an array pattern 104 in the array region a based on the first mask pattern 103, including: forming the array pattern 104 in the array region a based on the first mask pattern 103 and the second mask pattern 106, and not forming the array pattern 104 in the peripheral region b.

[0122] It is understood that in the embodiments of the present disclosure, by reducing the difference in pattern density between the array region and the peripheral region, the height difference between the first fill layer and the peripheral region is reduced, and the height difference between the second mask layer and the peripheral region is reduced. This prevents the formation of redundant patterns in the peripheral region when forming the array pattern, thereby reducing damage to the peripheral region. Furthermore, the reduction in the pattern density difference between the array region and the peripheral region reduces the loading effect between the array region and the peripheral region, thereby making the array pattern formed in the array region more uniform and improving the situation where abnormal patterns (such as distortion) are formed in the array pattern.

[0123] In some embodiments, before forming the first mask layer 102 on the substrate 101, the method for forming the semiconductor structure further includes: forming an amorphous carbon layer 124 on the substrate 101; when forming the array pattern 104, the amorphous carbon layer 124 can be first etched using the first mask pattern 103 and the second mask pattern 106 as masks, and the pattern formed by the overlap of the first mask pattern 103 and the second mask pattern 106 is transferred to the amorphous carbon layer 124 directly above the array area a to form a patterned amorphous carbon layer 124; then, the substrate 101 is etched using the patterned amorphous carbon layer 124 as a mask, and the remaining amorphous carbon layer 124 is removed to form the array pattern 104 in the array area a, and no array pattern 104 is formed in the peripheral area b.

[0124] In the embodiment of the present disclosure, during the process of transferring the pattern formed by the overlap of the first mask pattern 103 and the second mask pattern 106 to the amorphous carbon layer 124 directly above the array region a, because the first filler layer in the peripheral region is thicker, no openings penetrating the amorphous carbon layer 124 along the Z direction are formed in the amorphous carbon layer 124 directly above the peripheral region. Furthermore, when etching the oxide layer 125 in the substrate 101 using the patterned amorphous carbon layer 124 as a mask, the amorphous carbon layer 124 directly above the peripheral region b completely covers the oxide layer 125, thereby preventing the oxide layer 125 in the peripheral region b from being etched, thereby avoiding the formation of unnecessary patterns in the peripheral region b.

[0125] In some embodiments, the method for forming the semiconductor structure further includes: forming a capacitor hole array in the stacked structure using the array pattern 104 as a mask.

[0126] It should be noted that the method for forming a semiconductor structure provided by the present disclosure can be applied not only to the formation process of a capacitor hole array, but also to the formation process of other array patterns with small unit size and large aspect ratio.

[0127] In the embodiments of the present disclosure, the number of minimum repeating units in each mask pattern is merely illustrative. This disclosure does not impose any restrictions on the specific number of minimum repeating units in the mask pattern positioned directly above the array region a and the peripheral region b. In practical applications, the width of the peripheral region b in the X direction and the number of minimum repeating units in the mask pattern formed directly above the peripheral region b can be adjusted based on the density of the array pattern, thereby mitigating the loading effect during array pattern formation as needed.

[0128] In the embodiment of the present disclosure, by forming the first mask pattern directly above both the array region and the peripheral region, the difference in patterns directly above the peripheral region and directly above the array region is reduced, thereby reducing the load effect of the peripheral region and the array region in the process of forming the array pattern. This can improve the uniformity of the array pattern in the array region, effectively reduce the possibility of abnormalities in the array pattern, and avoid forming redundant patterns in the peripheral region, thereby avoiding damage to the peripheral region, thereby improving the reliability of the ultimately formed semiconductor structure.

[0129] Based on the same concept as the above embodiments, the present disclosure also provides a semiconductor structure, which is manufactured by the method for forming the semiconductor structure in any of the above embodiments. The technical effects that can be achieved by the method for forming the semiconductor structure in any of the above embodiments can also be achieved by this semiconductor structure, and will not be described one by one here.

[0130] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0131] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region; forming a first mask layer on the substrate, and forming a first mask pattern located directly above the array region and the peripheral region in the first mask layer; forming an array pattern in the array region based on the first mask pattern; The forming of a first mask pattern located directly above the array region and the peripheral region in the first mask layer includes: forming a first mask layer, a third mask layer, a fourth mask layer, and a first photoresist layer on the substrate; wherein the first photoresist layer includes a third mask pattern located directly above the array region and directly above the peripheral region; forming a fourth mask pattern in the fourth mask layer located directly above the array region and directly above the peripheral region based on the third mask pattern; forming a first dielectric layer on the sidewalls of the fourth mask pattern, and removing the fourth mask pattern; Using the first dielectric layer as a mask, etching the third mask layer to form a fifth mask pattern directly above the array region and directly above the peripheral region; The step of forming a first mask pattern in the first mask layer directly above the array region and the peripheral region further comprises: forming a second dielectric layer on the sidewalls of the fifth mask pattern; Using the second dielectric layer as a mask, the first mask layer is etched to form the first mask pattern directly above the array region and directly above the peripheral region; the remaining portion of the second dielectric layer is formed on the first mask pattern; The method further comprises: A first filling layer is formed at least between the gaps of the first mask pattern and the gaps of the second dielectric layer remaining on the first mask pattern; the first filling layer directly above the array area is flush with the first filling layer directly above the peripheral area; The method further comprises: etching the first filling layer and removing the second dielectric layer remaining on the first mask pattern to form a first groove; forming a second filling layer in the first groove; Parts of the first filling layer and the second filling layer are removed, so that the first filling layer directly above the array region is flush with the first filling layer directly above the peripheral region, and the first mask pattern is exposed.

2. The forming method according to claim 1, wherein: The cell size of the first mask pattern directly above the array region is a first size, and the cell size of the first mask pattern directly above the peripheral region is a second size; The first size is greater than or equal to the second size.

3. The forming method according to claim 2, wherein: The ratio of the first size to the second size is in the range of 1-1.

2.

4. The forming method according to claim 1, wherein: The method further includes forming a second mask layer on the first mask layer, and forming a second mask pattern in the second mask layer directly above the array region, while excluding the second mask pattern directly above the peripheral region.

5. The forming method according to claim 4, wherein: The forming an array pattern in the array area based on the first mask pattern includes: An array pattern is formed in the array region based on the first mask pattern and the second mask pattern, and the array pattern is not formed in the peripheral region.

6. The forming method according to claim 1, wherein: The etching of the first filling layer includes: The first filling layer is etched using a dry etching process.

7. The forming method according to claim 1, wherein: The material of the second filling layer is the same as that of the first filling layer.

8. The forming method according to claim 4, wherein: The step of forming a second mask layer on the first mask layer and forming a second mask pattern in the second mask layer directly above the array region, while excluding the second mask pattern directly above the peripheral region, comprises: forming a second mask layer and a fifth mask layer in sequence on the first mask layer directly above the array region and directly above the peripheral region, and forming a second photoresist layer on the fifth mask layer directly above the array region; the second photoresist layer includes a sixth mask pattern; etching the fifth mask layer based on the sixth mask pattern to form a seventh mask pattern, and removing the fifth mask layer directly above the peripheral region; A third dielectric layer is formed on the sidewalls and top surface of the seventh mask pattern, between two adjacent units of the seventh mask pattern, and on the second mask layer directly above the peripheral region.

9. The forming method according to claim 8, wherein: The array region includes a boundary region adjacent to the peripheral region; forming a second mask layer on the first mask layer, and forming a second mask pattern located directly above the array region in the second mask layer, and excluding the second mask pattern directly above the peripheral region, further comprising: forming a third photoresist layer on the third dielectric layer directly above the boundary region and the peripheral region; Based on the third photoresist layer, the third dielectric layer, and the seventh mask pattern, the second mask layer is etched to form a second mask pattern in the second mask layer.

10. The forming method according to claim 5, wherein: Before forming the first mask layer on the substrate, the forming method further includes: forming an amorphous carbon layer on the substrate; The forming of the array pattern in the array region based on the first mask pattern and the second mask pattern and not forming the array pattern in the peripheral region includes: Etching the amorphous carbon layer using the first mask pattern and the second mask pattern as masks, and transferring a pattern formed by overlapping the first mask pattern and the second mask pattern to the amorphous carbon layer directly above the array region to form a patterned amorphous carbon layer; The substrate is etched using the patterned amorphous carbon layer as a mask, and the remaining amorphous carbon layer is removed to form an array pattern in the array region, and no array pattern is formed in the peripheral region.

11. A semiconductor structure, characterized in that The semiconductor structure is obtained by the method for forming a semiconductor structure according to any one of claims 1 to 10.

Images