Memory device and method of manufacturing the same

Abstract

The embodiment of the invention discloses a memory device and a method of manufacturing the same. The memory device includes a transistor formed along a front side surface of a substrate. The memory device includes a first fuse resistor formed in a first metallization layer disposed vertically relative to the front side surface. The memory device includes a second fuse resistor formed in a second metallization layer disposed vertically relative to the front side, the first metallization layer being different from the second metallization layer. Each of the second fuse resistor and the first fuse resistor is coupled to the transistor.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device and a method for manufacturing the same. Background Art

[0002] Generally, there are two main types of data storage elements. The first type is a volatile memory device, in which the information stored in a particular storage element is lost the moment power is removed from the memory device. The second type is a non-volatile memory device, in which information is retained even after power is removed. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a transistor formed along a front side surface of a substrate; a first fuse resistor formed in a first metallization layer vertically arranged relative to the front side surface; and a second fuse resistor formed in a second metallization layer vertically arranged relative to the front side surface, the first metallization layer being different from the second metal layer; wherein the second fuse resistor and the first fuse resistor are each coupled to the transistor.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a one-time programmable (OTP) memory cell, comprising a transistor, a first resistor, and a second resistor; wherein the second resistor is coupled in series to the first resistor, and the first resistor is coupled in series to the transistor; wherein the first resistor, the second resistor, and the transistor are vertically spaced apart from each other.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a memory device is provided, comprising: forming a transistor along a front side surface of a substrate; forming a plurality of front side metal tracks disposed above the front side surface, wherein the plurality of front side metal tracks include word lines, bit lines and a first fuse resistor; and forming a plurality of back side metal tracks disposed above the back side surface of the substrate, wherein the plurality of back side metal tracks include a second fuse resistor; wherein the word line is electrically connected to a gate terminal of the transistor, the bit line is electrically connected to a first end of the second fuse resistor, the second end of the second fuse resistor is electrically connected to the first end of the first fuse resistor, and the second end of the first fuse resistor is electrically connected to a source / drain terminal of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of an example memory device including a memory array is shown in accordance with some embodiments.

[0008] Figure 2 According to some embodiments Figure 1 Schematic diagram of an e-fuse memory cell of a memory array.

[0009] Figure 3 According to some embodiments Figure 1 Another schematic diagram of an electrical fuse memory cell of a memory array.

[0010] Figure 4 According to some embodiments Figure 1 Another schematic diagram of an electric fuse memory cell of a memory array of FIG.

[0011] Figure 5 According to some embodiments Figure 1 An example layout of e-fuse memory cells of a memory array of FIG.

[0012] Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 According to some embodiments, Figure 5 A cross-sectional view of a semiconductor device formed by a layout.

[0013] Fig.11 According to some embodiments, Figure 5 A hybrid cross-sectional view of a semiconductor device formed by a layout.

[0014] Fig.12 According to some embodiments Figure 1 Another example layout of e-fuse memory cells for a memory array of FIG.

[0015] Fig.13 According to some embodiments, Fig.12 A hybrid cross-sectional view of a semiconductor device formed by a layout.

[0016] Fig.14 According to some embodiments Figure 1 Another example layout of e-fuse memory cells for a memory array of FIG.

[0017] Fig.15 According to some embodiments, Fig.14 A hybrid cross-sectional view of a semiconductor device formed by a layout.

[0018] Fig.16A hybrid cross-sectional view of a semiconductor device including an e-fuse memory cell is shown in accordance with some embodiments.

[0019] Fig.17 A hybrid cross-sectional view of a semiconductor device including an e-fuse memory cell is shown in accordance with some embodiments.

[0020] Fig.18 A hybrid cross-sectional view of a semiconductor device including an e-fuse memory cell is shown in accordance with some embodiments.

[0021] Fig.19 A hybrid cross-sectional view of a semiconductor device including an e-fuse memory cell is shown in accordance with some embodiments.

[0022] Fig. 20 A hybrid cross-sectional view of a semiconductor device including an e-fuse memory cell is shown in accordance with some embodiments.

[0023] Fig.21 A hybrid cross-sectional view of a semiconductor device including an e-fuse memory cell is shown in accordance with some embodiments.

[0024] Fig. 22 An example flow chart of a method for fabricating an e-fuse memory cell according to some embodiments is shown. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0026] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0027] One-time programmable (OTP) memory devices are one of various types of non-volatile memory devices. Example implementations of OTP memory devices include metal fuses, etc. Metal fuses use metal resistors as programming elements of corresponding OTP memory devices. Such metal fuses are sometimes referred to as efuse memory devices, in which metal resistors can usually be programmed (e.g., once). The programming process usually includes burning or burning out the metal resistor to change it from a short circuit (state) to an open circuit (state). E-fuse memory devices are commonly used in integrated circuits for adjusting circuits after the integrated circuit is manufactured. For example, an e-fuse memory device is used to provide repair information that controls the use of redundant cells when replacing defective cells of a memory array. Another use is to tune analog circuits by adjusting the capacitance or resistance value of an analog circuit or enabling and disabling parts of a system. In yet another example, a recent trend is that an integrated circuit (or chip) can include multiple e-fuse memory cells with respective programming states, which can be used together as keys for integrated circuits for encryption or decryption purposes.

[0028] In the prior art, the individual metal resistors of different electrical fuse memory cells of the OTP memory device are usually formed in a common metallization layer of a metallization layer disposed above a semiconductor substrate. This can result in the keys stored in the electrical fuse memory cells being easily decrypted. For example, by reverse engineering the integrated circuit, the different positions of the blown (open circuit) and intact (short circuit) fuse resistors can be identified respectively, so that the keys stored in the corresponding electrical fuse memory cells can be easily cracked.

[0029] In this regard, the present disclosure provides various embodiments of a one-time programmable (OTP) memory device, which includes a plurality of electrical fuse memory cells, each electrical fuse memory cell including a plurality of programming elements (e.g., fuses or metal resistors) electrically coupled to a transistor. Such a transistor is typically selected by a word line (WL) signal to control access to a corresponding electrical fuse memory cell (which is sometimes referred to as a WL transistor or access transistor). In various embodiments, the WL transistor is formed along a main (e.g., front side) surface of a substrate, and the fuse resistor is formed in or between different metallization layers arranged vertically relative to the front side surface. For example, a first fuse resistor may be formed (as a first metal track) in one of a plurality of front side metallization layers disposed above the front side of the substrate, and a second fuse resistor may be formed (as a second metal track) in one of a plurality of back side metallization layers disposed above the back side of the substrate. In another example, the first fuse resistor may be formed (as a first metal track) in a first front metallization layer of the plurality of front metallization layers, and the second fuse resistor may be formed (as a second metal track) in a second front metallization layer of the front metallization layers. In yet another example, the first fuse resistor may be formed (as a first metal track) in a first front metallization layer of the plurality of front metallization layers, the second fuse resistor may be formed (as a second metal track) in a second front metallization layer of the front metallization layers, and the third fuse resistor may be vertically formed (as one or more through-hole structures) between the first and second metallization layers.

[0030] By distributing the different programming elements (fuse resistors) of each e-fuse memory cell at corresponding locations (e.g., corresponding metallization layers), the key configuring the e-fuse memory cell can become apparently unbreakable. This is because, for example, due to process variations, the different fuse resistors of each e-fuse memory cell are randomly programmed. Therefore, even if all positions of blown (open circuit) and intact (short circuit) fuse resistors have been identified, it is almost impossible to identify which e-fuse memory cell has been programmed. For example, each e-fuse memory cell may have multiple fuse resistors distributed at various locations within the chip, and it is difficult to identify which of the blown fuse resistors belongs to the corresponding e-fuse memory cell. Therefore, the currently disclosed OTP memory device can provide a greatly enhanced level of security.

[0031] Figure 1 1 shows a block diagram of a memory device 100 according to various embodiments. Figure 1 In the illustrated embodiment, memory device 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuit 108, and control logic circuit 110. Although not shown in FIG. Figure 1, all components of the memory device 100 may be coupled to each other and to the control logic circuit 110. Figure 1 In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1 Some or all of the components shown in can be integrated together.For example, memory array 102 can include embedded I / O circuits (eg, 108).

[0032] The memory array 102 is a hardware component that stores data. In various embodiments, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other memory cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M Each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3, ... N , each column extends in a second direction (e.g., the Y direction). Each of the rows and columns may include one or more conductive (e.g., metal) structures used as access lines. Each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to a voltage or current through the corresponding conductive structures of the column and row. For example, each row may include one or more corresponding word lines (WL), and each column may include one or more corresponding bit lines (BL).

[0033] In some embodiments, each memory cell 103 is implemented as an electric fuse memory cell, which may include multiple fuse resistors and WL transistors. In various embodiments, each fuse resistor is coupled to a WL transistor, and the WL transistor and the fuse resistor are coupled between a corresponding BL and a source line that is typically connected to ground (VSS). For example, the fuse resistors are coupled in series with each other, and a terminal of one of the fuse resistors is electrically connected to a first source / drain terminal of the WL transistor. In addition, another of the fuse resistors has a terminal electrically connected to the corresponding BL. In another example, the fuse resistors are coupled in parallel with each other, and each of the fuse resistors has a first terminal electrically connected to a first source / drain of the WL transistor. In addition, each fuse resistor has a second terminal electrically connected to the corresponding BL. In either example, the gate terminal of the WL transistor is connected to the corresponding WL, and the second source / drain terminal of the WL transistor is connected to the source line. Reference will be made to each other, respectively. Figure 2 , Figure 3 and Figure 4 Details of various implementations of e-fuse memory cells are discussed in further detail.

[0034] In some other embodiments, each memory cell 103 may be implemented as any of a variety of other non-volatile memory cells. For example, the memory cell 103 may include a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell, an antifuse, etc., while remaining within the scope of the present disclosure.

[0035] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., WL) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert a conductive structure (e.g., BL) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the memory cells 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0036] Figure 2 , Figure 3 and Figure 4 2 and 4 respectively show example configurations 200, 300 and 400 of the e-fuse memory cell 103 according to various embodiments. Figure 2 , Figure 3 and Figure 4 The configurations in the disclosed e-fuse memory cells are respectively referred to as “e-fuse memory cell 200”, “e-fuse memory cell 300” and “e-fuse memory cell 400”. In various embodiments, each of the e-fuse memory cells 200 to 400 has a plurality of fuse resistors, so that the disclosed e-fuse memory cells present a logic state with randomly programmed fuse resistors. In addition, the plurality of fuse resistors are respectively physically formed at different vertical positions relative to the substrate, which makes it difficult to identify the position of the programmed fuse resistor.

[0037] First reference Figure 2, the electric fuse memory cell 200 includes a first fuse resistor 210, a second fuse resistor 220 and a WL transistor 230 connected in series with each other between BL and ground (VSS), wherein the WL transistor 230 is selected by WL. For example, the first fuse resistor 210 and the second fuse resistor 220 each have a first terminal and a second terminal, and the WL transistor 230 has a first source / drain terminal and a second source / drain terminal. The first terminal of the first fuse resistor 210 is connected to BL, the second terminal of the first fuse resistor 210 is connected to the first terminal of the second fuse resistor 220 at a node "X", the second terminal of the second fuse resistor 220 is connected to the first source / drain terminal of the WL transistor 230 at a node "Y", and the second source / drain terminal of the WL transistor 230 is connected to the ground.

[0038] The WL transistor 230 may be formed along a main (e.g., front side) surface of a semiconductor substrate, which is sometimes referred to as part of a front end of line (FEOL) process / network. On the front side surface, a plurality of first (or front side) metallization layers may be formed, each of which includes a plurality of interconnect (e.g., metal) structures / tracks, which are sometimes referred to as part of a back end of line (BEOL) process / network. Such front side metallization layers are sometimes referred to as M0 layers, M1 layers, M2 layers, etc., and the front side metal tracks (e.g., MX layers) included in the corresponding metallization layers are sometimes referred to as MX tracks. On the back side surface of the substrate, a plurality of second (or back side) metallization layers may be formed, each of which includes a plurality of interconnect (e.g., metal) structures / tracks. Such back side metallization layers are sometimes referred to as BM0 layers, BM1 layers, BM2 layers, etc. Such back side metallization layers are sometimes referred to as BM0 layers, BM1 layers, BM2 layers, etc., and therefore, the back side metal tracks included in the corresponding metallization layers (e.g., BMX layers) are sometimes referred to as BMX tracks.

[0039] In some embodiments, the first fuse resistor 210 may be formed as a plurality of backside metal tracks, and the second fuse resistor 220 may be formed as a plurality of frontside metal tracks. In some other embodiments, the first fuse resistor 210 may be formed as a plurality of frontside metal tracks in a first frontside metallization layer, and the second fuse resistor 220 may be formed as a plurality of frontside metal tracks in a different second frontside metallization layer. In other words, in various embodiments of the present disclosure, the metal tracks operable to serve as the first fuse resistor 210, the metal tracks operable to serve as the second fuse resistor 220, and the WL transistor 230 are vertically spaced apart from each other.

[0040] Next reference Figure 3, the electric fuse memory cell 300 is composed of a first fuse resistor 310, a second fuse resistor 320, a third fuse resistor 330 and a WL transistor 340 connected in series to each other between BL and ground (VSS), and the WL transistor 340 is selected by WL. For example, the first fuse resistor 310, the second fuse resistor 320 and the third fuse resistor 330 each have a first terminal and a second terminal, and the WL transistor 340 has a first source / drain terminal and a second source / drain terminal. The first terminal of the first fuse resistor 310 is connected to BL, the second terminal of the first fuse resistor 310 is connected to the first terminal of the second fuse resistor 320, the second terminal of the second fuse resistor 320 is connected to the first terminal of the third fuse resistor 330, the second terminal of the third fuse resistor 330 is connected to the first source / drain terminal of the WL transistor 340, and the second source / drain terminal of the WL transistor is connected to ground.

[0041] Similarly, the WL transistor 340 may be formed along the front side surface of the semiconductor substrate. In some embodiments, the first fuse resistor 310 may be formed as a plurality of back side metal tracks, and the third fuse resistor 330 may be formed as a plurality of front side metal tracks, and the second fuse resistor 320 coupled between the first and third fuse resistors 310 and 330 may be formed as a vertical back side via structure between the metal track that operably forms the first fuse resistor and the metal track that operably forms the third fuse resistor 330. In some other embodiments, the first fuse resistor 310 may be formed as a plurality of front side metal tracks in a first front side metallization layer, and the third fuse resistor 320 may be formed as a plurality of front side metal tracks in a different second front side metal layer. The second fuse resistor 320 coupled between the first and third fuse resistors 310 and 330 may be formed as a vertical front side via structure between the metal track that operably forms the first fuse resistor 310 and the metal track that operably forms the third fuse resistor 330. In other words, in various embodiments of the present disclosure, the metal track operable to serve as the first fuse resistor 310, the metal track operable to serve as the third fuse resistor 330, the via structure operable to serve as the second fuse resistor 320, and the WL transistor 340 are vertically spaced apart from each other.

[0042] Then refer to Figure 4, the electric fuse memory cell 400 is composed of a first fuse resistor 410, a second fuse resistor 420 and a WL transistor 430. Each of the first fuse resistor 410 and the second fuse resistor 420 is connected in series to the WL transistor 430 between BL and ground (VSS), wherein the WL transistor 430 is selected by WL. In other words, the first fuse resistor 410 and the second fuse resistor 420 can be connected to each other in parallel, and each of the first fuse resistor 410 and the second fuse resistor 420 is also connected in series to the WL transistor 430. For example, the first fuse resistor 410 and the second fuse resistor 420 each have a first terminal and a second terminal, and the WL transistor 430 has a first source / drain terminal and a second source / drain terminal. First terminals of the first and second fuse resistors 410 and 420 are commonly connected to BL, second terminals of the first and second fuse resistors 410 and 420 are commonly connected to a first source / drain terminal of a WL transistor 430 , and a second source / drain terminal of the WL transistor 430 is grounded.

[0043] Similarly, the WL transistor 430 can be formed along the front side surface of the semiconductor substrate. In some embodiments, the first fuse resistor 410 can be formed as a plurality of backside metal tracks, and the second fuse resistor 420 can be formed as a plurality of front side metal tracks. In some other embodiments, the first fuse resistor 410 can be formed as a plurality of front side metal tracks in a first front side metallization layer, and the second fuse resistor 420 can be formed as a plurality of front side metal tracks in a different second front side metallization layer. In other words, in various embodiments of the present disclosure, the metal tracks operable to serve as the first fuse resistor 410, the metal tracks operable to serve as the second fuse resistor 420, and the WL transistor 430 are vertically spaced apart from each other.

[0044] refer to Figure 5 , according to some embodiments, a method for forming an electrical fuse memory cell 200 ( Figure 2 ). As described above, the e-fuse memory cell 200 includes a WL transistor and first and second fuse resistors coupled in series with each other. The WL transistor may be composed of a plurality of sub-transistors (e.g., 100 sub-transistors) coupled in parallel with each other and formed along the front side surface of the substrate, while the first and second fuse resistors are each composed of a corresponding number of metal tracks spaced vertically from the front side surface. In some embodiments, the layout 500 may be configured to form the metal tracks of the first fuse resistor on the back side of the substrate, and the metal tracks of the second fuse resistor on the front side of the substrate.

[0045] As shown, layout 500 includes patterns 502, 504, 506, and 508, each of which is configured to form an oxide diffusion region (hereinafter, "oxide diffusion region 502", "oxide diffusion region 504", "oxide diffusion region 506", and "oxide diffusion region 508", respectively); and a plurality of patterns 512, a plurality of patterns 514, a plurality of patterns 516, and a plurality of patterns 518, each of which is configured to form a gate structure (hereinafter, "gate structure 512", "gate structure 514", "gate structure 516", and "gate structure 518", respectively). In some embodiments, oxide diffusion regions 502 to 508 may each extend along a first lateral direction (e.g., X direction), and gate structures 512 to 518 may each extend along a different second lateral direction (e.g., Y direction). It should be understood that layout 500 may include any number of each oxide diffusion region and gate structure while remaining within the scope of the present disclosure.

[0046] In some embodiments, the layout 500 can be used to form at least one electrical fuse memory cell 200 on a substrate. In addition, the oxide diffusion regions 502-504 together with the gate structures 512-514 can be disposed in a first region 501A of the substrate, while the oxide diffusion regions 506-508 together with the gate structures 516-518 can be disposed in a second region 501B of the substrate. Such first and second regions can be spaced apart from each other along the X direction using one or more dummy patterns (structures), such as Figure 5 shown.

[0047] Each of the gate structures 512 to 518 passes through a corresponding one of the oxide diffusion regions 502 to 508 to form a sub-transistor. In some embodiments, each of the oxide diffusion regions 502 to 508 is formed by a stacked structure protruding from the main (e.g., front side) surface of the substrate. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The portion of the semiconductor structure in the stack covered by the gate structure is retained, while the other portion is replaced with a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of a corresponding transistor (or sub-transistor), the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor structure can be configured as a source / drain structure (or terminal) of a transistor (or a sub-transistor), and the portion of the gate structure overlying (e.g., spanning) the remaining portion of the semiconductor structure can be constructed as a transistor (or sub-transistor).

[0048] For example, in Figure 5, the portion of the oxide diffusion region 502 covered by each gate structure 512 may include a plurality of nanostructures vertically separated from each other, which may serve as the channel of the first active sub-transistor. The portion of the oxide diffusion region 502 disposed on the opposite side of each gate structure 512 is replaced with an epitaxial structure. Such an epitaxial structure may serve as the source / drain terminal of the first active sub-transistor. The gate structure 512 may serve as the gate terminal of the first active sub-transistor. Similarly, the second active sub-transistor may be formed by each of the oxide diffusion region 504 and the gate structure 514. Therefore, it should be understood that the layout 500 (in region 501A) may be used to manufacture a certain number of these active sub-transistors, which are coupled in parallel to each other to serve collectively as the WL transistor 230 ( Figure 2 ).

[0049] For example, the source or drain terminals of adjacent first active sub-transistors (formed by oxide diffusion region 502 and adjacent gate structure 512) are connected to each other by sharing a first common epitaxial structure, and the drain or source terminals of adjacent first active sub-transistors (formed by oxide diffusion region 504 and adjacent gate structure 514) are connected to each other by sharing a second common epitaxial structure. In addition, each of such first common epitaxial structures is aligned with a corresponding one of the second common epitaxial structures along the Y direction, allowing them to be connected to each other through one or more metal tracks, which will be discussed below.

[0050] In addition, layout 500 (in region 501B) can be used to manufacture a certain number of pseudo sub-transistors. For example, a plurality of first pseudo sub-transistors may be formed by oxide diffusion regions 506 and gate structures 516, and a plurality of second pseudo sub-transistors may be formed by oxide scattering regions 508 and gate structures 518. In some embodiments, each of the first and second pseudo sub-transistors has a gate terminal, a drain terminal, and a source terminal connected to ground (VSS). As will be discussed below, the first and second pseudo sub-transistors may be formed to allow or otherwise facilitate connection between the front side and the back side of the substrate (e.g., a backside via structure, VB).

[0051] The layout 500 also includes patterns 520, 522, 524, and 526, each of which is configured to form a middle-end interconnect structure, sometimes referred to as MD (hereinafter, "MD 520", "MD 522", "MD524", and "MD526", respectively). Each pattern MD 520 to 526 can extend along the second lateral direction (e.g., the Y direction) to pass through a corresponding one of the oxide diffusion regions 502 to 508, and can be inserted between adjacent gate structures. Each pattern MD 520 to 526 is configured to couple the corresponding source / drain terminal to an upper metal track (e.g., M0 track) through a middle-end via structure (sometimes referred to as VD), and / or to a lower metal track (e.g., BM0 track) through a backside via structure (sometimes referred to as VB). For example, the layout 500 includes a plurality of patterns 528 , each of which is configured to form a VD (hereinafter referred to as “VD 528 ”), and a plurality of patterns 530 , each of which is configured to form a VB (hereinafter referred to as “VD 530 ”).

[0052] Layout 500 also includes patterns 532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552, 554, 556, 558, 560, 562, 564, 566, 568, 570, 572, and 574, each of which is configured to form a metal structure / track in a corresponding metallization layer. In some embodiments, the metal tracks formed by patterns 532, 534, 536, and 538 are each an M0 track (hereinafter referred to as “M0 track 532”, “M0 track 534”, “M0 track 536”, and “M0 track 538”, respectively); the metal tracks formed by patterns 540, 542, and 544 are each an M1 track (hereinafter referred to as “M1 track 540”, “M1 track 542”, and “M1 track 544”, respectively); the metal tracks formed by patterns 546, 548, 550, 552, and 554 are each an M2 track (hereinafter referred to as “M2 track 546”, “M2 track 548”, “M2 track 550”, “M2 track 552”, respectively). ” and “M2 track 554”); the metal tracks formed by patterns 556, 558, 560 and 562 are each BM0 tracks (hereinafter referred to as “BM0 track 556”, “BM0 track 558”, “BM0 track 560” and “BM0 track 562”, respectively); the metal tracks formed by pattern 564 are each BM1 tracks (hereinafter referred to as “BM1 track 564”); and the metal tracks formed by patterns 566, 568, 570, 572 and 574 are each BM2 tracks (hereinafter referred to as “BM2 track 566”, “BM2 track 568”, “BM2 track 570”, “BM1 track 572” and “BM2 track 574”, respectively).

[0053] In some embodiments, M0 rails 532-538, M1 rails 540-544, and M2 rails 546-554 are formed on the front side of the substrate, while BM0 rails 556-562, BM1 rails 564, and BM2 rails 566-574 are formed on the back side of the substrate. M0 rails 532-534 can connect WL transistor 230 ( Figure 2 ) is coupled to a second fuse resistor 220 ( Figure 2 ) terminal, and the other terminal of the second fuse resistor 220 can be coupled to the first fuse resistor 210 (formed by the BM2 tracks 566-574) through at least the M1 track 544, the M0 tracks 536-538, the MD 524-526, the VB530, the BM0 tracks 560-562 and the BM1 track 564. Figure 2 ) terminals.

[0054] The M0 track 532 may be coupled to a first one of the source / drain terminals of the WL transistor 230 (formed by the oxide diffusion region 502 and the gate structure 512) through the underlying MD 520 and VD528. Specifically, the M0 track 532 may be coupled to every other MD520 (or every other epitaxial structure formed in the oxide diffusion region 502). Similarly, the M0 track 534 may be coupled to a first source / drain terminal of the WL transistor 230 (formed by the oxide diffusion region 504 and the gate structure 514) through the underlying MD 522 and VD528. Specifically, the M0 track 534 may be coupled to every other one of the MDs 522 (or every other one of the epitaxial structures formed in the oxide diffusion region 504) aligned with the MD 520 (connected to the M0 track 532) in the Y direction, respectively. Each of the M0 rails 532 and 534 may have its right end coupled to the M1 rail 542 , and each of the M1 rails 542 may be coupled to the right ends of the M2 rails 550 - 552 and the M2 rail 554 .

[0055] As described above, the M2 rails 546-554 may collectively function as the second fuse resistor 220, and thus, the terminals coupled to the M1 rail 542 may function as the first source / drain terminals of the second fuse resistor 220 connected to the WL transistor 230 (eg, Figure 2 The opposite end of the M2 rail 554 and the M2 rails 546-548 (which serve as the other terminal of the second fuse resistor 220) may be coupled to one of the terminals of the first fuse resistor 210 formed by the BM2 rails 566-572 (e.g. Figure 2 Node X), which will be discussed below.

[0056] BM0 track 556 can be coupled to the second of the source / drain terminals of WL transistor 230 through a subset of VB530. Specifically, BM0 track 556 can be coupled to every other one of the epitaxial structures formed in oxide diffusion region 502. Similarly, BM0 track 558 can be coupled to the second source / drain terminal of WL transistor 230 through another subset of VB530. Specifically, BM0 track 558 can be coupled to every other one of the epitaxial structures formed in oxide diffusion region 504, and the epitaxial structures are respectively aligned along the Y direction with the epitaxial structures (connected to BM0 track 556) formed in oxide diffusion region 502. In some embodiments, each of BM0 tracks 556 and 558 can be configured to carry a power supply voltage, such as ground (VSS). Therefore, the second source / drain terminal of WL transistor 230 can be connected to ground.

[0057] In some embodiments, M2 tracks 546 and 548 may each extend away from M2 tracks 550-552 in the X direction to reach region 501B. As shown, along the Y direction, M2 tracks 546 and 548 each have a portion between the vertical projections of oxide diffusion regions 506 and 508. These portions of M2 tracks 546-548 may be coupled to each epitaxial structure (e.g., each source / drain terminal of a pseudo-sub-transistor) formed in oxide diffusion regions 506 and 508 through at least M1 track 544, M0 tracks 536-538, VD528, and MD524-526. These epitaxial structures may be further coupled to BM0 tracks 560-562 through yet another subset of VB530. BM0 tracks 560-562 may be coupled to BM1 track 564, and BM1 track 564 may be coupled to portions of BM2 tracks 566-568 in region 501B. Similar to M2 tracks 546 - 548 , each of BM2 tracks 566 - 568 extends toward BM2 tracks 570 - 572 to reach region 501A.

[0058] As described above, the BM2 rails 566-572 may be used together as the first fuse resistor 210. Therefore, the left end of the BM2 rail 574 and the right end of the BM2 rails 566-568 may be used as a connection to the second fuse resistor 220 (eg, Figure 2 The BM2 rail 574 and the opposite ends of the BM2 rails 570-572 (serving as the other terminal of the first fuse resistor 210) may be coupled to the BL. In some embodiments, similar to the M2 rails 546-548, each of the BM2 rails 570-572 may have a portion extending away from the BM2 rails 566-568 in the X direction to allow connection to the BL. Although Figure 5It is not explicitly shown, but it should be understood that such extensions of the M2 tracks 570-572 may be omitted in another region of the substrate in region 501A opposite to region 501B (in the X direction). The BL may be formed as one or more metal tracks disposed on the front side of the substrate. The BL may be coupled to the source / drain terminals of an input / output transistor or a peripheral transistor, as will be discussed below.

[0059] Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 A cross-sectional view of a semiconductor device 600 according to some embodiments is shown. The semiconductor device 600 may be respectively based on Figure 5 The layout 500 is formed. Therefore, Figure 5 Some of the reference numerals may be found in the following Figure 6-Figure 10 For example, Figure 6 The cross-sectional view is taken along line AA, as shown in Figure 5 As shown, line AA extends along the X direction through oxide diffusion regions 502 and 506 and M0 track 532; Figure 7 The cross-sectional view is taken along line BB, which extends along the X direction through the M2 rails 546 and 550 and the BM2 rails 566 and 570, as shown in FIG. Figure 5 As shown; Figure 8 The cross-sectional view is taken along line CC, which extends along the X direction through the M2 track 554 and the BM2 track 574, as shown in FIG. Figure 5 As shown; Fig. 9 The cross-sectional view is taken along line DD, which passes through the M2 track 554 and the BM2 track 574 along the Y direction, as shown in FIG. Figure 5 as shown; and Fig.10 The cross-sectional view is along Figure 5 The diagram is taken along the Y direction along the line EE that crosses the M2 tracks 550-554 and the BM2 tracks 570-574. It should be understood that Figure 6-Figure 10 The cross-sectional views are simplified for illustrative purposes and thus some components may be omitted.

[0060] exist Figure 6In the embodiment of the present invention, along the oxide diffusion region 502 in region 501A, a plurality of channels 610 and epitaxial structures 620 may be formed. Each channel 610 may be covered or wrapped by a corresponding one of the gate structures 512, and some of the epitaxial structures may be covered by a corresponding MD (not shown). Similarly, along the oxide diffusion region 506 in region 501B, a plurality of channels 630 and epitaxial structures 640 may be formed. Each channel 630 may be covered or wrapped by a corresponding one of the gate structures 516, and some of the epitaxial structures may be covered by a corresponding MD (not shown). Above the front side of the oxide diffusion region 502, an M0 track 532 is formed above the gate structure 512, and above the back side of the oxide diffusion region 502 (or the substrate in region 501A), a BM0 track 556 is formed. In addition, on the back side of the oxide diffusion region 506 (or the substrate in region 501B), a BM0 track 560 is formed.

[0061] exist Figure 7 In the embodiment of the present invention, over the front side of the substrate, M1 tracks 540-542 are formed in region 501A (e.g., in the region of oxide diffusion regions 502-504), and M1 track 544 is formed in region 501B (e.g., in the region of oxide diffusion regions 506-508). M2 tracks 546 and a portion of M2 track 550 are further formed over M1 tracks 540-542, and another portion of M2 track 546 is further formed over M1 track 5440. Over the back side of the substrate, BM2 tracks 566 and a portion of BM2 track 570 are formed in region 501A, and another portion of BM2 track 566 is formed in region 501B. In some embodiments, in region 501A, there may be no BM1 track between the back side of the substrate and the upper metal tracks (e.g., BM2 tracks 566 and 570), while in region 501B, BM1 track 564 may be between the back side of the substrate and BM2 track 564.

[0062] exist Figure 8 In the embodiment of the present invention, over the front side of the substrate, M1 tracks 540-542 are formed in region 501A (e.g., formed in the region of oxide diffusion regions 502-504), and M1 track 544 is formed in region 503B (e.g., formed in the region of oxide diffusion regions 506-508). M2 track 554 is further formed over M1 tracks 540-542. Over the back side of the substrate, BM2 track 574 is formed in region 501A. In some embodiments, in region 501A, there may be no BM1 track between the back side of the substrate and the upper metal track (e.g., BM2 track 574), while in region 501B, BM1 track 564 may be between the back side of the substrate and other BM2 tracks (or other upper metal tracks).

[0063] exist Fig. 9 , MD 520 and MD 522 are connected to the front side of epitaxial structure 620 in oxide diffusion regions 502 and 504, respectively. M2 track 554 is further formed above MD 520-522, with M0 tracks 532-534 interposed therebetween. In some embodiments, M2 track 554 can be between oxide diffusion regions 502 and 504 along the Y direction. On the back side, BM0 tracks 556 and 558 are connected to epitaxial structure 620 through the first and second of VB 530, respectively. BM2 track 574 is further formed above BM0 tracks 556-558. In some embodiments, BM2 track 574 can be between oxide diffusion regions 502 and 504 along the Y direction, and more specifically, BM2 track 574 can be vertically aligned with M2 track 554. In some embodiments, BM0 tracks 556-558 can be configured to carry a power supply voltage (e.g., ground) that connects the second source / drain terminal of WL transistor 230 to ground (as described above).

[0064] exist Fig.10 , MD 520 and MD 522 are connected to the front side of epitaxial structure 620 in oxide diffusion regions 502 and 504, respectively. Each of M2 tracks 550 to 554 is further formed above MD 520-522, with M0 tracks 532-534 and M1 track 542 interposed therebetween. In some embodiments, M2 tracks 550-554 may be interposed between oxide diffusion regions 502 and 504 along the Y direction. On the back side, BM0 tracks 556 and 558 are connected to epitaxial structure 620 through the first and second of VB 530, respectively. BM2 tracks 570-574 are further formed above BM0 tracks 556-558. In some embodiments, BM2 tracks 570-574 may be interposed between oxide diffusion regions 502 and 504 along the Y direction, and more specifically, BM2 tracks 570-574 may be vertically aligned with M2 tracks 550-554, respectively.

[0065] Fig.11 It shows that according to some embodiments, Figure 5 A hybrid cross-sectional view of another semiconductor device 1100 formed with the layout 500 is shown. Fig.11 The mixed cross-section diagram can be Figure 6-Figure 10 A combination of some cross-sectional views and may further include Figure 2 The schematic diagram of the configuration 200 is aligned with other components. In addition, for the purpose of illustration, the layout 500 ( Figure 5 )Adjustment Fig.11 The relative arrangement between components in the hybrid cross-sectional view.

[0066] For example, WL transistor 230 ( Figure 2 ) may be formed by oxide diffusion regions 502-504 and gate structures 512-514, the second fuse resistor 220 may be formed by M2 rails 546 to 554, and the first fuse resistor 210 may be formed by BM2 rails 566 to 574. The WL transistor 230 may have a gate terminal connected to a WL formed by at least one M0 rail, one of the source / drain terminals connected to the M2 rail 550 / 552 through at least the M0 rail 532 / 534 and the M1 rail 542, and the other source / drain terminal connected to the ground / VSS carried by the BM0 rails 556-558. Specifically, the M2 rails 546 / 548 (of the second fuse resistor 220) may be coupled to the BM2 rails 566 / 568 of the first fuse resistor 210 through at least the M1 rail 544, the M0 rails 560 / 562, the BM0 rails 560 / 562, and the BM1 rail 564.

[0067] As described above, similar to the M2 track 546 / 548 of the second fuse resistor 220 on the front side, the BM2 track 570 / 572 of the first fuse resistor 210 can be extended away from its other terminal (BM2 track 566 / 568) to allow the first fuse resistor 210 to be coupled to the BL, which can be formed by at least one M0 track 1102 in the region 501A. Therefore, the BM2 track 570 / 572 can extend away from the region 501B. In some embodiments, the BL 1102 can be coupled to the BM2 track 570 / 572 through at least one oxide diffusion region 1104 (or an epitaxial structure formed therein), one or more VBs 1106, one or more BM0 tracks 1108, and one or more BM1 tracks 1110, as shown in FIG. Fig.11 In some embodiments, BL 1102 may be coupled to an input / output transistor (part of I / O circuit 108 ) that may generate a programming voltage and a read voltage to be applied to BL 1102 .

[0068] Next reference Fig.12 , according to some embodiments, a method for forming an electrical fuse memory cell 200 ( Figure 2 ) is another example layout 1200. The layout 1200 is substantially similar to Figure 5 1200 is different from the layout 500 of FIG. 1200 , except that the layout 1200 is configured to form the first fuse resistor 210 on the front side of the substrate (or the same side as the second fuse resistor 220 ). Therefore, the following discussion of the layout 1200 will focus on the difference. Fig.13, a hybrid cross-sectional view of a semiconductor device 1300 that may be formed from the layout 1200 is shown according to some embodiments. Thus, the semiconductor device 1300 may be an implementation of the electrical fuse memory cell 200. For illustration purposes, the layout 1200 ( Fig.12 )Adjustment Fig.13 The relative arrangement between components in the hybrid cross-sectional view.

[0069] like Fig.12 As shown, layout 1200 includes patterns of oxide diffusion regions 1202 and 1204 and gate structures 1206 and 1208, respectively, formed along the front side surface of the substrate. Oxide diffusion regions 1202-1204 and gate structures 1206-1208 are operable to function as WL transistor 230, as shown in FIG. Fig.13 As shown. Refer again Fig.12 , the layout 1200 also includes a pattern for forming a plurality of M2 tracks 1220, 1222, 1224, 1226, and 1228 on the front side, respectively, and a pattern for forming a plurality of M4 tracks 1230, 1232, 1234, 1236, and 1238 on the back side, respectively. In some embodiments, the M2 tracks 1220 to 1228 may be vertically aligned with the M4 tracks 1230 to 1238, respectively. Fig.13 As shown, the M2 rails 1220-1226 are operable to serve as fuse resistor 220, and the M4 rails 1230-1236 are operable to serve as fuse resistor 210. One of the source / drain terminals of the WL transistor 230 is coupled to the BM0 rail 1210 / 1212 carrying ground / VSS, and the other source / drain terminal of the WL transistor 230 is coupled to a first terminal (e.g., M2 rail 1224 / 1226) of the fuse resistor 220. The fuse resistors 210 and 220 may have their second terminals (e.g., M2 rail 1220 / 1222 and M4 rail 1230 / 1232) coupled to each other through at least one M3 rail. In addition, the first terminal (e.g., M2 rail 1234 / 1236) of the fuse resistor 210 may be coupled to the BL, which may be formed by at least another metal rail.

[0070] Next reference Fig.14 , according to some embodiments, a method for forming an electrical fuse memory cell 300 ( Figure 3 ) is an example layout 1400. The layout 1400 is substantially similar to Fig.12 1400 is different from the layout 1200 of FIG. 1400 , except that the layout 1400 is configured to form an additional fuse resistor (e.g., 320) between two fuse resistors (e.g., 310 and 330) disposed on the front side of the substrate. Therefore, the following discussion of the layout 1400 will focus on the difference. Fig.15, a hybrid cross-sectional view of a semiconductor device 1500 that may be formed from the layout 1400 is shown according to some embodiments. Thus, the semiconductor device 1500 may be an implementation of the e-fuse memory cell 300. For illustration purposes, the layout 1400 ( Fig.14 )Adjustment Fig.15 The relative arrangement between components in the hybrid cross-sectional view.

[0071] like Fig.14 As shown, layout 1400 includes patterns of oxide diffusion regions 1402 and 1404 and gate structures 1406 and 1408, respectively, formed along the front side surface of the substrate. Oxide diffusion regions 1402-1404 and gate structures 1406-1408 are operable to function as WL transistor 330, as shown in FIG. Fig.15 As shown. Refer again Fig.14 , the layout 1400 also includes a pattern for forming a plurality of M2 tracks 1420, 1422, 1424, 1426, and 1428, respectively, over the front side, and a pattern for forming a plurality of M4 tracks 1430, 1432, 1434, 1436, and 1438, respectively, over the back side. In some embodiments, the M2 tracks 1420 to 1428 may be vertically aligned with the M4 tracks 1430 to 1438, respectively. Fig.15 As shown, the M2 rails 1420-1426 are operable to function as the fuse resistor 330, and the M4 rails 1430-1436 are operable to function as the fuse resistor 310. In addition, the layout 1400 includes a pattern for forming a via structure 1440 interposed between the M2 rails and the M4 rails (e.g., between the M2 rail 1428 and the M4 rail 1438). In some embodiments, such a via structure 1440 is operable to function as the fuse resistor 320 coupled between the fuse resistors 310 and 330. One of the source / drain terminals of the WL transistor 340 is coupled to the BM0 rail 1510 / 1512 carrying the ground / VSS, and the other source / drain terminal of the WL transistor 340 is coupled to the first terminal of the fuse resistor 330 (e.g., the M2 rail 1424 / 1426). The fuse resistors 310 and 330 may have second terminals (e.g., M2 tracks 1420 / 1422 and M4 tracks 1430 / 1432) coupled to each other through at least one M3 track and via structure 1440. In addition, a first terminal (e.g., M4 track 1434 / 1436) of the fuse resistor 310 may be coupled to a BL, which may be formed by at least another metal track.

[0072] Fig.16 FIG. 1 shows a hybrid cross-sectional view of a semiconductor device 1600 according to some embodiments. The semiconductor device 1600 is substantially similar to the semiconductor device 1100 ( Fig.11 ) and semiconductor device 1500( Fig.15 ) combination. The semiconductor device 1600 may be Figure 3 Another implementation of the electric fuse memory cell 300 is shown. For example, the semiconductor device 1600 includes a WL transistor 1640 formed along the front side of the substrate, a fuse resistor 1610 formed by a plurality of BM2 tracks, a fuse resistor 1630 formed by a plurality of M2 tracks, and a fuse resistor 1620 formed by a backside via structure, which may correspond to the WL transistor 340, the fuse resistor 310, the fuse resistor 330, and the fuse resistor 320, respectively.

[0073] Fig.17 FIG. 1 shows a hybrid cross-sectional view of a semiconductor device 1700 according to some embodiments. The semiconductor device 1700 is substantially similar to the semiconductor device 1500 ( Fig.15 ). The semiconductor device 1700 may be Figure 3 Another embodiment of the electric fuse memory cell 300 includes an additional fuse resistor coupled between the fuse resistors 310 and 340. For example, the semiconductor device 1700 includes a WL transistor 1740 formed along the front side of the substrate, a fuse resistor 1710 formed by a plurality of M4 tracks, a fuse resistor 1730 formed by a plurality of M2 tracks, and a fuse resistor 1720B formed by a backside via structure, which may correspond to the WL transistor 340, the fuse resistor 310, the fuse resistor 330, and the fuse resistor 320, respectively. The semiconductor device 1700 may also include another fuse resistor 1720A, which may be formed by an RRAM cell, an MRAM cell, or a PCRAM cell. Such an additional fuse resistor may be coupled between the fuse resistors 320 and 330 or between the fuse resistors 320 and 310 ( Figure 3 ).

[0074] In an example where the fuse resistor 1720A is implemented as an RRAM cell, the fuse resistor 1720A may include at least one variable resistance layer interposed between a top electrode and a bottom electrode. Fig.17 In some embodiments, the variable resistance layer includes at least one of nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminum oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO) and copper oxide (CuO).

[0075] In an example where the fuse resistor 1720A is implemented as a PCRAM cell, the fuse resistor 1720A may include at least one phase change material layer and a heater sandwiched between a top electrode and a bottom electrode. Fig.17In the example of can be implemented as M4 track and M3 track respectively. In some embodiments, the phase change material layer includes one of the following: a binary system of Ga-Sb, In-Sb, In-Se, Sb-Te, Ge-Te and Ge-Sb; a ternary system of Ge-Sb-Te, In-Sb-Te, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge and Ga-Sb-Te; or a quaternary system of Ag-In-Sb-Te, Ge-Sn-Sb-Te, Ge-Sb-Se-Te, Te-Ge-Sb-S, Ge-Sb-Te-O and Ge-Sb-Te-N. In some embodiments, the phase change material layer includes a chalcogenide alloy containing one or more elements from Group VI of the periodic table, such as GST, Ge-Sb-Te alloy (e.g., Ge2Sb2Te5). The heater formed of a metallic material may function as a heat sink during quenching of the phase change material layer (during a sudden cutoff of the current applied to the heater to freeze the amorphous phase).

[0076] In an example where the fuse resistor 1720A is implemented as an MRAM cell, the fuse resistor 1720A may include at least one ferromagnetic free layer, a dielectric spacer serving as a tunnel barrier, a ferromagnetic pinned layer, and an antiferromagnetic pinned layer, which are arranged in this order between a top electrode and a bottom electrode. Fig.17 In the example of , they can be implemented as M4 tracks and M3 tracks respectively. In some embodiments, the ferromagnetic free layer and the ferromagnetic pinned layer are composed of ferromagnetic materials, such as cobalt iron or nickel cobalt iron. The antiferromagnetic pinned layer is composed of antiferromagnetic materials, such as platinum manganese. The static magnetocouple between the ferromagnetic pinned layer and the antiferromagnetic pinned layer causes the ferromagnetic pinned layer to have a fixed magnetic moment. On the other hand, the ferromagnetic free layer has a magnetic moment, and by applying a magnetic field, the magnetic moment can be switched between a first orientation parallel to the magnetic moment of the ferromagnetic pinned layer and a second orientation antiparallel to the magnetic moment of the ferromagnetic pinned layer.

[0077] Fig.18 FIG. 1 shows a hybrid cross-sectional view of a semiconductor device 1800 according to some embodiments. The semiconductor device 1800 may be Figure 2 The semiconductor device 1800 is substantially similar to the semiconductor device 1300 ( Fig.13), except that one of the fuse resistors can also be formed along the front side surface of the substrate. For example, the semiconductor device 1800 includes a WL transistor 1830 formed along the front side of the substrate, a fuse resistor 1810 formed by a plurality of M2 tracks, and a fuse resistor 1820 formed by a gate structure. The fuse resistor 1820 may include a polysilicon material or a metal material. In some embodiments, the fuse resistor 1820 may be formed to be arranged in parallel with the gate terminal of the WL transistor 1830. In addition, in some embodiments, the width of the fuse resistor 1820 may be substantially narrower than the width of the gate terminal of the WL transistor 1830.

[0078] Fig.19 FIG. 1 shows a hybrid cross-sectional view of a semiconductor device 1900 according to some embodiments. The semiconductor device 1900 may be Figure 2 The semiconductor device 1900 is substantially similar to the semiconductor device 1300 ( Fig.13 ), except that the metal tracks of the fuse resistors are not vertically aligned. For example, the semiconductor device 1900 includes a WL transistor 1930 formed along the front side of the substrate, a fuse resistor 1910 formed by a plurality of M4 tracks, and a fuse resistor 1920 formed by a plurality of M2 tracks. In some embodiments, except for the metal track connecting the fuse resistor 1920 to the fuse resistor 1910, the metal tracks of the fuse resistor 1910 and the fuse resistor 1920 may not be vertically aligned.

[0079] Fig. 20 FIG. 2 shows a hybrid cross-sectional view of a semiconductor device 2000 according to some embodiments. The semiconductor device 2000 may be Figure 2 The semiconductor device 2000 is substantially similar to the semiconductor device 1300 ( Fig.13 ), except that the metal tracks of the fuse resistor are arranged in the same metallization layer. For example, the semiconductor device 2000 includes a WL transistor 2030 formed along the front side of the substrate, a fuse resistor 2010 formed by a plurality of M2 tracks, and a fuse resistor 2020 formed by a plurality of other M2 tracks. In some embodiments, in addition to the metal track connecting the fuse resistor 2020 to the fuse resistor 2010, the metal tracks of the fuse resistor 2010 and the fuse resistor 2020 can be laterally spaced apart from each other.

[0080] Fig.21 FIG. 2 shows a hybrid cross-sectional view of a semiconductor device 2100 according to some embodiments. The semiconductor device 2100 may be Figure 4For example, the semiconductor device 2100 includes a WL transistor 2130, a fuse resistor 2110, and a fuse resistor 2120 formed along the front side of the substrate, wherein the fuse resistors 2110 and 2120 are coupled to each other in parallel and are each connected in series to the WL transistor 2130. Fig.21 In the illustrative example of , fuse resistor 2110 may be formed by a via structure between an M2 track and an M3 track, and fuse resistor 2120 may be formed by another via structure placed between the same M2 track and M3 track.

[0081] Fig. 22 A flow chart of an example method 2200 for forming an electric fuse memory cell including a plurality of fuse resistors according to some embodiments is shown. The electric fuse memory cell fabricated by the method 2200 may include a first fuse resistor formed on a front side of a substrate and a second fuse resistor formed on a back side of the substrate. In some embodiments, the method 2200 may be performed to Figure 5 500 is shown in the figure to form an electrical fuse memory cell (e.g. Figure 2 200), and therefore, some of the references used above may be reused in the following discussion of method 2200. It should be noted that method 2200 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that in Fig. 22 Additional operations are provided before, during, and after method 2200, and some other operations may be only briefly described herein.

[0082] According to various embodiments, method 2200 begins with operation 2202 of providing a substrate. The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer overlying a bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0083] Method 2200 continues to operation 2204, in which, according to various embodiments, a stack including an alternating series of first and second nanostructures is formed. Such a stack can be formed based on one of the (oxide diffusion) patterns discussed above. The stack can be formed in the front side of the substrate. In some embodiments, the first nanostructure can include a SiGe sacrificial nanostructure, and the second nanostructure can include a Si channel nanostructure. Such a stack can sometimes be referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure can be 25% SiGe. The symbol "SiGe25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each SiGe sacrificial nanostructure can be any value between 0 and 100 (excluding 0 to 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure can include a first semiconductor material other than Si, and the first nanostructure can include a second semiconductor material other than SiGe, as long as the first and second semiconductor materials have different etching characteristics (e.g., etching rates), respectively.

[0084] The alternating series of nanostructures can be formed by epitaxially growing one layer and then the next until the desired number and thickness of nanostructures are obtained. The epitaxial material can be grown from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) or other suitable processes. Epitaxial silicon, silicon germanium and / or carbon doped silicon (Si:C) silicon can be doped (in situ doping) during deposition by adding dopants, i.e., n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor.

[0085] According to various embodiments, the method 2200 continues to operation 2206, in which a plurality of dummy gate structures are formed. Such dummy gate structures may be formed based on one of the above-mentioned (gate structure) patterns. The dummy gate structures may extend in a direction perpendicular to the length direction of the dielectric fin structure (and stack). In addition, in one of the various embodiments, the dummy gate structures may be formed shorter than the dielectric fin structures, so that the formed dummy gate structures are cut (or otherwise separated) by the dielectric fin structures.

[0086] A pseudo gate structure can be formed by depositing amorphous silicon (a-Si) on the stack. Other materials suitable for forming a pseudo gate (e.g., polysilicon) can be used while remaining within the scope of the present disclosure. The a-Si is then flattened to a desired level. A hard mask is deposited on top of the flattened a-Si and patterned. The hard mask can be formed by a nitride layer or an oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After the pseudo gate structure is formed, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any appropriate combination of these materials) followed by directional etching (e.g., RIE).

[0087] Method 2200 proceeds to operation 2208, in which, according to various embodiments, internal spacers are formed by replacing the ends of each SiGe sacrificial nanostructure with a dielectric material. When forming a pseudo gate structure covering certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the uncovered portions of the stack are removed. Next, the corresponding ends of each SiGe sacrificial nanostructure covering the stack are removed. The internal spacers are formed by filling these recesses of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD), or by single-layer doping (MLD) of nitride followed by spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5).

[0088] According to various embodiments, method 2200 proceeds to operation 2210, in which a plurality of epitaxial structures are formed. When forming the internal spacers, an epitaxial structure is formed on the exposed end of the Si nanostructure using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form the doped epitaxial structure to create the necessary junctions for the corresponding transistors (or sub-transistors). N-type and p-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and p-type devices can be formed by injecting boron (B). After the epitaxial structure is formed, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0089] According to various embodiments, method 2200 proceeds to operation 2212, where the dummy gate structure and the remaining SiGe sacrificial nanostructures are replaced with corresponding active gate structures. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process (e.g., RIE or chemical oxide removal (COR)). Next, the remaining SiGe sacrificial nanostructures are removed while keeping the Si channel nanostructures substantially intact by applying a selective etchant (e.g., hydrochloric acid (HCl)). After removing the SiGe sacrificial nanostructures, the top and bottom surfaces and sidewalls of each Si channel nanostructure can be exposed, except for the sidewalls that contact the dielectric fin structure. Next, a plurality of active gate structures can be formed to wrap each Si channel nanostructure, except for the sidewalls that contact the dielectric fin structure. Each active gate structure includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer). After forming the active gate structure, the WL transistor 230 ( Figure 2 ).

[0090] Method 2200 proceeds to operation 2214, in which a plurality of front-side interconnect structures are formed according to various embodiments. When forming the WL transistor (or its sub-transistor), a plurality of intermediate-end interconnect structures (e.g., VG, VD, MD) are formed thereon. For example, a plurality of VGs may be formed to be respectively connected to the gate terminals, and a plurality of MDs may be formed to be respectively connected to the source / drain terminals through a plurality of VDs. In addition, a plurality of back-end interconnect structures may be formed on the intermediate-end interconnect structures. Such back-end interconnect structures include the above-mentioned M0 tracks (e.g., 532-538), M1 tracks (e.g., 540-544), M2 tracks (e.g., 546-554), etc. In some embodiments, a plurality of M2 tracks may be operable as fuse resistors 220 ( Figure 2 In some embodiments, one terminal of the fuse resistor 220 is coupled to one source / drain terminal of the WL transistor 230 through a plurality of middle-end and back-end interconnect structures disposed on the front side.

[0091] The front-side interconnect structure is formed of a metal material. The metal material may be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front-side interconnect structure may be formed by covering the metal material on the front side of the substrate by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0092] The method 2200 proceeds to operation 2216, in which a plurality of backside interconnect structures are formed according to various embodiments. When forming the back-end metal track, the substrate is flipped, and a plurality of backside interconnect structures (e.g., BM0 track, BM1 track, BM2 track, etc.) are formed on the back side of the substrate. For example, after the substrate is flipped, a polishing process can be performed on the back side of the substrate until the bottom surface of the epitaxial structure (e.g., the source / drain terminals formed in operation 2210) is exposed. Next, one or more dielectric layers are formed on the polished backside surface, followed by the formation of the above-mentioned backside via structures (e.g., VB530), each of which can extend through one or more dielectric layers to reach the bottom surface of the corresponding epitaxial structure. Next, backside interconnect structures (e.g., 556-562, 564, 566-574, etc.) can be formed in the corresponding backside metallization layer. In some embodiments, the plurality of BM2 tracks are operable to serve as fuse resistors 210 ( Figure 2 ). In some embodiments, one terminal of the fuse resistor 210 is coupled to another terminal of the fuse resistor 220 through a plurality of middle-end and back-end interconnect structures disposed on the front side and further through a plurality of back-side interconnect structures. In some embodiments, such interconnect structures coupling the fuse resistor 210 to the fuse resistor 220 may be disposed in a region (e.g., region 501B) laterally surrounding a region (e.g., region 501A) where the WL transistor 230 is formed.

[0093] The backside interconnect structure is formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The backside interconnect structure can be formed by covering the metal material on the front side of the substrate by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or a combination thereof.

[0094] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a transistor formed along a front side surface of a substrate. The memory device includes a first fuse resistor formed in a first metallization layer disposed vertically relative to the front side surface. The memory device includes a second fuse resistor formed in a second metallization layer disposed vertically relative to the front side surface, the first metallization layer being different from the second metallization layer. The second fuse resistor and the first fuse resistor are each coupled to the transistor.

[0095] In some embodiments, the second fuse resistor, the first fuse resistor, and the transistor are coupled in series with each other.

[0096] In some embodiments, the second fuse resistor and the first fuse resistor are coupled in parallel to each other, and each of the second fuse resistor and the first fuse resistor is coupled in series to the transistor.

[0097] In some embodiments, one of the first fuse resistor or the second fuse resistor is configured to be randomly blown to permanently assume a logic state.

[0098] In some embodiments, the first fuse resistor includes a first metal track, a second metal track, a third metal track, a fourth metal track, and a fifth metal track, and the first to fifth metal tracks are arranged in a first metallization layer and extend along a first lateral direction; the second fuse resistor includes a sixth metal track, a seventh metal track, an eighth metal track, a ninth metal track, and a tenth metal track, and the sixth to tenth metal tracks are arranged in a second metallization layer and extend along the first lateral direction.

[0099] In some embodiments, the first metal track has a first end and a second end along a first lateral direction, wherein the first end of the first metal track is between the second metal track and the third metal track along a second lateral direction perpendicular to the first lateral direction, and wherein the second end of the first metal track is between the fourth metal track and the fifth metal track along the second lateral direction.

[0100] In some embodiments, the sixth metal track has a first end and a second end along the first lateral direction, wherein the first end of the sixth metal track along the second lateral direction is between the seventh metal track and the eighth metal track, and wherein the two ends of the sixth metal track along the second lateral direction are between the ninth metal track and the tenth metal track.

[0101] In some embodiments, the second metal track and the third metal track each have a first portion extending along the first lateral direction away from the first end of the first metal track, and wherein the seventh metal track and the eighth metal track each have a second portion extending along the first lateral direction away from the first end of the sixth metal track.

[0102] In some embodiments, the first portion and the second portion are coupled to each other through at least a plurality of through-hole structures.

[0103] In some embodiments, each of the plurality of via structures extends through a backside surface of the substrate opposite the frontside surface.

[0104] In some embodiments, the first portion and the second portion are disposed in a first region of the substrate, the first region is spaced apart from a second region of the substrate, and wherein at least the transistor is formed in the second region.

[0105] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a one-time programmable (OTP) memory cell, the OTP memory cell including a transistor, a first resistor, and a second resistor. The second resistor is coupled in series to the first resistor, and the first resistor is coupled in series to the transistor. The first resistor, the second resistor, and the transistor are vertically spaced apart from each other.

[0106] In some embodiments, one of the first resistor or the second resistor is configured to be randomly blown so that the OTP memory cell permanently assumes a logic state.

[0107] In some embodiments, the transistor is formed along a front side surface of the substrate, the first resistor includes a plurality of first metal tracks formed in one of a plurality of front side metallization layers disposed above the front side surface, and the second resistor includes a plurality of second metal tracks formed in one of a plurality of back side metallization layers disposed above the back side surface of the substrate.

[0108] In some embodiments, the transistor is formed along a front side surface of the substrate, the first resistor includes a plurality of first metal tracks formed in a first front side metal layer among a plurality of front side metallization layers disposed above the front side surface, and the second resistor includes a plurality of second metal tracks formed in a second front side metallization layer among the plurality of front side metallization layers.

[0109] In some embodiments, the OTP memory cell further includes a third resistor coupled in series between the first resistor and the second resistor.

[0110] In some embodiments, the transistor is formed along the front side surface of the substrate, the first resistor includes a plurality of first metal tracks formed in a first front side metal layer among a plurality of front side metallization layers disposed above the front side surface, the second resistor includes a plurality of second metal tracks formed in a second front side metallization layer among the plurality of front side metallization layers, and the third resistor includes a through-hole structure between the first front side metallization layer and the second front side metallization layer.

[0111] In some embodiments, the transistor is formed along a front side surface of the substrate, the first resistor includes a plurality of first metal tracks formed in one of a plurality of front side metallization layers disposed above the front side surface, the second resistor includes a plurality of second metal tracks formed in one of a plurality of back side metallization layers disposed above the back side surface of the substrate, and the third resistor includes a via structure between the back side surface and the back metallization layer.

[0112] In yet another aspect of the present disclosure, a method is disclosed. The method includes forming a transistor along a front side surface of a substrate. The method includes forming a plurality of front side metal tracks disposed above the front side surface, wherein the plurality of front side metal tracks include a word line, a bit line, and a first fuse resistor. The method includes forming a plurality of back side metal tracks disposed above a back side surface of the substrate, wherein the plurality of back side metal tracks include a second fuse resistor. The word line is electrically connected to a gate terminal of the transistor, the bit line is electrically connected to a first end of the second fuse resistor, the second end of the second fuse resistor is electrically connected to the first end of the first fuse resistor, and the second end of the first fuse resistor is electrically connected to a source / drain terminal of the transistor.

[0113] In some embodiments, the first fuse resistor and the second fuse resistor are vertically aligned with each other.

[0114] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: A transistor formed along a front side surface of the substrate; a first fuse resistor formed in a first metallization layer disposed vertically relative to the front surface; as well as a second fuse resistor formed in a second metallization layer disposed vertically relative to the front surface, the first metallization layer being different from the second metal layer; The second fuse resistor and the first fuse resistor are each coupled to the transistor.

2. The memory device according to claim 1, wherein: The second fuse resistor, the first fuse resistor, and the transistor are coupled to each other in series.

3. The memory device according to claim 1, wherein: The second fuse resistor and the first fuse resistor are coupled to each other in parallel, and each of the second fuse resistor and the first fuse resistor is coupled to the transistor in series.

4. The memory device according to claim 1, wherein: One of the first fuse resistor or the second fuse resistor is configured to be randomly blown so as to permanently assume a logic state.

5. The memory device according to claim 1, wherein: The first fuse resistor includes a first metal track, a second metal track, a third metal track, a fourth metal track and a fifth metal track, the first to fifth metal tracks are arranged in the first metallization layer and extend along a first lateral direction; The second fuse resistor includes a sixth metal track, a seventh metal track, an eighth metal track, a ninth metal track and a tenth metal track, the sixth to tenth metal tracks being arranged in the second metallization layer and extending along the first lateral direction.

6. The memory device according to claim 5, wherein: The first metal track has a first end and a second end along the first transverse direction, wherein the first end of the first metal track is between the second metal track and the third metal track along a second transverse direction perpendicular to the first transverse direction, and wherein the second end of the first metal track is between the fourth metal track and the fifth metal track along the second transverse direction.

7. A memory device comprising: A one-time programmable memory cell comprising a transistor, a first resistor and a second resistor; wherein the second resistor is coupled in series to the first resistor, and the first resistor is coupled in series to the transistor; The first resistor, the second resistor, and the transistor are vertically spaced apart from each other.

8. The memory device according to claim 7, wherein: The transistor is formed along a front side surface of the substrate, the first resistor comprises a plurality of first metal tracks formed in one of a plurality of front side metallization layers disposed above the front side surface, and the second resistor comprises a plurality of second metal tracks formed in one of a plurality of back side metallization layers disposed above the back side surface of the substrate.

9. The memory device according to claim 7, wherein: The transistor is formed along a front side surface of the substrate, the first resistor comprises a plurality of first metal tracks formed in a first front side metal layer among a plurality of front side metallization layers disposed above the front side surface, and the second resistor comprises a plurality of second metal tracks formed in a second front side metallization layer among the plurality of front side metallization layers.

10. A method for manufacturing a memory device, comprising: forming transistors along the front side surface of the substrate; forming a plurality of front side metal tracks disposed over the front side surface, wherein the plurality of front side metal tracks include word lines, bit lines, and a first fuse resistor; and forming a plurality of backside metal tracks disposed over a backside surface of the substrate, wherein the plurality of backside metal tracks include a second fuse resistor; wherein the word line is electrically connected to the gate terminal of the transistor, the bit line is electrically connected to the first end of the second fuse resistor, the second end of the second fuse resistor is electrically connected to the first end of the first fuse resistor, and the second end of the first fuse resistor is electrically connected to the source / drain terminal of the transistor.

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