Memory structure and its formation method

Abstract

A memory structure and a method for forming the same are disclosed. The method includes: providing a substrate; forming a floating gate precursor layer on the substrate, the floating gate precursor layer being made of MAX material; performing a phase transition treatment on the floating gate precursor layer to form an initial floating gate, the initial floating gate being made of MXene material; and performing an oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate. Multilayer MXene materials are less prone to oxidation and exhibit minimal lattice mismatch issues, resulting in high reliability. As a floating gate material, this improves the performance of the memory structure. Furthermore, during the oxidation treatment of the initial floating gate, the outer layer of the initial floating gate MXene material is oxidized to form a metal oxide. The metal oxide acts as a barrier layer to prevent the leakage of metal ions from the inner floating gate, further optimizing the performance of the memory structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a memory structure and a method for forming the same. Background Technology

[0002] Microcontrollers (MCUs), as chip-level computers, are widely used in new energy vehicles, communication modules, smart homes, and other fields. High-performance microcontrollers rely on high-performance embedded flash memory (eflash) cores. The floating-gate structure, as the mainstream structure of eflash memory, continues to shrink with the evolution of semiconductor manufacturing processes.

[0003] However, the current floating gate structure still has many problems. Summary of the Invention

[0004] The problem addressed by this invention is how to improve the reliability of floating gates in order to optimize the performance of memory structures.

[0005] To address the aforementioned problems, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate, wherein the floating gate precursor layer is made of MAX material; performing a phase transition treatment on the floating gate precursor layer to form an initial floating gate, wherein the initial floating gate is made of MXene material; and performing an oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate.

[0006] Optionally, the molecular formula of the MAX material is M n+1 AX n In this system, M represents a transition metal, A represents a main group element, and X represents carbon or nitrogen.

[0007] Optionally, the molecular formula of the MXene material is M n+1 X n T x Where M represents a transition metal, X represents carbon or nitrogen, and T represents a capping group; the capping groups include -F, -O, and -OH.

[0008] Optionally, the molecular formula of the material of the floating gate is M. n+1 X n , where M represents a transition metal and X represents carbon or nitrogen.

[0009] Optionally, the material of the barrier layer includes titanium oxide.

[0010] Optionally, the step of performing a phase transition treatment on the floating gate precursor layer to form the initial floating gate includes:

[0011] The floating gate precursor layer is etched to form the floating gate precursor body;

[0012] The floating gate precursor is subjected to phase change treatment to form the initial floating gate.

[0013] Optionally, the step of performing a phase transition treatment on the floating gate precursor layer to form the initial floating gate includes:

[0014] A floating gate precursor layer is formed on the substrate;

[0015] The floating gate precursor layer is subjected to phase change treatment to form a transition floating gate layer, wherein the transition floating gate layer is made of MXene material;

[0016] The transition floating gate layer is etched to form the initial floating gate.

[0017] Optionally, in the step of forming the floating gate precursor layer on the substrate, the floating gate precursor layer is formed by magnetron sputtering.

[0018] Optionally, in the step of oxidizing the initial floating gate to form the floating gate and the barrier layer surrounding the floating gate, the process gas for the oxidation process includes at least one of nitrogen and air.

[0019] Optionally, in the step of oxidizing the initial floating gate, the temperature range of the oxidation treatment is 50℃ to 200℃; and the time range of the oxidation treatment is 100min to 300min.

[0020] Optionally, in the step of oxidizing the initial floating gate, the thickness of the barrier layer is... Within the range.

[0021] Optionally, in the step of performing phase change treatment on the floating gate precursor layer, the phase change treatment method includes: wet etching.

[0022] Optionally, the etching solution for wet etching includes hydrogen chloride and lithium fluoride; the etching temperature for wet etching is 30°C to 50°C; and the etching time for wet etching is 100h to 150h.

[0023] Optionally, it may also include forming a tunneling layer on the surface of the barrier layer.

[0024] Optionally, in the step of forming a tunneling layer on the surface of the barrier layer, the material of the tunneling layer is silicon oxide.

[0025] Optionally, in the step of forming a tunneling layer on the surface of the barrier layer, the tunneling layer is formed by chemical vapor deposition.

[0026] Optionally, the thickness of the tunneling layer is... Within the range.

[0027] Optionally, a source / drain region is formed within the substrate; a select gate, an erase gate, and a control gate are formed on the substrate.

[0028] Accordingly, embodiments of the present invention also provide a memory structure, which is formed by the memory structure forming method described in any of the preceding claims.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the memory structure formation method of the present invention, an initial floating gate of MXene material is oxidized to form a floating gate and a barrier layer surrounding the floating gate. The multilayer MXene materials are less prone to oxidation and have minimal lattice mismatch issues, resulting in high reliability. As a floating gate material, this improves the performance of the memory structure. Furthermore, during the oxidation process of the initial floating gate, the outer layer of the initial floating gate MXene material is oxidized to form a metal oxide. This metal oxide acts as a barrier layer to prevent the leakage of metal ions from the inner floating gate, further optimizing the performance of the memory structure. Attached Figure Description

[0031] Figure 1 This is a process flow diagram of the formation process of the memory structure according to an embodiment of the present invention;

[0032] Figures 2 to 7 This is a cross-sectional structural schematic diagram of each step in the formation process of a memory structure according to an embodiment of the present invention. Detailed Implementation

[0033] As the background technology shows, with the evolution of semiconductor manufacturing processes, floating gate structures are continuously miniaturized, leading to a decrease in the reliability of floating gates. The reasons for this problem are analyzed below:

[0034] As the mainstream structure for EF-ASH memory, the floating gate structure continues to shrink with the evolution of semiconductor manufacturing processes. At nodes below 32nm, the traditional dielectric layer materials for charge storage lead to decreased reliability and severe leakage current in the floating gate structure.

[0035] To address the aforementioned technical problem, the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a floating gate precursor layer on the substrate, wherein the material of the floating gate precursor layer is MAX material; performing a phase transition treatment on the floating gate precursor layer to form an initial floating gate, wherein the initial floating gate is MXene material; and performing an oxidation treatment on the initial floating gate to form a floating gate and a barrier layer surrounding the floating gate.

[0036] In the memory structure formation method of the present invention, an initial floating gate of MXene material is oxidized to form a floating gate and a barrier layer surrounding the floating gate. The multilayer MXene materials are less prone to oxidation and have minimal lattice mismatch issues, resulting in high reliability. As a floating gate material, this improves the performance of the memory structure. Furthermore, during the oxidation process of the initial floating gate, the outer layer of the initial floating gate MXene material is oxidized to form a metal oxide. This metal oxide acts as a barrier layer to prevent the leakage of metal ions from the inner floating gate, further optimizing the performance of the memory structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figure 1 This is a process flow diagram illustrating the formation process of the memory structure according to an embodiment of the present invention, in conjunction with reference to [reference needed]. Figures 2 to 7 , Figures 2 to 7 This is a cross-sectional structural schematic diagram of each step in the formation process of a memory structure according to an embodiment of the present invention.

[0039] The process of forming the memory structure includes:

[0040] Step S10: Provide substrate 100;

[0041] Step S11: A dielectric layer 101 is formed on the substrate 100;

[0042] Step S12: A floating gate precursor layer 102 is formed on the substrate 100, wherein the material of the floating gate precursor layer 102 is MAX material;

[0043] Step S13: Perform phase change treatment on the floating gate precursor layer 102 to form an initial floating gate 104, wherein the initial floating gate 104 is made of MXene material;

[0044] Step S14: The initial floating gate 104 is oxidized to form a floating gate 105 and a barrier layer 106 surrounding the floating gate 105.

[0045] Step S15: A tunneling layer 107 is formed on the surface of the barrier layer 106;

[0046] Step S16: Form source / drain regions within the substrate 100;

[0047] Step S17: A selection gate 110, an erase gate 111, and a control gate 112 are formed on the substrate 100.

[0048] The following will provide a detailed explanation of each step in the formation process of the memory structure.

[0049] Please refer to Figure 2 In step S10, a substrate 100 is provided.

[0050] The substrate 100 is made of materials including silicon, silicon carbide, silicon germanium, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).

[0051] The substrate 100 provides a structural basis for forming the floating gate precursor layer 102.

[0052] Please continue to refer to this. Figure 2 In step S11, a dielectric layer 101 is formed on the substrate 100.

[0053] The dielectric layer 101 is made of silicon oxide. Specifically, in some embodiments of the present invention, the dielectric layer 101 is formed on the substrate 100 by thermal oxidation.

[0054] Please continue to refer to this. Figure 2 In step S12, a floating gate precursor layer 102 is formed on the substrate 100, and the material of the floating gate precursor layer 102 is MAX material.

[0055] The molecular formula of the MAX material is M n+1 AX n Where M represents a transition metal, A represents a main group element, and X represents carbon or nitrogen. Specifically, in some embodiments of the present invention, the material of the floating gate precursor layer 102 is titanium aluminum carbide (Ti3AlC2). The floating gate precursor layer 102 of MAX material provides the structural basis for forming the initial floating gate 104 of MXene material. Specifically, in some embodiments of the present invention, in the step of forming the floating gate precursor layer 102 on the substrate 100, the floating gate precursor layer 102 is formed by magnetron sputtering.

[0056] Please refer to Figures 3 to 4 In step S13, the floating gate precursor layer 102 is subjected to phase change treatment to form an initial floating gate 104, wherein the initial floating gate 104 is made of MXene material.

[0057] In some embodiments of the present invention, the step of performing a phase transition treatment on the floating gate precursor layer 102 to form the initial floating gate 104 includes: as follows Figure 3 As shown, the floating gate precursor layer 102 is etched to form the floating gate precursor body 103; as Figure 4 As shown, the floating gate precursor 103 is subjected to phase change treatment to form the initial floating gate 104.

[0058] In the step of etching the floating gate precursor layer 102 to form the floating gate precursor 103, the floating gate precursor layer 102 is patterned to form the floating gate precursor 103. The floating gate precursors 103 are separate from each other, providing a structural basis for the subsequent formation of the floating gate 105.

[0059] The phase change treatment transforms the MAX material into the MXene material. In the step of performing the phase change treatment on the floating gate precursor 103, the method includes wet etching. The etching solution for the wet etching includes hydrogen chloride and lithium fluoride; the etching temperature for the wet etching is 30°C to 50°C; and the etching time for the wet etching is 100h to 150h.

[0060] The molecular formula of the MXene material is M n+1 X n T x Where M represents a transition metal, X represents carbon or nitrogen, and T represents a capping group; the capping groups include -F, -O, and -OH.

[0061] In MAX materials, MX bonds have higher bond energies than MA bonds. Taking titanium aluminum carbide (Ti3AlC2) as an example, the titanium-carbon (Ti-C) bond has a higher bond energy than the titanium-aluminum (Ti-Al) bond. MXene is synthesized by selectively removing aluminum (Al) from titanium aluminum carbide (Ti3AlC2) through phase transition treatment. The resulting MXene is a two-dimensional material with a graphene-like structure. MXene materials have a large specific surface area, excellent conductivity, good self-lubricating properties, and abundant surface groups. MXene materials are composed of alternating carbon layers and transition metal layers, which endows them with good conductivity and pseudocapacitive properties, overcoming the problems of decreased floating gate reliability and severe leakage current in memory during the miniaturization process.

[0062] It should be noted that in some embodiments, during the phase transition treatment of the floating gate precursor layer to form the initial floating gate, the floating gate precursor layer is first etched, and then the etched floating gate precursor layer is subjected to phase transition treatment to form the initial floating gate of MXene material. However, this approach is only an example. In other embodiments, the floating gate precursor layer of MAX material can be subjected to phase transition treatment first to transform the MAX material into MXene material, and then the phase-transformed floating gate precursor layer can be etched to form the initial floating gate layer. For example, in other embodiments of the present invention, the step of performing phase transition treatment on the floating gate precursor layer to form the initial floating gate includes: forming a floating gate precursor layer on the substrate; performing phase transition treatment on the floating gate precursor layer to form a transition floating gate layer, wherein the transition floating gate layer is of MXene material; and performing etching treatment on the transition floating gate layer to form the initial floating gate.

[0063] The transition floating gate layer after phase transition processing is patterned to form initial floating gates. The initial floating gates are independent of each other, providing a structural basis for the subsequent formation of floating gates.

[0064] Please refer to Figure 5 In step S14, the initial floating gate 104 is oxidized to form a floating gate 105 and a barrier layer 106 surrounding the floating gate 105.

[0065] The molecular formula of the material of the floating gate 105 is M. n+1 X n In this context, M represents a transition metal and X represents carbon or nitrogen. Specifically, if titanium aluminum carbide (Ti3AlC2) is used as the material for the floating gate precursor layer 102, the floating gate 105 is a two-dimensional material composed of titanium and [other materials]. Introducing two-dimensional materials as the floating gate material overcomes problems such as decreased reliability and severe leakage current during memory structure miniaturization, thus promoting the miniaturization of memory structures.

[0066] In the step of oxidizing the initial floating gate 104 to form the floating gate 105 and the barrier layer 106 surrounding the floating gate 105, the process gas for the oxidation process includes at least one of nitrogen and air.

[0067] Specifically, in some embodiments of the present invention, in the step of oxidizing the initial floating gate 104, the temperature range of the oxidation treatment is 50°C to 200°C; and the time range of the oxidation treatment is 100 min to 300 min.

[0068] In the step of oxidizing the initial floating gate 104, the thickness of the barrier layer 106 is... Within the specified range. The thickness of the barrier layer 106 is positively correlated with the duration of the oxidation treatment, and the thickness of the barrier layer 106 can be adjusted according to actual production needs. The material of the barrier layer 106 includes titanium oxide. The function of the barrier layer 106 is to prevent the leakage of metal ions from the floating gate 105.

[0069] Please refer to Figure 6 In step S15, a tunneling layer 107 is formed on the surface of the barrier layer 106.

[0070] In the step of forming the tunneling layer 107 on the surface of the barrier layer 106, the material of the tunneling layer 107 is silicon oxide. The material of the tunneling layer 107 is different from the material of the barrier layer 106.

[0071] In the step of forming the tunneling layer 107 on the surface of the barrier layer 106, the tunneling layer 107 is formed by chemical vapor deposition. The thickness of the tunneling layer 107 is... Within the range.

[0072] Please refer to Figure 7 In step S16, a source / drain region is formed within the substrate 100. The source / drain region includes a source 108 and a drain 109.

[0073] Please continue to refer to this. Figure 7 In step S17, a selection gate 110, an erase gate 111, and a control gate 112 are formed on the substrate 100.

[0074] Accordingly, this embodiment of the invention also provides a memory structure, which is formed by the above-described method for forming a memory structure, and will not be described in detail here.

[0075] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a memory structure, characterized in that, include: Provide substrate; A floating gate precursor layer is formed on the substrate. The material of the floating gate precursor layer is a MAX material, and the molecular formula of the MAX material is M. n+1 AX n In this system, M represents a transition metal, A represents a main group element, and X represents carbon or nitrogen. The floating gate precursor layer undergoes a phase transition treatment to form an initial floating gate, wherein the initial floating gate is an MXene material with the molecular formula M. n+1 X n T x Where M represents a transition metal, X represents carbon or nitrogen, and T represents a capping group; the capping group includes -F, -O, and -OH. The initial floating gate is oxidized to form the floating gate and a barrier layer surrounding the floating gate.

2. The method for forming a memory structure as described in claim 1, characterized in that, The molecular formula of the material of the floating gate is M. n+1 X n , where M represents a transition metal and X represents carbon or nitrogen.

3. The method for forming a memory structure as described in claim 1, characterized in that, The barrier layer is made of titanium oxide.

4. The method for forming a memory structure as described in claim 1, characterized in that, The step of performing a phase transition treatment on the floating gate precursor layer to form the initial floating gate includes: The floating gate precursor layer is etched to form the floating gate precursor body; The floating gate precursor is subjected to phase change treatment to form the initial floating gate.

5. The method for forming a memory structure as described in claim 1, characterized in that, The step of performing a phase transition treatment on the floating gate precursor layer to form the initial floating gate includes: A floating gate precursor layer is formed on the substrate; The floating gate precursor layer is subjected to phase change treatment to form a transition floating gate layer, wherein the transition floating gate layer is made of MXene material; The transition floating gate layer is etched to form the initial floating gate.

6. The method for forming a memory structure as described in claim 1, 4, or 5, characterized in that, In the step of forming a floating gate precursor layer on the substrate, the floating gate precursor layer is formed by magnetron sputtering.

7. The method for forming a memory structure as described in claim 1, characterized in that, In the step of oxidizing the initial floating gate to form the floating gate and the barrier layer surrounding the floating gate, the process gas for the oxidation process includes at least one of nitrogen and air.

8. The method for forming a memory structure as described in claim 1, characterized in that, In the step of oxidizing the initial floating gate, the temperature range of the oxidation treatment is 50℃~200℃; and the time range of the oxidation treatment is 100min~300min.

9. The method for forming a memory structure as described in claim 1, characterized in that, In the step of oxidizing the initial floating gate, the thickness of the barrier layer is in the range of 100 Å to 200 Å.

10. The method for forming a memory structure as described in claim 1, characterized in that, In the step of performing phase change processing on the floating gate precursor layer, the phase change processing method includes: wet etching.

11. The method for forming a memory structure as described in claim 10, characterized in that, The etching solution for the wet etching process includes hydrogen chloride and lithium fluoride; the etching temperature for the wet etching process is 30℃~50℃; and the etching time for the wet etching process is 100h~150h.

12. The method for forming a memory structure as described in claim 1, characterized in that, Also includes: A tunneling layer is formed on the surface of the barrier layer.

13. The method for forming a memory structure as described in claim 12, characterized in that, In the step of forming a tunneling layer on the surface of the barrier layer, the material of the tunneling layer is silicon oxide.

14. The method for forming a memory structure as described in claim 12 or 13, characterized in that, In the step of forming a tunneling layer on the surface of the barrier layer, the tunneling layer is formed by chemical vapor deposition.

15. The method for forming a memory structure as described in claim 12, characterized in that, The thickness of the tunneling layer is in the range of 20 Å to 50 Å.

16. The method for forming a memory structure as described in claim 12, characterized in that, Also includes: Source / drain regions are formed within the substrate; A selection gate, an erase gate, and a control gate are formed on the substrate.

17. A memory structure, characterized in that, The memory structure is formed by the method for forming a memory structure as described in any one of claims 1 to 16.

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