Method for preparing strain channel finfet

Abstract

A method for preparing a strain channel FinFET, which method belongs to the technical field of integrated circuit manufacturing. After the manufacturing of a fin line is completed, amorphous silicon is generated by means of an amorphization implantation method; after being covered by a strain dielectric layer and annealed at a high temperature, the amorphous silicon is recrystallized, and in this case, tensile stress / compressive stress required by an N / PMOS can be formed between the crystalline silicon and a strain dielectric; and a strain dielectric material is then selectively removed to implement the preparation of a strain channel FinFET. In the method, the lattice mismatch between the strain dielectric material and the crystalline silicon is used to generate tensile stress or compressive stress required by a FinFET device. A single strain material is used to realize N / PMOS channel strain, so that the flow of channel stress engineering is simplified, the process complexity is reduced, and the method has the potential to be applied to technology nodes of 14 nm and above.

Description

Method for manufacturing strained channel finfet TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit manufacturing, especially for 14nm and above advanced technology nodes, and particularly relates to a preparation process of a strained channel FinFET. BACKGROUND

[0002] Traditional MOSFET devices mainly improve device performance and transistor density per unit area through equal proportion reduction, and improve channel mobility, device driving performance and circuit switching speed through reducing gate length and applying stress. However, as the process node continues to shrink, the short channel effect continues to strengthen, and the traditional method for improving the short channel effect will reduce the carrier mobility, resulting in reduced device speed. Therefore, new technologies need to be introduced to improve carrier mobility, and thus improve device performance and circuit switching speed.

[0003] In recent years, in view of the problem of reducing the carrier, the current mainstream FinFET structure mainly introduces stress through source / drain epitaxy to improve the carrier mobility. Specifically, silicon carbide (SiC) or doped silicon (SiGe) is formed in the source / drain of NMOS to form tensile stress to improve electron mobility. Silicon germanium (Si1-xGex) is formed in the source / drain of PMOS to form compressive stress to improve hole mobility. However, N / PMOS source / drain epitaxy includes two etchings, two processes, and two lithographies, which increases the complexity and cost of the process flow, and may cause process fluctuation problems. Therefore, it is urgent to develop a FinFET channel stress introduction method with low cost, simple process and reliability. SUMMARY

[0004] In view of the above problems, the present application provides a preparation method of a strained channel FinFET, comprising the following steps:

[0005] 1) Forming a Fin line on a semiconductor substrate;

[0006] 2) Using a standard CMOS process to form a shallow trench isolation between Fins;

[0007] 3) Amorphous implantation is performed on the Fin line to form an amorphous Fin line;

[0008] 4) Depositing a strain medium layer to completely cover the amorphous Fin line;

[0009] 5) High-temperature annealing to crystallize the amorphous Fin line to form stress silicon;

[0010] 6) Photoetching to form an etching area and selectively etching to remove the strain medium layer;

[0011] 7) Subsequently, a FinFET transistor is formed by using a standard FinFET process.

[0012] Further, the amorphous implantation device in step 3) is an ion implanter, and the implantation ions can be one of Ge, Si, Ar, H, etc., and the implantation energy ranges between 1-30 KeV.

[0013] Further, in step 4), the strain medium layer material can be silicon nitride (SiN x , x =1~1.5), silicon carbon nitride (Si y C z N4, y+z=3~4), silicon oxynitride (SiO a N b , a=0~2, b=0~4 ), silicon dioxide (SiO2), etc., and the deposition thickness of the strain medium layer ranges between 10-500 nm.

[0014] Further, in step 4), the deposition of the strain medium layer material can be one of chemical vapor deposition (Chemical Vapor Deposition), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), atomic layer deposition (Atom Layer Deposition, ALD), and plasma enhanced atomic layer deposition (Plasma Enhanced Atom Layer Deposition, PEALD).

[0015] Further, in step 4), after the strain medium layer completely covers the amorphous Fin lines, a part of the strain medium material is selectively etched to achieve the control of the size of the FinFET channel stress.

[0016] Further, in step 5), the high-temperature annealing method can be one of rapid thermal annealing (Rapid Thermal Annealing, RTA), laser annealing (Laser Annealing), flash annealing (Flash Annealing), and spike annealing (Spike Annealing), and the temperature range of the high-temperature annealing is 700℃-1800℃.

[0017] Further, the etching method in step 6) can be one of plasma etching, ion beam sputtering etching, reactive ion etching (RIE), inductively coupled plasma (ICP), wet etching, etc.

[0018] Advantages and positive effects of the present application are as follows:

[0019] 1) After the Fin line is made, amorphous silicon is generated by injection of amorphization method, and after the strain dielectric layer is covered and high temperature annealing, the amorphous silicon is recrystallized, at which time the tensile stress / compressive stress required by N / PMOS can be formed between the crystalline silicon and the strain dielectric layer, and then the strain channel FinFET is prepared by selectively removing the strain dielectric material. The present application utilizes the lattice mismatch between the strain dielectric material and the crystalline silicon to generate the tensile stress or compressive stress required by the FinFET device, and the N / PMOS channel strain is realized by using a single strain material, which reduces the process complexity.

[0020] 2) The process flow of the channel stress engineering is simplified. Specifically, the traditional stress introduction process is twice photolithography, twice etching, and twice epitaxy, while the process adopted by the present application is once photolithography, once etching, and once epitaxy.

[0021] 3) On the premise of reducing the process steps, the process fluctuation caused by more complex processes is avoided.

[0022] 4) The existing FinFET process will not be changed too much, and the traditional FinFET process flow can still be used after the stress engineering.

[0023] 5) In the case of small contact gate pitch (CPP), even the source / drain epitaxy method can not be used.

[0024] Based on the above characteristics, the preparation process of the strain channel FinFET of the present application has the potential to be applied to technology nodes of 14 nm and above. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIGS. 1-7 are schematic diagrams of each key process step of the strain channel FinFET of the present application. In each figure, (a) is a top view, (b) is a device cross-sectional view along the A-A' direction (channel cross section) of (a), and (c) is a device cross-sectional view along the B-B' direction (Fin arrangement) of (a). Among them:

[0026] FIG. 1 is a schematic diagram of the Fin etching step;

[0027] Figure 2 is a schematic diagram of the step of forming shallow trench isolation between Fins using standard process;

[0028] Figure 3 is a schematic diagram of the step of amorphization implantation of Fin lines to form amorphous Fin lines;

[0029] Figure 4 is a schematic diagram of the step of depositing a strain material layer to completely cover the amorphous Fin lines;

[0030] Figure 5 is a schematic diagram of the step of photoetching to form etching area and selectively etching to remove part of the strain medium layer;

[0031] Figure 6 is a schematic diagram of the step of high-temperature annealing to crystallize the amorphous Fin lines;

[0032] Figure 7 is a schematic diagram of selectively etching to remove the strain medium layer;

[0033] Figure 8 is a legend of the materials used in Figures 1-7. DETAILED DESCRIPTION

[0034] The present application provides a preparation process of a strain channel FinFET, which comprises the following steps:

[0035] 1) etching to form Fin lines on a semiconductor substrate, as shown in Figure 1;

[0036] 2) using standard CMOS process to form shallow trench isolation between Fins, as shown in Figure 2;

[0037] 3) amorphization implantation of Fin lines to form amorphous Fin lines, the amorphization implantation equipment is an ion implanter, and the implantation ions can be one of Ge, Si, Ar, H and other ions, and the implantation energy ranges between 1-30 KeV, as shown in Figure 3;

[0038] 4) depositing a strain material layer to completely cover the amorphous Fin lines, the strain medium layer material can be SiN x (x = 1-1.5), Si y C z N4(y+z = 3-4), SiO a N b (a = 0-2, b = 0-4), SiO2, etc., the strain medium layer deposition thickness is between 10-500 nm, and the strain layer material deposition can use chemical vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, as shown in Figure 4;

[0039] In order to adjust the size of the FinFET channel stress, the present application can selectively etch to remove part of the strain material layer after depositing a strain material layer to completely cover the amorphous Fin lines, as shown in Figure 5;

[0040] 5) high temperature annealing to crystallize the amorphous Fin lines to form stressed silicon, wherein the high temperature annealing is performed at a temperature ranging from 700°C to 1800°C, and the high temperature annealing can be performed by rapid thermal annealing, laser annealing, flash annealing or spike annealing, as shown in FIG. 6;

[0041] 6) photolithography to form etching regions, and selective etching to remove the strained dielectric layer, wherein the etching can be performed by plasma etching, ion beam sputtering etching, reactive ion etching, inductively coupled plasma etching, wet etching or other etching methods, as shown in FIG. 7;

[0042] 7) subsequent formation of a FinFET transistor by using standard FinFET process.

[0043] Finally, it should be noted that the purpose of the disclosed embodiments is to help further understand the present application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed embodiments, and the scope of the present application is defined by the scope of the claims.

Claims

1. A method for preparing a strain channel FinFET, comprising the following steps: 1) forming a Fin line on a semiconductor substrate; 2) forming a shallow trench isolation between Fins by using a standard CMOS process; 3) performing an amorphization implantation on the Fin line to form an amorphous Fin line; 4) depositing a strain dielectric layer to completely cover the amorphous Fin line; 5) performing a high-temperature annealing to crystallize the amorphous Fin line to form a stress silicon; 6) performing a photolithography to form an etching area and selectively etching to remove the strain dielectric layer; 7) subsequently forming a FinFET transistor by using a standard FinFET process.

2. The production method according to claim 1, wherein The amorphization implantation in step 3) is performed by an ion implanter, and the implanting ions are Ge, Si, Ar or H, and the implanting energy ranges from 1 to 30 KeV.

3. The production method according to claim 1, wherein The strain dielectric layer material in step 4) is silicon nitride, silicon carbon nitride, silicon oxynitride or silicon dioxide, and the deposition thickness of the strain dielectric layer ranges from 10 to 500 nm.

4. The production method according to claim 1, wherein In step 4), the deposition of the strain dielectric layer material is performed by chemical vapor deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition or plasma-enhanced atomic layer deposition.

5. The production method according to claim 1, wherein After the strain dielectric layer completely covers the amorphous Fin line in step 4), a part of the strain dielectric material is selectively etched and removed.

6. The production method according to claim 1, wherein In step 5), the high-temperature annealing is performed by one of rapid thermal annealing, laser annealing, flash annealing and spike annealing, and the temperature ranges from 700 to 1800 °C.

7. The production method according to claim 1, wherein In step 6), the etching is performed by plasma etching, ion beam sputtering etching, reactive ion etching, inductively coupled plasma etching or wet etching.

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