Memory device with support structure

Abstract

The invention relates to a memory device with a support structure. A memory device includes: a stack structure; the first supporting structures penetrate through the stacking structure, and the first supporting structures are separated from each other in a first direction; a first protruding pattern penetrating through the stack structure, the first protruding pattern being spaced apart from one of the first support structures in a second direction; a first outer support structure penetrating through the stacked structure, the first outer support structure extending from the first protruding pattern in the first direction; and an intermediate support structure penetrating the stack structure, the intermediate support structure extending in the second direction in a region between the first support structures, the intermediate support structure being in contact with the first external support structure.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices having support structures, and more particularly to memory devices having support structures located in a connection area. Background Art

[0002] The memory device may include a memory cell array in which data is stored, a peripheral circuit configured to perform a program operation, a read operation, or an erase operation on the memory cell array, and a control circuit configured to control the peripheral circuit.

[0003] The memory cell array may include a plurality of memory blocks. When the memory blocks are formed in a three-dimensional structure, the memory blocks may be separated from each other by slit regions.

[0004] A memory block formed in a three-dimensional structure may include a stacked structure in which memory cells are stacked on a substrate in a vertical direction. The stacked structure may include a plurality of gate lines and a plurality of insulating layers that are alternately stacked. When the memory block is configured by a stacked structure, a support structure may be used to prevent the stacked structure from bending or being damaged during the manufacturing process of the memory device. For example, the support structure may be located in a cell region or in a connection region defined at both ends of the cell region.

[0005] As the integration of memory devices increases, the size of support structures included in the cell region and the connection region decreases. Therefore, a bridge may occur in which some support structures contact each other. The bridge that occurs between support structures that should be electrically isolated from each other becomes a defect in the memory device, and thus the yield of the manufacturing process of the memory device may deteriorate. Summary of the invention

[0006] According to one aspect of the present disclosure, a memory device is provided, which includes: a stacked structure; a first support structure, which penetrates the stacked structure and is spaced apart from each other in a first direction; a first protruding pattern, which penetrates the stacked structure and is spaced apart from one of the first support structures in a second direction; a first external support structure, which penetrates the stacked structure and extends from the first protruding pattern along the first direction; and an intermediate support structure, which penetrates the stacked structure and extends in the second direction in a region between the first support structures and is in contact with the first external support structure.

[0007] According to another aspect of the present disclosure, a memory device is provided, comprising: a stacked structure; a first external support structure and a second external support structure, wherein the first external support structure and the second external support structure penetrate the stacked structure, and the first external support structure and the second external support structure extend parallel to each other in a first direction; an intermediate support structure, wherein the intermediate support structure extends in a second direction perpendicular to the first direction between the first external support structure and the second external support structure; and a protrusion pattern, wherein the protrusion pattern penetrates the stacked structure, and the protrusion pattern extends from the intermediate support structure along the first direction, wherein the protrusion pattern extends in a direction opposite to the direction in which the first external support structure and the second external support structure extend from the intermediate support structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Now, hereinafter, example embodiments will be described more fully with reference to the accompanying drawings; however, these embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the example embodiments to those skilled in the art.

[0009] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. Like reference numerals refer to like elements throughout.

[0010] Figure 1 is a diagram illustrating a memory device.

[0011] Figure 2 is a diagram illustrating a memory cell array.

[0012] Figure 3A is a view illustrating the structure of a memory device.

[0013] Figure 3B is a view illustrating a phenomenon in which bending occurs in a supporting structure.

[0014] Figure 3C is a view illustrating a defect caused by bending occurring in a supporting structure.

[0015] Figure 4A is a layout of a supporting structure according to a first embodiment of the present disclosure.

[0016] Figure 4B 2 is a view illustrating a layout of a second supporting structure and a first supporting structure adjacent to the second supporting structure according to a first embodiment of the present disclosure.

[0017] Figure 4C is a perspective view illustrating a supporting structure according to a first embodiment of the present disclosure.

[0018] Figure 5 2 is a view illustrating a supporting structure according to a second embodiment of the present disclosure.

[0019] Figure 6 is a view illustrating a supporting structure according to a third embodiment of the present disclosure.

[0020] Figure 7 2 is a view illustrating a supporting structure according to a fourth embodiment of the present disclosure.

[0021] Figure 8 is a view illustrating a supporting structure according to a fifth embodiment of the present disclosure.

[0022] Fig. 9 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0023] Fig.10 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0024] The specific structural and functional descriptions disclosed herein are merely exemplified for the purpose of describing the embodiments according to the conception of the present disclosure. Other embodiments according to the conception of the present disclosure can be implemented in various forms. Therefore, the present disclosure should not be interpreted as being limited to the embodiments set forth herein.

[0025] Hereinafter, it will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0026] Embodiments provide a memory device capable of reducing defects of the memory device.

[0027] Figure 1 is a diagram illustrating a memory device.

[0028] Reference Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0029] The memory cell array 110 may include first to j-th memory blocks BLK1 to BLKj. Each of the first to j-th memory blocks BLK1 to BLKj may include a memory cell capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line may be connected to each of the first to j-th memory blocks BLK1 to BLKj, and a bit line BL may be commonly connected to the first to j-th memory blocks BLK1 to BLKj.

[0030] The first to j-th memory blocks BLK1 to BLKj may be formed in a two-dimensional structure or a three-dimensional structure. A memory block having a two-dimensional structure may include memory cells arranged parallel to a substrate. A memory block having a three-dimensional structure may include memory cells stacked on a substrate in a vertical direction. In this embodiment, a memory block formed in a three-dimensional structure is disclosed.

[0031] The memory cell can store one bit or two bits or more of data according to the programming method. For example, the method of storing one bit of data in one memory cell is called a single-level cell (SLC) method, and the method of storing two bits of data in one memory cell is called a multi-level cell (MLC) method. The method of storing three bits of data in one memory cell is called a three-level cell (TLC) method, and the method of storing four bits of data in one memory cell is called a quad-level cell (QLC) method. In addition, five or more bits of data can be stored in one memory cell.

[0032] The peripheral circuit 170 may be configured to perform a program operation for storing data, a read operation for outputting data stored in the memory cell array 110, and an erase operation for erasing data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0033] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, and an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0034] The programming voltage may be a voltage applied to a selected word line among word lines WL in a programming operation, and may be used to increase the threshold voltage of a memory cell connected to the selected word line. The on-voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. The cut-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the cut-off voltage may be set to 0V. The precharge voltage may be a voltage higher than 0V, and may be applied to a bit line in a read operation. The verification voltage may be used to determine whether the threshold voltage of a selected memory cell has been increased to a target level in a verification operation. The verification voltage may be set to various levels according to the target level, and may be applied to a selected word line.

[0035] In a read operation of a selected memory cell, a read voltage may be applied to a selected word line. For example, the read voltage may be set to various levels according to the programming mode of the selected memory cell. A pass voltage may be a voltage applied to an unselected word line among word lines WL in a programming or read operation, and may be used to turn on a memory cell connected to the unselected word line.

[0036] The erase voltage may be used in an erase operation for erasing memory cells included in a selected memory block, and may be applied to the source line SL.

[0037] The row decoder 130 may be configured to send the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 through the global line, and may be connected to the first memory block BLK1 to the j-th memory block BLKj through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0038] The page buffer group 140 may include a page buffer (not shown) connected to each of the first to j-th memory blocks BLK1 to BLKj. The page buffer (not shown) may be connected to the first to j-th memory blocks BLK1 to BLKj through the bit lines BL, respectively. In a read operation, in response to a page buffer control signal PBSIG, the page buffer (not shown) may sense a current or voltage of the bit line BL that varies according to a threshold voltage of a selected memory cell, and may temporarily store the sensed data.

[0039] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 through the column line CL, and may send an enable signal through the column line. The page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0040] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may send a command CMD and an address ADD received from an external controller to the control circuit 180 through the input / output line I / O, and send data received from the external controller to the page buffer group 140 through the input / output line I / O. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller through the input / output line I / O.

[0041] The control circuit 180 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation on a storage block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation on a selected storage block and output the read data. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation on a selected storage block.

[0042] Figure 2 is a diagram illustrating a memory cell array.

[0043] Reference Figure 2 , the memory cell array 110 may be located on the peripheral circuit 170, but the locations of the memory cell array 110 and the peripheral circuit 170 are not limited to Figure 2 For example, the memory cell array 110 may be located on the same plane as the peripheral circuit 170, and the memory cell array 110 and the peripheral circuit 170 may be brought into contact with each other after the memory cell array 110 and the peripheral circuit 170 are formed on different substrates.

[0044] The memory cell array 110 may include a first storage block BLK1 to a j-th storage block BLKj. The first storage block BLK1 to the j-th storage block BLKj may be arranged to be spaced apart from each other along the Y direction. The first storage block BLK1 to the j-th storage block BLKj may be configured identically to each other and may be separated from each other by slit regions 1SR, 2SR, 3SR, ... Each of the slit regions 1SR, 2SR, 3SR, ... may extend along the X direction. For example, the first storage block BLK1 may be located between the first slit region 1SR and the second slit region 2SR, and the second storage block BLK2 may be located between the second slit region 2SR and the third slit region 3SR. The first storage block BLK1 and the second storage block BLK2 may be separated from each other by the second slit region 2SR.

[0045] The first storage block BLK1 to the j-th storage block BLKj may include a cell region CE and a first connection region 1CN and a second connection region 2CN. The cell region CE may be located between the first connection region 1CN and the second connection region 2CN. The memory cell may be included in the cell region CE, and the contact and the support structure may be included in the first connection region 1CN and the second connection region 2CN. The memory cell may be configured to store data, the contact may be configured to contact a gate line extending from the cell region CE, or may contact a peripheral circuit 170 located below the storage block, and the support structure may be configured to support a stacked structure located in the first connection region 1CN and the second connection region 2CN.

[0046] Figure 3A is a diagram illustrating the structure of a memory device.

[0047] Reference Figure 3A , exemplifies Figure 2 Layout of the first memory block BLK1 and the second memory block BLK2 among the first to j-th memory blocks BLK1 to BLKj is shown in FIG.

[0048] The first memory block BLK1 and the second memory block BLK2 may be located between the first to third slits 1SLT to 3SLT. The first to third slits 1SLT to 3SLT may be structures formed in the first to third slit regions 1SR to 3SR, and the first to third slits 1SLT to 3SLT may be formed of an insulating material or a conductive material, or may be formed of an insulating material and a conductive material.

[0049] Each of the first memory block BLK1 and the second memory block BLK2 may be divided into a cell region CE and a first connection region 1CN. A cell plug CP including a memory cell may be included in the cell region CE, and a first support structure 1SP and a second support structure 2SP for supporting the memory block and a contact electrically contacting a gate line extending from the cell region CE or electrically contacting a peripheral circuit located below the memory block may be included in the first connection region 1CN.

[0050] The memory cell and the selection transistor may be included in each of the cell plugs CP. For example, the cell plug CP corresponding to the memory cell and the selection transistor may include a core column CR, a channel layer CH, and a memory layer ML. The memory layer ML may include a tunnel insulating layer TX, a charge capture layer CG, and a blocking layer BX. The core column CR may have a circular column shape and may be formed of an insulating material or a conductive material. The channel layer CH may have a cylindrical shape surrounding the side surface of the core column CR and may be formed of polysilicon. The tunnel insulating layer TX may have a cylindrical shape surrounding the side surface of the channel layer CH and may be formed of an oxide layer. The charge capture layer CG may have a cylindrical shape surrounding the side surface of the tunnel insulating layer TX and may be formed of a nitride layer. The blocking layer BX may have a cylindrical shape surrounding the side surface of the charge capture layer CG and may be formed of an oxide layer.

[0051] The first support structures 1SP located in the first connection region 1CN may be spaced apart from each other along the X direction in the region adjacent to the first to third slits 1SLT to 3SLT. The first support structures may be adjacent to the first to third slits 1SLT to 3SLT, but may not be in contact with the first to third slits 1SLT to 3SLT. The first support structures 1SP may penetrate the stacked structure forming the memory block and may be formed of an insulating material. For example, the first support structures 1SP included in the first memory block BLK1 may include a support structure adjacent to the first slit 1SLT and a support structure adjacent to the second slit 2SLT.

[0052] The contact CT may be located between the first support structures 1SP and may be formed of a conductive material. The major axis length of each of the contacts CT may be shorter than the major axis length of each of the first support structures 1SP, and the minor axis length of each of the contacts CT may be shorter than the minor axis length of each of the first support structures 1SP.

[0053] The second support structure 2SP may be located between the first support structures 1SP spaced apart from each other in the Y direction and between the contacts CT spaced apart from each other in the Y direction. Since the second support structure 2SP performs the function of separating the stacked structure, the second support structure 2SP may include a first external support structure 1E_SP and a second external support structure 2E_SP extending in the X direction and parallel to each other, and an intermediate support structure C_SP extending in the Y direction. The second support structure 2SP included in the first memory block BLK1 will be described as an example. The second support structure 2SP may include a first external support structure 1E_SP and a second external support structure 2E_SP arranged parallel to each other in the X direction, and an intermediate support structure C_SP extending in the Y direction to connect the end of the first external support structure 1E_SP to the end of the second external support structure 2E_SP. The first external support structure 1E_SP, the second external support structure 2E_SP, and the intermediate support structure C_SP may be formed of an insulating material that penetrates the stacked structure. An insulating layer and a sacrificial layer may be stacked in a stacked structure surrounded by the second support structure 2SP, and an insulating layer and a gate line may be stacked in a stacked structure located outside the second support structure 2SP.

[0054] A third supporting structure 3SP for supporting the stack structure may be further included in a region surrounded by the first supporting structure 1SP, the second supporting structure 2SP, and the cell region CE. The third supporting structure 3SP may have a linear shape extending along the X direction and may be formed of an insulating material.

[0055] like Figure 3A As shown in , the portions of the first outer support structure 1E_SP and the second outer support structure 2E_SP that contact the intermediate support structure C_SP may form a right angle. In addition, since the area of ​​the intermediate support structure C_SP is larger than the area of ​​each of the first support structures 1SP adjacent to the intermediate support structure C_SP, during the etching process of forming a groove in the region where the second support structure 2SP is to be formed, bowing due to over-etching may occur at both ends of the groove where the intermediate support structure C_SP is to be formed.

[0056] The curvature that may occur in the trench in which the intermediate support structure C_SP is to be formed will be described in detail as follows.

[0057] Figure 3B is a view illustrating a phenomenon in which bending occurs in a supporting structure. Figure 3C is a view illustrating a defect caused by bending occurring in a supporting structure.

[0058] Reference Figure 3B and Figure 3C, in an etching process for forming an outer trench E_TC in which the second outer support structure 2E_SP is to be formed and an intermediate trench C_TC in which the intermediate support structure C_SP is to be formed, over-etching may occur in a region in which the outer trench E_TC and the intermediate trench C_TC contact each other, and thus a bending BW may occur. For example, the outer trench E_TC and the intermediate trench C_TC may be formed by performing an anisotropic dry etching process.

[0059] The anisotropic dry etching process may be performed by using the following principle.

[0060] Anisotropic dry etching process can be performed by using reactive ion etching (RIE) method or by applying the method obtained by RIE method. By using RIE method or by applying the method obtained by RIE method, plasma can be used in etching process. Positive ions generated by plasma can move in a direction perpendicular to substrate, and then can collide with etching target layer, therefore, the binding force of etching target layer surface may weaken. Molecules at the part where binding force weakens in etching target layer can be released together with free radicals. Therefore, since positive ions move in a direction perpendicular to etching target layer, the etching rate of the surface parallel to substrate is higher than the etching rate of the surface perpendicular to substrate. For this reason, outer groove E_TC and intermediate groove C_TC can be formed in a direction perpendicular to substrate.

[0061] However, as the depth of the outer groove E_TC and the middle groove C_TC becomes deeper, the direction of positive ion movement may change. For example, the area of ​​the portion 31 where the outer groove E_TC and the middle groove C_TC contact each other is greater than the area of ​​another region of the outer groove E_TC and the middle groove C_TC, and therefore, isotropic etching can be performed in a region having an area larger than the area of ​​the other region. At the portion 31 where the outer groove E_TC and the middle groove C_TC are vertically in contact with each other, a portion of the side surface of the outer groove E_TC and the middle groove C_TC may be overetched, and the shape in which the side surface becomes convex due to overetching may be referred to as a curved BW. Therefore, due to the curved BW, the side surface of the portion 31 where the outer groove E_TC and the middle groove C_TC contact each other may become close to the side surface of the contact hole CTH in which the first support structure 1SP will be formed. When overetching occurs, a portion of the outer groove E_TC and the middle groove C_TC may contact each other with the side surface of the contact hole CTH.

[0062] For example, when a bend BW occurs in an etching process for forming the outer trench E_TC, the middle trench C_TC, and the contact hole CTH in the stack structure STK in which the insulating layer IL and the gate line GL are alternately stacked, the middle trench C_TC and a portion of the contact hole CTH may contact each other. When the middle support structure C_SP and the first support structure 1SP formed as an insulating material are filled in the middle trench C_TC and the contact hole CTH after the etching process, some of the gate lines GL to be extended between the middle support structure C_SP and the first support structure 1SP may be cut, which may cause defects in the memory device.

[0063] Accordingly, a layout capable of suppressing the occurrence of the bend BW between the first supporting structure 1SP and the intermediate supporting structure C_SP is disclosed in the following embodiment.

[0064] Figure 4A is a layout of a supporting structure according to a first embodiment of the present disclosure. Figure 4B 2 is a view illustrating a layout of a second supporting structure and a first supporting structure adjacent to the second supporting structure according to a first embodiment of the present disclosure. Figure 4C is a perspective view illustrating a supporting structure according to a first embodiment of the present disclosure.

[0065] Reference Figure 4A , the second supporting structure 2SP may include first and second outer supporting structures 1E_SP and 2E_SP, first and second protruding patterns 1PR and 2PR, and an intermediate supporting structure C_SP.

[0066] The first outer supporting structure 1E_SP and the second outer supporting structure 2E_SP may extend along the X direction and may be arranged parallel to each other. The first protruding pattern 1PR and the second protruding pattern 2PR may be in contact with the first outer supporting structure 1E_SP and the second outer supporting structure 2E_SP, respectively, and may be arranged parallel to each other. For example, the first protruding pattern 1PR may extend from the first outer supporting structure 1E_SP along the X direction, and the second protruding pattern 2PR may extend from the second outer supporting structure 2E_SP along the X direction.

[0067] The intermediate support structure C_SP may be located between the first external support structure 1E_SP and the second external support structure 2E_SP in the Y direction. For example, one side surface of the intermediate support structure C_SP and one side surface of each of the first external support structure 1E_SP and the second external support structure 2E_SP may extend together along the Y direction. The first protruding pattern 1PR and the second protruding pattern 2PR may protrude along the X direction as extensions of the first external support structure 1E_SP and the second external support structure 2E_SP, respectively. For example, when it is assumed that the first external support structure 1E_SP and the second external support structure 2E_SP extend from portions where the intermediate support structure C_SP and the first external support structure 1E_SP and the second external support structure 2E_SP contact each other along the +X direction, the first protruding pattern 1PR and the second protruding pattern 2PR may extend from these portions along the -X direction. That is, the first protruding pattern 1PR and the second protruding pattern 2PR may protrude in a direction opposite to the direction in which the first external support structure 1E_SP and the second external support structure 2E_SP extend.

[0068] Reference Figure 4B , the first support structure 1SPa and 1SPb ( Figure 4A 1SP) and the contact CT shown in the figure can be arranged at the periphery of the second support structure 2SP. Figure 3B When the bend BW occurs at the portion where the second external support structure 2E_SP and the intermediate support structure C_SP contact each other, the intermediate support structure C_SP may be located in a region RG corresponding to a portion between the first support structures 1SPa and 1SPb in the X direction to prevent the bend BW from contacting the first support structures 1SPa and 1SPb. In addition to the intermediate support structure C_SP, a contact CT may also be located in the region RG between the first support structures 1SPa and 1SPb, and the contact CT may be aligned with and spaced apart from the intermediate support structure C_SP in the Y direction.

[0069] The size of the contact CT may be smaller than that of the first support structure 1SP, and the contact CT may be farther from the second support structure 2SP than the first support structure 1SP. Therefore, although the bend BW appears at the portion where the second outer support structure 2E_SP and the intermediate support structure C_SP contact each other, the bend BW and the contact CT or the first support structures 1SPa and 1SPb may also be difficult to contact each other. Specifically, the first length L1 may be a length extending along the +Y direction, and may be the shortest length between the bend BW and the contact CT. However, since the contact CT is farther from the second outer support structure 2E_SP and the second protruding pattern 2PR than the first support structures 1SPa and 1SPb in the +Y direction, even if the bend BW appears, the bend BW is difficult to contact the contact CT. In addition, since the bend BW and the first support structures 1SPa and 1SPb are adjacent to each other in the oblique direction (a combination of the +Y direction and the +X direction or a combination of the +Y direction and the -X direction), even when bending occurs, the phenomenon that the bend BW and the first support structures 1SPa and 1SPb contact each other can be prevented.

[0070] Since the intermediate support structure C_SP is located in the region RG corresponding to between the first support structures 1SP, the support force of the stacked structure may be reduced in the region corresponding to the -X direction from a portion where the intermediate support structure C_SP and the second outer support structure 2E_SP contact each other. Accordingly, the second protruding pattern 2PR may extend from the second outer support structure 2E_SP in the -X direction, so that the support force in the region where the support force may be reduced due to the position change of the intermediate support structure C_SP can be supplemented. Since the second protruding pattern 2PR extends in a linear shape along the ±X direction and there is no support structure in contact with it along the +Y direction or the -Y direction, the bending BW may not occur. Although the bending BW occurs from the second protruding pattern 2PR in the +Y direction, the size of the bending BW may be smaller than the size of the bending BW that occurs in the region where the intermediate support structure C_SP and the second outer support structure 2E_SP contact each other. Therefore, it will be difficult for the first support structure 1SPa and the second protruding pattern 2PR to contact each other due to the bending BW.

[0071] The intermediate support structure C_SP may have a linear shape extending along the ±Y direction, the second outer support structure 2E_SP may have a linear shape extending along the +X direction orthogonal to the ±Y direction, and the second protruding pattern 2PR may have a linear shape extending along the -X direction which is the opposite direction of the +X direction. Therefore, the intermediate support structure C_SP and the second protruding pattern 2PR may be in vertical contact with each other, and the intermediate support structure C_SP and the second outer support structure 2E_SP may also be in vertical contact with each other.

[0072] When it is assumed that the width of the intermediate support structure C_SP is the first width W1, the second outer support structure 2E_SP may have a second width W2 narrower than the first width W1. For example, the first width W1 may be the length in the ±X direction in the intermediate support structure C_SP, and the second width W2 may be the length in the ±Y direction in the second outer support structure 2E_SP. In order to ensure a margin between the bend BW and the first support structures 1SPa and 1SPb, the first width W1 may be set to be narrower than the first distance IT1, which is the distance in the ±X direction between the first support structures 1SPa and 1SPb.

[0073] The first outer supporting structure 1E_SP, which is parallel to the second outer supporting structure 2E_SP and in contact with the intermediate supporting structure C_SP, may also be in vertical contact with the intermediate supporting structure C_SP. The first protruding pattern 1PR may extend from the first outer supporting structure 1E_SP along the -X direction and may be arranged parallel to the second protruding pattern 2PR. Therefore, the first protruding pattern 1PR and the intermediate supporting structure C_SP may be in vertical contact with each other. The length of the first protruding pattern 1PR in the +X direction may be equal to the length of the second protruding pattern 2PR in the +X direction. The second distance IT2 between the first protruding pattern 1PR and the second protruding pattern 2PR in the ±Y direction may be equal to the length of the long axis of the intermediate supporting structure C_SP.

[0074] Reference Figure 4C , the first external support structure 1E_SP and the second external support structure 2E_SP, the intermediate support structure C_SP, and the first protruding pattern 1PR and the second protruding pattern 2PR can support the first stacked structure 1STK and the second stacked structure 2STK while penetrating the first stacked structure 1STK or the second stacked structure 2STK. For example, the first stacked structure 1STK surrounding the first external support structure 1E_SP and the second external support structure 2E_SP, the intermediate support structure C_SP, and the first protruding pattern 1PR and the second protruding pattern 2PR may include alternately stacked insulating layers and gate lines. The second stacked structure 2STK surrounded by the first external support structure 1E_SP and the second external support structure 2E_SP and the intermediate support structure C_SP may include alternately stacked insulating layers and sacrificial layers.

[0075] The insulating layer included in the first stack structure 1STK and the second stack structure 2STK may be formed of an oxide layer. The gate line included in the first stack structure 1STK may be formed of a conductive layer. For example, the gate line may be formed of a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co) or nickel (Ni) or of a semiconductor material such as silicon (Si) or polycrystalline silicon (poly-Si). The first external support structure 1E_SP and the second external support structure 2E_SP and the intermediate support structure C_SP may separate the first stack structure 1STK and the second stack structure 2STK from each other, and may support the first stack structure 1STK and the second stack structure 2STK. The first protruding pattern 1PR and the second protruding pattern 2PR may support the first stack structure 1STK.

[0076] Figure 5 2 is a view illustrating a supporting structure according to a second embodiment of the present disclosure.

[0077] Reference Figure 5 , the second supporting structure 2SP may include a first outer supporting structure 1E_SP and a second outer supporting structure 2E_SP, an intermediate supporting structure C_SP, and a first protruding pattern 1PR and a second protruding pattern 2PR. Each of the first protruding pattern 1PR and the second protruding pattern 2PR of the second supporting structure 2SP may have a width narrower than the width of each of the first outer supporting structure 1E_SP and the second outer supporting structure 2E_SP. For example, when it is assumed that the intermediate supporting structure C_SP has a first width W1, each of the first outer supporting structure 1E_SP and the second outer supporting structure 2E_SP may have a second width W2 narrower than the first width W1, and each of the first protruding pattern 1PR and the second protruding pattern 2PR may have a third width W3 narrower than the second width W2. When the lower surface 51 of the first protruding pattern 1PR and the lower surface 52 of the first external support structure 1E_SP extend along the same line, and the upper surface 53 of the second protruding pattern 2PR and the upper surface 54 of the second external support structure 2E_SP extend along the same line, the distance between the first protruding pattern 1PR and the second protruding pattern 2PR may have a third distance IT3 that is longer than the length of the long axis of the intermediate support structure C_SP.

[0078] Figure 6 is a view illustrating a supporting structure according to a third embodiment of the present disclosure.

[0079] Reference Figure 6, the second supporting structure 2SP may include a first outer supporting structure 1E_SP and a second outer supporting structure 2E_SP, an intermediate supporting structure C_SP, and a first protruding pattern 1PR and a second protruding pattern 2PR. Each of the first protruding pattern 1PR and the second protruding pattern 2PR of the second supporting structure 2SP may have a width wider than the width of each of the first outer supporting structure 1E_SP and the second outer supporting structure 2E_SP. For example, when it is assumed that the intermediate supporting structure C_SP has a first width W1, each of the first outer supporting structure 1E_SP and the second outer supporting structure 2E_SP may have a second width W2 narrower than the first width W1, and each of the first protruding pattern 1PR and the second protruding pattern 2PR may have a fourth width W4 wider than the second width W2. When the lower surface 61 of the first protruding pattern 1PR and the lower surface 62 of the first external support structure 1E_SP extend along the same line, and the upper surface 63 of the second protruding pattern 2PR and the upper surface 64 of the second external support structure 2E_SP extend along the same line, the distance between the first protruding pattern 1PR and the second protruding pattern 2PR may have a fourth distance IT4 that is shorter than the length of the long axis of the intermediate support structure C_SP.

[0080] Figure 7 2 is a view illustrating a supporting structure according to a fourth embodiment of the present disclosure.

[0081] Reference Figure 7 , the second support structure 2SP may include a first outer support structure 1E_SP and a second outer support structure 2E_SP, an intermediate support structure C_SP, and a third protruding pattern 3PR. The third protruding pattern 3PR of the second support structure 2SP may be in contact with one surface 71 of the intermediate support structure C_SP. For example, the third protruding pattern 3PR may not be in contact with the first outer support structure 1E_SP or the second outer support structure 2E_SP, but may be in contact with one surface 71 of the intermediate support structure C_SP. For example, a center point 72 in the Y direction of the third protruding pattern 3PR and a center point 73 in the Y direction of the intermediate support structure C_SP may be located on the same line 74 extending along the X direction. The width of the third protruding pattern 3PR may be narrower, equal to, or wider than the width of the first outer support structure 1E_SP or the second outer support structure 2E_SP. When the width of the third protruding pattern 3PR is wider than the width of the first outer support structure 1E_SP or the second outer support structure 2E_SP, the width of the third protruding pattern 3PR in the Y direction may be narrower than the length of the long axis of the intermediate support structure C_SP.

[0082] Figure 8 is a view illustrating a supporting structure according to a fifth embodiment of the present disclosure.

[0083] Reference Figure 8 , the second support structure 2SP may include a first outer support structure 1E_SP and a second outer support structure 2E_SP, an intermediate support structure C_SP, and a first protruding pattern 1PR to a third protruding pattern 3PR. In the first protruding pattern 1PR to the third protruding pattern 3PR of the second support structure 2SP, the first protruding pattern 1PR and the second protruding pattern 2PR may be in contact with the first outer support structure 1E_SP and the second outer support structure 2E_SP, respectively, and the third protruding pattern 3PR may be in contact with the intermediate support structure C_SP. For example, the first protruding pattern 1PR may protrude from the first outer support structure 1E_SP along the -X direction, the second protruding pattern 2PR may protrude from the second outer support structure 2E_SP along the -X direction, and the third protruding pattern 3PR may protrude from the intermediate support structure C_SP along the -X direction. The width of each of the first protruding pattern 1PR and the second protruding pattern 2PR may be equal to, wider than, or narrower than the width of the first outer support structure 1E_SP or the second outer support structure 2E_SP. The width of the third protruding pattern 3PR may be narrower than the length of the long axis of the intermediate support structure C_SP. The first to third protrusion patterns 1PR to 3PR may be spaced apart from each other.

[0084] exist Figure 8 In the embodiment, three protruding patterns 1PR, 2PR and 3PR are illustrated. In some embodiments, the second support structure 2SP may include four or more protruding patterns that contact the first outer support structure 1E_SP and the second outer support structure 2E_SP and the intermediate support structure C_SP along the -X direction. The corner of each of the protruding patterns 1PR to 3PR may have a right angle shape 81 or an arc shape 82.

[0085] Fig. 9 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0086] Reference Fig. 9 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0087] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a programming operation, a reading operation, or an erasing operation, or may control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0088] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. Exemplarily, the controller 3100 can communicate with an external device through at least one of various communication protocols such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), firmware, a universal flash storage (UFS), Wi-Fi, Bluetooth (Bluetooth) and NVMe. Exemplarily, the connector 3300 can be defined by at least one of the various communication protocols mentioned above.

[0089] The memory device 3200 may include a memory cell and may be connected to Figure 1 The memory device 100 shown in FIG. 1 is configured identically.

[0090] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a universal flash storage (UFS).

[0091] Fig.10 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0092] Reference Fig.10 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0093] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. Exemplarily, the signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firmware, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0094] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n may be connected to Figure 1 The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0095] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive the power PWR input from the host 4100 and may charge the power PWR. When the power supply from the host 4100 is not stable, the auxiliary power supply 4230 may provide power to the SSD 4200. Exemplarily, the auxiliary power supply 4230 may be located in the SSD 4200, or may be located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located in the mainboard and may provide auxiliary power to the SSD 4200.

[0096] The buffer memory 4240 may operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0097] According to the present disclosure, the layout of the support structure can be changed, so that defects that may occur in the manufacturing process of the memory device can be reduced. Accordingly, the yield of the manufacturing process of the memory device can be improved.

[0098] Although the present disclosure has been shown and described with reference to certain exemplary embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned exemplary embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0099] In the above-mentioned embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps do not necessarily have to be performed in the order described and may be reordered. The embodiments disclosed in this specification and the accompanying drawings are merely examples to facilitate understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0100] In addition, exemplary embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

[0101] CROSS-REFERENCE TO RELATED APPLICATIONS

[0102] This application claims the priority of Korean Patent Application No. 10-2023-0076119 filed on June 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: Stacked structure; a first supporting structure, the first supporting structure penetrating the stacked structure, the first supporting structures being spaced apart from each other in a first direction; a first protruding pattern, the first protruding pattern penetrating the stacked structure, the first protruding pattern being spaced apart from one of the first supporting structures in a second direction; a first external support structure, the first external support structure penetrating the stacked structure, the first external support structure extending from the first protrusion pattern along the first direction; as well as an intermediate support structure, the intermediate support structure penetrating the stacked structure, the intermediate support structure extending in the second direction in a region between the first support structures, the intermediate support structure contacting the first outer support structure.

2. The memory device according to claim 1, wherein: The first protrusion pattern has a linear shape extending in the first direction.

3. The memory device according to claim 1, wherein: The first outer supporting structure contacts the first protrusion pattern and has a linear shape extending in the first direction.

4. The memory device according to claim 1, wherein: The first protruding pattern and the first outer support structures are located between the intermediate support structures and some of the first support structures.

5. The memory device according to claim 1, wherein: A width of the intermediate support structure in the first direction is narrower than a distance between adjacent first support structures in the first direction.

6. The memory device according to claim 1, wherein: A width of the first protruding pattern in the second direction is equal to a width of the first outer supporting structure in the second direction.

7. The memory device according to claim 1, wherein: A width of the first protruding pattern in the second direction is narrower than a width of the first outer supporting structure in the second direction.

8. The memory device according to claim 1, wherein: A width of the first protruding pattern in the second direction is wider than a width of the first outer supporting structure in the second direction. 9 . The memory device of claim 1 , further comprising a contact located between the first support structures adjacent in the first direction.

10. The memory device according to claim 9, wherein: The contacts are aligned with and spaced apart from the intermediate support structure in the second direction.

11. The memory device according to claim 9, wherein: A portion of the first outer support structure is located between the contact and the intermediate support structure.

12. The memory device according to claim 1, wherein: The intermediate support structure is in perpendicular contact with the first outer support structure.

13. The memory device of claim 1 , further comprising: a second outer supporting structure, the second outer supporting structure being parallel to the first outer supporting structure, the second outer supporting structure being in contact with the intermediate supporting structure; as well as A second protrusion pattern, the second protrusion pattern is parallel to the first protrusion pattern, the second protrusion pattern protruding from the second outer support structure in the first direction.

14. The memory device according to claim 13, wherein: The length of the second protrusion pattern is equal to the length of the first protrusion pattern. 15 . The memory device of claim 1 , further comprising a third protrusion pattern parallel to the first protrusion pattern, the third protrusion pattern contacting the intermediate support structure.

16. The memory device of claim 1, wherein: A corner portion of the first protrusion pattern has a right angle shape or an arc shape.

17. A memory device, the memory device comprising: Stacked structure; a first external support structure and a second external support structure, the first external support structure and the second external support structure penetrating the stacked structure, the first external support structure and the second external support structure extending parallel to each other in a first direction; an intermediate support structure extending between the first outer support structure and the second outer support structure in a second direction perpendicular to the first direction; as well as a protruding pattern, the protruding pattern penetrating the stacked structure, the protruding pattern extending from the intermediate supporting structure along the first direction, Wherein, the protruding pattern extends in a direction opposite to a direction in which the first outer support structure and the second outer support structure extend from the intermediate support structure.

18. The memory device of claim 17, further comprising: a first supporting structure spaced apart from the protruding pattern along the second direction; a second support structure, the second support structure being spaced apart from the first support structure along the first direction, the second support structure being spaced apart from the first outer support structure along the second direction; as well as A contact is aligned with and spaced apart from the intermediate support structure along the second direction.

19. The memory device of claim 18, wherein: The area of ​​the first outer supporting structure in contact with the intermediate supporting structure is located between the contact piece and the intermediate supporting structure.

20. The memory device of claim 18, wherein: The distance between the contact and the first outer support structure is greater than the distance between the second support structure and the first outer support structure.

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