Signal switching jig, system and method for chip reliability test system

Abstract

The invention discloses a signal switching fixture, system and method for a chip reliability test system. The signal switching fixture comprises a plurality of mainboards, and at least one surface of each mainboard is coupled with a plurality of daughter boards or a plurality of mainboard expansion switching boards. The main board is used for dividing received signals into multiple paths and sending the signals to the corresponding daughter boards or the main board expansion adapter board. The daughter board is used for converting a received signal into an MIPI signal or sending a received SPI signal to a chip to be tested through the furnace throwing board, and the mainboard expansion adapter board is used for forwarding the received signal to another mainboard. According to the signal switching jig provided by the invention, the host and the signal switching jig can be separated from the tested chip needing to be put into a furnace, and meanwhile, one path of signal can be changed into multiple paths so as to realize the simultaneous operation of the testing process of one or more chips, so that the testing efficiency is greatly improved under the condition that the signal switching jig and a system do not occupy a relatively large area. The test efficiency and the test accuracy are greatly improved, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip manufacturing technology, and in particular to a signal switching fixture, system and method for a chip reliability testing system. Background Art

[0002] The quality characteristics of a chip refer to the inherent characteristics of a product, process or system related to requirements, including properties such as performance, life, practicality, reliability, ease of use, economy and aesthetics. Reliability refers to the ability of a product to perform as required, which is a collection of time-related quality characteristics of a product, including availability, reliability, recovery, maintainability and security, and in some cases, other characteristics such as environmental adaptability, durability, safety and information security.

[0003] Among them, chip reliability refers to the ability of a product to complete a specified function under specified conditions and within a specified time, and its probability is called reliability. Chip reliability is the most basic and important characteristic of chip product quality characteristics.

[0004] For example, for LCD (Liquid Crystal Display) products (LCD products refer to various displays and display panels that use liquid crystal display technology), IC-level and module-level reliability (RA) tests are required. The IC (integrated circuit chip) level mainly corresponds to the COB (Chip On Board, integrated circuits pressed on PCB boards). Since the driving-related circuits are all on the chip, only the chip is involved, so it is called the IC level. The module level specifically corresponds to the COG (Chip On Glass, which refers to the chip integrated into the substrate of the display screen), so it is called the module level.

[0005] The existing test system (test fixture) for reliability testing of LCD products usually requires that the entire test system including the LCD product be placed in a test furnace to perform operation tests in extreme high temperature, low temperature, high humidity and other environments, and then obtain the reliability results of the LCD product. However, since the test system is located in the test furnace, not only the life of the equipment is shortened, but also when the test system is in the furnace, it becomes difficult to operate the corresponding structures of the test system, which reduces the controllability or flexibility of the test, and is not conducive to maximizing the test efficiency. In addition, common test fixtures can often only be used to perform reliability tests on one chip, which greatly increases the production cost. Occasionally, there are test fixtures that can test multiple chips at the same time, but their number is limited to two or three. Moreover, the existing test fixtures often need to be tested as a whole in the furnace, which is very unfavorable for maintaining the service life of structures such as the host in the test fixture. Summary of the invention

[0006] The purpose of the present invention is to provide a signal transfer fixture, system and method for a chip reliability test system, which can realize the testing of a large number of chips without occupying a large area, and can improve the test efficiency while extending the equipment life of the test system and reducing the production cost.

[0007] In order to achieve the above objectives, the present invention is implemented by the following technical solutions:

[0008] A signal transfer fixture for a chip reliability test system, the signal transfer fixture comprising: a plurality of main boards, at least one side of the main board coupled to a plurality of daughter boards and / or a plurality of main board extension adapter boards; the main board is used to divide the received signal into multiple paths and send the signals to the corresponding daughter boards or main board extension adapter boards; the daughter boards are used to process the received signals and send the processed signals to the chip to be tested through a furnace board, or the daughter boards are used to send the received signals to the chip to be tested through the furnace board; the main board extension adapter board is used to transfer the received signals from one main board to another main board.

[0009] Optionally, the daughter board is used to convert the received signal into a MIPI signal and send it to the chip under test through the furnace board, or the daughter board is used to send the received SPI signal to the chip under test through the furnace board.

[0010] Optionally, the main board includes: a first printed circuit board, and a plurality of male socket units integrated on the first printed circuit board, wherein the male socket units are used to couple the daughter board or the main board expansion adapter board to the main board.

[0011] Optionally, each male socket unit includes a plurality of sub-male socket units, and the pin seats of the plurality of sub-male socket units are arranged and extended in different directions.

[0012] Optionally, the sub-board includes: a second printed circuit board, a pin unit integrated on the first surface of the second printed circuit board, a signal conversion unit, and an HDMI interface, an SPI interface, and an integrated interface located on the second surface.

[0013] Optionally, the pin unit includes a plurality of pin sub-units, and each of the pin sub-units matches and plugs into the male socket unit on the mainboard.

[0014] Optionally, the motherboard expansion adapter board includes: a third printed circuit board, an expansion pin unit located on the first surface and a preset signal line adapter located on the second surface integrated on the third printed circuit board. The expansion pin unit is plugged into the male socket unit on one of the motherboards; the preset signal line adapter is connected to the RGB+SPI signal interface on the other motherboard.

[0015] Optionally, the chip to be tested is a COB board or a COG board.

[0016] On the other hand, a signal transfer fixture system for a chip reliability test system is provided, comprising: a plurality of signal transfer fixtures as described above; the plurality of signal transfer fixtures are stacked in a height direction.

[0017] Optionally, the signal transfer fixture system used in the chip reliability testing system includes a plurality of support columns, and the mainboard of the signal transfer fixture includes a plurality of coupling holes. In the height direction, the adjacent plurality of signal transfer fixtures are respectively coupled to the two ends of the support columns through respective coupling holes arranged on the first printed circuit board so as to stack the plurality of signal transfer fixtures in the height direction.

[0018] Optionally, the signal transfer fixture system for the chip reliability testing system further includes a shelf, the shelf including a plurality of placement plates stacked in the height direction, and a plurality of the signal transfer fixtures are stacked in the height direction by being placed on the plurality of placement plates.

[0019] Optionally, the mainboards of the signal switching fixtures located at the upper part, the lower part, or the middle part among the plurality of signal switching fixtures stacked in the height direction are coupled to a plurality of mainboard expansion adapter boards.

[0020] Optionally, the signal adapter fixture is connected to a mainboard expansion adapter board on another signal adapter fixture via a preset signal line to receive an RGB+SPI signal; or the signal adapter fixture is connected to a host via a preset signal line to receive an RGB+SPI signal.

[0021] On the other hand, a method for reliability testing using a signal transfer fixture for a chip reliability test system according to an embodiment, or a signal transfer fixture system for a chip reliability test system according to any embodiment is provided, comprising: coupling the chip to be tested to a furnace board, coupling the furnace board to a sub-board of the signal transfer fixture, and establishing a signal connection between the signal transfer fixture and a host. The furnace board coupled with the chip to be tested is placed in a test furnace for providing a test environment. A point screen signal is sent to the signal transfer fixture through the host. The signal transfer fixture performs signal noise reduction processing or signal conversion processing on the point screen signal and divides it into multiple sub-point screen signals. The multiple sub-point screen signals are respectively sent to the corresponding chips to be tested via the corresponding furnace boards for reliability testing.

[0022] The present invention has at least one of the following technical effects:

[0023] The present invention can separate the host and the signal transfer fixture itself from the chip to be tested by the furnace through the signal transfer fixture provided, and at the same time convert the signal from one channel to multiple channels to realize the simultaneous testing process of one or more (large number) chips, which can greatly improve the test efficiency and test accuracy without occupying a large area and reduce the production cost.

[0024] The pin sockets of the plurality of sub-male socket units are arranged in different directions, which is conducive to the stable connection between the sub-board (or expansion adapter board) and the main board. It is also convenient to make the resistance of the corresponding wiring on the PCB of the main board and the sub-board more uniform, which is conducive to matching resistance. Because the setting of the socket is conducive to wiring around, the wiring can be made longer by bypassing, and the longer length is more conducive to matching resistance, thereby achieving uniform resistance.

[0025] Several signal transfer fixtures are stacked in the height direction, thereby saving space and further reducing production costs.

[0026] The provision of the mainboard expansion adapter board improves the scalability of the signal transfer fixture and the flexibility of testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The main structural block diagram of the chip reliability test system in the prior art;

[0028] Figure 2 A main structural block diagram of a chip reliability testing system provided by an embodiment of the present invention;

[0029] Figure 3 A main structural block diagram of a signal transfer fixture provided by an embodiment of the present invention;

[0030] Figure 4 A structural block diagram of a mainboard provided in one embodiment of the present invention;

[0031] Figure 5 A schematic diagram of the coupling relationship of a mainboard provided in one embodiment of the present invention;

[0032] Figure 6 A structural block diagram of a daughter board provided in one embodiment of the present invention;

[0033] Figure 7 A schematic diagram of the structure of a mainboard expansion adapter board provided in one embodiment of the present invention;

[0034] Figure 8 A schematic diagram of the structure of a signal transfer fixture system provided by an embodiment of the present invention;

[0035] Fig. 9 A schematic diagram of the structure of a signal transfer fixture system provided by another embodiment of the present invention;

[0036] Fig.10 A schematic flow chart of a chip reliability testing method provided in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following is a further detailed description of a signal transfer fixture, system and method for a chip reliability test system proposed in the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structure, proportion, size, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any modification of the structure, change in the proportional relationship or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed in the present invention.

[0038] As described in the background art, the existing test system for reliability testing of LCD products usually requires that the entire test system including the LCD product be placed in a test furnace to perform operation tests in extreme high temperature, low temperature, high temperature and high humidity environments, and then obtain the reliability results of the LCD product. Figure 1 As shown, the existing test fixture for reliability testing of LCD products includes: a host 1 and a binding board 2, and the chip 4 to be tested is set on the binding board 2. When the chip 4 to be tested is COG, its essence is to be electrically connected to the binding board 2 through a flexible printed circuit (Flexible Printed Circuit, FPC) 3 connected to COG, and to achieve the binding of COG. The host 1 and the binding board 2 are connected by a DuPont line 5; the host 1 directly outputs the MIPI (Mobile Industry Processor Interface) signal, and transmits the MIPI signal to the binding board 2 through the DuPont line 5. The DuPont line is limited to not supporting long-distance high-speed transmission ((the transmission distance of the DuPont line is generally within 20cm)). During the test, the signal lines, power lines, etc. between the various parts can only be connected, and the entire test fixture bound to the chip 4 to be tested can be put into the test furnace 6 for operation tests in extreme high temperature, low temperature, high humidity and other environments.

[0039] In this case, the life of some structures of the test fixture (such as the host 1, binding board 2, etc., whose ideal temperature for normal operation should not exceed 85°C and at most 125°C) is greatly affected by the extreme environment. Executing such a test method can easily cause them to be damaged prematurely, resulting in a short service life and high test cost. Even when the failure is not discovered in time, the erroneous test results obtained are also used as a reference, which seriously affects the test quality. In addition, this overall furnace-throwing method makes the maintenance of the test fixture quite difficult, making it difficult to reduce the maintenance cost. Moreover, when all the furnaces are thrown, it will become difficult to adjust the test conditions (such as the change and adjustment of the test voltage) of the corresponding structures of the test fixture, which reduces the controllability or flexibility of the test and is not conducive to maximizing the test efficiency. In addition, a test fixture can only bind one chip to be tested, which greatly increases the production cost and reduces the test efficiency.

[0040] In view of this, if Figure 2 As shown, this embodiment provides a signal transfer fixture for a chip reliability test system. The chip reliability test system includes: a host 10; a signal transfer fixture 40, which is coupled to the host 10. A plurality of furnace boards 11 are respectively coupled to the signal transfer fixture 40; each furnace board 11 is used to plug a chip to be tested 30; during testing, the furnace board 11 with the chip to be tested 30 is placed in a test furnace 20 for providing a test environment. The host 10 is used to generate and send a point screen signal (for example, RGB+SPI signal, RGB signal is red, green and blue signal, SPI signal is serial peripheral interface signal) to the signal transfer fixture 40. The signal transfer fixture 40 is used, for example, to convert the point screen signal (for example, convert it into a MIPI signal) and divide it into multiple sub-point screen signals. The furnace board 11 sends the received multiple sub-point screen signals to the corresponding chip to be tested 30 respectively for reliability testing.

[0041] like Figure 3 As shown, the signal adapter fixture 40 includes: a plurality of main boards 401, at least one side of the main board 401 is coupled to a plurality of sub-boards 402 and / or a plurality of main board expansion adapter boards 403; the main board 401 is used to divide the received signal into multiple paths and send them to the corresponding sub-boards 402 and / or main board expansion adapter boards 403.

[0042] The sub-board is used to process the received signal, and send the processed signal to the chip to be tested through the furnace board, or the sub-board is used to send the received signal to the chip to be tested through the furnace board. For example, the sub-board 402 is used to convert the received signal (SPI+RGB signal) into a MIPI signal and send it to the chip to be tested 30 through the furnace board 11, or the sub-board 402 is used to send the received SPI signal to the chip to be tested 30 through the furnace board 11. The mainboard expansion adapter board 403 is used to transfer the received signal to another mainboard 401. The independent coupling of each sub-board 402 to the mainboard 401 can also facilitate maintenance. When repairing, only the sub-board 402 needs to be removed for inspection, which will not affect the normal use of other sub-boards 402. By using the mainboard expansion adapter board 403, the expansion number is faster than directly increasing the number of coupled sub-boards 402, and more sub-paths can be expanded for chip testing.

[0043] The signal conversion fixture provided in this embodiment can simultaneously convert one signal into multiple signals to realize the simultaneous testing of one or more chips, which can greatly improve the testing efficiency and accuracy and reduce the production cost.

[0044] It is understandable that MIPI signals are suitable for electronic devices (such as smart phones, PADs, computers, etc.) with larger screens. SPI signals are suitable for electronic devices (such as watches, elderly phones, etc.) with smaller screens. That is, when the small screen needs to be dotted, the host 10 can process the RGB+SPI signal and only output the SPI signal.

[0045] Please continue to refer to Figure 3 As shown, in this embodiment or some other embodiments, the signal transfer fixture 40 is connected to the host 10 through a preset signal line 13, and the signal transfer fixture 40 is connected to the furnace board 11 through a signal line 12 that supports high-speed and long-distance transmission. Preferably, the signal line 12 is an HDMI line. By connecting the signal line 12 that supports high-speed and long-distance transmission to the furnace board 11, the host 10 and the signal transfer fixture 40 itself can be separated from the chip under test 30 that needs to be put into the furnace, thereby avoiding the host 10, the signal transfer fixture 40, etc. from affecting their service life and avoiding inconvenience in test operations.

[0046] like Figure 4 As shown, the main board 401 includes: a first printed circuit board 111 , and a plurality of male socket units 4012 integrated on the first printed circuit board 111 , wherein the male socket units 4012 are used to couple the sub-board 402 to the main board 401 .

[0047] In this embodiment, each male connector unit 4012 includes a plurality of sub-male connector units, and the plurality of sub-male connector units are arranged in a predetermined planar geometric shape, such as a triangle, a rectangle, or the like.

[0048] The male socket unit 4012 may include one or more sub-male socket units, but only one sub-male socket unit is also feasible. However, after being plugged into the daughter board, the sub-male socket unit is easy to collapse, which is not conducive to the stability of the daughter board. Therefore, it is preferred to include three sub-sockets (male sockets), which are extended in different directions, which is conducive to a more stable combination of the daughter board. At the same time, it is also convenient to make the resistance of the corresponding wiring on the PCB (printed circuit board) of the main board and the daughter board more uniform, which is conducive to matching resistance. Because the setting of the socket (male socket) unit is conducive to wiring around, and by detouring, the wiring can be made longer, and the longer length is more conducive to matching resistance, thereby achieving uniform resistance.

[0049] In this embodiment, eight male connector units 4012 may be provided on the main board 401 to connect a maximum of eight daughter boards 402 , but the number of the male connector units 4012 and daughter boards 402 provided is not limited thereto.

[0050] Please continue to refer to Figure 4 As shown, the main board 401 also includes: an RGB+SPI signal interface 4011 integrated on the first PCB board 111, a signal splitter 4013, an IIC adapter chip 4014, a main board address selection unit 4015, an IIC interface 4016, a main board switch 4017 and a main board power socket 4018 and other structures.

[0051] The RGB+SPI signal interface 4011 is used to couple with the host 10 to receive the point screen signal sent by the host 10. The RGB+SPI signal interface 4011 includes a coaxial line interface for receiving the RGB+SPI signal and / or a DuPont line interface for receiving the RGB+SPI signal, but the present invention is not limited thereto. In this embodiment, the RGB+SPI signal interface 4011 is coupled to the coaxial line interface via the coaxial line 13 to couple with the host 10.

[0052] The signal splitter 4013 is electrically connected to the male connector unit 4012 and the RGB+SPI signal interface 4011 respectively, and is used to split, amplify and enhance one channel of the dot screen signal from the RGB+SPI signal interface 4011 to obtain multiple channels of sub-dot screen signals.

[0053] The IIC adapter chip 4014 is electrically connected to the male socket unit 4012, and is used to divide the test signal from the host 10 into multiple paths and supply them to the daughter board 402 respectively, and also controls the voltage of the power chip on the daughter board 402, as well as the power-on and power-off timing.

[0054] The motherboard address selection unit 4015 can flexibly select the IIC address of the motherboard 401 to distinguish different motherboards 401 .

[0055] The IIC interface 4016 is electrically connected to the daughter board 402 and the IIC adapter chip 4014, respectively, and is used to send the test signal from the host 10 to the daughter board 402; the test signal is also used to read back the 3POWER (VSP, VSN, IOVCC) / 2POWER (VCI, IOVCC) data of the chip under test 30, and is used to monitor whether the chip under test 30 is working normally during the reliability test (or aging test).

[0056] The mainboard switch 4017 is coupled to the mainboard power socket 4018, and is used to control turning on or off the mainboard 401. The mainboard power socket 4018 is used to connect a DC power supply to provide a working voltage.

[0057] like Figure 5 As shown, the host 10 sends a point screen signal (such as RGB+SPI signal), which is transmitted to a plurality of signal splitters 4013 cascaded in a main board 401 in the signal transfer fixture 40 through the coaxial line 13 to deliver independent sub-point screen signals to different sub-boards. In the cascade network of this embodiment, the number of signal splitters 4013 is 15, and the input ends of every two signal splitters 4013 are connected to the output end of a signal splitter 4013, that is, the signal received by each signal splitter 4013 is divided into multiple paths (preferably into two paths, which is faster than dividing more paths in terms of signal transmission speed and less signal loss) through the multiple signal splitters 4013 connected to the output end and then output. Figure 5As shown in the figure, the host 10 sends a point screen signal, which is processed by 15 signal splitters 4013 of the cascade network and can be divided into 8 independently transmitted sub-point screen signals, which are respectively transmitted to 8 sub-boards 402. According to the difference of the chip 30 under test, each of the sub-boards 402 performs signal noise reduction or signal conversion processing on the sub-point screen signal to output MIPI signal, SPI signal, IC Power or backlight (BL) signal. For example, if it is necessary to output a MIPI signal, the sub-board converts the received RGB+SPI signal to obtain a MIPI signal, which is output from the HDMI output port of the sub-board. If it is necessary to output an SPI signal, it is necessary to send an SPI signal from the host and transmit it to the signal transfer fixture, and the signal transfer fixture receives the SPI signal and divides it. However, the transmission and branching process of SPI will experience a long distance, and the signal noise will be particularly large if the distance is too long. Based on this, the preferred embodiment of the present invention is set to perform noise reduction processing on the received and transmitted SPI signal by setting a corresponding circuit on the signal transfer fixture.

[0058] Please continue to refer to Figure 5 As shown, the host 10 is also provided with a structure for inputting test signals such as touch signals to the IIC adapter chip 4014 of the main board 401. The test signals pass through multiple sub-boards (for example, the above-mentioned 8 sub-boards 402), and transmit the test signals (IIC signals) to the corresponding chip 30 to be tested through the sub-boards 402.

[0059] In this embodiment, the signal splitter 4013 preferably includes four chips of model 74AVC8T245, which have the characteristics of unidirectional transmission and small signal reflection, but the present invention is not limited thereto.

[0060] The IIC adapter chip 401 may include chips of model PCA9518 and TCA9554, for example. PCA9518 is controlled by TCA9554 to control whether a signal is given to a corresponding daughter board. The IIC adapter chip 401 is not limited thereto.

[0061] like Figure 6 As shown, the sub-board 402 includes: a second printed circuit board 112, a pin unit 4121, a signal conversion unit 4122, an HDMI interface 4128, an SPI interface 4129 and other structures integrated on the second printed circuit board 112.

[0062] The pin unit 4121 is located on the first side of the second printed circuit board 112, and the backlight interface 4126, 2power interface 4127, HDMI interface 4128, SPI interface 4129 and integrated interface 4130 are all located on the second side of the second printed circuit board 112. The first side and the second side are arranged opposite to each other.

[0063] The pin unit 4121 on each daughter board 402 matches and plugs with the male socket unit 4012 on the main board 401 to bind the daughter board 402 to the main board 401 and establish a signal connection.

[0064] In this embodiment, the pin unit 4121 includes a plurality of pin sub-units, each of which matches and plugs into the male socket unit 4012 on the mainboard 401 .

[0065] The signal conversion unit 4122 is connected to the pin unit 4121 by signal; the HDMI interface 4128 establishes a signal connection between the signal conversion unit 4122 on the daughter board 401 and the furnace board 11 through the signal line 12 (preferably an HDMI line). The signal conversion unit 4122 is preferably a bridge chip for converting RGB+SPI signals to MIPI signals.

[0066] The signal conversion unit 4122 is used to convert the sub-point screen signal (such as RGB+SPI signal) from the mainboard 401 into a MIPI signal (MIPI high-speed signal) and output it to the chip under test 30 through the HDMI line and the furnace board 11 to perform point screen. That is, the electronic device with a relatively large screen (such as a mobile phone, a tablet, etc.) can be point screened.

[0067] The SPI interface 4129 is signal-connected to the pin unit 4121 , and the SPI interface 4129 establishes a signal connection between the daughter board 401 and the furnace board 11 through a signal line 12 (preferably an SPI signal line).

[0068] The SPI interface 4129 is used to output the sub-point screen signal (such as SPI signal) from the mainboard 401 after signal noise reduction through the SPI signal line and the furnace board 11 to the chip under test 30 to perform point screen. That is, the electronic device with a relatively small screen (such as an electronic watch, etc.) can be point screened.

[0069] Please continue to refer to Figure 6 As shown, the sub-board 401 further includes: a backlight chip 4123, a backlight current control unit 4124, a measuring unit 4125, a backlight interface 4126, a 2power interface 4127 and an integrated interface 4130 and other structures.

[0070] The backlight chip 4123 is used to supply power to the backlight module of the display panel. The backlight current control unit 4124 is used to adjust the backlight brightness. The measuring unit 4125 is used to test the VCI / IOVCC / VSP / VSN voltage and current. Specifically, the measuring unit 4125 may include a first measuring unit for measuring the VCI / IOVCC / VSP voltage and current, and a second measuring unit for measuring the VSN voltage and current. By continuously detecting the corresponding values ​​of the VCI / IOVCC / VSP / VSN voltage and current, the reliability of the chip under test during the entire aging test process can be reflected.

[0071] The backlight interface 4126 is used to connect the backlight. The 2power interface 4127 is respectively connected to the VCI interface, IOVCC interface and RESET interface in the furnace board 11, so that the furnace board 11 can support the chip to be tested driven by 2power, so that the VCI voltage and IOVCC voltage can be connected. The RESET interface is used for resetting.

[0072] The integrated interface (VSP / VSN / IOVCC / IIC interface) 4130 is used to connect to the VSP / VSN / IOVCC / IIC interface on the furnace board 11, so that the furnace board 11 can support the chip under test driven by 3power, so that the VSP voltage source, VSN voltage source and IOVCC voltage source can be connected to provide power for the chip under test 30.

[0073] like Figure 7 As shown, in this embodiment or some other embodiments, the mainboard expansion adapter board 403 includes: a third printed circuit board 113, an expansion pin unit 4231 integrated on the first surface of the third printed circuit board 113 and a coaxial line adapter interface 4232 located on the second surface.

[0074] The extended pin unit 4231 is plugged into the male socket unit 4012 on one of the main boards 401 ; the coaxial line adapter interface 4232 is connected to the RGB+SPI signal interface 4011 on the other main board 401 .

[0075] When the signal transfer fixture 40 includes a mainboard expansion transfer board 403 , the signal transfer fixture 40 can be connected to a mainboard expansion transfer board 403 on another signal transfer fixture 40 via a coaxial line.

[0076] In this embodiment, the chip under test 30 is a COB board or a COG board.

[0077] On the other hand, Figure 8 As shown, the present invention further provides a signal transfer fixture system for a chip reliability test system, comprising: a plurality of signal transfer fixtures 40 as described above; the plurality of signal transfer fixtures 40 are stacked in the height direction.

[0078] The signal transfer fixture proposed in this embodiment is conducive to the simultaneous touch-screening of a large number of chips under test, and the signal transfer fixture 40 is also particularly convenient for stacking multiple chips in space to avoid occupying a large test level surface area.

[0079] In this embodiment, please continue to refer to Figure 8 As shown, the signal transfer fixture system for the chip reliability test system includes a plurality of support columns 404, and the main board (first printed circuit board) of the signal transfer fixture 40 includes a plurality of coupling holes ( Figure 8 (not shown), in the height direction, the adjacent signal transfer fixtures 40 are respectively coupled to the two ends of the support column 404 through respective coupling holes on the first printed circuit board to stack the signal transfer fixtures 40 in the height direction.

[0080] In some other embodiments, such as Fig. 9 As shown, the signal transfer fixture system for the chip reliability test system also includes a shelf 405, and the shelf 405 includes a plurality of placement plates 406 stacked in the height direction, and a plurality of the signal transfer fixtures 40 are placed on the plurality of placement plates 406 to be stacked in the height direction.

[0081] In some other embodiments, the mainboards of the signal transfer fixtures located at the upper part, the lower part, or the middle part of the signal transfer fixtures stacked in the height direction are coupled to several mainboard extension adapter boards. For example, the male socket unit of the mainboard located at the upper part is mainly connected to the mainboard extension adapter board, so that the mainboards of the lower layers can obtain signals through the mainboard extension adapter board at the top layer, so that the preset signal lines of the mainboards of the lower layers can be arranged in an orderly manner. Since all signal transfer fixtures are prevented from directly obtaining signals from the host, the test environment can be made simpler and neater, and unnecessary losses caused by wire entanglement caused by leading out more preset signal lines with larger spans from the host can be avoided. At the same time, the mainboard of the signal transfer fixture located in the middle position can also be selected to couple several mainboard extension adapter boards, so that several layers of signal transfer fixtures on the upper and lower sides can establish connections with the mainboard extension adapter board through a relatively short and relatively symmetrical line distance, which will not cause the mainboards far away to use too long signal lines, nor will it cause signal differences. For example, when the distance is short, the preset signal line may use a DuPont line, and when the distance is long, a coaxial line is preferably used.

[0082] Preferably, for example, all male sockets of a main board on the top layer are coupled to the expansion adapter board (partial coupling to the expansion adapter board and partial coupling to the sub-board can also be selected according to actual needs), which is convenient for connecting wires and avoiding wire entanglement, and the entire signal transfer fixture system can be connected to the host with only one set of preset signal wires. The specific embodiment is not limited to this, and other convenient ways of arranging preset signal wires can also be used.

[0083] In this embodiment or some other embodiments, the signal transfer fixture is connected to the mainboard expansion adapter board on another signal transfer fixture through a preset signal line; or the signal transfer fixture is connected to the host through a preset signal line. The preset signal line preferably uses a coaxial line to transmit the signal, which has the advantage of better signal impedance matching and EMI characteristics, and can transmit the point screen signal losslessly when the speed reaches above 1Ghz.

[0084] For example, the male socket unit of each mainboard 401 can be extended to several mainboards through the mainboard expansion adapter board to realize the cascading of multiple mainboards. When there are 8 male socket units on a mainboard, 8 mainboards can be connected through 8 mainboard expansion adapter boards. 8 mainboards can be connected to 64 sub-boards, and one dot screen signal can be converted into 64 equivalent dot screen signals, which are respectively input to the tested chips 30 on 64 furnace boards 11 for testing. The IIC address of the mainboard can be controlled by a dip switch. In this way, 64 sub-boards can be controlled by only one host 10, and reliability testing can be performed at the same time. The test efficiency is greatly improved and the test cost is reduced.

[0085] Other aspects, such as Fig.10 As shown, this embodiment also provides a reliability test method, which is implemented by using the signal transfer fixture for the chip reliability test system as described above, or using the signal transfer fixture system for the chip reliability test system as described above, which includes:

[0086] Step S10: coupling the chip to be tested to the furnace board, coupling the furnace board to the daughter board of the signal transfer fixture, and establishing a signal connection between the signal transfer fixture and the host.

[0087] Step S20: placing the furnace plate coupled with the chip to be tested in a test furnace for providing a test environment.

[0088] Step S30: sending a screen-dotting signal to the signal transfer fixture through the host.

[0089] Step S40: the signal transfer fixture performs signal noise reduction processing (e.g., corresponding to SPI signal) or signal conversion processing (e.g., corresponding to MIPI signal) on one channel of the point screen signal and divides it into multiple sub-point screen signals. The multiple sub-point screen signals are respectively sent to the corresponding chip to be tested through the corresponding furnace board for reliability testing.

[0090] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0091] It should be noted that the devices and methods disclosed in the embodiments of this article can also be implemented in other ways. The device implementation described above is only schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of this article. In this regard, each box in the flowchart or block diagram can represent a part of a module, program or code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system for performing a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0092] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0093] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A signal transfer fixture for a chip reliability test system, characterized in that: The signal transfer fixture comprises: A plurality of main boards, at least one side of which is coupled to a plurality of daughter boards and / or a plurality of main board expansion adapter boards; The mainboard is used to divide the received signal into multiple paths and send them to the corresponding daughter boards or mainboard expansion adapter boards; The sub-board is used to process the received signal and send the processed signal to the chip to be tested through the furnace board, or the sub-board is used to send the received signal to the chip to be tested through the furnace board; The mainboard expansion adapter board is used to transfer the received signal from one mainboard to another mainboard.

2. The signal transfer fixture for the chip reliability test system according to claim 1, characterized in that: The daughter board is used to convert the received signal into a MIPI signal and send it to the chip to be tested through the furnace board, or the daughter board is used to send the received SPI signal to the chip to be tested through the furnace board.

3. The signal transfer fixture for the chip reliability test system according to claim 1 or 2, characterized in that The main board includes: a first printed circuit board, and a plurality of male socket units integrated on the first printed circuit board, wherein the male socket units are used to couple the daughter board or the main board expansion adapter board to the main board.

4. The signal transfer fixture for the chip reliability test system according to claim 3, characterized in that: Each male socket unit includes a plurality of sub-male socket units, and the pin seats of the plurality of sub-male socket units are arranged and extended in different directions.

5. The signal transfer fixture for the chip reliability test system according to claim 1, characterized in that: The sub-board includes: a second printed circuit board, a pin unit integrated on the first surface of the second printed circuit board, a signal conversion unit, and an HDMI interface, an SPI interface, and an integrated interface located on the second surface.

6. The signal transfer fixture for the chip reliability test system according to claim 5, characterized in that: The pin unit includes a plurality of pin sub-units, and each of the pin sub-units matches and plugs with the male socket unit on the mainboard.

7. The signal transfer fixture for the chip reliability test system according to claim 1, characterized in that: The mainboard expansion adapter board comprises: a third printed circuit board, an expansion pin unit located on a first surface and a preset signal line transfer interface located on a second surface integrated on the third printed circuit board; The extended pin unit is plugged into the male socket unit on one of the main boards; the preset signal line adapter is connected to the RGB+SPI signal interface on the other main board.

8. The signal transfer fixture for the chip reliability test system according to claim 1, characterized in that: The chip to be tested is a COB board or a COG board.

9. A signal transfer fixture system for a chip reliability test system, characterized in that: include: A signal transfer fixture as described in any one of claims 1 to 8; wherein the signal transfer fixtures are stacked in the height direction.

10. The signal transfer fixture system for the chip reliability test system according to claim 9, characterized in that: The signal transfer fixture system used in the chip reliability testing system includes a plurality of support columns, and the mainboard of the signal transfer fixture includes a plurality of coupling holes. In the height direction, the adjacent signal transfer fixtures are respectively coupled to the two ends of the support columns through respective coupling holes arranged on the first printed circuit board so as to stack the signal transfer fixtures in the height direction.

11. The signal transfer fixture system for a chip reliability test system according to claim 9, characterized in that: The signal transfer fixture system for the chip reliability test system also includes a shelf, which includes a plurality of placement plates stacked in the height direction, and a plurality of the signal transfer fixtures are stacked in the height direction by being placed on the plurality of placement plates.

12. The signal transfer fixture system for a chip reliability test system according to claim 10 or 11, characterized in that: The mainboards of the signal transfer fixtures located at the upper part, the lower part, or the middle part among the plurality of signal transfer fixtures stacked in the height direction are coupled to a plurality of mainboard expansion transfer boards.

13. The signal transfer fixture system for a chip reliability test system according to any one of claims 9 to 12, characterized in that: The signal transfer fixture is connected to a mainboard expansion adapter board on another signal transfer fixture through a preset signal line to receive an RGB+SPI signal; or the signal transfer fixture is connected to a host through a preset signal line to receive an RGB+SPI signal.

14. A method for performing reliability testing using the signal transfer fixture for a chip reliability test system according to any one of claims 1 to 8, or using the signal transfer fixture system for a chip reliability test system according to any one of claims 9 to 13, characterized in that: include: The chip to be tested is coupled to the furnace board, the furnace board is coupled to the daughter board of the signal transfer fixture, and a signal connection between the signal transfer fixture and the host is established; Placing the furnace plate coupled with the chip to be tested in a test furnace for providing a test environment; Sending a screen-pointing signal to the signal transfer fixture through the host; The signal transfer fixture performs signal noise reduction processing or signal conversion processing on one path of the point screen signal and divides it into multiple paths of sub-point screen signals; The multiple sub-point screen signals are respectively sent to the corresponding chips to be tested through the corresponding furnace boards to perform reliability testing.

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