Apparatus and method for OS-CFAR detection, and radar system

Abstract

The invention relates to an apparatus and a method for OS-CFAR detection, and a radar system. An apparatus for OS-CFAR detection is provided. The apparatus includes a memory circuit including a plurality of memory segments, where the memory circuit is configured to store address data indicative of addresses of data elements of radar data at further memory circuits, and a control circuit configured to control the memory segments to store address data indicative of addresses of the data elements of the radar data at the further memory circuits. The control circuit is configured to execute a sorting algorithm for OS-CFAR detection using the following steps: comparing a new data element of radar data with at least one data element indicated by address data stored in the storage circuit, determining a storage segment of a plurality of storage segments based on the comparison, the address data of the new data element is to be stored at the storage segment, and controlling the storage circuit to shift the address data stored at the determined storage segment to other storage segments.

Description

Technical Field

[0001] The present disclosure relates to ranking OS-CFAR (Ordered Statistical Constant False Alarm Rate).Examples relate to devices for OS-CFAR detection, radar systems, and methods for OS-CFAR detection. Background Art

[0002] Traditionally, ranking algorithms used for OS-CFAR techniques require memory and computationally intensive processing. Such memory and computational requirements pose challenges, especially in real-time or resource-constrained scenarios. Therefore, improved ranking for OS-CFAR detection is needed. Summary of the invention

[0003] This need is met by the independent claim. Further advantageous embodiments are given by the dependent claims.

[0004] Some aspects of the present disclosure relate to an apparatus for OS-CFAR detection, comprising a storage circuit including a plurality of storage segments, wherein the storage circuit is configured to store address data indicating addresses of data elements of radar data at another storage circuit, and a control circuit configured to perform a sorting algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by the address data stored in the storage circuit, determining one storage segment of the plurality of storage segments based on the comparison, at which the address data of the new data element is to be stored, and controlling the storage circuit to shift the address data stored at the determined storage segment to other storage segments.

[0005] Some aspects of the present disclosure relate to radar systems including an apparatus as described herein and a radar sensor configured to generate radar data.

[0006] Some aspects of the present disclosure relate to a method for OS-CFAR detection, including storing address data indicating addresses of data elements of radar data at another storage circuit at a storage circuit including multiple storage segments, and executing a sorting algorithm for OS-CFAR detection by a control circuit using the following steps: comparing a new data element of the radar data with at least one data element indicated by the address data stored in the storage circuit, determining one storage segment of the multiple storage segments based on the comparison, where the address data of the new data element is to be stored, and controlling the storage circuit to shift the address data stored at the determined storage segment to other storage segments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some examples of apparatus and / or methods will be described below, by way of example only, and with reference to the accompanying drawings, in which:

[0008] Figure 1 An example of a device for OS-CFAR detection is shown;

[0009] Figure 2a to Figure 2d An example of a ranking algorithm for OS-CFAR detection is shown;

[0010] Figure 3 An example of removing address data from a storage circuit is shown;

[0011] Figure 4a and Figure 4b An example of a shift register is shown;

[0012] Figure 5 An example of OS-CFAR detection is shown;

[0013] Figure 6 An example of a radar system is shown; and

[0014] Figure 7 An example of a method for OS-CFAR detection is shown. DETAILED DESCRIPTION

[0015] Some examples are now described in more detail with reference to the accompanying drawings. However, other possible examples are not limited to the features of these embodiments described in detail. Other examples may include modifications of features and equivalents and alternatives of features. In addition, the terms used to describe some examples in this article should not limit other possible examples.

[0016] Throughout the description of the drawings, the same or similar reference numerals represent the same or similar elements and / or features, which may be implemented in the same or modified form while providing the same or similar functions. For clarity, the thickness of the lines, layers and / or regions in the drawings may also be exaggerated.

[0017] When two elements A and B are combined using "or", this should be understood to disclose all possible combinations, i.e. only A, only B and A and B, unless explicitly defined otherwise in individual cases. As alternative wording for the same combination, "at least one of A and B" or "A and / or B" can be used. The same applies to combinations of more than two elements.

[0018] If singular forms such as "a", "an", and "the" are used, and the use of only a single element is not explicitly or implicitly defined as mandatory, other examples may also use several elements to achieve the same function. If the function is described below as being implemented using multiple elements, other examples may use a single element or a single processing entity to achieve the same function. It should also be understood that the terms "comprises", "comprising", "includes", and / or "includes" when used describe the presence of specified features, wholes, steps, operations, processes, elements, parts, and / or groups thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, processes, elements, parts, and / or groups thereof.

[0019] Figure 1 An example of an apparatus 100 for OS-CFAR detection is shown. OS-CFAR detection is a technique for adaptive thresholding for signal processing of radar data, for example to detect or track targets in the presence of clutter or noise.

[0020] The device 100 includes a memory circuit 110 and a control circuit 120. The control circuit 120 is coupled to the memory circuit 110 for controlling the memory circuit, as further described below.

[0021] The device 100 may be partially or fully integrated into a radar sensor. Alternatively, the device 100 may be outside the radar sensor. The (raw) radar data acquired by the radar sensor or the radar data obtained therefrom (e.g. by preprocessing the raw radar data) may be stored in a further storage circuit 130, for example via direct memory access. The further storage circuit 130 may be outside the storage circuit 110 and optionally outside the device 100. The radar data may, for example, indicate an IF (intermediate frequency) signal of the radar sensor or a preprocessed version thereof (e.g. a noise-reduced, DC (direct current) removed version thereof). The radar sensor may acquire radar data by mixing the reflection of the transmitted signal with a local oscillator signal of a specific frequency.

[0022] The device 100 can be coupled to the further storage circuit 130 so that it at least partially has access, for example, read access and optionally write access, to the further storage circuit 130. Thus, the device 100 can at least partially retrieve the radar data stored therein. The device 100 can, for example, directly retrieve the data via an interface circuit or, if the device 100 includes the further storage circuit 130.

[0023] The storage circuit 110 may be any device for storing data, such as a random access memory, a cache, etc. In some examples, the storage circuit 110 may include or may be a parallel shift register, as further explained below. The storage circuit 110 may also be implemented as a buffer memory, i.e. it may temporarily store (address) data while the sorting algorithm for OS-CFAR detection is executed by the control circuit 120. Since the OS-CFAR algorithm may require a subset of the radar data to be sorted or re-ordered, the use of a buffer memory may ensure that the original radar data stored at the further storage circuit 130 may remain unchanged, i.e. in its original order. In addition, the buffer implementation of the storage circuit 110 may offload external processing circuits for further processing of the radar data.

[0024] The storage circuit 110 includes a plurality of storage (or memory) segments 111 to 113 . Figure 1 Three storage segments 111 to 113 are shown for exemplary purposes only. In other examples, the storage circuit 110 may include any number of storage segments, such as any number n ≥ 2. Figure 1 The boxes shown indicating the storage segments 111 to 113 should be understood as an abstract representation of the storage segments 111 to 113: Figure 1 The form, size or arrangement of the storage segments 111 to 113 shown is for exemplary purposes. For example, the storage circuit 110 may present a linear, array or three-dimensional arrangement of storage segments.

[0025] Storage segments 111 to 113 may include (or may be) at least one corresponding memory cell or physical bit. Storage segments 111 to 113 may refer to different structures, sizes, or portions of memory aligned with a specific type or size of data to be stored in the memory. Storage segments 111 to 113 may indicate the order of data stored therein, such as causing storage segment 111 to store a first portion of data, storage segment 112 to store a second portion of data after the first portion, and storage segment 113 to store a third portion of data after the second portion.

[0026] The storage circuit 110 is configured to store (at the storage segments 111 to 113) address data indicating the address of a data element of the radar data at the further storage circuit 130. The data element may refer to a sample of the radar data or a value (e.g., a distance) derived from the radar data. For example, the data element may be a subset of (e.g., modified) samples of the radar data, such as a subset of samples selected within one chirp of the radar data. The data elements may be selected according to the OS-CFAR algorithm. For example, as further explained below, the data elements may be selected by windowing.

[0027] The address data may indicate an address so that the address data may be mapped to the address of a data element, for example, based on a specific scheme. The address data may, for example, indicate a unique identifier (or index, pointer, etc.) assigned to a corresponding storage location in another storage circuit. The address data may, for example, indicate a logical address that can be converted into a physical address of another storage circuit 130. In some examples, the address data may indicate a relative address of a data element, that is, the address data may indicate a position at another storage circuit relative to a predetermined position, for example, relative to a (starting) address of a specific data element within a data set (or window) to be sorted. For example, the address data may be determined by numbering or indexing these data elements. The number or index assigned to the data element may correspond to their order in the data sequence of the radar data. This may limit the length of the address data to the number of data elements stored for OS-CFAR processing.

[0028] Performing a sorting algorithm, such as arranging values ​​(data elements) in order of magnitude, may be the most computationally and memory-intensive part of OS-CFAR in many applications. Conventional OS-CFAR buffers may require as much memory as the raw radar data. This means that, conventionally, the minimum size of the memory may be equal to the size of the data element itself. In contrast, the storage circuit 110 may require a smaller minimum size because it does not have to store the data element itself, but rather stores an index (e.g., as an integer) representing the data position (address) within a window of radar data, for example. Therefore, the device 100 can achieve a reduction in memory size or storage capacity requirements. In a specific application, the data elements each have a size of 24 bits, while their pointers each have a size of only 4 bits. The device 100 can therefore implement index sorting, which may only require minimal logic added in the addressing path. The device 100 can also achieve a reduced memory area, which leads to reduced resources and power consumption.

[0029] The control circuit 120 may be, for example, a single dedicated processor, a single shared processor, or multiple individual processors (some or all of which may be shared), a digital signal processor (DSP) hardware, an application specific integrated circuit (ASIC), a microcontroller, or a field programmable gate array (FPGA). The control circuit 120 may, for example, be optionally coupled to a read-only memory (ROM), a random access memory (RAM), and / or a non-volatile memory for storing software.

[0030] The control circuit 120 is configured to execute a sorting algorithm for OS-CFAR detection. The purpose of the sorting algorithm is to bring the address data into a specific order for OS-CFAR detection. The choice of the sorting algorithm may depend on the target application, for example, on the size or characteristics of the address data, the number of ordered statistics required, the performance requirements of OS-CFAR detection, etc. The control circuit 120 may execute any sorting algorithm, such as at least one of a merge sort, a quick sort, a heap sort, a selection sort, etc. In some examples, the control circuit 120 is configured to execute an insertion sort for OS-CFAR detection. Insertion sort may be a comparison-based sorting algorithm that may iteratively construct the final sorted address data one element at a time. Insertion sort may improve sorting efficiency, especially for small-sized data such as the address data used herein.

[0031] In some examples, the execution of the sorting algorithm may require preprocessing of the data elements. The preprocessing may be performed by a processing circuit external to the control circuit 120 or by the control circuit 120 itself. In the latter case, the control circuit 120 may be configured to determine the data elements, such as to render the data elements in a data format required for OS-CFAR detection. For example, the control circuit 120 may determine a range representation of radar data indicating the distance of a potential target within the field of view of the radar sensor. The control circuit 120 may, for example, perform a Fourier transform (e.g., a fast Fourier transform) on the radar data along a fast time to generate a range representation. The data elements may be selected from the range representation.

[0032] In some examples, the radar data may be initially provided in a Cartesian format having a real part and an imaginary part. In such a case, the control circuit 120 may be further configured to determine the data elements by converting the radar data into a polar coordinate representation having an amplitude and an angle. For example, the data may be converted to a polar coordinate format by applying Pythagorean addition to the real and imaginary parts. The data elements may be selected so that these data elements are or indicate the amplitude of the polar coordinate representation of the radar data.

[0033] These magnitudes may be represented as integer values, which in a specific example may have a length of 24 bits. In a Cartesian format, a data instance of radar data may have a length of 48 bits. However, the storage circuit 110 may store relative indices of these data instances or values, rather than the magnitudes or real and imaginary parts themselves. Depending on the maximum size N of the subset (array) of radar data to be sorted, the length of the index may be W according to Equation 1:

[0034] W = ceil(log2 N)

[0035] Equation 1

[0036] For amplitude values, the integer width W int For 24 bits, the number of bits B required is reduced according to equation 2:

[0037] B=ceil(log2 N) / W int =ceil(log2 16) / 24≈17%

[0038] Equation 2

[0039] In case the control circuit 120 performs pre-processing of the radar data, the device 100 may have an additional advantage: since access to the raw memory (further storage circuit 130) is anyway required for the pre-processing, e.g. for the conversion from a Cartesian format (IQ format or real and imaginary parts) to a polar format (amplitude and angle), the control circuit 120 may use this access to perform a sorting algorithm, as described below.

[0040] The control circuit 120 is configured to perform a sorting algorithm using the following steps: compare the new data element of the radar data with at least one (e.g., different) data element indicated by the address data stored in the storage circuit 110, determine one of the plurality of storage segments 111 to 113 based on the comparison, where the address data of the new data element is to be stored, and control the storage circuit 110 to shift the address data stored at the determined storage segment to other storage segments. That is, the comparison is performed on the data elements, and at the same time, the sorting is performed on their address data.

[0041] For example, there may be a plurality of data elements, such as a plurality of data elements of a window of radar data, whose addresses may be stored in a sorted manner at the storage circuit 110. For example, the control circuit 120 may be configured to select a window of radar data comprising a plurality of data elements, for example, some of which are in front of the measured data element and other data elements are behind the measured data element. The control circuit 120 may be configured to execute a sorting algorithm for the selected window. The control circuit 120 may, for example, select a new data element from the plurality of data elements in a predefined manner. For example, the control circuit 120 may view the data elements in the plurality of data elements one by one in a predefined order of the data elements at the further storage circuit 130. The control circuit 120 may then index or number the new data element, for example, according to the relative position of the new data element at the further storage circuit 130.

[0042] The comparison may be performed based on any predefined comparison criteria. For example, the comparison criteria may define a mathematical relationship between the new data element and an already processed data element (thus having address data already stored at storage circuit 110), which mathematical relationship must be true to satisfy the predefined comparison criteria. For example, control circuit 120 may perform the comparison by determining whether the new data element has a (distance) value that is smaller (or larger) than the value of the already processed data element, such as a predefined value. If so, the comparison criteria is determined to be satisfied.

[0043] Satisfaction of the comparison criteria may indicate the location of the address data in the storage segments 111 to 113 where the new data element is to be inserted. For example, if the control circuit 120 determines that the storage segment indicates that the data element satisfies the comparison criteria, the storage segment or an adjacent storage segment may be determined as the location where the new data element is to be stored.

[0044] The comparison may also be performed along the data elements that have been processed until the comparison criteria are met. Thus, the new data element may be compared to the existing list of sorted elements step by step. For example, if one data element does not meet the comparison criteria, the control circuit 120 may select another data element that has been processed and perform the comparison again. For example, the control circuit 120 may be configured to continuously select storage segments in ascending or descending order, and compare the corresponding data element indicated by the address data stored at the selected storage segment with the new data element until the comparison meets the predefined comparison criteria.

[0045] Shifting address data may include storing the address data at another storage segment (different from the determined storage segment) and optionally deleting the address data from the determined storage segment. The other storage segment may be a predefined storage segment in a plurality of storage segments 111 to 113, for example, a storage segment predefined relative to the determined storage segment, such as a storage segment behind or in front of the determined storage segment. In some examples, the control circuit 120 is also configured to control the storage circuit 110 to shift all address data stored in the storage segment in front of or behind the determined storage segment by a predefined number of storage segments, for example, by one, two or more storage segments. For example, the storage circuit 110 may push all address data at the determined storage segment and / or behind / in front of the determined storage segment to the side. For example, an element that has not yet been compared may have its address data moved further toward the end of the storage circuit 110.

[0046] In order to insert the new data element into the correct position, in some examples, the control circuit 120 may also be configured to control the storage circuit 110 to store the address data of the new data element at the determined storage segment.

[0047] Figure 2a to Figure 2d A specific example of how to perform the sorting algorithm is shown. Figure 2a to Figure 2d The first step, the second step, the third step, and the fourth step of the example of the sorting algorithm 200 are shown respectively. Figure 2a to Figure 2d In the example of , the sorting algorithm 200 is an insertion sort. The sorting algorithm 200 can be executed by a device for OS-CFAR detection as described herein, for example, by the device 100.

[0048] A control circuit, for example control circuit 120, may be configured to sort data elements 210 of the radar data stored in further storage circuit 130. Figure 2a , data elements 210 are shown in their original, unordered state, including a first data element 211 having a value of 4, a second data element 212 having a value of 8, a third data element 213 having a value of 3, and a fourth data element 214 having a value of 5.

[0049] The data elements 210 are indexed according to their position at the further storage circuit. The first data element 211 has an index of 1, the second data element 212 has an index of 2, the third data element 213 has an index of 3, and the fourth data element 214 has an index of 4.

[0050] exist Figure 2a In the first step (step 0) shown, the control circuit 120 selects the first data element 211 as a new data element and compares the new data element with at least one data element indicated by address data stored in the storage circuit 220. The storage circuit 220 may be an example of an implementation of the storage circuit 110. The storage circuit 220 includes a plurality of storage segments in a specific order: a first storage segment 221, a second storage segment 222 following the first storage segment 221, a third storage segment 223 following the second storage segment 222, and a fourth storage segment 224 following the third storage segment 223. In the first step, the storage circuit 220 has not yet been filled with any address data (e.g., Figure 2a to Figure 2d An initial ordering may be shown.) Therefore, the control circuit 120 controls the storage circuit 220 to store the address data (index 1) of the new data element at the first storage segment 221 .

[0051] exist Figure 2b In the second step (step 1) shown, the control circuit 120 selects the second data element 212 (8) as a new data element and compares the new data element with at least one data element indicated by the address data stored in the storage circuit 220. The control circuit 120 selects the first storage segment 221 and compares the first data element 211 indicated by the address data stored at the selected first storage segment 221 with the new data element.

[0052] The control circuit 120 then determines a storage segment of the plurality of storage segments 221 to 224 that will store the address data (index 2) of the new data element based on the comparison. For example, in response to determining that the comparison satisfies a predefined comparison criterion, the control circuit 120 may determine a desired storage segment for the address data of the new data element. Figure 2a to Figure 2d An example predefined comparison criterion may be “the currently checked data element (the data element indicated by the address data stored at the currently selected storage segment) is greater than the new data element.” Since 4 (the first data element 211) is not greater than 8 (the new data element), the predefined comparison criterion is not met.

[0053] Since the subsequent storage segments 222 to 224 are empty, the (next) second storage segment 222 is determined as the desired storage segment for the address data of the new data element. The control circuit 120 controls the storage circuit 220 to store the address data at the determined second storage segment 222 .

[0054] exist Figure 2c In the third step (step 2) shown, the control circuit 120 selects the third data element 213 (3) as the new data element and compares the new data element with at least one data element indicated by the address data stored in the storage circuit 220. The control circuit 120 selects the first storage segment 221 and compares the first data element 211 indicated by the address data stored at the selected first storage segment 221 with the new data element. Since 4 (the first data element 211) is greater than 3 (the new data element), the predefined comparison criterion is satisfied.

[0055] The control circuit 120 determines the first storage segment 221 to store the address data (index 3) of the new data element because it is the storage segment that has satisfied the comparison. Then, the control circuit 120 controls the storage circuit 220 to shift the address data stored at the determined first storage segment 221 to the other storage segments, to the storage segment 222. The control circuit 120 controls the storage circuit 220 to shift all the address data stored in the storage segments after the determined first storage segment 221 by one storage segment. Therefore, the index 2 previously stored at the second storage segment 222 is shifted to the storage segment 223. Then, the control circuit 120 controls the storage circuit 220 to store the address data of the new data element at the determined first storage segment 221.

[0056] exist Figure 2dIn the fourth step (step 3) shown, the control circuit 120 selects the fourth data element 214 (5) as the new data element and compares the new data element with at least one data element indicated by the address data stored in the storage circuit 220. The control circuit 120 selects the first storage segment 221 and compares the third data element 213 indicated by the address data stored at the selected first storage segment 221 with the new data element. Since 3 (the third data element 213) is not greater than 5 (the new data element), the predefined comparison criterion is not satisfied.

[0057] The control circuit 120 selects the storage segments 221 to 224 successively in ascending order, and compares the corresponding data element indicated by the address data stored at the selected storage segment with the new data element until the comparison satisfies the predefined comparison criterion. Then, the control circuit selects the second storage segment 222 and compares the first data element 211 indicated by the address data stored at the selected second storage segment 222 with the new data element. Since 4 (the first data element 211) is not greater than 5 (the new data element), the predefined comparison criterion is not satisfied. Then, the control circuit selects the third storage segment 223 and compares the second data element 212 indicated by the address data stored at the selected third storage segment 223 with the new data element. Since 8 (the second data element 212) is greater than 5 (the new data element), the predefined comparison criterion is satisfied.

[0058] The control circuit 120 determines the first storage segment 221 to store the address data (index 3) of the new data element because it is the storage segment that has satisfied the comparison. Then, the control circuit 120 controls the storage circuit 220 to shift the address data stored at the determined first storage segment 221 to other storage segments, to the storage segment 222. The control circuit 120 controls the storage circuit 220 to shift all the address data stored in the storage segments after the determined first storage segment 221 by one storage segment. Therefore, the index 2 previously stored at the second storage segment 222 is shifted to the storage segment 223. Then, the control circuit 120 controls the storage circuit to store the address data of the new data element at the determined first storage segment 221.

[0059] The control circuit 120 determines the third storage segment 223 to store the address data (index 4) of the new data element because it is the storage segment that has satisfied the comparison. The control circuit 120 then controls the storage circuit 220 to shift the address data stored at the determined first storage segment 221 to the other (next or later) storage segment, to the storage segment 224. Then, the control circuit 120 controls the storage circuit 220 to store the address data of the new data element at the determined third storage segment 223.

[0060] Return to reference Figure 1 , the device 100 can additionally provide improved changes between windows or subsets of radar data. For example, the sorting algorithm can be repeatedly performed on a sliding window of radar data. It should be noted that the window does not necessarily include continuous data points of the radar data. For example, the window can include two separate arrays of continuous data elements.

[0061] When the sorting algorithm is completed for the currently selected data element, the window may be shifted by a predefined number of data elements along the radar data. The control circuit 120 may, for example, be further configured to execute the sorting algorithm for a first window of data elements of the radar data. After the sorting algorithm for the first window is executed (completed, i.e., all data elements of the first window are sorted), the control circuit 120 may select a second window of data elements of the radar data and execute the sorting algorithm for the second window.

[0062] In some examples, the control circuit 120 can perform a sorting algorithm for the second window by only partially removing the address data stored in the storage circuit 110 during the execution of the sorting algorithm for the first window. That is, instead of resetting the storage circuit 110 to sort the next window, a portion of the pre-sorted address data is retained. For example, a portion of the data elements of the first window and the second window are common, such as when the sliding of the window from the first position (of the first window) to the second position (of the second window) does not skip all data elements from the first window. The storage circuit 110 can at least partially retain the address data of the data elements that the first and second windows have in common, while the address data of the non-common data elements can be deleted. For example, the control circuit 120 can trigger the removal of the address data indicating the lowest index, or trigger the removal of the address data inserted into the storage circuit 110 the longest time ago among all the address data stored in the storage circuit 110. By retaining at least a portion of the address data, the second window has been pre-sorted, and only the newly entered data elements must be sorted. Therefore, the device 100 can reduce the amount of calculations used to perform the sorting algorithm.

[0063] The control circuit 120 may also be configured to remove only partially the address data by controlling the storage circuit 110 to shift the address data to be retained in the storage circuit 110 during the execution of the sorting algorithm for the second window to at least one storage segment storing the address data to be removed. For example, the (partial) removal of address data when changing the window may generally leave gaps between the portions of the address data stored in the storage circuit 110. For example, if the address data at the storage segment 112 is removed, an empty memory space is left between the storage segments 111 and 113. Conversely, the device 100 may perform the removal by overwriting the address data to be deleted with the address data to be retained.

[0064] For example, the control circuit 120 can control the storage circuit 110 to pull the address data to be retained in the previous or subsequent storage segment into the storage segment to be emptied. The continuous address data sequence to be retained (or all the address data before or after the address data to be removed) can be collectively shifted by a predefined number of storage segments to overwrite the address data to be removed. The control circuit 120 can, for example, rearrange the remaining address data into a continuous data sequence within the storage segments 111 to 113. The device 100 can therefore improve the pre-ordering of the second window.

[0065] The partial removal of address data can further reduce the number of insertion operations. For example, the control circuit 120 can be further configured to perform the sorting algorithm for the second window by controlling the storage circuit 110 to exclusively insert address data of data elements of the second window that have not been inserted during the execution of the sorting algorithm for the first window. That is, only data elements that are not common to the first and second windows can have their address data inserted during the execution of the sorting algorithm for the second window.

[0066] Figure 3 An example of how to control the storage circuit 310 to change the window is shown. Figure 3 An example of data removal 300 during window change is shown. Storage circuit 310 includes storage segments 311, 312, 313 and 314 filled with address data 3, 1, 4 and 2, respectively. During window change, the oldest address data, i.e., indicating the lowest index (in Figure 3 In the example of 1), the address data is to be deleted. The control circuit as described herein, for example, the control circuit 120, can perform the deletion by shifting the address data to be retained in the storage circuit 310 to the storage segment 312 storing the address data to be deleted. Figure 3 In the example of , the control circuit 120 may shift each of the indexes 4 and 2 to the left by one memory segment. The resulting memory segments 311 to 313 store address data 3, 4, and 2, respectively, while the memory segment 314 is empty.

[0067] Return to reference Figure 1 , the device 100 can additionally improve the sorting algorithm in hardware. In some examples, the storage circuit 110 may include a parallel shift register that couples multiple storage segments in cascade. The parallel shift register can be a digital circuit that includes a group of corresponding storage segments operating in parallel, and the group is connected as a cascade. The above-mentioned storage segments can be a group of parallel shift registers. The cascade can define the order of the storage segments. The number of parallel storage segments can, for example, be selected to be greater than or equal to the bit length of a portion of address data to be stored at a storage segment. The portion of the address data can indicate a data element of the radar data.

[0068] The storage segments 111 , 112 , 113 may be or include at least one of a flip-flop, a latch, a transmission gate, and the like.

[0069] The parallel storage segments of a group can be controlled simultaneously so that data can be loaded into the group in parallel, wherein each bit of the data enters its corresponding storage segment. Likewise, when a trigger is applied, the bits stored in the storage segments of a group can be shifted or transferred in parallel from one group to another. The main operation of such a parallel shift register can be to shift the stored (address) data by one or more groups (a predefined number of storage segments) in a specific direction (left or right). This operation can be achieved by a clock signal that synchronizes the shifting of the address data between the affected storage segments.

[0070] In many sorting algorithms, multiple elements must be moved toward the end of the buffer. This may require many read / write transactions on conventional memory, for example, when using memory macros. Since the storage circuit 110 of the device 100 can be implemented as a scannable register (standard (STD) logic) array, the address data stored therein can be shifted more easily. Therefore, the use of parallel shift registers can simplify the shift operation. In addition, the shift register can reduce the space required to implement the storage circuit 110. Therefore, the sort buffer can be kept small while still maintaining full sorting capabilities.

[0071] In a specific embodiment of the parallel shift register 110, nm (nanometer) size integration of scannable storage segments with asynchronous reset can be achieved. One storage segment may require a unit area of ​​8.7GE (gate equivalent) NAND-2 gates (NAND gates with two input nodes). Assuming that the radar sensor has three receiving channels, the length of a portion of the address data is 4 bits and the window length is 16 data elements, the shift register 110 can occupy a unit area of ​​approximately 3×4×16×8.7GE=1.67kGE (kilogate equivalent).

[0072] Figure 4a and Figure 4b Two examples of parallel shift registers 400 are shown. The shift register 400 includes a plurality of groups (storage segments) 421, 422, 423 coupled in cascade. Each group includes at least two flip-flops operating in parallel. Figure 4a and Figure 4b In the example of FIG. 4 , three groups 421 , 422 , 423 are shown. However, in other examples, the shift register 400 may include any number k≧2 of groups.

[0073] The groups 421, 422, 423 are coupled to respective output nodes 431, 432, 433, each of which connects the output of one group to the input node of the following group, thereby forming a cascade. Thus, the groups 421, 422, 423 are connected in series or sequentially.

[0074] The shift register 400 includes a plurality of multiplexers (MUX) 441, 442, 443, each of which is connected to the input of a corresponding one of the groups 421, 422, 423. Therefore, each group can be coupled to a corresponding multiplexer in the plurality of multiplexers 441, 442, 443. Each of the multiplexers 441, 442, 443 can be a digital electronic device or circuit for selecting a plurality of input signals based on a control signal generated by a control circuit (e.g., control circuit 120) as described herein and routing the plurality of input signals to a single output line connected to a corresponding group in the plurality of groups 421, 422, 423. Therefore, the function of the multiplexers 441, 442, 443 can be to select input signals from a plurality of input nodes and pass the selected input signals as outputs. The selection can be determined by a control signal provided to the multiplexer. For example, the control signal can be provided via a control line (not shown). The control signal may, for example, be in the form of a binary coded signal, where each unique combination represents a particular input selection.

[0075] The shift register 400 includes two input nodes for each of the multiplexers 441, 442, 443: a first input node 451 and a second input node 452. The first input node 451 is coupled to the corresponding output node 431, 432, 433 of the previous group (or flip-flop) in the cascade. The second input node 452 is coupled to the data input carrying the address data. Therefore, the control circuit 120 can control one or more of the multiplexers 441, 442, 443 to select the corresponding first input node 451 for shifting (pushing) the address data from one group to the next group. In addition, the control circuit 120 can control one or more of the multiplexers 441, 442, 443 to select the corresponding second input node 452 for inserting, for example, the address data of the new data element.

[0076] exist Figure 4b In the embodiment of the present invention, the shift register 400 also includes a third input node 453 for each multiplexer in the multiplexers 441, 442, 443. The third input node 453 is coupled to the corresponding output nodes 431, 432, 433 of the subsequent groups (or triggers) in the cascade. Therefore, the control circuit 120 can control one or more multiplexers in the multiplexers 441, 442, 443 to select the corresponding third input node 453 for shifting the address data from one group back to the previous group. Therefore, the shift register 400 can shift the address data in both directions to the previous or subsequent triggers in the cascade together with the first input node. This can further help to utilize the fact of the moving window: the shift register 400 can have a third input node 453 to expand the functionality of the shift register 400 using the "pull" option, which, as described above, simplifies the removal of address data when changing the window. This can enable the subsequent sorting to reuse the pre-sorted address data of the previous window.

[0077] In other examples, the configuration of the shift register 400 can be similar to Figure 4a and Figure 4b . For example, the first input node 451 can be coupled to the corresponding output nodes 431, 432, 433 of the subsequent group in the cascade or to the corresponding output nodes 431, 432, 433 of any other group, for example, the group is more than one group on the left (front) or right (back) in the cascade. In other examples, the shift register 400 can have more than two input nodes for additional functions. The shift register 400 can also include asynchronous and / or synchronous input nodes. In addition, the shift register 400 is not limited to the following. Figure 4a and Figure 4bThe DQ logic shown in: In other examples, the shift register 400 may have a negated input or output, or any additional logic circuit. In addition, the shift register 400 may alternatively be implemented using a storage technology different from a flip-flop, such as a latch or the like.

[0078] Return to reference Figure 1 , the device 100 may further perform OS-CFAR detection itself, while alternatively, OS-CFAR detection may be performed by external processing circuitry. In some examples, the control circuit 120 is further configured to select a data element indicated by address data stored at a predefined storage segment in the plurality of storage segments after executing the sorting algorithm. The predefined storage segments may be defined to implement certain statistical analysis of OS-CFAR detection. Since the sorted address data is arranged, for example, according to the amplitude indication of the data element, the predefined k-th position in the order of the storage segments 111, 112, 113 may correspond to the k-th highest or smallest amplitude in the data element. k may be selected based on the target application, for example to balance sensitivity to weak targets and increase robustness to clutter and noise.

[0079] Assuming that the data element represents the signal environment of the data element under test, such as the left and right arrays of the data element under test, OS-CFAR detection can be performed by determining whether the data element under test is sufficiently prominent or distinguishable from its signal environment, and thus by applying adaptive threshold processing. For example, the control circuit 120 can be configured to compare the selected data element with the data element under test, and determine the presence of the target and / or the movement of the target based on the comparison.

[0080] An optional intermediate process may be that the control circuit 120 is further configured to apply a predefined gain to the selected data element and compare the selected data element with the gain applied to the data element under test. That is, the data element under test may need to be differentiated relative to the selected data element by a certain level defined by the gain.

[0081] Figure 5 An example of a process flow for OS-CFAR detection 500 is shown. OS-CFAR detection 500 may be performed by a device described herein, such as device 100. OS-CFAR detection 500 includes selecting 510 a window of radar data by a control circuit. The window includes a plurality of data elements 511 (background signals) preceding and following a data element under test 512 (unit under test, CUT). OS-CFAR detection 500 also includes executing 520 a sorting algorithm for the selected window by the control circuit. The sorting algorithm may be performed by buffering address data of the data elements 511 in a storage circuit and sorting the address data, as described above with reference to Figure 1 As explained.

[0082] The OS-CFAR detection 500 also includes, after executing the sorting algorithm, selecting 530 by a selector k a data element indicated by address data at a predefined storage segment of the storage circuit, and applying 540 a predefined gain to the selected data element by a multiplier. The OS-CFAR detection 500 also includes comparing 550 the selected data element with the gain applied to the measured data element 512 by a comparator, and determining 560 the presence of a target and / or the movement of a target based on the comparison. For example, N (e.g., 4) values ​​can be arranged in order of magnitude by a sorting algorithm. The minimum magnitude can appear at output tab 0 and the maximum magnitude appears at output tab N-1. The selector k can select one of these outputs, and then scale the output by a configurable gain (g). The scaled output can then be compared with the unit under test, and the comparator can create a binary decision of whether the target is detected.

[0083] Return to reference Figure 1 , the device 100 can achieve a further increase in the efficiency of external processing circuits for processing radar data. Further processing can include sophisticated radar data analysis, such as determining at least one of the distance, angle, and speed of the target. For example, the control circuit 120 can be configured to send an interrupt to the processing circuit to trigger further processing of the radar data in response to determining the presence of the target and / or the movement of the target. By limiting the further processing to the relevant radar data indicating the target, the processing circuit, such as the main processor, can be unloaded. The device 100 can therefore improve the computational and resource efficiency of the further processing of the radar data.

[0084] In general, the device 100 can optionally provide (e.g., embedded) index sorting using hardware acceleration using shift registers. Index sorting can be based on element-by-element comparison and insertion of new address data in a determined location (storage segment). When a new data element is to be sorted, each data element indicated by the address data stored in the storage circuit 110 can be read, for example, in ascending order until the new data element fits the sorting (comparison) criteria. Instead of retaining the value of the data element in the sorted list, the address (pointer) of the value is retained. The address width can be reduced to a minimum value, which can be defined by the maximum window length of the CFAR (e.g., 4 bits for a 16-sample window width). Therefore, the device 100 can save the memory area required for the sorting algorithm.

[0085] Figure 6An example of a radar system 600 is shown. Radar system 600 includes a device 610 as described herein, such as device 100, and a radar sensor 620 configured to generate radar data. Radar sensor 620 may be, for example, a FMCW (Frequency Modulated Continuous Wave) radar sensor.

[0086] Although the device 610 and the radar sensor 620 are Figure 6 610 is depicted as a separate block, but in other examples, device 610 may be partially or entirely included in radar sensor 620, which accordingly includes all or part of the control circuitry and storage circuitry of device 610. Therefore, radar sensor 620 may include device 610.

[0087] In the case where the device 610 is only partially included in the radar sensor 620, the radar system 600 can perform distributed processing, for example in the form of a first control (sub)circuit included in the radar sensor 620 and a second control (sub)circuit outside the radar sensor and communicating with the first control circuit via an interface circuit, which distributed processing performs corresponding parts of the processing steps.

[0088] In the case where device 610 is integrated in radar sensor 620 , control circuit and radar sensor 620 may be integrated (embedded) together in a single semiconductor chip, or in more than one semiconductor chip.

[0089] Where device 610 is not included in radar sensor 620 , control circuitry may take the form of circuitry external to radar sensor 620 and may be communicatively coupled thereto via interface circuitry.

[0090] Optionally, radar system 600 can implement parallel processing in a multi-antenna environment. For example, radar sensor 620 may include a first antenna configured to receive a first signal from a field of view of radar sensor 620. Radar sensor 620 is configured to generate radar data based on the first signal. Radar sensor 620 may include at least one second antenna configured to receive at least one second signal from a field of view of radar sensor 620. Radar sensor 620 is configured to generate second radar data based on the second signal. Radar system 600 may include at least one second device as described herein, such as device 100, which is configured to process the second radar data. Radar system 600 may benefit from index sorting because saving memory area may be even more relevant for a multi-antenna system with parallel processing.

[0091] Radar system 600 may also include processing circuitry external to radar sensor 620. The processing circuitry is configured to perform further processing of the radar data in response to receiving an interrupt from device 610. In some examples, radar system 600 also includes additional storage circuitry.

[0092] In combination with the proposed technology or for example reference Figure 1 The one or more examples described above are used to explain more details and aspects of the radar system 600. The radar system 600 may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples described above.

[0093] Radar system 600 may optionally utilize hardware acceleration using shift registers to provide (eg, embedded) index sorting. Device 610 may save memory area in radar system 600 required for sorting algorithms.

[0094] Figure 7 An example of a method 700 for OS-CFAR detection is shown. The method 700 may be performed by an apparatus for OS-CFAR detection as described herein, such as the apparatus 100. The method 700 includes storing 710 address data at a storage circuit including a plurality of storage segments, the address data indicating an address of a data element of radar data at a further storage circuit.

[0095] The method 700 also includes executing, by the control circuit, a sorting algorithm for OS-CFAR detection using the following steps: comparing 720 a new data element of the radar data with at least one data element indicated by address data stored in a storage circuit, determining 730 one of a plurality of storage segments based on the comparison at which the address data of the new data element is to be stored, and controlling 740 the storage circuit to shift the address data stored at the determined storage segment to other storage segments.

[0096] The method 700 may optionally utilize hardware acceleration using shift registers to provide (eg, embedded) index sorting. The method 700 may save memory area and computational resources required for the sorting algorithm.

[0097] The aspects and features described with respect to a specific one of the previous examples may also be combined with one or more of the other examples to replace the same or similar features of the other example or to additionally introduce features into the other example.

[0098] Some examples of the proposed technique are presented below:

[0099] Examples (e.g., Example 1) relate to an apparatus for OS-CFAR detection, comprising a storage circuit having a plurality of storage segments, wherein the storage circuit is configured to store address data indicating addresses of data elements of radar data at another storage circuit, and a control circuit configured to perform a sorting algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by the address data stored in the storage circuit, determining one storage segment of the plurality of storage segments based on the comparison, where the address data of the new data element is to be stored, and controlling the storage circuit to shift the address data stored at the determined storage segment to other storage segments.

[0100] Another example (eg, Example 2) relates to the previous example (eg, Example 1) or to any other example, further comprising: the control circuit is further configured to control the storage circuit to store the address data of the new data element at the determined storage segment.

[0101] Another example (e.g., Example 3) relates to a previous example (e.g., one of Examples 1 or 2) or to any other example, and also includes: the control circuit is also configured to control the storage circuit to shift all address data stored in storage segments before or after the determined storage segment by a predefined number of storage segments.

[0102] Another example (eg, Example 4) relates to a previous example (eg, one of Examples 1 to 3) or to any other example, further comprising: the control circuit is configured to perform insertion sort for OS-CFAR detection.

[0103] Another example (eg, Example 5) relates to a previous example (eg, one of Examples 1 to 4) or to any other example, further comprising: the storage circuit comprises a parallel shift register coupling a plurality of storage segments in cascade.

[0104] Another example (e.g., Example 6) relates to a previous example (e.g., Example 5) or to any other example, and further includes: multiple storage segments are coupled to corresponding multiplexers, wherein the multiplexers include input nodes coupled to corresponding output nodes of previous or subsequent storage segments in the cascade, and input nodes coupled to data inputs.

[0105] Another example (e.g., Example 7) relates to a previous example (e.g., Example 6) or to any other example, further including: the multiplexer also includes an input node coupled to a corresponding output node of another storage segment in a previous or subsequent storage segment in the cascade.

[0106] Another example (e.g., Example 8) relates to a previous example (e.g., one of Examples 1 to 7) or to any other example, and also includes: the control circuit is configured to continuously select storage segments in ascending or descending order, and compare the corresponding data elements indicated by the address data stored at the selected storage segments with the new data elements until the comparison satisfies a predefined comparison criterion.

[0107] Another example (e.g., Example 9) relates to a previous example (e.g., one of Examples 1 to 8) or to any other example, and also includes: the control circuit is also configured to perform a sorting algorithm on a first window of data elements of the radar data, after performing the sorting algorithm for the first window, select a second window of data elements of the radar data, and perform the sorting algorithm on the second window by only partially removing address data stored in the storage circuit during the execution of the sorting algorithm for the first window.

[0108] Another example (e.g., Example 10) relates to a previous example (e.g., Example 9) or to any other example, and further includes: the control circuit is also configured to execute the sorting algorithm for the second window by controlling the storage circuit to exclusively insert address data of data elements of the second window that have not been inserted during the execution of the sorting algorithm for the first window.

[0109] Another example (e.g., Example 11) relates to a previous example (e.g., one of Examples 1 to 10) or to any other example, and further includes: the control circuit is also configured to select a window of radar data that includes multiple data elements before and after the measured data element, wherein the control circuit is configured to perform a sorting algorithm on the selected window.

[0110] Another example (e.g., Example 12) relates to a previous example (e.g., one of Examples 1 to 11) or to any other example, and also includes: the control circuit is also configured to, after executing the sorting algorithm, select a data element indicated by address data stored at a predefined storage segment in a plurality of storage segments, compare the selected data element with the measured data element, and determine the presence of a target and / or the movement of a target based on the comparison.

[0111] Another example (e.g., Example 13) relates to a previous example (e.g., Example 12) or to any other example, and further includes: the control circuit is also configured to apply a predefined gain to the selected data element and compare the selected data element with the gain applied to the measured data element.

[0112] Another example (e.g., Example 14) relates to a previous example (e.g., one of Examples 12 or 13) or to any other example, and also includes: the control circuit is configured to, in response to determining the presence of a target and / or motion, send an interrupt to the processing circuit for triggering further processing of the radar data.

[0113] Another example (eg, Example 15) relates to a previous example (eg, one of Examples 1 to 14) or to any other example, and further includes: the control circuit is further configured to determine the data element by performing a Fourier transform on the radar data.

[0114] Another example (eg, Example 16) relates to a previous example (eg, one of Examples 1 to 15) or to any other example, further comprising: the control circuit is further configured to determine the data element by converting the radar data into a polar coordinate representation.

[0115] Another example (eg, Example 17) relates to a previous example (eg, Example 16) or to any other example, further comprising: the data element is a magnitude of a polar coordinate representation of radar data.

[0116] Examples (eg, Example 18) relate to a radar system comprising an apparatus according to a previous example (eg, any of Examples 1 to 17) or according to any other example, and a radar sensor configured to generate radar data.

[0117] Another example (eg, Example 19) relates to a previous example (eg, Example 18) or to any other example, and further includes: a radar sensor includes the device.

[0118] Another example (e.g., Example 20) relates to a previous example (e.g., one of Examples 18 or 19) or to any other example, and also includes: the radar sensor includes a first antenna, the first antenna being configured to receive a first signal from a field of view of the radar sensor, wherein the radar sensor is configured to generate radar data based on the first signal, wherein the radar sensor includes at least one second antenna, the at least one second antenna being configured to receive at least one second signal from the field of view of the radar sensor, wherein the radar sensor is configured to generate second radar data based on the second signal, and wherein the radar system includes at least one second device according to a previous example (e.g., any one of Examples 1 to 17) or according to any other example, wherein the second device is configured to process the second radar data.

[0119] Another example (e.g., Example 21) relates to a previous example (e.g., one of Examples 18 to 20) or to any other example, and also includes processing circuitry external to the radar sensor, wherein the processing circuitry is configured to perform further processing of the radar data in response to receiving an interrupt from the device.

[0120] Another example (eg, Example 22) relates to a previous example (eg, one of Examples 18 to 21) or to any other example, and further includes an additional storage circuit.

[0121] An example (e.g., Example 23) relates to a method for OS-CFAR detection, comprising storing address data indicating an address of a data element of radar data at another storage circuit at a storage circuit comprising a plurality of storage segments, and executing a sorting algorithm for OS-CFAR detection by a control circuit using the following steps: comparing a new data element of the radar data with at least one data element indicated by the address data stored in the storage circuit, determining one storage segment of the plurality of storage segments based on the comparison, where the address data of the new data element is to be stored, and controlling the storage circuit to shift the address data stored at the determined storage segment to other storage segments.

[0122] Another example (e.g., Example 24) involves a non-transitory machine-readable medium having a program stored thereon, the program having program code that, when executed on a processor or programmable hardware, is used to perform the method of any of the previous examples (e.g., Example 23) or any other example.

[0123] Another example (eg, Example 25) relates to a program having program code for executing the method of any one of the previous examples (eg, Example 23) or any other example when the program is executed on a processor or programmable hardware.

[0124] The example may further be or relate to a (computer) program, which includes a program code, which executes one or more of the above methods when the program is executed on a computer, a processor or other programmable hardware component. Therefore, the steps, operations or processes of the different methods in the above methods may also be performed by a programmed computer, a processor or other programmable hardware component. The example may also cover a program storage device, such as a digital data storage medium, which is machine-readable, processor-readable or computer-readable, and encodes and / or contains machine-executable, processor-executable or computer-executable programs and instructions. The program storage device may include or may be, for example, a digital storage device, a magnetic storage medium such as a disk and a tape, a hard drive or an optically readable digital data storage medium. Other examples may also include a computer, a processor, a control unit, a (field) programmable logic array ((F)PLA), a (field) programmable gate array ((F)PGA), a graphics processor unit (GPU), an application-specific integrated circuit (ASIC), an integrated circuit (IC) or a system on a chip (SoC) system programmed to perform the steps of the above methods.

[0125] It should also be understood that the disclosure of multiple steps, processes, operations or functions disclosed in the specification or claims should not be interpreted as implying that these operations must rely on the order described, unless explicitly stated in individual cases or necessary for technical reasons. Therefore, the foregoing description does not limit the execution of several steps or functions to a specific order. In addition, in other examples, a single step, function, process or operation can include and / or be decomposed into multiple sub-steps, sub-functions, sub-processes or sub-operations.

[0126] If some aspects have been described with respect to an apparatus or system, these aspects should also be understood as descriptions of the corresponding methods. For example, the blocks, devices or functional aspects of an apparatus or system may correspond to features of the corresponding methods, such as method steps. Therefore, aspects described with respect to methods should also be understood as descriptions of corresponding blocks, corresponding elements, properties or functional features of the corresponding apparatus or corresponding system.

[0127] The following claims are hereby included in the detailed description, where each claim can stand on its own as a separate example. It should also be noted that, although in the claims, a dependent claim refers to a specific combination with one or more other claims, other examples may also include a combination of a dependent claim with the subject matter of any other dependent or independent claim. Unless it is stated in individual cases that a specific combination is not intended, such a combination is explicitly proposed here. In addition, features of a claim should also be included for any other independent claim, even if the claim is not directly defined as being dependent on the other independent claim.

Claims

1. A device (100) for ordered statistical constant false alarm rate (OS-CFAR) detection, comprising: a storage circuit (110) comprising a plurality of storage segments (111, 112, 113), wherein the storage circuit (110) is configured to store address data indicating addresses of data elements of radar data at a further storage circuit (130); and A control circuit (120) configured to execute a ranking algorithm for OS-CFAR detection using the following steps: comparing a new data element of the radar data with at least one data element indicated by address data stored in the memory circuit (110); determining, based on the comparing, a storage segment of the plurality of storage segments at which address data of the new data element is to be stored; and The storage circuit (110) is controlled to shift the address data stored at the determined storage segment to other storage segments.

2. The device (100) according to claim 1, wherein The control circuit (120) is further configured to control the storage circuit (110) to store the address data of the new data element at the determined storage segment.

3. The device (100) according to any one of the preceding claims, wherein: The control circuit (120) is further configured to control the storage circuit (110) to shift all address data stored in the storage segments preceding or following the determined storage segment by a predefined number of storage segments.

4. The device (100) according to any one of the preceding claims, wherein: The control circuit (120) is configured to perform insertion sort for OS-CFAR detection.

5. The device (100) according to any one of the preceding claims, wherein: The storage circuit (110) includes a parallel shift register coupling the plurality of storage segments in cascade.

6. The device (100) according to claim 5, wherein: The plurality of storage segments are coupled to respective multiplexers, wherein the multiplexers include: an input node coupled to a corresponding output node of a preceding or succeeding storage segment in the cascade; and An input node coupled to the data input.

7. The device (100) according to claim 6, wherein The multiplexer also includes an input node coupled to a corresponding output node of another one of the preceding or succeeding memory segments in the cascade.

8. The device (100) according to any one of the preceding claims, wherein: The control circuit (120) is further configured to: executing the sorting algorithm on a first window of data elements of the radar data; selecting a second window of data elements of the radar data after executing the sorting algorithm for the first window; as well as The sorting algorithm for the second window is performed by only partially removing the address data stored in the storage circuit (110) during the execution of the sorting algorithm for the first window.

9. The device (100) according to claim 8, wherein The control circuit (120) is further configured to execute the sorting algorithm for the second window by controlling the storage circuit (110) to exclusively insert address data of data elements of the second window that have not been inserted during execution of the sorting algorithm for the first window.

10. The device (100) according to any one of the preceding claims, wherein The control circuit (120) is further configured to, after executing the sorting algorithm: selecting a data element indicated by address data stored at a predefined storage segment among the plurality of storage segments; comparing the selected data element with the tested data element; as well as The presence of an object and / or motion of an object is determined based on the comparison.

11. The device (100) according to claim 10, wherein The control circuit (120) is configured to: in response to determining the presence of an object and / or motion, send an interrupt to the processing circuit for triggering further processing of the radar data.

12. A radar system (600), comprising: The device (610) according to any of the preceding claims; as well as A radar sensor (620) is configured to generate radar data.

13. The radar system (600) of claim 12, wherein: The radar sensor (620) comprises a first antenna, the first antenna being configured to receive a first signal from a field of view of the radar sensor (620), wherein the radar sensor (620) is configured to generate the radar data based on the first signal, wherein the radar sensor (620) comprises at least one second antenna, the at least one second antenna being configured to receive at least one second signal from the field of view of the radar sensor (620), wherein the radar sensor (620) is configured to generate second radar data based on the second signal, and wherein the radar system comprises at least one second device according to any one of claims 1 to 11, the second device being configured to process the second radar data.

14. The radar system (600) of any one of claims 12 or 13, further comprising a processing circuit external to the radar sensor (620), wherein the processing circuit is configured to: perform further processing of the radar data in response to receiving an interrupt from the device (610).

15. A method (700) for ordered statistical constant false alarm rate (OS-CFAR) detection, comprising: storing (710) at a storage circuit comprising a plurality of storage segments address data indicative of an address of a data element of radar data at another storage circuit; and The sorting algorithm for OS-CFAR detection is performed by the control circuit using the following steps: comparing the new data element of the radar data with at least one data element indicated by address data stored in the storage circuit (720); determining (730) a storage segment of the plurality of storage segments at which address data of the new data element is to be stored based on the comparing; as well as The storage circuit is controlled (740) to shift the address data stored at the determined storage segment to other storage segments.

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