High-power-supply-rejection-ratio low-noise LDO implementation circuit

Abstract

The invention discloses a high-power-supply-rejection-ratio low-noise LDO (Low Dropout Regulator) implementation circuit, which belongs to the technical field of integrated circuits and comprises a voltage reference source, an internal LDO circuit, a voltage follower, a filter circuit and a non-overlapping clock generation circuit, the output end of a first error amplifier EA1 of the internal LDO circuit is connected with the grid electrode of a PMOS tube PM511 in the output stage circuit, the source electrode of a PMOS tube PM303 and the source electrode of a PMOS tube PM301 of the filter circuit are connected with the drain electrode of the PMOS tube PM511, the grid electrode of the PMOS tube PM303 is connected with the output end of the power-on OK detection circuit, and the drain electrode of the PMOS tube PM303 is connected with the drain electrode of the PMOS tube PM302 and the positive electrode of a capacitor Cbig. The drain electrode of the PMOS transistor PM301 is connected with the source electrode of the PMOS transistor PM302 and the positive electrode of the capacitor Csmall; the input positive end of a second error amplifier EA2 of the voltage follower is connected with the positive electrode of the capacitor CF1, and the output end of the second error amplifier EA2 is connected with the grid electrode of the PMOS tube PM622. According to the invention, a high PSRR LDO architecture is realized with low power consumption, the performance requirement is reduced, and the overhead of the system is greatly reduced.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a high power supply rejection ratio and low noise LDO implementation circuit. Background Art

[0002] Low dropout linear regulators (LDOs) are currently widely used in various devices, such as various smart phones, personal laptops, smart mobile terminals and other mobile portable devices. In order to ensure that the device system works more safely and reliably, high-quality power is essential. Currently, most mobile portable devices have a large number of precision sensor systems and radio frequency transceiver circuits for transmitting communication information. These precision and noise-sensitive systems require the system to provide a low-noise and high power supply rejection ratio (PSRR) power supply.

[0003] In traditional high PSRR LDO solutions, in order to reduce the multiplication effect of the output error amplifier on the reference voltage noise, the output stage often adopts a voltage follower solution. The first internal LDO multiplies it to the output voltage. In order to reduce the noise and PSRR influence of the reference voltage, a low-pass filter is used after the first internal LDO to minimize the influence of the previous stage. The noise and PSRR of the system output are mainly contributed by the voltage follower of the output stage. In traditional LDO solutions, the noise is mainly composed of four parts: the noise generated by the bandgap reference itself, the noise of the first internal LDO, the noise generated by the reference voltage filter circuit, the noise generated by the LDO error amplifier, etc. Similarly, the power supply noise coupled to the LDO also consists of four parts: the path from the power supply to the bandgap reference voltage, the path from the power supply to the first internal LDO, the path from the power supply to the error amplifier output, and the path from the power supply to the output through the power tube. As modern devices have higher and higher requirements for system power consumption, lower quiescent current means higher noise. Fast transient response of LDO is also a challenge. Therefore, the part that generates reference voltage and first internal LDO for the system cannot consume too much quiescent power. More power consumption will be allocated to the error amplifier of LDO. Therefore, the reference voltage and first internal LDO will contribute too much noise output to the system. What's worse, in order to achieve high PSRR, the bandgap reference requires a very complex architecture, which will increase quiescent power consumption and wafer cost.

[0004] Therefore, in order to improve the noise performance and PSRR of the system reference voltage, a simple RC filter circuit is a feasible solution. To realize a low-bandwidth low-pass filter, relatively large resistors and capacitors are required. To achieve such a goal, a considerable chip area is required. However, based on cost considerations or packaging considerations, the chip area cannot be increased indefinitely, and the resistors and capacitors cannot be too large. Therefore, a large off-chip capacitor CBP is needed to simply realize a low-cutoff frequency low-pass filter, which can significantly improve the system's noise performance and PSRR. However, when using external capacitors, ESD issues need to be considered. The introduction of ESD devices will increase the area and be sensitive to high-temperature leakage, and will also increase the user's overall machine cost.

[0005] Therefore, a circuit LDO is needed to avoid ESD problems and solve the problem of unstable power supply. Summary of the invention

[0006] In view of some existing problems, the present invention aims to provide a high power supply rejection ratio and low noise LDO implementation circuit to solve the problems raised in the above background technology.

[0007] To achieve the above object, the present invention provides the following technical solutions: A high power supply rejection ratio low noise LDO implementation circuit, comprising a voltage reference source, an internal LDO circuit, a voltage follower, a filter circuit and a non-overlapping clock generation circuit; The internal LDO circuit includes a first error amplifier EA1, a first bias circuit, an output stage circuit, a phase compensation network circuit and a power-on OK detection circuit; the input VREF of the voltage reference source is connected to the positive input terminal of the first error amplifier EA1, the output terminal of the first error amplifier EA1 is connected to the gate of the PMOS tube PM511 in the output stage circuit, the source of the PMOS tube PM511 in the output stage circuit is connected to the power supply VIN, the drain of the PMOS tube PM511 in the output stage circuit is connected to one end of the resistor divider R501, the other end of the resistor divider R501 is simultaneously connected to the negative input terminal of the first error amplifier EA1 and one end of the resistor R502, and the other end of the resistor R502 is grounded; the drain of the PMOS tube PM511 is connected to an input terminal of the power-on OK detection circuit, and the other input terminal of the power-on OK detection circuit is connected to the power supply VIN; The phase compensation network circuit is connected to the gate of the PMOS tube PM511 in the output stage circuit; The first bias circuit is electrically connected to the first error amplifier EA1 and the power-on OK detection circuit; The filter circuit includes a PMOS tube PM301, a PMOS tube PM302, a PMOS tube PM303, a resistor RF1, a capacitor Csmall, a capacitor Cbig and a capacitor CF1. The source of the PMOS tube PM303 and the source of the PMOS tube PM301 are both connected to the drain of the PMOS tube PM511. The gate of the PMOS tube PM303 is connected to the output end of the power-on OK detection circuit. The gate of the PMOS tube PM301 is connected to the output signal PH1b of the non-overlapping clock generation circuit. The drain is connected to the drain of the PMOS tube PM302 and the positive electrode of the capacitor Cbig, and the negative electrode of the capacitor Cbig is grounded; the drain of the PMOS tube PM301 is connected to the source of the PMOS tube PM302 and the positive electrode of the capacitor Csmall, and the negative electrode of the capacitor Csmall is grounded; the gate of the PMOS tube PM302 is connected to the output signal PH2b of the non-overlapping clock generating circuit, the positive electrode of the capacitor Cbig is connected to one end of the resistor RF1, the other end of the resistor RF1 is connected to the positive electrode of the capacitor CF1, and the negative electrode of the capacitor CF1 is grounded; The voltage follower includes a second error amplifier EA2 and a PMOS tube PM622, the positive input terminal of the second error amplifier EA2 is connected to the positive electrode of the capacitor CF1, the negative input terminal of the second error amplifier EA2 is connected to the power supply VOUT, the output terminal of the second error amplifier EA2 is connected to the gate of the PMOS tube PM622, the source of the PMOS tube PM622 is connected to the power supply VIN, and the drain of the PMOS tube PM622 is connected to the power supply VOUT.

[0008] As a further solution of the present invention: the non-overlapping clock generating circuit includes a NAND gate NAND1, a NAND gate NAND2, an IN gate INV0, an IN gate INV1, an IN gate INV2, an IN gate INV3, an IN gate INV4, an IN gate INV5, an IN gate INV6, an IN gate INV7, an IN gate INV8, an IN gate INV9, an IN gate INV10, an IN gate INV11, an IN gate INV12, a resistor R11, a resistor R12, a capacitor C1 and a capacitor C2; The CLK signal is simultaneously connected to one input terminal of the NAND gate NAND1 and the input terminal of the NAND gate INV0, and the other input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate INV10; The output end of the NOT gate INV0 is connected to one input end of the NAND gate NAND2, and the other input end of the NAND gate NAND2 is connected to the output end of the NAND gate INV4; The output end of the AND gate NAND1 is connected to the input end of the NOT gate INV1, the output end of the NOT gate INV1 is connected to the input end of the NOT gate INV2, the output end of the NOT gate INV2 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the positive electrode of the capacitor C1 and the input end of the NOT gate INV3, the output end of the NOT gate INV3 is connected to the input end of the NOT gate INV4, the output end of the NOT gate INV4 is connected to the input end of the NOT gate INV5, the output end of the NOT gate INV5 is connected to the input end of the NOT gate INV6, and the output end of the NOT gate INV6 outputs the signal PH1b; the negative electrode of the capacitor C1 is grounded; The output end of the AND gate NAND2 is connected to the input end of the NOT gate INV7, the output end of the NOT gate INV7 is connected to the input end of the NOT gate INV8, the output end of the NOT gate INV8 is connected to one end of the resistor R12, the other end of the resistor R12 is simultaneously connected to the positive electrode of the capacitor C2 and the input end of the NOT gate INV9, the output end of the NOT gate INV9 is connected to the input end of the NOT gate INV10, the output end of the NOT gate INV10 is connected to the input end of the NOT gate INV11, the output end of the NOT gate INV11 is connected to the input end of the NOT gate INV12, and the output end of the NOT gate INV12 outputs the signal PH2b; the negative electrode of the capacitor C2 is grounded.

[0009] As a further solution of the present invention: the first error amplifier EA1 in the internal LDO circuit includes NMOS tube NM501, NMOS tube NM502, NMOS tube NM506, NMOS tube NM507, NMOS tube NM508, NMOS tube NM509, NMOS tube NM513, NMOS tube NM514, PMOS tube PM503, PMOS tube PM504, PMOS tube PM501 and PMOS tube PM502; The source of the PMOS tube PM503 and the source of the PMOS tube PM504 are connected to the power source VIN; the gate of the PMOS tube PM503 is connected to the drain of the PMOS tube PM503, the gate of the PMOS tube PM504, and the drain of the NMOS tube NM513; the drain of the PMOS tube PM504 is connected to the drain of the NMOS tube NM514; The gate of NMOS tube NM513 is connected to the gate of NMOS tube NM514, the source of NMOS tube NM513 is connected to the drain of NMOS tube NM501 and the drain of NMOS tube NM506 at the same time; the source of NMOS tube NM514 is connected to the drain of NMOS tube NM502 and the drain of NMOS tube NM509 at the same time; The gate of the NMOS tube NM501 is connected to the gate of the PMOS tube PM502; the gate of the NMOS tube NM502 is connected to the gate of the PMOS tube PM501 and the output VREF of the voltage reference source; the gate of the NMOS tube NM501 is the input negative electrode of the first error amplifier EA1; the gate of the NMOS tube NM502 is the input positive electrode of the first error amplifier EA1; the drain of the NMOS tube NM514 is the output end of the first error amplifier EA1; The drain of the PMOS tube PM501 is simultaneously connected to the gate of the NMOS tube NM506, the gate of the NMOS tube NM507, and the drain of the NMOS tube NM507; the source of the NMOS tube NM506 and the source of the NMOS tube NM507 are both grounded; the drain of the PMOS tube PM502 is simultaneously connected to the gate of the NMOS tube NM508, the gate of the NMOS tube NM509, and the drain of the NMOS tube NM508; the source of the NMOS tube NM508 and the source of the NMOS tube NM509 are both grounded.

[0010] As a further solution of the present invention: the power-on OK detection circuit in the internal LDO circuit includes a PMOS tube PM507, a PMOS tube PM508, an NMOS tube NM510 and an NMOS tube NM511, the source of the PMOS tube PM507 ​​and the source of the PMOS tube PM508 are both connected to the power supply VIN, the drain of the PMOS tube PM507 ​​is simultaneously connected to the gate of the PMOS tube PM508, the drain of the NMOS tube NM510 and the gate of the NMOS tube NM511, and the drain of the NMOS tube NM511 is simultaneously connected to the drain of the PMOS tube PM508 and the gate of the PMOS tube PM303 in the filter circuit; The gate of the NMOS tube NM510 is connected to the drain of the NMOS tube NM514 and the gate of the PMOS tube PM511 in the output stage circuit; the source of the NMOS tube NM510 and the source of the NMOS tube NM511 are both grounded.

[0011] As a further solution of the present invention: the first bias circuit in the internal LDO circuit includes NMOS tube NM503, NMOS tube NM504, NMOS tube NM505, NMOS tube NM512, PMOS tube PM505, PMOS tube PM506, current source I501 and current source I502; The input end of the current source I501 and the input end of the current source I502 are both connected to the power source VIN; the output end of the current source I501 is simultaneously connected to the gate of the NMOS tube NM512, the drain of the NMOS tube NM512, and the gate of the NMOS tube NM513; the source of the NMOS tube NM512 is grounded; the output end of the current source I502 is simultaneously connected to the gate of the NMOS tube NM503, the drain of the NMOS tube NM503, the gate of the NMOS tube NM504, and the gate of the NMOS tube NM505; The drain of NMOS tube NM504 is connected to the source of NMOS tube NM501; the drain of NMOS tube NM505 ​​is connected to the drain of PMOS tube PM505, the gate of PMOS tube PM505, the gate of PMOS tube PM506, and the gate of PMOS tube PM507; the source of PMOS tube PM505 and the source of PMOS tube PM506 are both connected to the power supply VIN; the source of MOS tube NM503, the source of NMOS tube NM504, and the source of NMOS tube NM505 ​​are grounded.

[0012] As a further solution of the present invention: the phase compensation network circuit in the internal LDO circuit includes a resistor R503 and a capacitor C503, one end of the capacitor C503 is connected to the power supply VIN; the other end of the capacitor C503 is connected to one end of the resistor R503, and the other end of the resistor R503 is connected to the gate of the PMOS tube PM511; The output stage circuit in the internal LDO circuit includes a PMOS tube PM511, a resistor R501, a resistor R502, a capacitor C501 and a capacitor C502; the drain of the PMOS tube PM511 is connected to one end of the resistor R501 and one end of the capacitor C502, the capacitor C502 is connected in parallel to both ends of the resistor R501, the other end of the resistor R501 is connected to one end of the resistor R502, and the other end of the resistor R502 and the other end of the capacitor C502 are both grounded.

[0013] As a further solution of the present invention: the voltage follower includes a second bias circuit, a second error amplifier EA2, a load adaptive current bias circuit and a compensation circuit; The second bias circuit in the voltage follower includes a current source I601, an NMOS transistor NM605, an NMOS transistor NM606, an NMOS transistor NM607, an NMOS transistor NM614, a PMOS transistor PM606, a PMOS transistor PM607 and a PMOS transistor PM608; The input end of the current source I601 is connected to the power source VIN; the output end of the current source I601 is simultaneously connected to the drain of the NMOS tube NM605, the gate of the NMOS tube NM605, and the gate of the NMOS tube NM606; the drain of the NMOS tube NM606 is simultaneously connected to the drain of the PMOS tube PM606, the gate of the PMOS tube PM606, the gate of the PMOS tube PM607, and the gate of the PMOS tube PM608; The drain of the PMOS tube PM607 is connected to the drain of the NMOS tube NM614 and the gate of the NMOS tube NM614 at the same time; the drain of the PMOS tube PM608 is connected to the drain of the NMOS tube NM607 and the gate of the NMOS tube NM607 at the same time; The source of the PMOS tube PM606, the source of the PMOS tube PM607, and the source of the PMOS tube PM608 are connected to the power source VIN; The source of the NMOS tube NM605 , the source of the NMOS tube NM606 , the source of the NMOS tube NM614 , and the source of the NMOS tube NM607 are grounded.

[0014] As a further solution of the present invention: the second error amplifier EA2 in the voltage follower includes a first-stage amplifier circuit, a second-stage amplifier circuit and a current detection circuit; The first stage amplifier circuit includes NMOS tube NM601, NMOS tube NM602, NMOS tube NM603, NMOS tube NM604, NMOS tube NM608, NMOS tube NM609, NMOS tube NM610, NMOS tube NM615, NMOS tube NM616, PMOS tube PM601, PMOS tube PM602, PMOS tube PM603 and PMOS tube PM604; The gate of the NMOS tube NM601 is connected to the positive electrode of the capacitor CF1 in the filter circuit, and the gate of the MOS tube NM602 is connected to the drain of the PMOS tube PM622; the gate of the NMOS tube NM601 is the positive input electrode of the second error amplifier EA2, and the gate of the NMOS tube NM602 is the negative input electrode of the second error amplifier EA2; The source of the NMOS tube NM601 is simultaneously connected to the source of the NMOS tube NM602 and the drain of the NMOS tube NM608, and the gate of the NMOS tube NM608 is simultaneously connected to the gate of the NMOS tube NM609, the gate of the NMOS tube NM610, and the gate of the NMOS tube NM607 in the second bias circuit; The drain of the NMOS tube NM601 is connected to the source of the NMOS tube NM603, the drain of the NMOS tube NM602 is connected to the source of the NMOS tube NM603, and the gate of the NMOS tube NM603 is connected to the gate of the NMOS tube NM604; The drain of the NMOS tube NM603 is connected to the drain of the PMOS tube PM601 and the source of the PMOS tube PM603 at the same time, the drain of the NMOS tube NM604 is connected to the drain of the PMOS tube PM602 and the source of the PMOS tube PM604 at the same time, and the source of the PMOS tube PM601 and the source of the PMOS tube PM602 are connected to the power supply VIN; The gate of the PMOS transistor PM601 is simultaneously connected to the gate of the PMOS transistor PM602, the gate of the PMOS transistor PM603, the drain of the PMOS transistor PM603, and the drain of the NMOS transistor NM615; the gate of the PMOS transistor PM604 is simultaneously connected to the drain of the PMOS transistor PM604 and the drain of the NMOS transistor NM616; The gate of the NMOS tube NM615 is connected to the gate of the NMOS tube NM616 and the gate of the NMOS tube NM614 in the second bias circuit at the same time; the source of the NMOS tube NM615 is connected to the drain of the NMOS tube NM609, and the source of the NMOS tube NM616 is connected to the drain of the NMOS tube NM610; The source of the NMOS tube NM608, the source of the NMOS tube NM609, and the source of the NMOS tube NM610 are grounded; The second stage amplifying circuit includes NMOS tube NM611, NMOS tube NM617, NMOS tube NM625, NMOS tube NM626, PMOS tube PM605 and PMOS tube PM609; The source of the PMOS tube PM609 and the source of the PMOS tube PM605 are connected to the power supply VIN; the gate of the PMOS tube PM609 is connected to the gate of the PMOS tube PM608 in the second bias circuit; the gate of the PMOS tube PM605 is connected to the gate of the PMOS tube PM604 in the first-stage amplifier circuit; the drain of the PMOS tube PM609 is simultaneously connected to the drain of the PMOS tube PM605, the drain of the NMOS tube NM617, and the drain of the NMOS tube NM625; the drain of the PMOS tube PM609 is the output end of the second error amplifier EA2; The gate of the NMOS tube NM617 is connected to the gate of the NMOS tube NM625 and the gate of the NMOS tube NM616 in the first-stage amplifier circuit at the same time; the source of the NMOS tube NM617 is connected to the drain of the NMOS tube NM611, the source of the NMOS tube NM625 is connected to the drain of the NMOS tube NM626, and the gate of the NMOS tube NM611 is connected to the gate of the NMOS tube NM610 in the first-stage amplifier circuit; The source of the NMOS tube NM611 and the source of the NMOS tube NM626 are grounded; The current detection circuit includes a PMOS tube PM621, a PMOS tube PM622, a PMOS tube PM625, a PMOS tube PM626, an NMOS tube NM618 and an NMOS tube NM619; The source of the PMOS tube PM621 and the source of the PMOS tube PM622 are connected to the power source VIN; The gate of the PMOS tube PM622 is connected to the gate of the PMOS tube PM621 and the drain of the PMOS tube PM609 in the second-stage amplifier circuit; the drain of the PMOS tube PM622 is connected to the source of the PMOS tube PM626 and the gate of the NMOS tube NM602 in the first-stage amplifier circuit; The drain of the PMOS tube PM621 is connected to the source of the PMOS tube PM625, the gate of the PMOS tube PM625 is simultaneously connected to the gate of the PMOS tube PM626, the drain of the PMOS tube PM626, and the drain of the NMOS tube NM619, and the drain of the PMOS tube PM625 is simultaneously connected to the drain of the NMOS tube NM618, the screen of the NMOS tube NM618, and the gate of the NMOS tube NM619; The source of the NMOS tube NM618 and the source of the NMOS tube NM619 are grounded.

[0015] As a further solution of the present invention: the load adaptive current bias circuit in the voltage follower includes NMOS tube NM612, NMOS tube NM620, NMOS tube NM621, NMOS tube NM622, NMOS tube NM623, PMOS tube PM610, PMOS tube PM611, PMOS tube PM612, PMOS tube PM613, resistor R601 and capacitor C601; The source of the PMOS tube PM610, the source of the PMOS tube PM611, the source of the PMOS tube PM612, and the source of the PMOS tube PM613 are connected to the power source VIN; The gate of the PMOS transistor PM610 is simultaneously connected to the drain of the PMOS transistor PM610, the gate of the PMOS transistor PM611, and the drain of the NMOS transistor NM620; the drain of the PMOS transistor PM611 is connected to the gate of the NMOS transistor NM612 and the gate of the NMOS transistor NM611 in the second-stage amplifier circuit; The gate of the PMOS tube PM612 is simultaneously connected to the drain of the PMOS tube PM612, the gate of the PMOS tube PM613, and the drain of the NMOS tube NM612; the source of the NMOS tube NM612 is connected to the drain of the NMOS tube NM621; the gate of the NMOS tube NM620 is simultaneously connected to the gate of the NMOS tube NM621 and the gate of the NMOS tube NM619 in the current detection circuit; The drain of the PMOS transistor PM613 is connected to the gate of the NMOS transistor NM622, the drain of the NMOS transistor NM622, and one end of the resistor R601. The other end of the resistor R601 is simultaneously connected to one end of the capacitor C601, the gate of the NMOS transistor NM623, and the gate of the NMOS transistor NM626 in the second-stage amplifier circuit; the other end of the capacitor C601 is grounded; the drain of the NMOS transistor NM623 is connected to the source of the NMOS transistor NM601 in the first-stage amplifier circuit; The source of the NMOS tube NM620 , the source of the NMOS tube NM621 , the source of the NMOS tube NM622 , and the source of the NMOS tube NM623 are all grounded.

[0016] As a further solution of the present invention: the compensation circuit in the voltage follower includes an NMOS tube NM613, an NMOS tube NM624, a PMOS tube PM614, a PMOS tube PM615, a PMOS tube PM616, a PMOS tube PM617, a PMOS tube PM623, a PMOS tube PM624, a resistor R602, a resistor R603, a resistor R604 and a capacitor C602; The source of the PMOS tube PM614 and the source of the PMOS tube PM616 are connected to the power source VIN; The gate of the PMOS tube PM614 is simultaneously connected to the drain of the PMOS tube PM614, the gate of the PMOS tube PM615, and the drain of the NMOS tube NM624. The gate of the NMOS tube NM624 is connected to the gate of the NMOS tube NM623 in the load adaptive current bias circuit. The source of the PMOS tube PM615 is connected to one end of the resistor R602, one end of the resistor R603, and the source of the PMOS tube PM623; the other end of the resistor R602 is connected to the drain of the PMOS tube PM602 in the first-stage amplifier circuit; the other end of the resistor R603 is connected to the source of the PMOS tube PM624 and one end of the resistor R604, and the other end of the resistor R604 is connected to the drain of the PMOS tube PM617; The drain of the PMOS transistor PM615 is simultaneously connected to one end of the capacitor C602, the drain of the PMOS transistor PM623, the drain of the PMOS transistor PM624, and the source of the PMOS transistor PM617; the other end of the capacitor C602 is simultaneously connected to the gate of the PMOS transistor PM623 and the gate of the PMOS transistor PM624; The gate of the PMOS tube PM617 is simultaneously connected to the gate of the PMOS tube PM616, the drain of the PMOS tube PM616, and the drain of the NMOS tube NM613; the gate of the NMOS tube NM613 is connected to the gate of the NMOS tube NM612 in the load adaptive current bias circuit; The source of the NMOS tube NM624 and the source of the NMOS tube NM613 are grounded.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The present invention solves the technical problem that the traditional architecture must use a large off-chip capacitor to implement a low-cutoff frequency low-pass filter circuit in a traditional high-PSRR LDO architecture. The high-PSRR LDO architecture is implemented with low power consumption by using on-chip devices without increasing too much area. The reference voltage VREF is then amplified to a normal output voltage by a first internal LDO. The noise and PSRR of the voltage reference source and the first internal LDO itself are filtered out by a third low-pass filter to completely filter out high-frequency ripple signals, thereby providing a stable and clean output reference voltage for the second voltage follower. In this way, the performance requirements for the voltage reference source and the first internal LDO can be reduced, thereby greatly reducing the system overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The figure is a circuit architecture diagram of a high power supply rejection ratio low noise LDO implementation circuit.

[0019] Figure 2 The present invention is a schematic diagram of the circuit structure of a non-overlapping clock generation circuit in a high power supply rejection ratio low noise LDO implementation circuit.

[0020] Figure 3 The figure is a schematic diagram of the internal LDO circuit structure in a high power supply rejection ratio low noise LDO implementation circuit.

[0021] Figure 4The schematic diagram of the circuit structure of a voltage follower in a high power supply rejection ratio low noise LDO implementation circuit is shown in FIG.

[0022] Figure 5 This is a schematic diagram showing the principle of achieving high PSRR using a low-pass filter in a high power supply rejection ratio low noise LDO implementation circuit.

[0023] In the figure: 1. Internal LDO circuit; 2. Voltage follower; 3. Filter circuit. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", and "connected" should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, or an electrical connection, a direct connection, or an indirect connection through an intermediate medium, or the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] See also Figure 1-5 , a high power supply rejection ratio low noise LDO implementation circuit, including a voltage reference source, an internal LDO circuit 1, a voltage follower 2, a filter circuit 3 and a non-overlapping clock generation circuit; The internal LDO circuit 1 includes a first error amplifier EA1, a first bias circuit, an output stage circuit, a phase compensation network circuit and a power-on OK detection circuit; the input VREF of the voltage reference source is connected to the positive input terminal of the first error amplifier EA1, the output terminal of the first error amplifier EA1 is connected to the gate of the PMOS tube PM511 in the output stage circuit, the source of the PMOS tube PM511 in the output stage circuit is connected to the power supply VIN, the drain of the PMOS tube PM511 in the output stage circuit is connected to one end of the resistor divider R501, the other end of the resistor divider R501 is simultaneously connected to the negative input terminal of the first error amplifier EA1 and one end of the resistor R502, and the other end of the resistor R502 is grounded; the drain of the PMOS tube PM511 is connected to one input terminal of the power-on OK detection circuit, and the other input terminal of the power-on OK detection circuit is connected to the power supply VIN; The phase compensation network circuit is connected to the gate of the PMOS tube PM511 in the output stage circuit; The first bias circuit is electrically connected to the first error amplifier EA1 and the power-on OK detection circuit; The filter circuit 3 includes a PMOS transistor PM301, a PMOS transistor PM302, a PMOS transistor PM303, a resistor RF1, a capacitor Csmall, a capacitor Cbig and a capacitor CF1. The source of the PMOS transistor PM303 and the source of the PMOS transistor PM301 are both connected to the drain of the PMOS transistor PM511. The gate of the PMOS transistor PM303 is connected to the output end of the power-on OK detection circuit. The gate of the PMOS transistor PM301 is connected to the output signal PH1b of the non-overlapping clock generation circuit. The PMOS transistor PM303 The drain of the PMOS tube PM301 is connected to the drain of the PMOS tube PM302 and the positive electrode of the capacitor Cbig, and the negative electrode of the capacitor Cbig is grounded; the drain of the PMOS tube PM301 is connected to the source of the PMOS tube PM302 and the positive electrode of the capacitor Csmall, and the negative electrode of the capacitor Csmall is grounded; the gate of the PMOS tube PM302 is connected to the output signal PH2b of the non-overlapping clock generating circuit, the positive electrode of the capacitor Cbig is connected to one end of the resistor RF1, the other end of the resistor RF1 is connected to the positive electrode of the capacitor CF1, and the negative electrode of the capacitor CF1 is grounded; The voltage follower 2 includes a second error amplifier EA2 and a PMOS tube PM622, wherein the positive input terminal of the second error amplifier EA2 is connected to the positive electrode of the capacitor CF1, the negative input terminal of the second error amplifier EA2 is connected to the power supply VOUT, the output terminal of the second error amplifier EA2 is connected to the gate of the PMOS tube PM622, the source of the PMOS tube PM622 is connected to the power supply VIN, and the drain of the PMOS tube PM622 is connected to the power supply VOUT; like Figure 2 As shown, the non-overlapping clock generating circuit includes a NAND gate NAND1, a NAND gate NAND2, a NOT gate INV0, a ​​NOT gate INV1, a NOT gate INV2, a NOT gate INV3, a NOT gate INV4, a NOT gate INV5, a NOT gate INV6, a NOT gate INV7, a NOT gate INV8, a NOT gate INV9, a NOT gate INV10, a NOT gate INV11, a NOT gate INV12, a resistor R11, a resistor R12, a capacitor C1 and a capacitor C2; The CLK signal is simultaneously connected to one input terminal of the NAND gate NAND1 and the input terminal of the NAND gate INV0, and the other input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate INV10; The output end of the NOT gate INV0 is connected to one input end of the NAND gate NAND2, and the other input end of the NAND gate NAND2 is connected to the output end of the NAND gate INV4; The output end of the AND gate NAND1 is connected to the input end of the NOT gate INV1, the output end of the NOT gate INV1 is connected to the input end of the NOT gate INV2, the output end of the NOT gate INV2 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the positive electrode of the capacitor C1 and the input end of the NOT gate INV3, the output end of the NOT gate INV3 is connected to the input end of the NOT gate INV4, the output end of the NOT gate INV4 is connected to the input end of the NOT gate INV5, the output end of the NOT gate INV5 is connected to the input end of the NOT gate INV6, and the output end of the NOT gate INV6 outputs the signal PH1b; the negative electrode of the capacitor C1 is grounded; The output end of the AND gate NAND2 is connected to the input end of the NOT gate INV7, the output end of the NOT gate INV7 is connected to the input end of the NOT gate INV8, the output end of the NOT gate INV8 is connected to one end of the resistor R12, the other end of the resistor R12 is simultaneously connected to the positive electrode of the capacitor C2 and the input end of the NOT gate INV9, the output end of the NOT gate INV9 is connected to the input end of the NOT gate INV10, the output end of the NOT gate INV10 is connected to the input end of the NOT gate INV11, the output end of the NOT gate INV11 is connected to the input end of the NOT gate INV12, and the output end of the NOT gate INV12 outputs the signal PH2b; the negative electrode of the capacitor C2 is grounded; Figure 1 The voltage reference source and the first internal LDO in the circuit generally have a low PSRR bandwidth due to their low power consumption. The principle of enhancing PSRR through low-pass RC is as follows: Figure 5 As shown: Figure 5 (a) shows the PSRR Bode plot of VOUT_PRIM. Figure 5 (b) shows the Bode plot of VOUT_CLEAN after passing through the first-order low-pass filter (solid line). It can be seen from the figure that the PSRR enhancement frequency range is from the low-pass filter cutoff frequency (fc) to the first internal LDO PSRR bandwidth (f-3dB). If f-3dB is 100 times fc, VOUT_CLEAN can be improved by 40dB. Assuming that the first internal LDO dc PSRR is 50dB, f-3dB is 100Hz, fc=1Hz, VOUT_CLEAN can achieve 90dB PSRR at medium and high frequencies (greater than 1kHz); Figure 5 (c) Shows the principle of using a second-order low-pass filter circuit to enhance the PSRR of VOUT_CLEAN in a higher frequency range (greater than 100kHz).

[0027] In order to achieve a better PSRR enhancement effect, the cutoff frequency of the third low-pass filter needs to be very low (generally below 1Hz). The filter uses an on-chip capacitor CF. Generally, the on-chip capacitor is used in the range of 10pF-100pF. In order to achieve a low cutoff frequency, a relatively large filter resistor RF needs to be implemented. For example, to achieve a 1s time constant, the resistor needs to be 10GΩ-100GΩ, which is impossible to achieve with an on-chip resistor. Based on this problem, the present invention innovatively uses a switch capacitor to implement a large resistor and implements this low-pass filter. The third low-pass filter implemented by the switch capacitor uses PMOS tubes PM1 and PM2. The gates of these two PMOS tubes are connected to non-overlapping edge clocks, namely PH1b and PH2b. PM1 and PM2 are divided into two parts in each cycle as switches. The first half of the cycle charges Csmall, and the second half of the cycle transfers the charge of Csmall to Cbig. The principle of charge transfer is used to be equivalent to a larger resistor. The resistance value of this equivalent resistor and the cutoff frequency of the low-pass filter are determined by the following formula:

[0028]

[0029] In order to achieve a lower cut-off frequency, it is necessary to increase the ratio of Cbig and Csmall and reduce the clock frequency. Assuming Cbig = 100pF, Csmall = 0.1pF, a clock frequency of 1kHz is required to achieve an equivalent time constant of 1s, thus achieving an equivalent resistance of up to 10GΩ. Figure 1 The switched capacitor low-pass filter circuit in the circuit combines with RF1 and CF1 to form a second-order low-pass filter, achieving the PSRR enhancement effect on the higher frequency band of VOUT_PRIM.

[0030] In the switched capacitor low-pass filter solution mentioned in the present invention, when the system is powered on, due to the relatively low clock frequency, the ratio of Cbig to Csmall is relatively large. If the switched capacitor is solely used to carry the charge to achieve the power-on climb of VOUT_CLEAN, the climb time will be very long (related to the cutoff frequency of the filter), which is unacceptable in the application. Therefore, during power-on, VOUT_PRIM and VOUT_CLEAN are short-circuited by a switch to achieve a faster power-on speed. For a low-dropout LDO, if the system power supply is lower than its output voltage, the LDO will enter a dropout mode. At this time, VOUT_PRIM and VOUT_CLEAN are both equal to the input voltage. If the input recovers quickly, VOUT_PRIM can respond quickly. Due to the low-pass filter, VOUT_CLEAN still cannot recover quickly. Therefore, a first internal LDO dropout mode detection circuit is used. In this way, when the system exits the dropout mode, there will be enough time to use the PMOS tube PM3 as a switch to charge VOUT_CLEAN to the voltage of VOUT_PRIM.

[0031] like Figure 3 As shown, the first error amplifier EA1 includes NMOS tube NM501, NMOS tube NM502, NMOS tube NM506, NMOS tube NM507, NMOS tube NM508, NMOS tube NM509, NMOS tube NM513, NMOS tube NM514, PMOS tube PM503, PMOS tube PM504, PMOS tube PM501 and PMOS tube PM502; The source of the PMOS tube PM503 and the source of the PMOS tube PM504 are connected to the power source VIN; the gate of the PMOS tube PM503 is connected to the drain of the PMOS tube PM503, the gate of the PMOS tube PM504, and the drain of the NMOS tube NM513; the drain of the PMOS tube PM504 is connected to the drain of the NMOS tube NM514; The gate of NMOS tube NM513 is connected to the gate of NMOS tube NM514, the source of NMOS tube NM513 is connected to the drain of NMOS tube NM501 and the drain of NMOS tube NM506 at the same time; the source of NMOS tube NM514 is connected to the drain of NMOS tube NM502 and the drain of NMOS tube NM509 at the same time; The gate of the NMOS tube NM501 is connected to the gate of the PMOS tube PM502; the gate of the NMOS tube NM502 is connected to the gate of the PMOS tube PM501 and the output VREF of the voltage reference source; the gate of the NMOS tube NM501 is the input negative electrode of the first error amplifier EA1; the gate of the NMOS tube NM502 is the input positive electrode of the first error amplifier EA1; the drain of the NMOS tube NM514 is the output end of the first error amplifier EA1; The drain of the PMOS tube PM501 is simultaneously connected to the gate of the NMOS tube NM506, the gate of the NMOS tube NM507, and the drain of the NMOS tube NM507; the source of the NMOS tube NM506 and the source of the NMOS tube NM507 are both grounded; the drain of the PMOS tube PM502 is simultaneously connected to the gate of the NMOS tube NM508, the gate of the NMOS tube NM509, and the drain of the NMOS tube NM508; the source of the NMOS tube NM508 and the source of the NMOS tube NM509 are both grounded; The power-on OK detection circuit includes a PMOS tube PM507, a PMOS tube PM508, an NMOS tube NM510 and an NMOS tube NM511. The source of the PMOS tube PM507 ​​and the source of the PMOS tube PM508 are both connected to the power supply VIN. The drain of the PMOS tube PM507 ​​is simultaneously connected to the gate of the PMOS tube PM508, the drain of the NMOS tube NM510 and the gate of the NMOS tube NM511. The drain of the NMOS tube NM511 is simultaneously connected to the drain of the PMOS tube PM508 and the gate of the PMOS tube PM303 in the filter circuit 3. The gate of the NMOS tube NM510 is connected to the drain of the NMOS tube NM514 and the gate of the PMOS tube PM511 in the output stage circuit; the source of the NMOS tube NM510 and the source of the NMOS tube NM511 are both grounded; The first bias circuit includes an NMOS transistor NM503, an NMOS transistor NM504, an NMOS transistor NM505, an NMOS transistor NM512, a PMOS transistor PM505, a PMOS transistor PM506, a current source I501, and a current source I502; The input end of the current source I501 and the input end of the current source I502 are both connected to the power source VIN; the output end of the current source I501 is simultaneously connected to the gate of the NMOS tube NM512, the drain of the NMOS tube NM512, and the gate of the NMOS tube NM513; the source of the NMOS tube NM512 is grounded; the output end of the current source I502 is simultaneously connected to the gate of the NMOS tube NM503, the drain of the NMOS tube NM503, the gate of the NMOS tube NM504, and the gate of the NMOS tube NM505; The drain of NMOS tube NM504 is connected to the source of NMOS tube NM501; the drain of NMOS tube NM505 ​​is connected to the drain of PMOS tube PM505, the gate of PMOS tube PM505, the gate of PMOS tube PM506, and the gate of PMOS tube PM507; the source of PMOS tube PM505 and the source of PMOS tube PM506 are both connected to the power supply VIN; the source of MOS tube NM503, the source of NMOS tube NM504, and the source of NMOS tube NM505 ​​are grounded; The phase compensation network circuit includes a resistor R503 and a capacitor C503, one end of the capacitor C503 is connected to the power supply VIN; the other end of the capacitor C503 is connected to one end of the resistor R503, and the other end of the resistor R503 is connected to the gate of the PMOS tube PM511; The output stage circuit includes a PMOS tube PM511, a resistor R501, a resistor R502, a capacitor C501 and a capacitor C502; the drain of the PMOS tube PM511 is connected to one end of the resistor R501 and one end of the capacitor C502, the capacitor C502 is connected in parallel to both ends of the resistor R501, the other end of the resistor R501 is connected to one end of the resistor R502, and the other end of the resistor R502 and the other end of the capacitor C502 are both grounded.

[0032] The high PSRR first internal LDO circuit structure proposed in the present invention is as follows Figure 3 As shown, considering that the reference voltage can work normally during creepage, the first internal LDO input stage adopts a dual input stage design, which are NM501, NM502, PM501, and PM502, respectively. This can broaden the common mode range of the input stage; the compensation network adopts type-2 and feedforward compensation, which are R503, C503, R501, C501, and R502, respectively; the power-on OK detection part can detect whether the buffer enters the voltage difference mode. When VIN is lower than the VOUT_PRIM design value, VFB will be lower than VREF, thereby making the input stage current unbalanced, which will cause vo1 to drop to 0, and turn off NM10, FAST becomes high, and thus FASTb becomes low, and vice versa.

[0033] like Figure 4 As shown, the voltage follower 2 includes a second bias circuit, a second error amplifier EA2, a load adaptive current bias circuit and a compensation circuit; The second bias circuit includes a current source I601, an NMOS transistor NM605, an NMOS transistor NM606, an NMOS transistor NM607, an NMOS transistor NM614, a PMOS transistor PM606, a PMOS transistor PM607 and a PMOS transistor PM608; The input end of the current source I601 is connected to the power source VIN; the output end of the current source I601 is simultaneously connected to the drain of the NMOS tube NM605, the gate of the NMOS tube NM605, and the gate of the NMOS tube NM606; the drain of the NMOS tube NM606 is simultaneously connected to the drain of the PMOS tube PM606, the gate of the PMOS tube PM606, the gate of the PMOS tube PM607, and the gate of the PMOS tube PM608; The drain of the PMOS tube PM607 is connected to the drain of the NMOS tube NM614 and the gate of the NMOS tube NM614 at the same time; the drain of the PMOS tube PM608 is connected to the drain of the NMOS tube NM607 and the gate of the NMOS tube NM607 at the same time; The source of the PMOS tube PM606, the source of the PMOS tube PM607, and the source of the PMOS tube PM608 are connected to the power source VIN; The source of the NMOS tube NM605, the source of the NMOS tube NM606, the source of the NMOS tube NM614, and the source of the NMOS tube NM607 are grounded; The second error amplifier EA2 includes a first-stage amplifier circuit, a second-stage amplifier circuit and a current detection circuit; The first stage amplifier circuit includes NMOS tube NM601, NMOS tube NM602, NMOS tube NM603, NMOS tube NM604, NMOS tube NM608, NMOS tube NM609, NMOS tube NM610, NMOS tube NM615, NMOS tube NM616, PMOS tube PM601, PMOS tube PM602, PMOS tube PM603 and PMOS tube PM604; The gate of the NMOS tube NM601 is connected to the positive electrode of the capacitor CF1 in the filter circuit 3, and the gate of the MOS tube NM602 is connected to the drain of the PMOS tube PM622; the gate of the NMOS tube NM601 is the positive input electrode of the second error amplifier EA2, and the gate of the NMOS tube NM602 is the negative input electrode of the second error amplifier EA2; The source of the NMOS tube NM601 is simultaneously connected to the source of the NMOS tube NM602 and the drain of the NMOS tube NM608, and the gate of the NMOS tube NM608 is simultaneously connected to the gate of the NMOS tube NM609, the gate of the NMOS tube NM610, and the gate of the NMOS tube NM607 in the second bias circuit; The drain of the NMOS tube NM601 is connected to the source of the NMOS tube NM603, the drain of the NMOS tube NM602 is connected to the source of the NMOS tube NM603, and the gate of the NMOS tube NM603 is connected to the gate of the NMOS tube NM604; The drain of the NMOS tube NM603 is connected to the drain of the PMOS tube PM601 and the source of the PMOS tube PM603 at the same time, the drain of the NMOS tube NM604 is connected to the drain of the PMOS tube PM602 and the source of the PMOS tube PM604 at the same time, and the source of the PMOS tube PM601 and the source of the PMOS tube PM602 are connected to the power supply VIN; The gate of the PMOS transistor PM601 is simultaneously connected to the gate of the PMOS transistor PM602, the gate of the PMOS transistor PM603, the drain of the PMOS transistor PM603, and the drain of the NMOS transistor NM615; the gate of the PMOS transistor PM604 is simultaneously connected to the drain of the PMOS transistor PM604 and the drain of the NMOS transistor NM616; The gate of the NMOS tube NM615 is connected to the gate of the NMOS tube NM616 and the gate of the NMOS tube NM614 in the second bias circuit at the same time; the source of the NMOS tube NM615 is connected to the drain of the NMOS tube NM609, and the source of the NMOS tube NM616 is connected to the drain of the NMOS tube NM610; The source of the NMOS tube NM608, the source of the NMOS tube NM609, and the source of the NMOS tube NM610 are grounded; The second stage amplifying circuit includes NMOS tube NM611, NMOS tube NM617, NMOS tube NM625, NMOS tube NM626, PMOS tube PM605 and PMOS tube PM609; The source of the PMOS tube PM609 and the source of the PMOS tube PM605 are connected to the power supply VIN; the gate of the PMOS tube PM609 is connected to the gate of the PMOS tube PM608 in the second bias circuit; the gate of the PMOS tube PM605 is connected to the gate of the PMOS tube PM604 in the first-stage amplifier circuit; the drain of the PMOS tube PM609 is simultaneously connected to the drain of the PMOS tube PM605, the drain of the NMOS tube NM617, and the drain of the NMOS tube NM625; the drain of the PMOS tube PM609 is the output end of the second error amplifier EA2; The gate of the NMOS tube NM617 is connected to the gate of the NMOS tube NM625 and the gate of the NMOS tube NM616 in the first-stage amplifier circuit at the same time; the source of the NMOS tube NM617 is connected to the drain of the NMOS tube NM611, the source of the NMOS tube NM625 is connected to the drain of the NMOS tube NM626, and the gate of the NMOS tube NM611 is connected to the gate of the NMOS tube NM610 in the first-stage amplifier circuit; The source of the NMOS tube NM611 and the source of the NMOS tube NM626 are grounded; The current detection circuit includes a PMOS tube PM621, a PMOS tube PM622, a PMOS tube PM625, a PMOS tube PM626, an NMOS tube NM618 and an NMOS tube NM619; The source of the PMOS tube PM621 and the source of the PMOS tube PM622 are connected to the power source VIN; The gate of the PMOS tube PM622 is connected to the gate of the PMOS tube PM621 and the drain of the PMOS tube PM609 in the second-stage amplifier circuit; the drain of the PMOS tube PM622 is connected to the source of the PMOS tube PM626 and the gate of the NMOS tube NM602 in the first-stage amplifier circuit; The drain of the PMOS tube PM621 is connected to the source of the PMOS tube PM625, the gate of the PMOS tube PM625 is simultaneously connected to the gate of the PMOS tube PM626, the drain of the PMOS tube PM626, and the drain of the NMOS tube NM619, and the drain of the PMOS tube PM625 is simultaneously connected to the drain of the NMOS tube NM618, the screen of the NMOS tube NM618, and the gate of the NMOS tube NM619; The source of the NMOS tube NM618 and the source of the NMOS tube NM619 are grounded; The load adaptive current bias circuit includes an NMOS tube NM612, an NMOS tube NM620, an NMOS tube NM621, an NMOS tube NM622, an NMOS tube NM623, a PMOS tube PM610, a PMOS tube PM611, a PMOS tube PM612, a PMOS tube PM613, a resistor R601 and a capacitor C601; The source of the PMOS tube PM610, the source of the PMOS tube PM611, the source of the PMOS tube PM612, and the source of the PMOS tube PM613 are connected to the power source VIN; The gate of the PMOS transistor PM610 is simultaneously connected to the drain of the PMOS transistor PM610, the gate of the PMOS transistor PM611, and the drain of the NMOS transistor NM620; the drain of the PMOS transistor PM611 is connected to the gate of the NMOS transistor NM612 and the gate of the NMOS transistor NM611 in the second-stage amplifier circuit; The gate of the PMOS tube PM612 is simultaneously connected to the drain of the PMOS tube PM612, the gate of the PMOS tube PM613, and the drain of the NMOS tube NM612; the source of the NMOS tube NM612 is connected to the drain of the NMOS tube NM621; the gate of the NMOS tube NM620 is simultaneously connected to the gate of the NMOS tube NM621 and the gate of the NMOS tube NM619 in the current detection circuit; The drain of the PMOS transistor PM613 is connected to the gate of the NMOS transistor NM622, the drain of the NMOS transistor NM622, and one end of the resistor R601. The other end of the resistor R601 is simultaneously connected to one end of the capacitor C601, the gate of the NMOS transistor NM623, and the gate of the NMOS transistor NM626 in the second-stage amplifier circuit; the other end of the capacitor C601 is grounded; the drain of the NMOS transistor NM623 is connected to the source of the NMOS transistor NM601 in the first-stage amplifier circuit; The source of the NMOS tube NM620, the source of the NMOS tube NM621, the source of the NMOS tube NM622, and the source of the NMOS tube NM623 are all grounded; The compensation circuit includes an NMOS tube NM613, an NMOS tube NM624, a PMOS tube PM614, a PMOS tube PM615, a PMOS tube PM616, a PMOS tube PM617, a PMOS tube PM623, a PMOS tube PM624, a resistor R602, a resistor R603, a resistor R604 and a capacitor C602; The source of the PMOS tube PM614 and the source of the PMOS tube PM616 are connected to the power source VIN; The gate of the PMOS tube PM614 is simultaneously connected to the drain of the PMOS tube PM614, the gate of the PMOS tube PM615, and the drain of the NMOS tube NM624. The gate of the NMOS tube NM624 is connected to the gate of the NMOS tube NM623 in the load adaptive current bias circuit. The source of the PMOS tube PM615 is connected to one end of the resistor R602, one end of the resistor R603, and the source of the PMOS tube PM623; the other end of the resistor R602 is connected to the drain of the PMOS tube PM602 in the first-stage amplifier circuit; the other end of the resistor R603 is connected to the source of the PMOS tube PM624 and one end of the resistor R604, and the other end of the resistor R604 is connected to the drain of the PMOS tube PM617; The drain of the PMOS transistor PM615 is simultaneously connected to one end of the capacitor C602, the drain of the PMOS transistor PM623, the drain of the PMOS transistor PM624, and the source of the PMOS transistor PM617; the other end of the capacitor C602 is simultaneously connected to the gate of the PMOS transistor PM623 and the gate of the PMOS transistor PM624; The gate of the PMOS tube PM617 is simultaneously connected to the gate of the PMOS tube PM616, the drain of the PMOS tube PM616, and the drain of the NMOS tube NM613; the gate of the NMOS tube NM613 is connected to the gate of the NMOS tube NM612 in the load adaptive current bias circuit; The source of the NMOS tube NM624 and the source of the NMOS tube NM613 are grounded; The high PSRR voltage follower circuit structure proposed in the present invention adopts a three-stage structure to improve PSRR: this architecture requires that the common-mode voltage of the input stage can also work normally in the power supply, so the first amplifier stage adopts the NMOS differential pair input stage quasi-folded common source and common gate (Folded Cascode) structure; the second amplifier stage adopts the common source amplifier circuit structure; the third stage is the output amplifier stage. The static current of this voltage follower increases adaptively with the increase of load current. The purpose of doing so is to gradually increase the system bandwidth with the increase of load, thereby widening the PSRR bandwidth and achieving low static power consumption and high PSRR. The specific design idea is that the input differential pair tail current gradually increases with the increase of load and quickly reaches the upper limit value, and the second-stage static bias current changes linearly with the load. The phase compensation network uses a Miller compensation with a dynamic zeroing resistor in a cross-connected manner between the output end with a certain driving capability of the first stage and the output of the second stage to stabilize the system. The zero point position of the compensation scheme will be adaptively adjusted with the load change to match the requirements of the loop characteristics under different loads, thereby achieving system loop stability under full load.

[0034] The present invention solves the technical problem that the traditional architecture must use a large off-chip capacitor to implement a low-cutoff frequency low-pass filter circuit in a traditional high-PSRR LDO architecture, and uses on-chip devices to implement a high-PSRR LDO architecture with low power consumption without increasing too much area, wherein a voltage reference source generates a reference voltage VREF, and the reference voltage VREF is amplified to a normal output voltage (VOUT_PRIM) by a first internal LDO (Internal LDO), and the noise and PSRR of the voltage reference source and the first internal LDO themselves are filtered out by a third low-pass filter to completely filter out high-frequency ripple signals, thereby providing a stable and clean output reference voltage (VOUT_CLEAN) for a second voltage follower, so that the performance requirements for the voltage reference source and the first internal LDO can be reduced, thereby greatly reducing the system overhead.

[0035] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is therefore intended that all changes that fall within the meaning and range of equivalents of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0036] In addition, it should be understood that although the present specification is described in accordance with implementation methods, not every implementation method includes only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A high power supply rejection ratio low noise LDO implementation circuit, characterized in that: It includes a voltage reference source, an internal LDO circuit (1), a voltage follower (2), a filter circuit (3) and a non-overlapping clock generation circuit; The internal LDO circuit (1) comprises a first error amplifier EA1, a first bias circuit, an output stage circuit, a phase compensation network circuit and a power-on OK detection circuit; an input VREF of a voltage reference source is connected to an input positive terminal of the first error amplifier EA1, an output terminal of the first error amplifier EA1 is connected to a gate of a PMOS transistor PM511 in the output stage circuit, a source of the PMOS transistor PM511 in the output stage circuit is connected to a power supply VIN, a drain of the PMOS transistor PM511 in the output stage circuit is connected to one end of a resistor divider R501, the other end of the resistor divider R501 is simultaneously connected to an input negative terminal of the first error amplifier EA1 and one end of a resistor R502, and the other end of the resistor R502 is grounded; a drain of the PMOS transistor PM511 is connected to an input terminal of the power-on OK detection circuit, and the other input terminal of the power-on OK detection circuit is connected to the power supply VIN; The phase compensation network circuit is connected to the gate of the PMOS tube PM511 in the output stage circuit; The first bias circuit is electrically connected to the first error amplifier EA1 and the power-on OK detection circuit; The filter circuit (3) comprises a PMOS transistor PM301, a PMOS transistor PM302, a PMOS transistor PM303, a resistor RF1, a capacitor Csmall, a capacitor Cbig and a capacitor CF1, the source of the PMOS transistor PM303 and the source of the PMOS transistor PM301 are both connected to the drain of the PMOS transistor PM511, the gate of the PMOS transistor PM303 is connected to the output end of the power-on OK detection circuit, the gate of the PMOS transistor PM301 is connected to the output signal PH1b of the non-overlapping clock generation circuit, and the PMOS transistor PM30 The drain of PMOS transistor PM301 is connected to the drain of PMOS transistor PM302 and the positive electrode of capacitor Cbig, and the negative electrode of capacitor Cbig is grounded; the drain of PMOS transistor PM301 is connected to the source of PMOS transistor PM302 and the positive electrode of capacitor Csmall, and the negative electrode of capacitor Csmall is grounded; the gate of PMOS transistor PM302 is connected to the output signal PH2b of the non-overlapping clock generating circuit, the positive electrode of capacitor Cbig is connected to one end of resistor RF1, the other end of resistor RF1 is connected to the positive electrode of capacitor CF1, and the negative electrode of capacitor CF1 is grounded; The voltage follower (2) comprises a second error amplifier EA2 and a PMOS tube PM622, wherein the positive input terminal of the second error amplifier EA2 is connected to the positive electrode of the capacitor CF1, the negative input terminal of the second error amplifier EA2 is connected to the power supply VOUT, the output terminal of the second error amplifier EA2 is connected to the gate of the PMOS tube PM622, the source of the PMOS tube PM622 is connected to the power supply VIN, and the drain of the PMOS tube PM622 is connected to the power supply VOUT.

2. A high power supply rejection ratio low noise LDO implementation circuit according to claim 1, characterized in that: The non-overlapping clock generating circuit includes a NAND gate NAND1, a NAND gate NAND2, a NOT gate INV0, a ​​NOT gate INV1, a NOT gate INV2, a NOT gate INV3, a NOT gate INV4, a NOT gate INV5, a NOT gate INV6, a NOT gate INV7, a NOT gate INV8, a NOT gate INV9, a NOT gate INV10, a NOT gate INV11, a NOT gate INV12, a resistor R11, a resistor R12, a capacitor C1 and a capacitor C2; The CLK signal is simultaneously connected to one input terminal of the NAND gate NAND1 and the input terminal of the NAND gate INV0, and the other input terminal of the NAND gate NAND1 is connected to the output terminal of the NAND gate INV10; The output end of the NOT gate INV0 is connected to one input end of the NAND gate NAND2, and the other input end of the NAND gate NAND2 is connected to the output end of the NAND gate INV4; The output end of the AND gate NAND1 is connected to the input end of the NOT gate INV1, the output end of the NOT gate INV1 is connected to the input end of the NOT gate INV2, the output end of the NOT gate INV2 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the positive electrode of the capacitor C1 and the input end of the NOT gate INV3, the output end of the NOT gate INV3 is connected to the input end of the NOT gate INV4, the output end of the NOT gate INV4 is connected to the input end of the NOT gate INV5, the output end of the NOT gate INV5 is connected to the input end of the NOT gate INV6, and the output end of the NOT gate INV6 outputs the signal PH1b; the negative electrode of the capacitor C1 is grounded; The output end of the AND gate NAND2 is connected to the input end of the NOT gate INV7, the output end of the NOT gate INV7 is connected to the input end of the NOT gate INV8, the output end of the NOT gate INV8 is connected to one end of the resistor R12, the other end of the resistor R12 is simultaneously connected to the positive electrode of the capacitor C2 and the input end of the NOT gate INV9, the output end of the NOT gate INV9 is connected to the input end of the NOT gate INV10, the output end of the NOT gate INV10 is connected to the input end of the NOT gate INV11, the output end of the NOT gate INV11 is connected to the input end of the NOT gate INV12, and the output end of the NOT gate INV12 outputs the signal PH2b; the negative electrode of the capacitor C2 is grounded.

3. A high power supply rejection ratio low noise LDO implementation circuit according to claim 2, characterized in that: The first error amplifier EA1 in the internal LDO circuit (1) comprises an NMOS tube NM501, an NMOS tube NM502, an NMOS tube NM506, an NMOS tube NM507, an NMOS tube NM508, an NMOS tube NM509, an NMOS tube NM513, an NMOS tube NM514, a PMOS tube PM503, a PMOS tube PM504, a PMOS tube PM501 and a PMOS tube PM502; The source of the PMOS tube PM503 and the source of the PMOS tube PM504 are connected to the power source VIN; the gate of the PMOS tube PM503 is connected to the drain of the PMOS tube PM503, the gate of the PMOS tube PM504, and the drain of the NMOS tube NM513; the drain of the PMOS tube PM504 is connected to the drain of the NMOS tube NM514; The gate of NMOS tube NM513 is connected to the gate of NMOS tube NM514, the source of NMOS tube NM513 is connected to the drain of NMOS tube NM501 and the drain of NMOS tube NM506 at the same time; the source of NMOS tube NM514 is connected to the drain of NMOS tube NM502 and the drain of NMOS tube NM509 at the same time; The gate of the NMOS tube NM501 is connected to the gate of the PMOS tube PM502; the gate of the NMOS tube NM502 is connected to the gate of the PMOS tube PM501 and the output VREF of the voltage reference source; the gate of the NMOS tube NM501 is the input negative electrode of the first error amplifier EA1; the gate of the NMOS tube NM502 is the input positive electrode of the first error amplifier EA1; the drain of the NMOS tube NM514 is the output end of the first error amplifier EA1; The drain of the PMOS tube PM501 is simultaneously connected to the gate of the NMOS tube NM506, the gate of the NMOS tube NM507, and the drain of the NMOS tube NM507; the source of the NMOS tube NM506 and the source of the NMOS tube NM507 are both grounded; the drain of the PMOS tube PM502 is simultaneously connected to the gate of the NMOS tube NM508, the gate of the NMOS tube NM509, and the drain of the NMOS tube NM508; the source of the NMOS tube NM508 and the source of the NMOS tube NM509 are both grounded.

4. A high power supply rejection ratio low noise LDO implementation circuit according to claim 3, characterized in that: The power-on OK detection circuit in the internal LDO circuit (1) comprises a PMOS tube PM507, a PMOS tube PM508, an NMOS tube NM510 and an NMOS tube NM511, the source of the PMOS tube PM507 ​​and the source of the PMOS tube PM508 are both connected to the power source VIN, the drain of the PMOS tube PM507 ​​is simultaneously connected to the gate of the PMOS tube PM508, the drain of the NMOS tube NM510 and the gate of the NMOS tube NM511, and the drain of the NMOS tube NM511 is simultaneously connected to the drain of the PMOS tube PM508 and the gate of the PMOS tube PM303 in the filter circuit (3); The gate of the NMOS tube NM510 is connected to the drain of the NMOS tube NM514 and the gate of the PMOS tube PM511 in the output stage circuit; the source of the NMOS tube NM510 and the source of the NMOS tube NM511 are both grounded.

5. A high power supply rejection ratio low noise LDO implementation circuit according to claim 4, characterized in that: The first bias circuit in the internal LDO circuit (1) comprises an NMOS transistor NM503, an NMOS transistor NM504, an NMOS transistor NM505, an NMOS transistor NM512, a PMOS transistor PM505, a PMOS transistor PM506, a current source I501 and a current source I502; The input end of the current source I501 and the input end of the current source I502 are both connected to the power source VIN; the output end of the current source I501 is simultaneously connected to the gate of the NMOS tube NM512, the drain of the NMOS tube NM512, and the gate of the NMOS tube NM513; the source of the NMOS tube NM512 is grounded; the output end of the current source I502 is simultaneously connected to the gate of the NMOS tube NM503, the drain of the NMOS tube NM503, the gate of the NMOS tube NM504, and the gate of the NMOS tube NM505; The drain of NMOS tube NM504 is connected to the source of NMOS tube NM501; the drain of NMOS tube NM505 ​​is connected to the drain of PMOS tube PM505, the gate of PMOS tube PM505, the gate of PMOS tube PM506, and the gate of PMOS tube PM507; the source of PMOS tube PM505 and the source of PMOS tube PM506 are both connected to the power supply VIN; the source of MOS tube NM503, the source of NMOS tube NM504, and the source of NMOS tube NM505 ​​are grounded.

6. A high power supply rejection ratio low noise LDO implementation circuit according to claim 5, characterized in that: The phase compensation network circuit in the internal LDO circuit (1) comprises a resistor R503 and a capacitor C503, one end of the capacitor C503 is connected to the power source VIN; the other end of the capacitor C503 is connected to one end of the resistor R503, and the other end of the resistor R503 is connected to the gate of the PMOS tube PM511; The output stage circuit in the internal LDO circuit (1) comprises a PMOS transistor PM511, a resistor R501, a resistor R502, a capacitor C501 and a capacitor C502; the drain of the PMOS transistor PM511 is connected to one end of the resistor R501 and one end of the capacitor C502, the capacitor C502 is connected in parallel to both ends of the resistor R501, the other end of the resistor R501 is connected to one end of the resistor R502, and the other end of the resistor R502 and the other end of the capacitor C502 are both grounded.

7. A high power supply rejection ratio low noise LDO implementation circuit according to claim 6, characterized in that: The voltage follower (2) comprises a second bias circuit, a second error amplifier EA2, a load adaptive current bias circuit and a compensation circuit; The second bias circuit in the voltage follower (2) comprises a current source I601, an NMOS transistor NM605, an NMOS transistor NM606, an NMOS transistor NM607, an NMOS transistor NM614, a PMOS transistor PM606, a PMOS transistor PM607 and a PMOS transistor PM608; The input end of the current source I601 is connected to the power source VIN; the output end of the current source I601 is simultaneously connected to the drain of the NMOS tube NM605, the gate of the NMOS tube NM605, and the gate of the NMOS tube NM606; the drain of the NMOS tube NM606 is simultaneously connected to the drain of the PMOS tube PM606, the gate of the PMOS tube PM606, the gate of the PMOS tube PM607, and the gate of the PMOS tube PM608; The drain of the PMOS tube PM607 is connected to the drain of the NMOS tube NM614 and the gate of the NMOS tube NM614 at the same time; the drain of the PMOS tube PM608 is connected to the drain of the NMOS tube NM607 and the gate of the NMOS tube NM607 at the same time; The source of the PMOS tube PM606, the source of the PMOS tube PM607, and the source of the PMOS tube PM608 are connected to the power source VIN; The source of the NMOS tube NM605 , the source of the NMOS tube NM606 , the source of the NMOS tube NM614 , and the source of the NMOS tube NM607 are grounded.

8. A high power supply rejection ratio low noise LDO implementation circuit according to claim 7, characterized in that: The second error amplifier EA2 in the voltage follower (2) comprises a first-stage amplifier circuit / a second-stage amplifier circuit and a current detection circuit; The first stage amplifier circuit includes NMOS tube NM601, NMOS tube NM602, NMOS tube NM603, NMOS tube NM604, NMOS tube NM608, NMOS tube NM609, NMOS tube NM610, NMOS tube NM615, NMOS tube NM616, PMOS tube PM601, PMOS tube PM602, PMOS tube PM603 and PMOS tube PM604; The gate of the NMOS tube NM601 is connected to the positive electrode of the capacitor CF1 in the filter circuit (3), and the gate of the MOS tube NM602 is connected to the drain of the PMOS tube PM622; the gate of the NMOS tube NM601 is the positive input electrode of the second error amplifier EA2, and the gate of the NMOS tube NM602 is the negative input electrode of the second error amplifier EA2; The source of the NMOS tube NM601 is simultaneously connected to the source of the NMOS tube NM602 and the drain of the NMOS tube NM608, and the gate of the NMOS tube NM608 is simultaneously connected to the gate of the NMOS tube NM609, the gate of the NMOS tube NM610, and the gate of the NMOS tube NM607 in the second bias circuit; The drain of the NMOS tube NM601 is connected to the source of the NMOS tube NM603, the drain of the NMOS tube NM602 is connected to the source of the NMOS tube NM603, and the gate of the NMOS tube NM603 is connected to the gate of the NMOS tube NM604; The drain of the NMOS tube NM603 is connected to the drain of the PMOS tube PM601 and the source of the PMOS tube PM603 at the same time, the drain of the NMOS tube NM604 is connected to the drain of the PMOS tube PM602 and the source of the PMOS tube PM604 at the same time, and the source of the PMOS tube PM601 and the source of the PMOS tube PM602 are connected to the power supply VIN; The gate of the PMOS transistor PM601 is simultaneously connected to the gate of the PMOS transistor PM602, the gate of the PMOS transistor PM603, the drain of the PMOS transistor PM603, and the drain of the NMOS transistor NM615; the gate of the PMOS transistor PM604 is simultaneously connected to the drain of the PMOS transistor PM604 and the drain of the NMOS transistor NM616; The gate of the NMOS tube NM615 is connected to the gate of the NMOS tube NM616 and the gate of the NMOS tube NM614 in the second bias circuit at the same time; the source of the NMOS tube NM615 is connected to the drain of the NMOS tube NM609, and the source of the NMOS tube NM616 is connected to the drain of the NMOS tube NM610; The source of the NMOS tube NM608, the source of the NMOS tube NM609, and the source of the NMOS tube NM610 are grounded; The second stage amplifying circuit includes NMOS tube NM611, NMOS tube NM617, NMOS tube NM625, NMOS tube NM626, PMOS tube PM605 and PMOS tube PM609; The source of the PMOS tube PM609 and the source of the PMOS tube PM605 are connected to the power supply VIN; the gate of the PMOS tube PM609 is connected to the gate of the PMOS tube PM608 in the second bias circuit; the gate of the PMOS tube PM605 is connected to the gate of the PMOS tube PM604 in the first-stage amplifier circuit; the drain of the PMOS tube PM609 is simultaneously connected to the drain of the PMOS tube PM605, the drain of the NMOS tube NM617, and the drain of the NMOS tube NM625; the drain of the PMOS tube PM609 is the output end of the second error amplifier EA2; The gate of the NMOS tube NM617 is connected to the gate of the NMOS tube NM625 and the gate of the NMOS tube NM616 in the first-stage amplifier circuit at the same time; the source of the NMOS tube NM617 is connected to the drain of the NMOS tube NM611, the source of the NMOS tube NM625 is connected to the drain of the NMOS tube NM626, and the gate of the NMOS tube NM611 is connected to the gate of the NMOS tube NM610 in the first-stage amplifier circuit; The source of the NMOS tube NM611 and the source of the NMOS tube NM626 are grounded; The current detection circuit includes a PMOS tube PM621, a PMOS tube PM622, a PMOS tube PM625, a PMOS tube PM626, an NMOS tube NM618 and an NMOS tube NM619; The source of the PMOS tube PM621 and the source of the PMOS tube PM622 are connected to the power source VIN; The gate of the PMOS tube PM622 is connected to the gate of the PMOS tube PM621 and the drain of the PMOS tube PM609 in the second-stage amplifier circuit; the drain of the PMOS tube PM622 is connected to the source of the PMOS tube PM626 and the gate of the NMOS tube NM602 in the first-stage amplifier circuit; The drain of the PMOS tube PM621 is connected to the source of the PMOS tube PM625, the gate of the PMOS tube PM625 is simultaneously connected to the gate of the PMOS tube PM626, the drain of the PMOS tube PM626, and the drain of the NMOS tube NM619, and the drain of the PMOS tube PM625 is simultaneously connected to the drain of the NMOS tube NM618, the screen of the NMOS tube NM618, and the gate of the NMOS tube NM619; The source of the NMOS tube NM618 and the source of the NMOS tube NM619 are grounded.

9. A high power supply rejection ratio low noise LDO implementation circuit according to claim 8, characterized in that: The load adaptive current bias circuit in the voltage follower (2) comprises an NMOS tube NM612, an NMOS tube NM620, an NMOS tube NM621, an NMOS tube NM622, an NMOS tube NM623, a PMOS tube PM610, a PMOS tube PM611, a PMOS tube PM612, a PMOS tube PM613, a resistor R601 and a capacitor C601; The source of the PMOS tube PM610, the source of the PMOS tube PM611, the source of the PMOS tube PM612, and the source of the PMOS tube PM613 are connected to the power source VIN; The gate of the PMOS transistor PM610 is simultaneously connected to the drain of the PMOS transistor PM610, the gate of the PMOS transistor PM611, and the drain of the NMOS transistor NM620; the drain of the PMOS transistor PM611 is connected to the gate of the NMOS transistor NM612 and the gate of the NMOS transistor NM611 in the second-stage amplifier circuit; The gate of the PMOS tube PM612 is simultaneously connected to the drain of the PMOS tube PM612, the gate of the PMOS tube PM613, and the drain of the NMOS tube NM612; the source of the NMOS tube NM612 is connected to the drain of the NMOS tube NM621; the gate of the NMOS tube NM620 is simultaneously connected to the gate of the NMOS tube NM621 and the gate of the NMOS tube NM619 in the current detection circuit; The drain of the PMOS transistor PM613 is connected to the gate of the NMOS transistor NM622, the drain of the NMOS transistor NM622, and one end of the resistor R601. The other end of the resistor R601 is simultaneously connected to one end of the capacitor C601, the gate of the NMOS transistor NM623, and the gate of the NMOS transistor NM626 in the second-stage amplifier circuit; the other end of the capacitor C601 is grounded; the drain of the NMOS transistor NM623 is connected to the source of the NMOS transistor NM601 in the first-stage amplifier circuit; The source of the NMOS tube NM620 , the source of the NMOS tube NM621 , the source of the NMOS tube NM622 , and the source of the NMOS tube NM623 are all grounded.

10. A high power supply rejection ratio low noise LDO implementation circuit according to claim 9, characterized in that: The compensation circuit in the voltage follower (2) comprises an NMOS transistor NM613, an NMOS transistor NM624, a PMOS transistor PM614, a PMOS transistor PM615, a PMOS transistor PM616, a PMOS transistor PM617, a PMOS transistor PM623, a PMOS transistor PM624, a resistor R602, a resistor R603, a resistor R604 and a capacitor C602; The source of the PMOS tube PM614 and the source of the PMOS tube PM616 are connected to the power source VIN; The gate of the PMOS tube PM614 is simultaneously connected to the drain of the PMOS tube PM614, the gate of the PMOS tube PM615, and the drain of the NMOS tube NM624. The gate of the NMOS tube NM624 is connected to the gate of the NMOS tube NM623 in the load adaptive current bias circuit. The source of the PMOS tube PM615 is connected to one end of the resistor R602, one end of the resistor R603, and the source of the PMOS tube PM623; the other end of the resistor R602 is connected to the drain of the PMOS tube PM602 in the first-stage amplifier circuit; the other end of the resistor R603 is connected to the source of the PMOS tube PM624 and one end of the resistor R604, and the other end of the resistor R604 is connected to the drain of the PMOS tube PM617; The drain of the PMOS transistor PM615 is simultaneously connected to one end of the capacitor C602, the drain of the PMOS transistor PM623, the drain of the PMOS transistor PM624, and the source of the PMOS transistor PM617; the other end of the capacitor C602 is simultaneously connected to the gate of the PMOS transistor PM623 and the gate of the PMOS transistor PM624; The gate of the PMOS tube PM617 is simultaneously connected to the gate of the PMOS tube PM616, the drain of the PMOS tube PM616, and the drain of the NMOS tube NM613; the gate of the NMOS tube NM613 is connected to the gate of the NMOS tube NM612 in the load adaptive current bias circuit; The source of the NMOS tube NM624 and the source of the NMOS tube NM613 are grounded.

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