Undershoot voltage generating circuit

Abstract

The invention belongs to the field of radio frequency circuits, and relates to an undershoot voltage generating circuit, which adopts a resistor R1 and a capacitor C1 to stabilize the circuit, and a current source Ib provides operational amplifier bias current. The MOS transistor P5 serves as a current-voltage conversion tube, the drain electrode of the MOS transistor P5 is connected with the four voltage regulation and control resistors connected in series, and the grid electrode of the MOS transistor P5 is connected with the output end of the clamping operational amplifier. And the clamping operational amplifier associates node voltage VX with reference voltage VREF, and dynamically regulates and controls grid voltage of the MOS transistor P5 through a feedback loop. And the MOS transistor P6, the MOS transistor Q6 and the MOS transistor Q7 form a current mirror image circuit which is used for copying the grid voltage of the MOS transistor P5 so as to generate the reference current. The reference current is injected into the RC low-pass circuit, and finally undershoot voltage is generated. The problem of overshoot fluctuation difficult to test existing in circuits such as a power amplifier is solved.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency circuits, and in particular relates to an undershoot voltage generating circuit. Background Art

[0002] Analog LDO (low dropout linear regulator) is widely used in low-input, high-precision power supply circuits due to its advantages such as low power consumption, high integration, low noise, and adjustable temperature coefficient. Especially in the receiving and transmitting parts of RF circuits, low-noise amplifiers, power amplifiers, and mixers all require analog LDOs with low noise, high power supply rejection ratio, and built-in temperature coefficient to optimize the temperature characteristics of the circuit and improve the linearity of the circuit. Among them, circuits such as power amplifiers have overshoot fluctuations that are difficult to test. It is easier to solve this problem in analog LDOs used for power supply than in power amplifiers.

[0003] Therefore, how to make the analog LDO output voltage undershoot at the initial startup and restore to the default value after a period of time has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an undershoot voltage generating circuit to introduce an undershoot voltage that can be maintained for a certain period of time when the analog LDO circuit is started, so as to solve the problem of overshoot fluctuations in circuits such as power amplifiers that are difficult to test.

[0005] The present invention is achieved in that: An undershoot voltage generating circuit, the undershoot voltage generating circuit comprising: Resistors RT1, RT2, RT3 and RT4 are connected in series in sequence and connected to one end of capacitor C2 to form an RC low-pass circuit. The other end of capacitor C2 is grounded. A voltage output end VOUT is between resistor RT4 and capacitor C2. The other end of resistor RT1 is connected to a reference voltage VREF. MOS transistor P7, MOS transistor P8, MOS transistor P4 and MOS transistor Q8, MOS transistor Q9, MOS transistor Q10 and MOS transistor Q11 constitute an enable control circuit, wherein the gate of MOS transistor Q10 is connected to the gate of MOS transistor P7 and to the control signal EN, the drain of MOS transistor Q10 is connected to the drain of MOS transistor P7 and to the gate of MOS transistor P4, the source of MOS transistor Q10 is grounded, the sources of MOS transistor P7 and MOS transistor P4 are connected to the power supply VDD, the drain of MOS transistor P4 is connected to the gate of MOS transistor P5, and is used to control the on and off of MOS transistor P5; the drain of MOS transistor P4 is connected to the gate of MOS transistor P6, the source of MOS transistor P6 is connected to the power supply VDD, the drain of MOS transistor P6 is connected to the drain and gate of MOS transistor Q7, the gate of MOS transistor Q7 is connected to the gate of MOS transistor Q6, the source of MOS transistor Q6 is grounded, the drain of MOS transistor Q6 is connected to the reference voltage VREF, and the source of MOS transistor Q7 is grounded; The drain of the MOS transistor Q11 is connected to the drain of the MOS transistor P8, and is connected to the gates of the MOS transistor Q8 and the MOS transistor Q9, and is used to control the on and off of the MOS transistor Q8 and the MOS transistor Q9. The source of the MOS transistor Q11 is grounded, and the source of the MOS transistor P8 is connected to the power supply VDD. The gates of the MOS transistor P8 and the MOS transistor Q11 are connected and then connected to the gate of the MOS transistor P4. MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor Q3, MOS transistor Q4, MOS transistor Q5, current source Ib, resistor R1 and capacitor C1 form a clamping operational amplifier; wherein, the gate of MOS transistor P1 is connected to reference voltage VREF, the source of MOS transistor P1 is connected to current source Ib, and current source Ib is connected to power supply VDD; the gate of MOS transistor P2 is connected to the drain of MOS transistor P5; the source of MOS transistor P2 is connected to current source Ib; the drain of MOS transistor P1 is connected to the drain and gate of MOS transistor Q4, and is also connected to the drain of MOS transistor Q9; the drain of MOS transistor P2 is connected to the drain of MOS transistor Q5, the gate of MOS transistor Q5 is connected to the gate of MOS transistor Q4, and the source of MOS transistor Q5, the source of MOS transistor Q9, and the source of MOS transistor Q4 are grounded; The gate of the MOS transistor Q8 is connected to the gate of the MOS transistor Q9, the drain of the MOS transistor Q8 is connected to one end of the resistor R1 and the drain of the MOS transistor Q5, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain of the MOS transistor Q3, the gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q8, the source of the MOS transistor Q3 is grounded, the drain of the MOS transistor Q3 is connected to the drain of the MOS transistor P3, and the gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q5; The gate of the MOS transistor P3 is powered by a bias voltage Vb provided by an external circuit, the source of the MOS transistor P3 is connected to the power supply VDD, the drain of the MOS transistor P3 is connected to the gate of the MOS transistor P5, and the source of the MOS transistor P5 is connected to the power supply VDD; the drain of the MOS transistor P5 is connected to four voltage control resistors RV1, RV2, R3 and RV4 connected in series, the other end of the voltage control resistor RV4 is grounded, and the drain of the MOS transistor P5 is the node voltage VX.

[0006] Furthermore, the resistor R1 and the capacitor C1 are used to stabilize the circuit, and the current source Ib provides an operational amplifier bias current; the MOS transistor P5 is used as a current-voltage conversion tube, and the gate is connected to the output end of the clamping operational amplifier; the clamping operational amplifier associates the node voltage VX with the reference voltage VREF, and dynamically adjusts the gate voltage of the MOS transistor P5 through a feedback loop; the MOS transistor P6 and the MOS transistor Q6 and the MOS transistor Q7 form a current mirror circuit, which is used to copy the gate voltage of the MOS transistor P5, and then generate a reference current.

[0007] Furthermore, the reference current is injected into the RC low-pass circuit to generate an undershoot voltage.

[0008] Compared with the prior art, the present invention has the following beneficial effects: the circuit structure is simple, easy to transplant, the undershoot voltage accuracy is high, and the circuit power consumption is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a circuit structure provided by an embodiment of the present invention; Figure 2 yes Figure 1 The waveform diagram of the undershoot voltage generating circuit shown. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0011] In view of the fact that in the prior art, the power amplifier itself has a certain temperature coefficient, which will affect its gain and power linearity, it is easier to solve this problem in the analog LDO used for power supply than in the power amplifier.

[0012] The present invention provides an undershoot voltage generating circuit. After the undershoot voltage generating circuit is connected to a main circuit, when the main circuit is started, an undershoot voltage that can last for a period of time is introduced into the output voltage. After the startup is completed, the undershoot voltage generating circuit will be closed and the output voltage will return to a normal value.

[0013] Please refer to Figure 1 The embodiment of the present invention provides an undershoot voltage generating circuit. The undershoot voltage generating circuit includes an RC low-pass circuit and an enable control circuit. Resistors RT1, RT2, RT3 and RT4 are connected in series in sequence and connected to one end of capacitor C2 to form an RC low-pass circuit. The other end of capacitor C2 is connected to the ground GND. A voltage output terminal VOUT is between resistor RT4 and capacitor C2. The other end of resistor RT1 is connected to a reference voltage VREF. MOS transistor P7, MOS transistor P8, MOS transistor P4, MOS transistor Q8, MOS transistor Q9, MOS transistor Q10 and MOS transistor Q11 constitute an enable control circuit, wherein the gate of MOS transistor Q10 is connected to the gate of MOS transistor P7 and to the control signal EN. Figure 1 The two nodes a in the diagram represent connection. The drain of the MOS transistor Q10 is connected to the drain of the MOS transistor P7 and to the gate of the MOS transistor P4. The source of the MOS transistor Q10 is connected to the ground line GND. The sources of the MOS transistors P7 and P4 are connected to the power supply VDD. The drain of the MOS transistor P4 is connected to the gate of the MOS transistor P5 for controlling the on and off of the MOS transistor P5. The drain of the MOS transistor P4 is connected to the gate of the MOS transistor P6. The source of the MOS transistor P6 is connected to the power supply VDD. The drain of the MOS transistor P6 is connected to the drain and gate of the MOS transistor Q7. The gate of the MOS transistor Q7 is connected to the gate of the MOS transistor Q6. The source of the MOS transistor Q6 is grounded. The drain of the MOS transistor Q6 is connected to the reference voltage VREF. The source of the MOS transistor Q7 is grounded.

[0014] The drain of the MOS transistor Q11 is connected to the drain of the MOS transistor P8. Figure 1It is marked as node b and is connected to the gates of MOS transistor Q8 and MOS transistor Q9, and is used to control the on and off of MOS transistor Q8 and MOS transistor Q9. The source of MOS transistor Q11 is connected to the ground line GND, and the source of MOS transistor P8 is connected to the power supply VDD; the gates of MOS transistor P8 and MOS transistor Q11 are connected to the gate of MOS transistor P4.

[0015] MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor Q3, MOS transistor Q4, MOS transistor Q5, current source Ib, resistor R1 and capacitor C1 form a clamping operational amplifier; wherein, the gate of MOS transistor P1 is connected to reference voltage VREF, the source of MOS transistor P1 is connected to current source Ib, and current source Ib is connected to power supply VDD; the gate of MOS transistor P2 is connected to the drain of MOS transistor P5, that is, node voltage VX; the source of MOS transistor P2 is connected to current source Ib, and current source Ib is connected to power supply VDD; the drain of MOS transistor P1 is connected to the drain and gate of MOS transistor Q4, and is also connected to the drain of MOS transistor Q9; the drain of MOS transistor P2 is connected to the drain of MOS transistor Q5, the gate of MOS transistor Q5 is connected to the gate of MOS transistor Q4, and the source of MOS transistor Q5, the source of MOS transistor Q9, and the source of MOS transistor Q4 are grounded; The gate of MOS transistor Q8 is connected to the gate of MOS transistor Q9, the drain of MOS transistor Q8 is connected to one end of resistor R1 and the drain of MOS transistor Q5, the other end of resistor R1 is connected to one end of capacitor C1, the other end of capacitor C1 is connected to the drain of MOS transistor Q3, the gate of MOS transistor Q3 is connected to the drain of MOS transistor Q8, the source of MOS transistor Q3 is grounded, the drain of MOS transistor Q3 is connected to the drain of MOS transistor P3, and the gate of MOS transistor Q3 is connected to the drain of MOS transistor Q5.

[0016] The gate of the MOS transistor P3 is powered by a bias voltage Vb provided by an external circuit, the source of the MOS transistor P3 is connected to the power supply VDD, the drain of the MOS transistor P3 is connected to the gate of the MOS transistor P5, the source of the MOS transistor P5 is connected to the power supply VDD, the drain of the MOS transistor P5 is connected to four voltage control resistors RV1, voltage control resistor RV2, voltage control resistor R3 and voltage control resistor RV4 connected in series, the other end of the voltage control resistor RV4 is grounded, and the drain of the MOS transistor P5 is the node voltage VX.

[0017] Among them, the resistor R1 and the capacitor C1 are used to stabilize the circuit, and the current source Ib provides the operational amplifier bias current. The MOS transistor P5 is used as a current-voltage conversion tube, and the drain is connected to four voltage control resistors RV1, RV2, R3 and RV4 connected in series, and the gate is connected to the output end of the clamping operational amplifier. The clamping operational amplifier associates the node voltage VX with the reference voltage VREF, and dynamically regulates the gate voltage of the MOS transistor P5 through a feedback loop. The MOS transistor P6 and the MOS transistor Q6 and the MOS transistor Q7 form a current mirror circuit, which is used to copy the gate voltage of the MOS transistor P5 and then generate a reference current. The reference current is injected into the RC low-pass circuit, and finally an undershoot voltage is generated. In addition, the MOS transistor P7, the MOS transistor P8, the MOS transistor P4 and the MOS transistors Q8~Q11 form an enable control circuit. The timing setting of the control signal EN is the same as the enable signal of the main circuit, which is used to associate the main circuit with the undershoot voltage generation circuit, so that when the main circuit is started, the undershoot voltage generation circuit is turned on and the output voltage of the main circuit is undershoot. After the main circuit is started up, the undershoot voltage generating circuit is turned off.

[0018] Figure 2 It is a waveform diagram of the undershoot voltage generation circuit. REF It is the transient reference voltage generated after the reference current is injected into the resistor. V OUT is the output voltage of the undershoot voltage generation circuit. LDO_VOUT is the LDO output voltage to which the undershoot voltage generation circuit is applied.

[0019] Please refer to Figure 2 In the initial startup stage, VOUT experiences a slow rise. Since the analog LDO output voltage follows the VOUT change trend, an undershoot voltage that can last for a period of time is introduced into the analog LDO output voltage.

[0020] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An undershoot voltage generating circuit, characterized in that: The undershoot voltage generating circuit comprises: Resistors RT1, RT2, RT3 and RT4 are connected in series in sequence and connected to one end of capacitor C2 to form an RC low-pass circuit. The other end of capacitor C2 is grounded. A voltage output end VOUT is between resistor RT4 and capacitor C2. The other end of resistor RT1 is connected to a reference voltage VREF. MOS transistor P7, MOS transistor P8, MOS transistor P4 and MOS transistor Q8, MOS transistor Q9, MOS transistor Q10 and MOS transistor Q11 constitute an enable control circuit, wherein the gate of MOS transistor Q10 is connected to the gate of MOS transistor P7 and to the control signal EN, the drain of MOS transistor Q10 is connected to the drain of MOS transistor P7 and to the gate of MOS transistor P4, the source of MOS transistor Q10 is grounded, the sources of MOS transistor P7 and MOS transistor P4 are connected to the power supply VDD, the drain of MOS transistor P4 is connected to the gate of MOS transistor P5, and is used to control the on and off of MOS transistor P5; the drain of MOS transistor P4 is connected to the gate of MOS transistor P6, the source of MOS transistor P6 is connected to the power supply VDD, the drain of MOS transistor P6 is connected to the drain and gate of MOS transistor Q7, the gate of MOS transistor Q7 is connected to the gate of MOS transistor Q6, the source of MOS transistor Q6 is grounded, the drain of MOS transistor Q6 is connected to the reference voltage VREF, and the source of MOS transistor Q7 is grounded; The drain of the MOS transistor Q11 is connected to the drain of the MOS transistor P8, and is connected to the gates of the MOS transistor Q8 and the MOS transistor Q9, and is used to control the on and off of the MOS transistor Q8 and the MOS transistor Q9. The source of the MOS transistor Q11 is grounded, and the source of the MOS transistor P8 is connected to the power supply VDD. The gates of the MOS transistor P8 and the MOS transistor Q11 are connected and then connected to the gate of the MOS transistor P4. MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor Q3, MOS transistor Q4, MOS transistor Q5, current source Ib, resistor R1 and capacitor C1 form a clamping operational amplifier; wherein, the gate of MOS transistor P1 is connected to reference voltage VREF, the source of MOS transistor P1 is connected to current source Ib, and current source Ib is connected to power supply VDD; the gate of MOS transistor P2 is connected to the drain of MOS transistor P5; the source of MOS transistor P2 is connected to current source Ib; the drain of MOS transistor P1 is connected to the drain and gate of MOS transistor Q4, and is also connected to the drain of MOS transistor Q9; the drain of MOS transistor P2 is connected to the drain of MOS transistor Q5, the gate of MOS transistor Q5 is connected to the gate of MOS transistor Q4, and the source of MOS transistor Q5, the source of MOS transistor Q9, and the source of MOS transistor Q4 are grounded; The gate of the MOS transistor Q8 is connected to the gate of the MOS transistor Q9, the drain of the MOS transistor Q8 is connected to one end of the resistor R1 and the drain of the MOS transistor Q5, the other end of the resistor R1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to the drain of the MOS transistor Q3, the gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q8, the source of the MOS transistor Q3 is grounded, the drain of the MOS transistor Q3 is connected to the drain of the MOS transistor P3, and the gate of the MOS transistor Q3 is connected to the drain of the MOS transistor Q5; The gate of the MOS transistor P3 is powered by a bias voltage Vb provided by an external circuit, the source of the MOS transistor P3 is connected to the power supply VDD, the drain of the MOS transistor P3 is connected to the gate of the MOS transistor P5, and the source of the MOS transistor P5 is connected to the power supply VDD; the drain of the MOS transistor P5 is connected to four voltage control resistors RV1, RV2, R3 and RV4 connected in series, the other end of the voltage control resistor RV4 is grounded, and the drain of the MOS transistor P5 is the node voltage VX.

2. The undershoot voltage generating circuit according to claim 1, characterized in that: The resistor R1 and the capacitor C1 are used to stabilize the circuit, and the current source Ib provides an operational amplifier bias current; the MOS transistor P5 is used as a current-voltage conversion tube, and the gate is connected to the output end of the clamping operational amplifier; the clamping operational amplifier associates the node voltage VX with the reference voltage VREF, and dynamically adjusts the gate voltage of the MOS transistor P5 through a feedback loop; the MOS transistor P6 and the MOS transistor Q6 and the MOS transistor Q7 form a current mirror circuit, which is used to copy the gate voltage of the MOS transistor P5, and then generate a reference current.

3. The undershoot voltage generating circuit according to claim 2, characterized in that: The reference current is injected into the RC low-pass circuit to generate an undershoot voltage.

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