Signal clock recovery method and device for high-speed serial data and communication equipment

Abstract

The invention provides a signal clock recovery method and device for high-speed serial data and communication equipment, and relates to the technical field of digital signal processing, and the method comprises the steps: carrying out the histogram statistical analysis of a collected signal based on a voltage direction, and obtaining a probability density curve; obtaining a bottom value and a top value based on the probability density curve; obtaining a high level threshold value and a low level threshold value based on the bottom value and the top value; based on the high level threshold value and the low level threshold value, extracting and obtaining a signal edge cross point sequence; calculating a signal edge cross point difference value based on the signal edge cross point sequence; and performing clock recovery based on the signal edge cross point difference to obtain standard clock data. Through the steps, the problem that in the prior art, the reliability of generating the jitter signal is relatively low is solved.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a signal clock recovery method, device and communication equipment for high-speed serial data. Background Art

[0002] With the continuous development of digital communication technology, data transmission rates are getting higher and higher. In communication systems with on-chip clocks, the timing correlation between clocks and data is a prerequisite for correct communication. However, when the data rate of high-speed serial buses reaches Gbit / s, signal integrity and quality are severely challenged. However, the efficiency of traditional serial data clock recovery technology needs to be improved. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a signal clock recovery method, device and communication equipment for high-speed serial data, so as to improve the problem of relatively low reliability of generating jitter signals existing in the prior art.

[0004] To achieve the above purpose, the embodiment of the present application adopts the following technical solution: a signal clock recovery method for high-speed serial data, comprising:

[0005] Performing histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtaining a bottom value of the probability density curve and a top value of the probability density curve;

[0006] Based on the bottom value and the top value, obtaining a high level threshold and a low level threshold;

[0007] Extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold;

[0008] Based on the signal edge crossing point sequence, a signal edge crossing point difference is calculated; based on the signal edge crossing point difference, clock recovery is performed to obtain standard clock data.

[0009] In a preferred embodiment of the present application, the step of obtaining a high level threshold and a low level threshold based on the bottom value and the top value includes:

[0010] Based on the bottom value and the top value, a jump crossing point threshold and a hysteresis range are calculated; the jump crossing point threshold is obtained by multiplying the sum of the bottom value and the top value by a first preset coefficient; the hysteresis range is obtained by multiplying the difference between the top value and the bottom value by a second preset coefficient; the first preset coefficient is greater than the second preset coefficient, and both the first preset coefficient and the second preset coefficient are less than 1;

[0011] A high level threshold and a low level threshold are calculated based on the transition crossing point threshold and the hysteresis range.

[0012] In a preferred embodiment of the present application, the high level threshold and the low level threshold are calculated based on the transition crossing point threshold and the hysteresis range, including:

[0013] The sum of the transition crossing point threshold and the hysteresis range is used as a high level threshold;

[0014] The difference between the transition crossing point threshold and the hysteresis range is used as a low level threshold.

[0015] In a preferred embodiment of the present application, the step of extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold includes:

[0016] Comparing the signal voltage value with the high level threshold and the low level threshold;

[0017] If the signal voltage value is higher than or equal to the transition crossing point threshold and higher than or equal to the high level threshold, the judgment result is a high level signal;

[0018] If the signal voltage value is lower than the low level threshold, the judgment result is a low level signal;

[0019] If the signal voltage value is greater than the low level threshold and less than the high level threshold, the judgment result is a target level signal;

[0020] When the decision result is a target level signal, a signal edge crossing point sequence is obtained.

[0021] In a preferred embodiment of the present application, when the judgment result is a target level signal, extracting and obtaining a signal edge crossing point sequence includes:

[0022] When the judgment result is a target level signal, a rising edge intersection point and a falling edge intersection point are extracted respectively; the rising edge intersection point means that the signal is a low level signal in n-1 clock cycles, and the signal is a high level signal in n clock cycles; the falling edge intersection point means that the signal is a high level signal in n-1 clock cycles, and the signal is a low level signal in n clock cycles;

[0023] A signal edge crossing point sequence is obtained based on the rising edge crossing point and the falling edge crossing point.

[0024] In a preferred embodiment of the present application, the step of calculating the signal edge crossing point difference based on the signal edge crossing point sequence; and performing clock recovery based on the signal edge crossing point difference to obtain standard clock data includes:

[0025] Based on the signal edge crossing point sequence, determine the time position of the edge crossing point in the (n+1)th clock cycle and the time position of the edge crossing point in the (n)th clock cycle, and perform a difference processing on the two to obtain a signal edge crossing point difference;

[0026] Calculating a single-bit average symbol width based on the signal edge crossing point difference;

[0027] Calculating an optimal symbol width based on the single-bit average symbol width;

[0028] Calculate the optimal symbol width to perform linear fitting on the signal edge crossing point sequence, and calculate the slope value and the offset value;

[0029] Based on the slope value and the offset value, clock recovery is performed to obtain standard clock data.

[0030] In a preferred embodiment of the present application, the slope value and the offset value satisfy the following relationship:

[0031]

[0032] LSMy=Y

[0033] (LSMk,LSMb)=LSM(LSMx,LSMy)

[0034] Among them, LSMk refers to the slope value; LSMb refers to the bias value; LSMx refers to the observed value of the signal edge crossing point sequence on the horizontal axis, that is, the value of the independent variable in the linear fitting; LSMy refers to the observed value of the signal edge crossing point sequence on the vertical axis, that is, the value of the dependent variable in the linear fitting; LSMx(n-1) refers to the observed value of the signal edge crossing point sequence on the horizontal axis in n-1 clock cycles; M(n) refers to the signal edge crossing point difference in n clock cycles; M(n-1) refers to the signal edge crossing point difference in n-1 clock cycles; Mpretty refers to the optimal symbol width.

[0035] In a preferred embodiment of the present application, the optimal symbol width satisfies the following relationship:

[0036]

[0037] Among them, Mpretty refers to the optimal symbol width, M refers to the signal edge crossing point difference, and Mmean refers to the single-bit average symbol width.

[0038] The present application also provides a high-speed serial data signal clock recovery device, including:

[0039] A threshold calculation module is used to perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtain the bottom value of the probability density curve and the top value of the probability density curve; and obtain a high level threshold and a low level threshold based on the bottom value and the top value;

[0040] An edge extraction module, used for extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold;

[0041] The clock recovery module is used to calculate the signal edge crossing point difference based on the signal edge crossing point sequence.

[0042] On the basis of the above, the embodiment of the present application further provides a communication device, including:

[0043] Memory for storing computer programs;

[0044] The processor connected to the memory is used to execute the computer program stored in the memory to implement the above-mentioned signal clock recovery method for high-speed serial data.

[0045] Based on the above, an embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is run, each step of the above-mentioned signal clock recovery method for high-speed serial data is executed.

[0046] The signal clock recovery method, device and communication equipment of high-speed serial data provided by the present application, the method, firstly, performs histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtains the bottom value of the probability density curve and the top value of the probability density curve; then obtains the high level threshold and the low level threshold based on the bottom value and the top value; then extracts and obtains the signal edge intersection sequence based on the high level threshold and the low level threshold; calculates the signal edge intersection difference based on the signal edge intersection sequence; finally, performs clock recovery based on the signal edge intersection difference to obtain standard clock data. Based on the above content, it can be seen that the selection of threshold and the selection of hysteresis voltage in the technical solution of the present application are obtained by performing histogram statistics on the signal, so that the signal characteristics can be more accurately reflected, and the interference of noise on clock recovery can be effectively reduced. In addition, the technical solution of the present application reduces the interference of noise on edge extraction through hysteresis comparison, and the calculation process only needs three state values, which reduces the amount of calculation and can improve the data processing capacity per unit time. Based on this, the technical solution of the present application can effectively improve the efficiency of serial data clock recovery. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.

[0048] Figure 1 A structural block diagram of a communication device provided in an embodiment of the present application.

[0049] Figure 2 A schematic flow chart of a signal clock recovery method for high-speed serial data provided in an embodiment of the present application.

[0050] Figure 3 A schematic diagram of a signal voltage direction histogram provided in an embodiment of the present application.

[0051] Figure 4 A schematic diagram of edge extraction provided in an embodiment of the present application.

[0052] Figure 5 A schematic diagram of a comparative waveform diagram provided in an embodiment of the present application.

[0053] Figure 6 Provided in the embodiments of this application Figure 5 The corresponding eye diagram.

[0054] Figure 7 A schematic diagram of the edge extraction results of a measured signal provided in an embodiment of the present application.

[0055] Figure 8 A schematic diagram of the measured standard clock recovery results provided in an embodiment of the present application.

[0056] Fig. 9 A schematic diagram of the measured eye diagram generation results provided in an embodiment of the present application.

[0057] Fig.10 Block diagram of a signal clock recovery apparatus for high-speed serial data. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0060] like Figure 1 As shown, an embodiment of the present application provides a communication device, which may include a memory, a processor, and a signal clock recovery device for high-speed serial data.

[0061] Wherein, the memory and the processor are directly or indirectly electrically connected to realize data transmission or interaction. For example, the memory and the processor can be electrically connected through one or more communication buses or signal lines. The signal clock recovery device for high-speed serial data includes at least one software function module stored in the memory in the form of software or firmware. The processor is used to execute an executable computer program stored in the memory, for example, the software function module and computer program included in the signal clock recovery device for high-speed serial data, so as to realize the signal clock recovery method for high-speed serial data provided in the embodiment of the present application.

[0062] Optionally, the memory can be, but is not limited to, random access memory (RAM), read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0063] Furthermore, the processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a system on chip (SoC), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0064] Understandably, Figure 1 The structure shown is for illustration only. The communication device may also include Figure 1 More or fewer components as shown, or with Figure 1 The different configurations shown, for example, may also include a communication unit for exchanging information with other devices (such as an oscilloscope, etc.).

[0065] Combination Figure 2 The embodiment of the present application also provides a signal clock recovery method for high-speed serial data that can be applied to the above communication device. The method steps defined in the process related to the signal clock recovery method for high-speed serial data can be implemented by the communication device.

[0066] The following will Figure 2 The specific process shown is explained in detail.

[0067] A signal clock recovery method for high-speed serial data, comprising:

[0068] Step S10, performing histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; and obtaining a bottom value and a top value of the probability density curve.

[0069] In the embodiment of the present application, the signal may be collected by a device such as an oscilloscope or a data acquisition card. The histogram statistical analysis refers to dividing the voltage data of the signal into several intervals and counting the number of data points in each interval. These statistical results are then plotted as Figure 3 The histogram shown is, for example, segmenting the voltage signal data, for example, dividing the voltage value from -5V to +5V into 20 intervals, and then counting the number of samples in each interval to draw a voltage histogram. The probability density curve is a continuous curve obtained by smoothing the histogram (such as using the kernel density estimation method). It represents the probability density distribution of the signal voltage. The bottom value refers to the peak value of the 40% area on the left side of the probability density curve, which is usually used to represent the distribution characteristics of the lower voltage range in the signal. The top value refers to the peak value of the 40% area on the right side of the probability density curve, which is usually used to represent the distribution characteristics of the higher voltage range in the signal.

[0070] Step S20: Obtain a high level threshold and a low level threshold based on the bottom value and the top value.

[0071] In signal processing and analysis, determining the high level threshold and the low level threshold is a crucial step, especially when performing signal classification or signal detection. The high level threshold can be used to distinguish the threshold of the high level area in the signal, and is usually selected near the top value or slightly higher. For example, the high level threshold may be set slightly higher than the top value +1.2V, such as +1.3V, to ensure that the high level signal is correctly distinguished. The low level threshold is used to distinguish the threshold of the low level area in the signal. It is usually selected near the bottom value or slightly lower. For example, the low level threshold may be set slightly lower than the bottom value -1.8V, such as -1.9V, to ensure that the low level signal is correctly distinguished.

[0072] In the embodiment of the present application, the high level threshold and the low level threshold are obtained based on the following steps:

[0073] Step S21, based on the bottom value and the top value, calculate and obtain the jump cross point threshold and hysteresis range; the jump cross point threshold is obtained by multiplying the sum of the bottom value and the top value by the first preset coefficient; the hysteresis range is obtained by multiplying the difference between the top value and the bottom value by the second preset coefficient; the first preset coefficient is greater than the second preset coefficient, and the first preset coefficient and the second preset coefficient are both less than 1; the jump cross point threshold refers to how the system judges the high and low states of the signal when the signal passes through a certain threshold point. The hysteresis range is used in the signal judgment process, and the hysteresis mechanism will introduce a certain range to reduce misjudgment caused by signal fluctuations. This hysteresis can keep the system stable when the signal approaches the threshold and avoid frequent switching.

[0074] The transition crossing point threshold satisfies the following relationship:

[0075] Vth=(Vtop+Vbase) / 2

[0076] Among them, Vth represents the transition crossing point threshold, Vtop represents the top value, and Vbase represents the bottom value.

[0077] The hysteresis range satisfies the following relationship:

[0078] Vhs=(Vtop-Vbase)*0.1

[0079] Among them, Vhs represents the hysteresis range, Vtop represents the top value, and Vbase represents the bottom value.

[0080] Step S22: Calculate a high level threshold and a low level threshold based on the transition crossing point threshold and the hysteresis range.

[0081] The high level threshold satisfies the following relationship:

[0082] Vhi=Vth+Vhs

[0083] Among them, Vhi represents the high level threshold, Vth represents the transition crossing point threshold, and Vhs represents the hysteresis range.

[0084] The low level threshold satisfies the following relationship:

[0085] Vlo=Vth-Vhs

[0086] Among them, Vlo represents the low level threshold, Vth represents the transition crossing point threshold, and Vhs represents the hysteresis range.

[0087] Specifically, the high level threshold and the low level threshold are calculated based on the transition intersection threshold and the hysteresis range, including: taking the sum of the transition intersection threshold and the hysteresis range as the high level threshold; taking the difference between the transition intersection threshold and the hysteresis range as the low level threshold.

[0088] Step S30: extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold.

[0089] In the implementation of the present application, the step of extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold includes:

[0090] Comparing the signal voltage value with the high level threshold and the low level threshold;

[0091] If the signal voltage value is higher than or equal to the transition crossing point threshold and higher than or equal to the high level threshold, the judgment result is a high level signal; if the signal voltage value is lower than the low level threshold, the judgment result is a low level signal; if the signal voltage value is greater than the low level threshold and less than the high level threshold, the judgment result is a target level signal;

[0092] When the decision result is a target level signal, a signal edge crossing point sequence is obtained.

[0093] It should be noted that the signal voltage value refers to the voltage value measured at a specific time point, representing the instantaneous state of the signal. The target level signal refers to a target level signal whose signal voltage value is between a high level threshold and a low level threshold.

[0094] Under ideal conditions, there is only one intersection point between the edge of the level signal and the threshold. Therefore, to extract the rising edge intersection point, it is only necessary to satisfy X[n-1]<Vth And Vth≤X[n], and to extract the falling edge intersection point, it is only necessary to satisfy X[n-1]>Vth And Vth≥X[n]. X[n] represents the signal voltage value at the n clock cycle, X[n-1] represents the signal voltage value at the (n-1) clock cycle, and Vth represents the jump intersection threshold.

[0095] However, the actual communication systems are not ideal, so noise interference may occur near the decision threshold. If the traditional single threshold method is still used to extract edge intersections, misjudgment may occur. Therefore, in order to reduce noise interference, the technical solution of this application uses hysteresis comparison to extract edge intersections. That is:

[0096]

[0097] LS(n)=AH(n)|(AL(n)&LS(n-1))

[0098] Wherein, AH(n) indicates that the signal voltage value at the n clock cycle is a high-level signal, AL(n) indicates that the signal voltage value at the n clock cycle is a low-level signal, X[n] indicates the signal voltage value at the n clock cycle, Vhi indicates the high-level threshold, Vth indicates the transition crossing point threshold, Vlo indicates the low-level threshold, LS(n) indicates the signal edge crossing point sequence at the n clock cycle, and LS(n-1) indicates the signal edge crossing point sequence at the (n-1) clock cycle.

[0099] Specifically, when the judgment result is a target level signal, extracting and obtaining a signal edge crossing point sequence includes:

[0100] like Figure 4 As shown, when the judgment result is a target level signal, a rising edge intersection point and a falling edge intersection point are extracted respectively; the rising edge intersection point means that the signal is a low level signal in n-1 clock cycles, and the signal is a high level signal in n clock cycles; the falling edge intersection point means that the signal is a high level signal in n-1 clock cycles, and the signal is a low level signal in n clock cycles;

[0101] A signal edge crossing point sequence is obtained based on the rising edge crossing point and the falling edge crossing point.

[0102] The rising edge intersection point satisfies the following relationship:

[0103] LS(n-1)≡0And LS(n)≡1

[0104] The falling edge intersection point satisfies the following relationship:

[0105] LS(n-1)≡1And LS(n)≡0

[0106] Among them, LS(n) represents the signal edge crossing point sequence in the n clock cycle; LS(n-1) represents the signal edge crossing point sequence in the (n-1) clock cycle; LS(n-1)=0and LS(n)=1 means that the signal is a low level signal in the n-1 clock cycle, and the signal is a high level signal in the n clock cycle; LS(n-1)=1and LS(n)=0 means that the signal is a high level signal in the n-1 clock cycle, and the signal is a low level signal in the n clock cycle.

[0107] Step S40: Calculate the signal edge crossing point difference based on the signal edge crossing point sequence; perform clock recovery based on the signal edge crossing point difference to obtain standard clock data.

[0108] Step S40 can be broken down into:

[0109] Step S41: Based on the signal edge crossing point sequence, determine the time position of the edge crossing point in the (n+1)th clock cycle and the time position of the edge crossing point in the nth clock cycle, and perform difference processing on the two to obtain the signal edge crossing point difference; that is, satisfy the following relationship:

[0110] M(n)=L(n+1)-L(n)

[0111] Among them, M(n) represents the signal edge crossing point difference in the nth clock cycle; L(n) represents the time position of the edge crossing point in the nth clock cycle; L(n+1) represents the time position of the edge crossing point in the n+1th clock cycle.

[0112] Step S42, calculating a single-bit average symbol width based on the signal edge crossing point difference;

[0113] The bit stream composed of 0 and 1 will form a level signal with a fixed time width after timing and be transmitted in the channel. The level time width corresponding to a single bit is recorded as the single-bit symbol width. A normal data stream can be regarded as composed of random 0 and 1 bits, so there will be continuous 0 or continuous 1, and the corresponding symbol width is also an integer multiple of the single-bit symbol width. In a normal data stream, the maximum symbol width of a single bit will not be greater than 1.5 times Mmin. Therefore, the single-bit average symbol width satisfies the following relationship:

[0114] Mmeam=meam(M<1.5*Mmin)

[0115] Among them, Mmean represents the average symbol width of a single bit; M represents the maximum symbol width of a single bit in a normal data stream; and Mmin represents the minimum symbol width in the narrowest pulse width in a data stream without idle time.

[0116] However, the calculation of Mmean does not utilize all data information. In order to obtain more accurate information, all data should be utilized, that is, the optimal symbol width is calculated by the method described in step S43:

[0117] Step S43, calculating an optimal symbol width based on the single-bit average symbol width;

[0118] The optimal symbol width satisfies the following relationship:

[0119]

[0120] Among them, Mpretty refers to the optimal symbol width, M refers to the signal edge crossing point difference, and Mmean refers to the single-bit average symbol width.

[0121] In order to reduce the impact of low-frequency jitter on the clock, it is necessary to perform linear fitting on the signal edge crossing point sequence according to the calculated Mpretty, and use the least squares method to perform linear fitting calculation to obtain the slope LSMk and the offset LSMb, that is, step S44:

[0122] Step S44, calculating the optimal symbol width, performing linear fitting on the signal edge crossing point sequence, and calculating the slope value and the offset value;

[0123] The slope value and the offset value satisfy the following relationship:

[0124]

[0125] LSMy=Y

[0126] (LSMk,LSMb)=LSM(LSMx,LSMy)

[0127] Among them, LSMk refers to the slope value; LSMb refers to the bias value; LSMx refers to the observed value of the signal edge crossing point sequence on the horizontal axis, that is, the value of the independent variable in the linear fitting; LSMy refers to the observed value of the signal edge crossing point sequence on the vertical axis, that is, the value of the dependent variable in the linear fitting; LSMx(n-1) refers to the observed value of the signal edge crossing point sequence on the horizontal axis in n-1 clock cycles; M(n) refers to the signal edge crossing point difference in n clock cycles; M(n-1) refers to the signal edge crossing point difference in n-1 clock cycles; Mpretty refers to the optimal symbol width.

[0128] Step S45: Perform clock recovery based on the slope value and the offset value to obtain standard clock data.

[0129] When performing clock recovery, the symbol rate must also be calculated to ensure that the system can receive and decode data at the correct rate, that is:

[0130]

[0131] Among them, SymbolRate represents the symbol rate, fs represents the sampling frequency, that is, the number of times the signal is sampled per second, and the unit is usually Hertz; LSMk refers to the slope value.

[0132] The standard clock satisfies the following relationship:

[0133] CLK(n)=n*LSMk+LSMb

[0134] CLK(n) represents the standard clock, n represents the serial number of the clock cycle; LSMk represents the slope value; and LSMb represents the offset value.

[0135] Conformance testing is a necessary condition for large-scale production of communication systems, and the eye diagram can reflect the signal quality issues as a whole and is the key to consistency testing. The shape of the eye diagram can reflect the size of the inter-symbol crosstalk and system performance. From the eye diagram, not only can the inter-symbol crosstalk and noise be observed, but also the parameters of some modules at the receiving end, such as the receiving filter, can be adjusted according to the eye diagram to adjust the system performance.

[0136] Therefore, after obtaining the standard clock data in the above step S40, the following step is further performed: the original waveform data and the standard clock data are plotted in the same coordinate system to obtain Figure 5 The comparison waveform is shown in the figure. The recovered clock edge position is used as the starting time, and the original data is cut into pieces according to a fixed length and superimposed to obtain Figure 6 The eye diagram is shown.

[0137] That is, by plotting the original waveform data (i.e., the actual transmitted signal) and the standard clock data (i.e., the ideal clock signal) in the same coordinate system, the relationship between the signal and the clock can be more clearly seen, thereby helping to analyze the quality of the signal and the accuracy of clock recovery. The horizontal axis of the coordinate system usually represents time, and the vertical axis represents voltage value. The original waveform data and the standard clock data are displayed in different colors or line types in the same figure, so that the relationship between them can be intuitively compared.

[0138] By analyzing the waveform in the waveform diagram drawn in the above steps, the edge position of the standard clock data (i.e., the rising edge or falling edge of the clock) is identified. These positions represent the boundary points of the clock signal. From the original waveform data, take the clock edge position as the starting point and cut out several data segments according to a fixed time length. For example, if the length of each segment is one symbol period, then multiple data segments based on the clock edge will be obtained. These data segments are superimposed in the same coordinate system for drawing. The starting point of each segment is aligned to the clock edge position. Since the time axes of multiple data segments are aligned, the overlapping area will form an "eye" shaped pattern, called an eye diagram.

[0139] It can be seen that the main purpose of the above is to check the synchronization of the signal and the clock and the signal quality by plotting the original waveform data and the standard clock data in the same coordinate system. This can help find the deviation of clock recovery or the distortion of the signal; and by slicing and superimposing the signal in multiple clock cycles, an eye diagram is generated to analyze the quality characteristics of the signal, such as jitter, distortion, etc. This is an effective signal quality inspection tool for evaluating the performance of digital communication systems.

[0140] In eye diagram analysis, the extraction of standard clock is the basis for eye diagram drawing. Before implementing the eye diagram analysis function, the test instrument must recover the standard clock signal from the measured signal. Therefore, in the analysis of serial data, clock recovery often plays an important role, and it can be considered that clock recovery is the basis for analyzing serial data.

[0141] Due to the characteristics of hardware circuits, it is impossible to flexibly adjust parameters, so the clock recovery circuit is usually matched with the protocol specification and cannot be universal. Therefore, the present application proposes a constant clock recovery and eye diagram generation method for high-speed serial data. All steps of the method are implemented by software and have great flexibility. The method realizes the automatic selection of the decision threshold, and completes the extraction of the signal transition edge through hysteresis comparison, and then recovers the clock according to the signal transition edge, and finally completes the drawing of the eye diagram according to the recovered clock. This method does not require manual parameter configuration, thereby lowering the threshold for use. At the same time, the full software implementation method enables it to adapt to various types of protocols, thereby reducing the cost of use.

[0142] Based on the above steps S10 to S40, it can be seen that the technical solution described in the present application has the following advantages: 1) The selection of the threshold and the selection of the hysteresis voltage are obtained by performing histogram statistics on the signal, so it can more accurately reflect the signal characteristics and effectively reduce the interference of noise on clock recovery; 2) The interference of noise on edge extraction is reduced by hysteresis comparison, and the calculation process only requires three state values, which reduces the amount of calculation and improves the data processing capability per unit time; 3) The linear fitting of the signal edge by the least squares method reduces the interference of low-frequency jitter on the clock.

[0143] The following is a detailed description of the technical solution of this application in combination with actual engineering tests:

[0144] The PRBS random code waveform is transmitted through an arbitrary waveform generator with a baud rate of 1 Gbps, and the waveform data is collected by an oscilloscope. Then, the standard clock recovery and eye diagram generation method proposed in the above steps S10 to S40 is used for offline analysis.

[0145] The analysis results are as follows:

[0146] Reference Figure 7 , the signal transition edge is successfully extracted by the method proposed in this application; refer to Figure 8 , the standard clock of the signal is successfully recovered by the method proposed in this application; Fig. 9 , the signal eye diagram was successfully drawn using the method proposed in the present application. It can be seen that the method proposed in the present application is effective for clock recovery and eye diagram generation of high-speed serial data.

[0147] Combination Fig.10The embodiment of the present application also provides a high-speed serial data signal clock recovery device applicable to the above communication device. The high-speed serial data signal clock recovery device may include a threshold calculation module, an edge extraction module and a clock recovery module.

[0148] The threshold calculation module can be used to perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtain the bottom value and the top value of the probability density curve; and obtain a high level threshold and a low level threshold based on the bottom value and the top value. In the embodiment of the present application, the threshold calculation module can be used to perform Figure 2 As shown in step S10 to step S20, the relevant contents of the threshold calculation module can refer to the above description of step S10 to step S20.

[0149] The edge extraction module can be used to extract a signal edge crossing point sequence based on the high level threshold and the low level threshold. In the embodiment of the present application, the edge extraction module can be used to perform Figure 2 As shown in step S30, the relevant contents of the edge extraction module can refer to the above description of step S30.

[0150] The clock recovery module can be used to calculate the signal edge crossing point difference based on the signal edge crossing point sequence. In the embodiment of the present application, the clock recovery module can be used to perform Figure 2 As shown in step S40, the relevant contents of the clock recovery module can refer to the above description of step S40.

[0151] In an embodiment of the present application, corresponding to the above-mentioned signal clock recovery method for high-speed serial data applied to the communication device, a computer-readable storage medium is also provided, in which a computer program is stored, and when the computer program is run, each step of the signal clock recovery method for high-speed serial data is executed. Among them, each step executed when the aforementioned computer program is run will not be repeated here one by one, and reference can be made to the above explanation of the signal clock recovery method for high-speed serial data.

[0152] In summary, the signal clock recovery method, device and communication equipment for high-speed serial data provided by the present application first perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtain the bottom value of the probability density curve and the top value of the probability density curve; then obtain the high level threshold and the low level threshold based on the bottom value and the top value; then extract and obtain the signal edge intersection sequence based on the high level threshold and the low level threshold; calculate the signal edge intersection difference based on the signal edge intersection sequence; finally perform clock recovery based on the signal edge intersection difference to obtain standard clock data. Based on the above content, it can be seen that the selection of thresholds and the selection of hysteresis voltage in the technical solution of the present application are obtained by performing histogram statistics on the signal, so that the signal characteristics can be more accurately reflected, and the interference of noise on clock recovery can be effectively reduced. In addition, the technical solution of the present application reduces the interference of noise on edge extraction through hysteresis comparison, and the calculation process only requires three state values, which reduces the amount of calculation and can improve the data processing capacity per unit time. Based on this, the technical solution of the present application can effectively improve the efficiency of serial data clock recovery.

[0153] In several embodiments provided in the embodiments of the present application, it should be understood that the disclosed device and method can also be implemented in other ways. The device and method embodiments described above are merely schematic, for example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the device, method and computer program product according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0154] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0155] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a communication device, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk. It should be noted that, in this article, the term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, article or device. Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0156] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A signal clock recovery method for high-speed serial data, characterized in that: include: Perform histogram statistical analysis on the collected signals based on the voltage direction to obtain a probability density curve; Based on the probability density curve, obtaining a bottom value of the probability density curve and a top value of the probability density curve; Based on the bottom value and the top value, obtaining a high level threshold and a low level threshold; Extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold; Based on the signal edge crossing point sequence, a signal edge crossing point difference is calculated; based on the signal edge crossing point difference, clock recovery is performed to obtain standard clock data.

2. The signal clock recovery method of high-speed serial data according to claim 1, characterized in that: The step of obtaining a high level threshold and a low level threshold based on the bottom value and the top value comprises: Based on the bottom value and the top value, a jump crossing point threshold and a hysteresis range are calculated; the jump crossing point threshold is obtained by multiplying the sum of the bottom value and the top value by a first preset coefficient; the hysteresis range is obtained by multiplying the difference between the top value and the bottom value by a second preset coefficient; the first preset coefficient is greater than the second preset coefficient, and both the first preset coefficient and the second preset coefficient are less than 1; A high level threshold and a low level threshold are calculated based on the transition crossing point threshold and the hysteresis range.

3. The signal clock recovery method of high-speed serial data according to claim 2, characterized in that: The step of calculating a high level threshold and a low level threshold based on the transition crossing point threshold and the hysteresis range comprises: The sum of the transition crossing point threshold and the hysteresis range is used as a high level threshold; The difference between the transition crossing point threshold and the hysteresis range is used as a low level threshold.

4. The signal clock recovery method of high-speed serial data according to claim 3, characterized in that: The step of extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold comprises: Comparing the signal voltage value with the high level threshold and the low level threshold; If the signal voltage value is higher than or equal to the transition crossing point threshold and higher than or equal to the high level threshold, the judgment result is a high level signal; If the signal voltage value is lower than the low level threshold, the judgment result is a low level signal; If the signal voltage value is greater than the low level threshold and less than the high level threshold, the judgment result is a target level signal; When the decision result is a target level signal, a signal edge crossing point sequence is obtained.

5. The signal clock recovery method of high-speed serial data according to claim 4, characterized in that: When the judgment result is a target level signal, extracting and obtaining a signal edge crossing point sequence comprises: When the judgment result is a target level signal, a rising edge intersection point and a falling edge intersection point are extracted respectively; the rising edge intersection point means that the signal is a low level signal in n-1 clock cycles, and the signal is a high level signal in n clock cycles; the falling edge intersection point means that the signal is a high level signal in n-1 clock cycles, and the signal is a low level signal in n clock cycles; A signal edge crossing point sequence is obtained based on the rising edge crossing point and the falling edge crossing point.

6. The signal clock recovery method of high-speed serial data according to claim 1, characterized in that: The step of calculating a signal edge crossing point difference based on the signal edge crossing point sequence; Performing clock recovery based on the signal edge crossing point difference to obtain standard clock data includes: Based on the signal edge crossing point sequence, determine the time position of the edge crossing point in the (n+1)th clock cycle and the time position of the edge crossing point in the (n)th clock cycle, and perform a difference processing on the two to obtain a signal edge crossing point difference; Calculating a single-bit average symbol width based on the signal edge crossing point difference; Calculating an optimal symbol width based on the single-bit average symbol width; Calculate the optimal symbol width to perform linear fitting on the signal edge crossing point sequence, and calculate the slope value and the offset value; Based on the slope value and the offset value, clock recovery is performed to obtain standard clock data.

7. The signal clock recovery method of high-speed serial data according to claim 6, characterized in that: The slope value and the offset value satisfy the following relationship: LSMy=Y (LSMk,LSMb)=LSM(LSMx,LSMy) Among them, LSMk refers to the slope value; LSMb refers to the bias value; LSMx refers to the observed value of the signal edge crossing point sequence on the horizontal axis, that is, the value of the independent variable in the linear fitting; LSMy refers to the observed value of the signal edge crossing point sequence on the vertical axis, that is, the value of the dependent variable in the linear fitting; LSMx(n-1) refers to the observed value of the signal edge crossing point sequence on the horizontal axis in n-1 clock cycles; M(n) refers to the signal edge crossing point difference in n clock cycles; M(n-1) refers to the signal edge crossing point difference in n-1 clock cycles; Mpretty refers to the optimal symbol width.

8. The signal clock recovery method of high-speed serial data according to claim 7, characterized in that: The optimal symbol width satisfies the following relationship: Among them, Mpretty refers to the optimal symbol width, M refers to the signal edge crossing point difference, and Mmean refers to the single-bit average symbol width.

9. A signal clock recovery device for high-speed serial data, characterized in that: include: A threshold calculation module is used to perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; Obtaining a bottom value of the probability density curve and a top value of the probability density curve; obtaining a high level threshold and a low level threshold based on the bottom value and the top value; An edge extraction module, used for extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold; A clock recovery module, used for calculating a signal edge crossing point difference based on the signal edge crossing point sequence; Clock recovery is performed based on the signal edge crossing point difference to obtain standard clock data.

10. A communication device, characterized in that: include: Memory for storing computer programs; A processor connected to the memory is used to execute a computer program stored in the memory to implement the signal clock recovery method for high-speed serial data as described in any one of claims 1-8.

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