Signal clock recovery method, device and communication equipment for high-speed serial data

Abstract

The signal clock recovery method, device and communication equipment of high-speed serial data provided by the present application relate to the field of digital signal processing technology. The method comprises: performing histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtaining the bottom value and the top value based on the probability density curve; obtaining the high level threshold and the low level threshold based on the bottom value and the top value; extracting and obtaining the signal edge crossing point sequence based on the high level threshold and the low level threshold; calculating the signal edge crossing point difference based on the signal edge crossing point sequence; performing clock recovery based on the signal edge crossing point difference to obtain standard clock data. Through the above steps, the problem of relatively low reliability of generating jitter signals existing in the prior art is improved.

Description

Technical Field

[0001] This application relates to the field of digital signal processing technology, and more specifically, to a signal clock recovery method, device, and communication device for high-speed serial data. Background Art

[0002] With the continuous development of digital communication technology, the data transmission rate is also getting higher and higher. In a communication system with a clock on the same path, the timing correlation between the clock and the data is a prerequisite for correct communication. However, when the data rate of a high-speed serial bus reaches Gbit / s, both signal integrity and quality are severely challenged, and the efficiency of traditional serial data clock recovery technology needs to be improved. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a signal clock recovery method, device, and communication device for high-speed serial data, so as to improve the relatively low reliability of generating jitter signals in the existing technology.

[0004] To achieve the above purpose, the embodiments of this application adopt the following technical solutions: A signal clock recovery method for high-speed serial data, including:

[0005] Performing histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtaining the bottom value of the probability density curve and the top value of the probability density curve;

[0006] Based on the bottom value and the top value, obtaining a high-level threshold and a low-level threshold;

[0007] Based on the high-level threshold and the low-level threshold, extracting a signal edge crossing point sequence;

[0008] Based on the signal edge crossing point sequence, calculating the difference between signal edge crossing points; performing clock recovery based on the difference between signal edge crossing points to obtain standard clock data.

[0009] In a preferred selection of the embodiments of this application, the step of obtaining a high-level threshold and a low-level threshold based on the bottom value and the top value includes:

[0010] Based on the bottom value and the top value, calculating a jump crossing point threshold and a hysteresis range; the jump crossing point threshold is obtained by multiplying the sum value of the bottom value and the top value by a first preset coefficient; the hysteresis range is obtained by multiplying the difference between the top value and the bottom value by a second preset coefficient; the first preset coefficient is greater than the second preset coefficient, and both the first preset coefficient and the second preset coefficient are less than 1;

[0011] Calculate the high-level threshold and the low-level threshold based on the jump crossover threshold and the hysteresis range.

[0012] In a preferred selection of the embodiments of the present application, the calculating the high-level threshold and the low-level threshold based on the jump crossover threshold and the hysteresis range includes:

[0013] Take the sum value of the jump crossover threshold and the hysteresis range as the high-level threshold;

[0014] Take the difference value of the jump crossover threshold and the hysteresis range as the low-level threshold.

[0015] In a preferred selection of the embodiments of the present application, the extracting the signal edge crossover point sequence based on the high-level threshold and the low-level threshold includes:

[0016] Compare the signal voltage value with the high-level threshold and the low-level threshold;

[0017] If the signal voltage value is higher than or equal to the jump crossover threshold and higher than or equal to the high-level threshold, the judgment result is a high-level signal;

[0018] If the signal voltage value is lower than the low-level threshold, the judgment result is a low-level signal;

[0019] If the signal voltage value is greater than the low-level threshold and less than the high-level threshold, the judgment result is a target-level signal;

[0020] When the judgment result is a target-level signal, obtain the signal edge crossover point sequence.

[0021] In a preferred selection of the embodiments of the present application, the extracting the signal edge crossover point sequence when the judgment result is a target-level signal includes:

[0022] When the judgment result is a target-level signal, respectively extract the rising-edge crossover point and the falling-edge crossover point; the rising-edge crossover point refers to that the signal is a low-level signal at the (n - 1)th clock cycle and the signal is a high-level signal at the nth clock cycle; the falling-edge crossover point refers to that the signal is a high-level signal at the (n - 1)th clock cycle and the signal is a low-level signal at the nth clock cycle;

[0023] Based on the rising-edge crossover point and the falling-edge crossover point, obtain the signal edge crossover point sequence.

[0024] In a preferred selection of the embodiments of the present application, the calculating the signal edge crossover point difference based on the signal edge crossover point sequence; performing clock recovery based on the signal edge crossover point difference to obtain standard clock data includes:

[0025] Based on the signal edge crossing point sequence, determine the time position of the edge crossing point in the (n + 1)-th clock cycle and the time position of the edge crossing point in the n-th clock cycle, and perform a difference operation on the two to obtain the signal edge crossing point difference;

[0026] Based on the signal edge crossing point difference, calculate the single-bit average symbol width;

[0027] Based on the single-bit average symbol width, calculate the optimal symbol width;

[0028] Perform a linear fit on the signal edge crossing point sequence using the optimal symbol width, and calculate the slope value and the offset value;

[0029] Based on the slope value and the offset value, perform clock recovery to obtain standard clock data.

[0030] In a preferred selection of the embodiments of the present application, the slope value and the offset value satisfy the following relational expressions:

[0031]

[0032] LSMy = Y

[0033] (LSMk, LSMb) = LSM(LSMx, LSMy)

[0034] Wherein, LSMk refers to the slope value; LSMb refers to the offset value; LSMx refers to the observed value of the signal edge crossing point sequence on the horizontal axis, that is, the value of the independent variable in the linear fit; LSMy refers to the observed value of the signal edge crossing point sequence on the vertical axis, that is, the value of the dependent variable in the linear fit; LSMx(n - 1) refers to the observed value of the signal edge crossing point sequence on the horizontal axis in the (n - 1)-th clock cycle; M(n) refers to the signal edge crossing point difference in the n-th clock cycle; M(n - 1) refers to the signal edge crossing point difference in the (n - 1)-th clock cycle; Mpretty refers to the optimal symbol width.

[0035] In a preferred selection of the embodiments of the present application, the optimal symbol width satisfies the following relational expressions:

[0036]

[0037] Wherein, Mpretty refers to the optimal symbol width, M refers to the signal edge crossing point difference, and Mmean refers to the single-bit average symbol width.

[0038] The embodiments of the present application further provide a signal clock recovery device for high-speed serial data, including:

[0039] A threshold calculation module, configured to perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtain the bottom value of the probability density curve and the top value of the probability density curve; and obtain a high-level threshold and a low-level threshold based on the bottom value and the top value;

[0040] An edge extraction module, configured to extract a signal edge intersection point sequence based on the high-level threshold and the low-level threshold;

[0041] A clock recovery module, configured to calculate the difference between signal edge intersection points based on the signal edge intersection point sequence.

[0042] Based on the above, an embodiment of the present application further provides a communication device, including:

[0043] A memory, configured to store a computer program;

[0044] A processor connected to the memory, configured to execute the computer program stored in the memory to implement the above-mentioned signal clock recovery method for high-speed serial data.

[0045] Based on the above, an embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program runs, it executes each step of the above-mentioned signal clock recovery method for high-speed serial data.

[0046] The signal clock recovery method, device and communication device for high-speed serial data provided by the present application, the method first performs histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtains the bottom value of the probability density curve and the top value of the probability density curve; then obtains a high-level threshold and a low-level threshold based on the bottom value and the top value; then extracts a signal edge intersection point sequence based on the high-level threshold and the low-level threshold; calculates the difference between signal edge intersection points based on the signal edge intersection point sequence; and finally performs clock recovery based on the difference between signal edge intersection points to obtain standard clock data. Based on the above content, it can be seen that in the technical solution of the present application, the selection of the threshold and the selection of the hysteresis voltage are obtained by performing histogram statistics on the signal, so it can more accurately reflect the signal characteristics and effectively reduce the interference of noise on clock recovery. In addition, the technical solution of the present application reduces the interference of noise on edge extraction through hysteresis comparison, and the calculation process only requires three state values, reducing the calculation amount and improving the data processing ability per unit time. Based on this, the technical solution of the present application can effectively improve the efficiency of serial data clock recovery. Description of the Drawings

[0047] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows.

[0048] Figure 1 It is a structural block diagram of a communication device provided by an embodiment of the present application.

[0049] Figure 2 It is a schematic flowchart of a signal clock recovery method for high-speed serial data provided by an embodiment of the present application.

[0050] Figure 3 It is a schematic diagram of a signal voltage direction histogram provided by an embodiment of the present application.

[0051] Figure 4 It is a schematic diagram of edge extraction provided by an embodiment of the present application.

[0052] Figure 5 It is a schematic diagram of a comparison waveform provided by an embodiment of the present application.

[0053] Figure 6 provided by an embodiment of the present application Figure 5 corresponding eye diagram.

[0054] Figure 7 It is a schematic diagram of the measured signal edge extraction result provided by an embodiment of the present application.

[0055] Figure 8 It is a schematic diagram of the measured standard clock recovery result provided by an embodiment of the present application.

[0056] Figure 9 It is a schematic diagram of the measured eye diagram generation result provided by an embodiment of the present application.

[0057] Figure 10 It is a block schematic diagram of a signal clock recovery device for high-speed serial data. Specific embodiments

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Generally, the components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application to be protected, but merely represents the selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0060] As Figure 1 shown, an embodiment of the present application provides a communication device, which may include a memory, a processor, and a signal clock recovery device for high-speed serial data.

[0061] Among them, the memory and the processor are directly or indirectly electrically connected to achieve data transmission or interaction. For example, the memory and the processor can be electrically connected through one or more communication buses or signal lines. The signal clock recovery device for high-speed serial data includes at least one software function module stored in the memory in the form of software or firmware. The processor is used to execute the executable computer program stored in the memory, for example, the software function module and computer program included in the signal clock recovery device for high-speed serial data, to implement the signal clock recovery method for high-speed serial data provided by the embodiment of the present application.

[0062] Optionally, the memory may be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0063] And, the processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a system on chip (SoC), etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0064] It can be understood that Figure 1 the structure shown is only schematic, and the communication device may further include more or fewer components than those Figure 1 shown, or have a different configuration from that Figure 1 shown. For example, it may further include a communication unit for information interaction with other devices (such as an oscilloscope, etc.).

[0065] Combined with Figure 2 Moreover, an embodiment of the present application also provides a signal clock recovery method for high-speed serial data applicable to the above communication device. Among them, the method steps defined by the process related to the signal clock recovery method for high-speed serial data can be implemented by the communication device.

[0066] Next, the specific process shown below Figure 2 will be elaborated in detail.

[0067] A signal clock recovery method for high-speed serial data includes:

[0068] Step S10: Perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtain the bottom value of the probability density curve and the top value of the probability density curve.

[0069] In an embodiment of the present application, the signal can be collected by devices such as an oscilloscope or a data acquisition card. The histogram statistical analysis refers to dividing the voltage data of the signal into several intervals and counting the number of data points in each interval. Then, these statistical results are plotted as a histogram as shown in Figure 3 For example, the voltage signal data is segmented. For instance, the voltage value from -5V to +5V is divided into 20 intervals, and then the number of samples in each interval is counted to draw a voltage histogram. The probability density curve is a continuous curve obtained by smoothing the histogram (such as using the kernel density estimation method). It represents the probability density distribution of the signal voltage. The bottom value refers to the peak value in the left 40% area of the probability density curve, which is usually used to represent the distribution characteristics of the lower voltage range in the signal. The top value refers to the peak value in the right 40% area of the probability density curve, which is usually used to represent the distribution characteristics of the higher voltage range in the signal.

[0070] Step S20: Based on the bottom value and the top value, obtain a high-level threshold and a low-level threshold.

[0071] In signal processing and analysis, determining the high-level threshold and the low-level threshold is a crucial step, especially when performing signal classification or signal detection. The high-level threshold can be used to distinguish the high-level area in the signal. It is usually selected near or slightly higher than the top value. For example, the high-level threshold may be set slightly higher than the top value +1.2V, such as +1.3V, to ensure correct discrimination of high-level signals. The low-level threshold is used to distinguish the low-level area in the signal. It is usually selected near or slightly lower than the bottom value. For example, the low-level threshold may be set slightly lower than the bottom value -1.8V, such as -1.9V, to ensure correct discrimination of low-level signals.

[0072] In the embodiments of the present application, the high-level threshold and the low-level threshold are obtained based on the following steps:

[0073] Step S21: Based on the bottom value and the top value, calculate the jump crossover threshold and the hysteresis range; the jump crossover threshold is obtained by multiplying the sum of the bottom value and the top value by a first preset coefficient; the hysteresis range is obtained by multiplying the difference between the top value and the bottom value by a second preset coefficient; the first preset coefficient is greater than the second preset coefficient, and both the first preset coefficient and the second preset coefficient are less than 1; the jump crossover threshold refers to how the system determines the high and low states of a signal when the signal passes through a certain threshold point. The hysteresis range is used in the signal decision-making process, and the hysteresis mechanism will introduce a certain range to reduce misjudgment caused by signal fluctuations. This hysteresis can keep the system stable when the signal is close to the threshold and avoid frequent switching.

[0074] The jump crossover threshold satisfies the following relational expression:

[0075] Vth = (Vtop + Vbase) / 2

[0076] where Vth represents the jump crossover threshold, Vtop represents the top value, and Vbase represents the bottom value.

[0077] The hysteresis range satisfies the following relational expression:

[0078] Vhs = (Vtop - Vbase)*0.1

[0079] where Vhs represents the hysteresis range, Vtop represents the top value, and Vbase represents the bottom value.

[0080] Step S22: Based on the jump crossover threshold and the hysteresis range, calculate the high-level threshold and the low-level threshold.

[0081] The high-level threshold satisfies the following relational expression:

[0082] Vhi = Vth + Vhs

[0083] where Vhi represents the high-level threshold, Vth represents the jump crossover threshold, and Vhs represents the hysteresis range.

[0084] The low-level threshold satisfies the following relational expression:

[0085] Vlo = Vth - Vhs

[0086] where Vlo represents the low-level threshold, Vth represents the jump crossover threshold, and Vhs represents the hysteresis range.

[0087] Specifically, calculating the high-level threshold and the low-level threshold based on the jump crossover threshold and the hysteresis range includes: taking the sum value of the jump crossover threshold and the hysteresis range as the high-level threshold; taking the difference value between the jump crossover threshold and the hysteresis range as the low-level threshold.

[0088] Step S30: Extract a signal edge crossover point sequence based on the high-level threshold and the low-level threshold.

[0089] In the implementation of this application, extracting the signal edge crossover point sequence based on the high-level threshold and the low-level threshold includes:

[0090] Comparing the signal voltage value with the high-level threshold and the low-level threshold;

[0091] If the signal voltage value is higher than or equal to the jump crossover threshold and higher than or equal to the high-level threshold, the judgment result is a high-level signal; if the signal voltage value is lower than the low-level threshold, the judgment result is a low-level signal; if the signal voltage value is greater than the low-level threshold and less than the high-level threshold, the judgment result is a target-level signal;

[0092] When the judgment result is a target-level signal, obtain the signal edge crossover point sequence.

[0093] It should be noted that the signal voltage value refers to the voltage value measured at a specific time point and represents the instantaneous state of the signal. The target-level signal refers to the target-level signal whose signal voltage value is between the high-level threshold and the low-level threshold.

[0094] In an ideal state, there is only one crossover point between the edge of the level signal and the threshold. Therefore, for the extraction of the rising edge crossover point, only X[n - 1] < Vth And Vth ≤ X[n] needs to be satisfied, and for the extraction of the falling edge crossover point, only X[n - 1] > Vth And Vth ≥ X[n] needs to be satisfied. X[n] represents the signal voltage value at the nth clock cycle, X[n - 1] represents the signal voltage value at the (n - 1)th clock cycle, and Vth represents the jump crossover threshold.

[0095] However, real communication systems are all non-ideal. Therefore, noise interference may occur near the decision threshold. If the traditional single-threshold method is still used for edge crossover point extraction, misjudgment may occur. Therefore, in order to reduce noise interference, the technical solution of this application uses hysteresis comparison for edge crossover point extraction. That is:

[0096]

[0097] LS(n) = AH(n) | (AL(n) & LS(n - 1))

[0098] Wherein, AH(n) represents that the signal voltage value at the nth clock cycle is a high-level signal, AL(n) represents that the signal voltage value at the nth clock cycle is a low-level signal, X[n] represents the signal voltage value at the nth clock cycle, Vhi represents the high-level threshold, Vth represents the transition crossover threshold, Vlo represents the low-level threshold, LS(n) represents the signal edge crossover point sequence at the nth clock cycle, and LS(n - 1) represents the signal edge crossover point sequence at the (n - 1)th clock cycle.

[0099] Specifically, when the judgment result is the target level signal, extracting the signal edge crossover point sequence includes:

[0100] As Figure 4 shown, when the judgment result is the target level signal, the rising edge crossover point and the falling edge crossover point are respectively extracted; the rising edge crossover point refers to that the signal is a low-level signal at the (n - 1)th clock cycle and a high-level signal at the nth clock cycle; the falling edge crossover point refers to that the signal is a high-level signal at the (n - 1)th clock cycle and a low-level signal at the nth clock cycle;

[0101] Based on the rising edge crossover point and the falling edge crossover point, the signal edge crossover point sequence is obtained.

[0102] The rising edge crossover point satisfies the following relational expression:

[0103] LS(n - 1) ≡ 0 And LS(n) ≡ 1

[0104] The falling edge crossover point satisfies the following relational expression:

[0105] LS(n - 1) ≡ 1 And LS(n) ≡ 0

[0106] Wherein, LS(n) represents the signal edge crossover point sequence at the nth clock cycle; LS(n - 1) represents the signal edge crossover point sequence at the (n - 1)th clock cycle; LS(n - 1) = 0 and LS(n) = 1 means that the signal is a low-level signal at the (n - 1)th clock cycle and a high-level signal at the nth clock cycle; LS(n - 1) = 1 and LS(n) = 0 means that the signal is a high-level signal at the (n - 1)th clock cycle and a low-level signal at the nth clock cycle.

[0107] Step S40: Calculate the signal edge crossover point difference based on the signal edge crossover point sequence; perform clock recovery based on the signal edge crossover point difference to obtain the standard clock data.

[0108] Step S40 can be refined as follows:

[0109] Step S41: Based on the signal edge crossing point sequence, determine the time position of the edge crossing point in the (n + 1)-th clock cycle and the time position of the edge crossing point in the n-th clock cycle, and perform a difference operation on the two to obtain the signal edge crossing point difference; that is, the following relational expression is satisfied:

[0110] M(n) = L(n + 1) - L(n)

[0111] where M(n) represents the signal edge crossing point difference in the n-th clock cycle; L(n) represents the time position of the edge crossing point in the n-th clock cycle; L(n + 1) represents the time position of the edge crossing point in the (n + 1)-th clock cycle.

[0112] Step S42: Calculate the single-bit average symbol width based on the signal edge crossing point difference.

[0113] After timing, the bit stream composed of 0s and 1s will form a level signal with a fixed time width for transmission in the channel. Denote the level time width corresponding to a single bit as the single-bit symbol width. A normal data stream can be regarded as composed of random 0s and 1s bits, so there will be consecutive 0s or consecutive 1s, and the corresponding symbol width is also an integer multiple of the single-bit symbol width. In a normal data stream, the maximum symbol width of a single bit will not be greater than 1.5 times of Mmin. Therefore, the single-bit average symbol width satisfies the following relational expression:

[0114] Mmeam = meam(M < 1.5 * Mmin)

[0115] where Mmean represents the single-bit average symbol width; M represents the maximum symbol width of a single bit in a normal data stream; Mmin represents the minimum symbol width among the narrowest pulse widths in a data stream without idle time.

[0116] However, the calculation of Mmean does not utilize all data information. To obtain more accurate information, all data should be utilized, that is, calculate the optimal symbol width through the method described in Step S43:

[0117] Step S43: Calculate the optimal symbol width based on the single-bit average symbol width.

[0118] The optimal symbol width satisfies the following relational expression:

[0119]

[0120] where Mpretty refers to the optimal symbol width, M refers to the signal edge crossing point difference, and Mmean refers to the single-bit average symbol width.

[0121] To reduce the impact of low-frequency jitter on the clock, it is necessary to linearly fit the signal edge crossing point sequence according to the calculated Mpretty, and use the least squares method to perform the linear fitting calculation to obtain the slope LSMk and the offset LSMb, that is, step S44:

[0122] Step S44: Calculate the best symbol width to linearly fit the signal edge crossing point sequence, and calculate the slope value and the offset value;

[0123] The slope value and the offset value satisfy the following relational expressions:

[0124]

[0125] LSMy = Y

[0126] (LSMk, LSMb) = LSM(LSMx, LSMy)

[0127] Wherein, LSMk refers to the slope value; LSMb refers to the offset value; LSMx refers to the observed value of the signal edge crossing point sequence on the horizontal axis, that is, the value of the independent variable in the linear fitting; LSMy refers to the observed value of the signal edge crossing point sequence on the vertical axis, that is, the value of the dependent variable in the linear fitting; LSMx(n - 1) refers to the observed value of the signal edge crossing point sequence at n - 1 clock cycles on the horizontal axis; M(n) refers to the difference of the signal edge crossing points at n clock cycles; M(n - 1) refers to the difference of the signal edge crossing points at n - 1 clock cycles; Mpretty refers to the best symbol width.

[0128] Step S45: Based on the slope value and the offset value, perform clock recovery to obtain standard clock data.

[0129] When performing clock recovery, it is also necessary to calculate the symbol rate to ensure that the system can receive and decode data at the correct rate, that is:

[0130]

[0131] Wherein, SymbolRate represents the symbol rate, fs represents the sampling frequency, that is, the number of times the signal is sampled per second, and the unit is usually Hertz; LSMk refers to the slope value.

[0132] The standard clock satisfies the following relational expressions:

[0133] CLK(n) = n * LSMk + LSMb

[0134] CLK(n) represents the standard clock, n represents the serial number of the clock cycle; LSMk refers to the slope value; LSMb refers to the offset value.

[0135] Conformance testing is a necessary condition to meet the large-scale production of communication systems. The eye diagram can reflect the signal quality problem as a whole and is the key in conformance testing. The shape of the eye diagram can reflect the magnitude of inter-symbol interference and system performance. From the eye diagram, not only can inter-symbol interference and noise be observed, but also the parameters of some modules at the receiving end, such as the receiving filter, can be adjusted according to the eye diagram to adjust the system performance.

[0136] Therefore, after obtaining the standard clock data in the above step S40, it further includes: plotting the original waveform data and the standard clock data in the same coordinate system to obtain Figure 5 the comparison waveform diagram as shown. Taking the recovered clock edge position as the starting moment, the original data is sliced and superimposed according to a fixed length to obtain Figure 6 the eye diagram as shown.

[0137] That is: by plotting the original waveform data (i.e., the actually transmitted signal) and the standard clock data (i.e., the ideal clock signal) in the same coordinate system, the relationship between the signal and the clock can be seen more clearly, thus helping to analyze the signal quality and the accuracy of clock recovery. The abscissa of the coordinate system usually represents time, and the ordinate represents the voltage value. The original waveform data and the standard clock data are displayed in the same graph with different colors or line types, so that their relationship can be visually compared.

[0138] By analyzing the waveforms in the waveform diagram plotted in the above steps, identify the edge positions of the standard clock data (i.e., the rising or falling edges of the clock). These positions represent the boundary points of the clock signal. From the original waveform data, starting from the clock edge position, several data segments are sliced according to a fixed time length. For example, if the length of each segment is one symbol period, then multiple data segments based on the clock edge will be obtained. These data segments are superimposed and plotted in the same coordinate system. The starting point of each segment is aligned to the clock edge position. Since the time axes of multiple data segments are aligned, the overlapping area will form an "eye"-shaped pattern, called the eye diagram.

[0139] It can be seen that the main purpose above is to check the synchronization between the signal and the clock and the signal quality by plotting the original waveform data and the standard clock data in the same coordinate system. This can help detect deviations in clock recovery or signal distortion; and by slicing and superimposing the signal over multiple clock cycles to generate an eye diagram and analyze the signal quality characteristics, such as jitter, distortion, etc. This is an effective signal quality inspection tool for evaluating the performance of digital communication systems.

[0140] In eye diagram analysis, the extraction of the standard clock is the basis for drawing the eye diagram. Before implementing the eye diagram analysis function, the test instrument must recover the standard clock signal from the signal under test. Therefore, in the analysis of serial data, clock recovery often plays an important role, and it can be considered that clock recovery is the basis for analyzing serial data.

[0141] Due to the characteristics of the hardware circuit, it cannot flexibly adjust parameters. Therefore, the clock recovery circuit usually matches the protocol specification and cannot be made universal. Therefore, this application proposes a method for constant clock recovery and eye diagram generation of high-speed serial data. All steps of this method are implemented by software, which has great flexibility. This method realizes the automatic selection of the decision threshold, extracts the signal transition edge through hysteresis comparison, then recovers the clock according to the signal transition edge, and finally completes the drawing of the eye diagram according to the recovered clock. This method does not require manual parameter configuration, thus reducing the usage threshold. At the same time, the all-software implementation method enables it to adapt to various types of protocols, thereby reducing the usage cost.

[0142] Based on the above steps S10 - S40, it can be seen that the technical solution of this application has the following advantages: 1) The selection of the threshold and the hysteresis voltage is obtained by performing a histogram statistics on the signal. Therefore, it can more accurately reflect the signal characteristics and effectively reduce the interference of noise on clock recovery; 2) The interference of noise on edge extraction is reduced through hysteresis comparison. The calculation process only requires three state values, reducing the calculation amount and improving the data processing ability per unit time; 3) The interference of low-frequency jitter on the clock is reduced by linearly fitting the signal edge using the least squares method.

[0143] The following combines with actual engineering tests to elaborate on the technical solution of this application in detail:

[0144] The PRBS random code waveform is emitted through an arbitrary waveform generator at a baud rate of 1 Gbps. The waveform data is collected by an oscilloscope, and then the offline analysis is carried out using the standard clock recovery and eye diagram generation method proposed in the above steps S10 - S40.

[0145] The analysis results are as follows:

[0146] Refer to Figure 7 , the transition edge of the signal is successfully extracted by the method proposed in this application; refer to Figure 8 , the standard clock of the signal is successfully recovered by the method proposed in this application; refer to Figure 9 , the signal eye diagram is successfully drawn using the method proposed in this application. Thus, it can be seen that the method proposed in this application is effective for clock recovery and eye diagram generation of high-speed serial data.

[0147] Combined with Figure 10, embodiments of the present application further provide a signal clock recovery device for high-speed serial data applicable to the above communication device. Among them, the signal clock recovery device for high-speed serial data may include a threshold calculation module, an edge extraction module, and a clock recovery module.

[0148] The threshold calculation module can be used to perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; obtain the bottom value of the probability density curve and the top value of the probability density curve; and obtain a high-level threshold and a low-level threshold based on the bottom value and the top value. In the embodiments of the present application, the threshold calculation module can be used to execute Figure 2 the steps S10 - S20 shown. For the relevant content of the threshold calculation module, reference can be made to the description of steps S10 - S20 above.

[0149] The edge extraction module can be used to extract a signal edge intersection point sequence based on the high-level threshold and the low-level threshold. In the embodiments of the present application, the edge extraction module can be used to execute Figure 2 the step S30 shown. For the relevant content of the edge extraction module, reference can be made to the description of step S30 above.

[0150] The clock recovery module can be used to calculate the difference between signal edge intersection points based on the signal edge intersection point sequence. In the embodiments of the present application, the clock recovery module can be used to execute Figure 2 the step S40 shown. For the relevant content of the clock recovery module, reference can be made to the description of step S40 above.

[0151] In the embodiments of the present application, corresponding to the above signal clock recovery method for high-speed serial data applied to the communication device, a computer-readable storage medium is further provided. A computer program is stored in the computer-readable storage medium, and when the computer program runs, it executes each step of the signal clock recovery method for high-speed serial data. Among them, the steps executed when the foregoing computer program runs will not be elaborated here one by one, and reference can be made to the foregoing explanation of the signal clock recovery method for high-speed serial data.

[0152] In summary, for the signal clock recovery method, apparatus, and communication device for high-speed serial data provided in this application, first, the collected signal is statistically analyzed by histogram based on the voltage direction to obtain a probability density curve; the bottom value of the probability density curve and the top value of the probability density curve are obtained; then, based on the bottom value and the top value, a high-level threshold and a low-level threshold are obtained; then, based on the high-level threshold and the low-level threshold, a signal edge crossing point sequence is extracted; based on the signal edge crossing point sequence, the difference between signal edge crossing points is calculated; and finally, clock recovery is performed based on the difference between signal edge crossing points to obtain standard clock data. Based on the above, it can be seen that in the technical solution of this application, the selection of the threshold and the selection of the hysteresis voltage are obtained by performing a histogram statistics on the signal. Therefore, it can more accurately reflect the signal characteristics and effectively reduce the interference of noise on clock recovery. In addition, the technical solution of this application reduces the interference of noise on edge extraction through hysteresis comparison. The calculation process only requires three state values, reducing the calculation amount and improving the data processing ability per unit time. Based on this, the technical solution of this application can effectively improve the efficiency of serial data clock recovery.

[0153] In several embodiments provided in the embodiments of the present application, it should be understood that the disclosed apparatus and method can also be implemented in other ways. The apparatus and method embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of apparatuses, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0154] In addition, each functional module in various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0155] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a communication device, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs. It should be noted that in this article, the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

[0156] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A signal clock recovery method for high-speed serial data, characterized in that: include: Perform histogram statistical analysis on the collected signals based on the voltage direction to obtain a probability density curve; Based on the probability density curve, obtain the bottom value of the probability density curve and the top value of the probability density curve; the bottom value refers to the peak value of the 40% area on the left side of the probability density curve, and the top value refers to the peak value of the 40% area on the right side of the probability density curve; Based on the bottom value and the top value, a high level threshold and a low level threshold are obtained; the step of obtaining the high level threshold and the low level threshold based on the bottom value and the top value comprises: based on the bottom value and the top value, a jump crossing point threshold and a hysteresis range are calculated; the jump crossing point threshold is obtained by multiplying the sum of the bottom value and the top value by a first preset coefficient; the hysteresis range is obtained by multiplying the difference between the top value and the bottom value by a second preset coefficient; the first preset coefficient is greater than the second preset coefficient, and the first preset coefficient and the second preset coefficient are both less than 1; based on the jump crossing point threshold and the hysteresis range, a high level threshold and a low level threshold are calculated; Extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold; Based on the signal edge crossing point sequence, a signal edge crossing point difference is calculated; based on the signal edge crossing point difference, clock recovery is performed to obtain standard clock data.

2. The signal clock recovery method of high-speed serial data according to claim 1, characterized in that: The step of calculating a high level threshold and a low level threshold based on the transition crossing point threshold and the hysteresis range comprises: The sum of the transition crossing point threshold and the hysteresis range is used as a high level threshold; The difference between the transition crossing point threshold and the hysteresis range is used as a low level threshold.

3. The signal clock recovery method of high-speed serial data according to claim 2, characterized in that: The step of extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold comprises: Comparing the signal voltage value with the high level threshold and the low level threshold; If the signal voltage value is higher than or equal to the transition crossing point threshold and higher than or equal to the high level threshold, the judgment result is a high level signal; If the signal voltage value is lower than the low level threshold, the judgment result is a low level signal; If the signal voltage value is greater than the low level threshold and less than the high level threshold, the judgment result is a target level signal; When the decision result is a target level signal, a signal edge crossing point sequence is obtained.

4. The signal clock recovery method of high-speed serial data according to claim 3, characterized in that: When the judgment result is a target level signal, extracting and obtaining a signal edge crossing point sequence comprises: When the judgment result is a target level signal, a rising edge intersection point and a falling edge intersection point are extracted respectively; the rising edge intersection point means that the signal is a low level signal in n-1 clock cycles, and the signal is a high level signal in n clock cycles; the falling edge intersection point means that the signal is a high level signal in n-1 clock cycles, and the signal is a low level signal in n clock cycles; A signal edge crossing point sequence is obtained based on the rising edge crossing point and the falling edge crossing point.

5. The signal clock recovery method of high-speed serial data according to claim 1, characterized in that: The step of calculating a signal edge crossing point difference based on the signal edge crossing point sequence; Performing clock recovery based on the signal edge crossing point difference to obtain standard clock data includes: Based on the signal edge crossing point sequence, determine the time position of the edge crossing point in the (n+1)th clock cycle and the time position of the edge crossing point in the (n)th clock cycle, and perform a difference processing on the two to obtain a signal edge crossing point difference; Calculating a single-bit average symbol width based on the signal edge crossing point difference; Calculating an optimal symbol width based on the single-bit average symbol width; Calculate the optimal symbol width to perform linear fitting on the signal edge crossing point sequence, and calculate the slope value and the offset value; Based on the slope value and the offset value, clock recovery is performed to obtain standard clock data.

6. The signal clock recovery method of high-speed serial data according to claim 5, characterized in that: The slope value and the offset value satisfy the following relationship: LSMy=Y (LSMk, LSMb) = LSM (LSMx, LSMy) Among them, LSMk refers to the slope value; LSMb refers to the bias value; LSMx refers to the observed value of the signal edge crossing point sequence on the horizontal axis, that is, the value of the independent variable in the linear fitting; LSMy refers to the observed value of the signal edge crossing point sequence on the vertical axis, that is, the value of the dependent variable in the linear fitting; LSMx(n-1) refers to the observed value of the signal edge crossing point sequence on the horizontal axis in n-1 clock cycles; M(n) refers to the signal edge crossing point difference in n clock cycles; M(n-1) refers to the signal edge crossing point difference in n-1 clock cycles; Mpretty refers to the optimal symbol width.

7. The signal clock recovery method of high-speed serial data according to claim 6, characterized in that: The optimal symbol width satisfies the following relationship: Among them, Mpretty refers to the optimal symbol width, M refers to the signal edge crossing point difference, and Mmean refers to the single-bit average symbol width.

8. A signal clock recovery device for high-speed serial data, characterized in that: include: A threshold calculation module is used to perform histogram statistical analysis on the collected signal based on the voltage direction to obtain a probability density curve; Based on the probability density curve, the bottom value of the probability density curve and the top value of the probability density curve are obtained; the bottom value refers to the peak value of the 40% area on the left side of the probability density curve, and the top value refers to the peak value of the 40% area on the right side of the probability density curve; based on the bottom value and the top value, a high level threshold and a low level threshold are obtained; the step of obtaining the high level threshold and the low level threshold based on the bottom value and the top value includes: based on the bottom value and the top value, a jump crossing point threshold and a hysteresis range are calculated; the jump crossing point threshold is obtained by multiplying the sum of the bottom value and the top value by a first preset coefficient; the hysteresis range is obtained by multiplying the difference between the top value and the bottom value by a second preset coefficient; the first preset coefficient is greater than the second preset coefficient, and the first preset coefficient and the second preset coefficient are both less than 1; based on the jump crossing point threshold and the hysteresis range, a high level threshold and a low level threshold are calculated; An edge extraction module, used for extracting and obtaining a signal edge crossing point sequence based on the high level threshold and the low level threshold; The clock recovery module is used to calculate the signal edge crossing point difference based on the signal edge crossing point sequence; perform clock recovery based on the signal edge crossing point difference to obtain standard clock data.

9. A communication device, characterized in that: include: Memory for storing computer programs; A processor connected to the memory is used to execute a computer program stored in the memory to implement the signal clock recovery method for high-speed serial data as described in any one of claims 1 to 7.

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