Online upgrading system based on D trigger and upgrading method thereof

Abstract

The invention discloses an online upgrading system based on a D trigger and an upgrading method thereof.The system comprises a first chip, a channel change-over switch chip, the D trigger, a nonvolatile memory FLASH and a CPU, a GPIO1 output pin of the CPU is connected with the D input end of the D trigger, a GPIO2 output pin of the CPU is connected with the CLK input end of the D trigger, the Q output end of the D trigger is connected with the RESET pin of the first chip, and the RESET pin of the first chip is connected with the channel change-over switch chip. A Q # output end of the D trigger is connected with an SEL pin of the channel change-over switch chip, a main SPI interface of the first chip is connected with a slave SPI interface of the nonvolatile memory FLASH through the channel change-over switch chip, and a main SPI interface of the CPU is connected with the slave SPI interface of the nonvolatile memory FLASH through the channel change-over switch chip. According to the method and the device, the FLASH can be upgraded under the condition that the equipment is not disassembled or powered off, so that remote online upgrading is realized, and the whole system does not need to be disassembled.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to an online upgrading system based on a D flip-flop and an upgrading method thereof. Background Art

[0002] At present, in system design, due to the increasing flexibility of programming, the architecture based on field programmable gate array FPGA is increasingly used. FPGA is a product further developed on the basis of programmable devices such as GAL and CPLD. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

[0003] With the large-scale deployment of FPGA devices, the demand for FPGA online update functions is also increasing. Usually, when the FPGA program needs to be updated or upgraded on a device board that uses FPGA, the latest burning file needs to be written into the FPGA's external FLASH through technical means; then, the latest burning file needs to be loaded and run by powering on the device again.

[0004] However, during the entire FLASH burning process, the device needs to be powered off, disassembled, connected to an FPGA-specific external debugger, and use professional tool software. The entire upgrade process is time-consuming, labor-intensive, and very cumbersome, and the entire system needs to be disassembled, which adds extra costs. Summary of the invention

[0005] Purpose of the invention: The purpose of the present invention is to provide an online upgrade system and upgrade method based on a D flip-flop, which solves the problem that the existing FLASH upgrade process, for example, based on FPGA, requires powering off and disassembling the device, which is time-consuming, labor-intensive and very cumbersome.

[0006] Technical solution: The present invention discloses an online upgrade system based on a D flip-flop, the system comprising: a first chip, a channel switching switch chip, a D flip-flop, a non-volatile memory FLASH and a CPU, wherein the GPIO1 output pin of the CPU is connected to the D input terminal of the D flip-flop, the GPIO2 output pin of the CPU is connected to the CLK input terminal of the D flip-flop, the Q output terminal of the D flip-flop is connected to the RESET pin of the first chip, the Q# output terminal of the D flip-flop is connected to the SEL pin of the channel switching switch chip, the master SPI interface of the first chip is connected to the slave SPI interface of the non-volatile memory FLASH through the channel switching switch chip, and the master SPI interface of the CPU is connected to the slave SPI interface of the non-volatile memory FLASH through the channel switching switch chip;

[0007] Among them, when the CPU controls the D input of the D flip-flop to be low level and inputs a rising edge trigger signal to the CLK of the D flip-flop, the CPU updates the data of FLASH and performs the upgrade operation; otherwise, the CPU cannot update the data of FLASH.

[0008] Furthermore, the CPU is also connected to a network interface.

[0009] Furthermore, the first chip is a field programmable gate array chip FPGA; the model of the channel switching switch chip is Broadchip BCT4567; and the model of the D trigger is SN74LVC1G74DCUR of Texas Instruments.

[0010] Furthermore, the preset input terminal of the D flip-flop is powered on by a resistor pull-up by default, that is, a high level. When the preset input terminal receives a high level, the Q output terminal of the D flip-flop will be forced to a high level, and the Q# output terminal will be forced to a low level.

[0011] Furthermore, the channel switching switch chip includes three channels, A, B, and C. According to the high and low levels of the SEL pin, channel A and channel C are selected to be turned on, and channel B is in a high impedance state; or channel B and channel C are selected to be turned on, and channel A is in a high impedance state.

[0012] The present invention also includes an upgrade method of an online upgrade system based on a D flip-flop, comprising the following steps:

[0013] (1) The CPU inputs a low level to the D input of the D flip-flop through the GPIO1 output pin, and then sends a rising edge trigger signal to the CLK input of the D flip-flop through the GPIO2 output pin. Then the Q output of the D flip-flop outputs a low level, and the Q# output outputs a high level.

[0014] (2) At this time, the RESET pin of the first chip is pulled low, and the first chip enters a reset state; the SEL pin of the channel switching chip is pulled high, the data channel of the non-volatile memory FLASH is disconnected from the first chip, and is connected to the main SPI interface of the CPU, and the CPU performs read and write operations on the non-volatile memory FLASH through the main SPI interface; the CPU then obtains the data to be updated through the network interface to update the FLASH data and perform the upgrade operation;

[0015] (3) After the CPU completes the upgrade of the non-volatile memory FLASH, it performs a check to ensure that there are no errors. Then, the CPU inputs a high level to the D input of the D flip-flop through the GPIO1 output pin, and then sends a rising edge trigger signal to the CLK input of the D flip-flop through the GPIO2 output pin. Then, the Q output of the D flip-flop outputs a high level, and the Q# output outputs a low level.

[0016] (4) At this time, the RESET pin of the first chip is pulled high, and the first chip is released from the reset state; and the SEL pin of the channel switching chip is pulled low, the data channel of the non-volatile memory FLASH is disconnected from the CPU, and is connected to the main SPI interface of the first chip. The CPU then disconnects the data update of the non-volatile memory FLASH, and the upgrade operation is completed.

[0017] Furthermore, in the step (2), the SEL pin of the channel switching switch chip is pulled high, the data channel of the non-volatile memory FLASH is disconnected from the first chip, and is connected to the main SPI interface of the CPU, specifically referring to: the channel switching switch chip selects channel A and channel C to be connected according to the high level of the SEL pin, so that the data channel of the non-volatile memory FLASH is connected to the main SPI interface of the CPU; selects channel B to be in a high impedance state, so that the data channel of the non-volatile memory FLASH is disconnected from the first chip; in the step (4), the SEL pin of the channel switching switch chip is pulled low, the data channel of the non-volatile memory FLASH is disconnected from the CPU, and is connected to the main SPI interface of the first chip, specifically referring to: the channel switching switch chip selects channel B and channel C to be connected according to the low level of the SEL pin, so that the data channel of the non-volatile memory FLASH is connected to the main SPI interface of the first chip; selects channel A to be in a high impedance state, so that the data channel of the non-volatile memory FLASH is disconnected from the CPU.

[0018] Furthermore, before step (1), the preset input terminal of the D flip-flop is powered on by default, that is, at a high level, by means of a resistor pull-up. The Q output terminal of the D flip-flop is forced to a high level, and the Q# output terminal is forced to a low level. At this time, the RESET pin of the first chip is pulled high, the first chip is released from the reset state, the SEL pin of the channel switching chip is pulled low, the data channel of the non-volatile memory FLASH is connected to the main SPI interface of the first chip, and the first chip executes a normal power-on loading process.

[0019] Beneficial effects of the present invention:

[0020] (1) The present invention can upgrade, for example, FPGA-based FLASH without disassembling the device or powering off the device, thereby realizing remote online upgrade without disassembling the entire system.

[0021] (2) The present invention can provide high reliability and stability for the circuit by using a D flip-flop. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural diagram of an online upgrade system based on a D flip-flop of the present invention;

[0023] Figure 2This is the truth table diagram of the channel switching chip;

[0024] Figure 3 The figure is a flow chart of the online upgrade method based on D flip-flop of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0026] As described in the background technology, with the large-scale deployment of FPGA devices, the demand for FPGA online update function is also increasing. Generally, when the field programmable gate array chip FPGA is powered on, it automatically updates the program source file through SPI loading. For example, in the existing technology, the SPI pin of the field programmable gate array chip FPGA is directly interconnected with the non-volatile memory FLASH. However, during the entire process of burning FLASH, the FPGA device needs to be powered off and disassembled, making the entire upgrade process time-consuming and labor-intensive, and very cumbersome, and the entire system needs to be disassembled. Therefore, how to ensure the success of FPGA online update without powering off or disassembling has become a technical problem that the industry urgently needs to solve.

[0027] In view of this, the present application proposes an online upgrade system based on a D flip-flop for online updating of FPGA. Figure 1 The system comprises: a first chip 1, a channel switching chip 2, a D trigger 3, a non-volatile memory FLASH 4 and a CPU 5, wherein the first chip 1 is a field programmable gate array chip FPGA; a GPIO1 output pin of the CPU 5 is connected to a D input end of the D trigger 3, a GPIO2 output pin of the CPU 5 is connected to a CLK input end of the D trigger 3, a Q output end of the D trigger 3 is connected to a RESET pin of the first chip 1, a Q# output end of the D trigger 3 is connected to a SEL pin of the channel switching chip 2, a master SPI interface of the first chip 1 is connected to a slave SPI interface of the non-volatile memory FLASH 4 through the channel switching chip 2, and a master SPI interface of the CPU 5 is connected to a slave SPI interface of the non-volatile memory FLASH 4 through the channel switching chip 2; the CPU 5 is also connected to a network interface 6, and a source file to be updated is obtained through the network interface 6.

[0028] In this system, when CPU 5 controls the D input of D flip-flop 3 to be low level and inputs a rising edge trigger signal to the CLK of D flip-flop 3, CPU 5 updates the data of FLASH and performs an upgrade operation; otherwise, CPU 5 cannot update the data of FLASH, then the first chip 1, i.e., FPGA, automatically obtains the data file stored in FLASH from the main SPI interface, and performs loading and self-starting processes according to the data file.

[0029] In this embodiment, a channel switching switch chip 2 is added between the first chip 1 and the non-volatile memory FLASH 4. The model of the channel switching switch chip 2 is Broadchip BCT4567. The channel switching switch chip 2 has the characteristics of low on-resistance and fast response time, and does not affect the normal transmission of signals when it is enabled.

[0030] The channel switching switch chip 2 is a bidirectional analog switching switch chip. The chip includes three channels, A, B, and C, which can also be called the first to third channels. Each channel has 4 signal lines. Figure 2 The function of the chip is to select channel A and channel C to be turned on and channel B to be in high impedance state, that is, the first channel and the third channel are turned on and the second channel is in high impedance state, according to the high and low levels of the SEL pin; or to select channel B and channel C to be turned on and channel A to be in high impedance state, that is, the first channel is in high impedance state and the second channel and the third channel are turned on.

[0031] In this embodiment, a D flip-flop 3 is selected to simultaneously control the RESET pin of the first chip 1 and the SEL pin of the channel switching switch chip 2. The D flip-flop 3 is a common digital circuit element and is widely used in digital logic circuits. The D flip-flop 3 has a bistable characteristic. It usually has two stable output states and can switch between the two states through a specific control signal. The model of the D flip-flop 3 selected in this embodiment is the SN74LVC1G74DCUR of Texas Instruments. The D flip-flop 3 generally has a D input terminal for data input and a CLK input terminal for clock input; when the rising edge of the clock input signal arrives, the D flip-flop 3 copies the data state of the D input terminal to the Q output terminal, and reversely copies the input state of the D input terminal to the Q# output terminal. There may be different types of D flip-flops, but the basic principles are the same.

[0032] The D flip-flop 3 usually has a preset input terminal. When the preset input terminal receives a high level, the Q output terminal of the D flip-flop 3 will be forced to a high level, and the Q# output terminal will be forced to a low level. In this embodiment, the Q output terminal of the D flip-flop 3 controls the RESET pin of the first chip 1, and the Q# output terminal controls the SEL pin of the channel switching switch chip 2. The preset input terminal of the D flip-flop 3 is pulled up by a resistor by default, that is, a high level when powered on. In this embodiment, when the system is powered on for the first time, the first chip 1, i.e., the FPGA, automatically releases the reset, the channel switching switch chip 2 selects the SPI of the first chip 1 to the non-volatile memory FLASH 4, and the FPGA executes the normal power-on loading process.

[0033] like Figure 3 As shown, based on the online upgrade system of the D flip-flop, this embodiment also proposes an upgrade method of the online upgrade system based on the D flip-flop, the method comprising the following steps:

[0034] First, before step (1), the preset input terminal of the D flip-flop 3 is powered on by default, that is, at a high level, by means of a resistor pull-up. The Q output terminal of the D flip-flop 3 is forced to be a high level, and the Q# output terminal is forced to be a low level. At this time, the RESET pin of the first chip 1 is pulled high, the first chip 1 is released from the reset state, the SEL pin of the channel switching chip 2 is pulled low, the data channel of the non-volatile memory FLASH 4 is connected to the main SPI interface of the first chip 1, and the first chip 1 executes a normal power-on loading process.

[0035] Step (1), when the FPGA FLASH needs to be updated online, the CPU 5 inputs a low level data to the D input terminal of the D flip-flop 3 through the GPIO1 output pin, and then gives a rising edge trigger signal to the clock CLK input terminal of the D flip-flop 3 through the GPIO2 output pin, then the Q output terminal of the D flip-flop 3 outputs a low level, and the Q# output terminal outputs a high level;

[0036] Step (2), at this time, the RESET pin of the first chip 1, i.e., the FPGA, is pulled low, and the first chip 1 enters a reset state; and the SEL pin of the channel switching switch chip 2 is pulled high, and the data channel of the non-volatile memory FLASH 4 is disconnected from the first chip 1, and is connected to the main SPI interface of the CPU 5, specifically: the channel switching switch chip 2 selects channel A and channel C to be connected according to the high level of the SEL pin, i.e., the first channel and the third channel are connected, so that the data channel of the non-volatile memory FLASH 4 is connected to the main SPI interface of the CPU 5; selects channel B to be in a high impedance state, i.e., the second channel is in a high impedance state, so that the data channel of the non-volatile memory FLASH 4 is disconnected from the first chip 1; thus, it can be seen that the channel in the channel switching switch chip 2 connected to the first chip 1 is channel B, i.e., the second channel, the channel connected to the CPU 5 is channel A, i.e., the first channel, and the channel connected to the non-volatile memory FLASH 4 is channel C, i.e., the third channel; CPU 5, that is, the non-volatile memory FLASH4 is read and written through the main SPI interface; the CPU then obtains the data to be updated through the network interface 6 to update the FLASH data and perform the upgrade operation; at this point, the FPGA FLASH can be updated online;

[0037] Step (3), after CPU 5 completes the upgrade of non-volatile memory FLASH 4, that is, after the read and write operations are completed, it performs verification to ensure that there are no errors, CPU 5 inputs the data to the D input terminal of D flip-flop 3 as a high level through GPIO1 output pin, and then sends a rising edge trigger signal to the clock CLK input terminal of the D flip-flop through GPIO2 output pin, then the Q output terminal of D flip-flop 3 outputs a high level, and the Q# output terminal outputs a low level;

[0038] Step (4), at this time, the RESET pin of the first chip 1, i.e., the FPGA, is pulled high, and the first chip 1 automatically releases the reset state; and the SEL pin of the channel switching switch chip 2 is pulled low, and the data channel of the non-volatile memory FLASH 4 is disconnected from the CPU 5, and is connected to the main SPI interface of the first chip 1, specifically: the channel switching switch chip 2 selects the B channel and the C channel to be connected according to the low level of the SEL pin, i.e., the second channel and the third channel are connected, so that the data channel of the non-volatile memory FLASH 4 is connected to the main SPI interface of the first chip 1; selects the A channel high impedance state, i.e., the first channel is in a high impedance state, so that the data channel of the non-volatile memory FLASH 4 is disconnected from the CPU 5; the CPU 5 immediately disconnects the data update of the non-volatile memory FLASH 4, and the upgrade operation ends. The main SPI interface of the first chip 1 is connected, and the first chip 1, i.e., the FPGA, automatically obtains the data file stored in the FLASH from the main SPI interface, and loads and self-starts the process according to the data file. Since the positive and negative outputs of the D flip-flop 3 are usually synchronized with the clock signal, there is no timing problem. The present invention can upgrade the FPGA-based FLASH without disassembling the device or powering off the device, thereby realizing remote online upgrade without disassembling the entire system.

Claims

1. An online upgrade system based on a D flip-flop, characterized in that: The system comprises: a first chip, a channel switching switch chip, a D flip-flop, a non-volatile memory FLASH and a CPU, wherein a GPIO1 output pin of the CPU is connected to a D input end of the D flip-flop, a GPIO2 output pin of the CPU is connected to a CLK input end of the D flip-flop, a Q output end of the D flip-flop is connected to a RESET pin of the first chip, a Q# output end of the D flip-flop is connected to a SEL pin of the channel switching switch chip, a master SPI interface of the first chip is connected to a slave SPI interface of the non-volatile memory FLASH through the channel switching switch chip, and a master SPI interface of the CPU is connected to a slave SPI interface of the non-volatile memory FLASH through the channel switching switch chip; Among them, when the CPU controls the D input of the D flip-flop to be low level and inputs a rising edge trigger signal to the CLK of the D flip-flop, the CPU updates the data of FLASH and performs the upgrade operation; otherwise, the CPU cannot update the data of FLASH.

2. The online upgrade system based on D flip-flop according to claim 1, characterized in that: The CPU is also connected to a network interface.

3. The online upgrade system based on D flip-flop according to claim 1, characterized in that: The first chip is a field programmable gate array chip FPGA; the model of the channel switching switch chip is Broadcore BCT4567; and the model of the D trigger is SN74LVC1G74DCUR of Texas Instruments.

4. The online upgrade system based on D flip-flop according to claim 1, characterized in that: The preset input terminal of the D flip-flop is powered on by a resistor pull-up by default, that is, a high level. When the preset input terminal receives a high level, the Q output terminal of the D flip-flop will be forced to a high level, and the Q# output terminal will be forced to a low level.

5. The online upgrade system based on D flip-flop according to claim 3, characterized in that: The channel switching chip includes three channels, A, B, and C. According to the high and low levels of the SEL pin, the A channel and the C channel are turned on, and the B channel is in high impedance state; Or select channel B and channel C to be turned on and channel A to be in high impedance state.

6. An upgrade method for an online upgrade system based on a D flip-flop according to any one of claims 1 to 5, characterized in that: The following steps are involved: (1) The CPU inputs a low level to the D input of the D flip-flop through the GPIO1 output pin, and then sends a rising edge trigger signal to the CLK input of the D flip-flop through the GPIO2 output pin. Then the Q output of the D flip-flop outputs a low level, and the Q# output outputs a high level. (2) At this time, the RESET pin of the first chip is pulled low, and the first chip enters a reset state; the SEL pin of the channel switching chip is pulled high, the data channel of the non-volatile memory FLASH is disconnected from the first chip, and is connected to the main SPI interface of the CPU, and the CPU performs read and write operations on the non-volatile memory FLASH through the main SPI interface; the CPU then obtains the data to be updated through the network interface to update the FLASH data and perform the upgrade operation; (3) After the CPU completes the upgrade of the non-volatile memory FLASH, it performs a check to ensure that there are no errors. Then, the CPU inputs a high level to the D input of the D flip-flop through the GPIO1 output pin, and then sends a rising edge trigger signal to the CLK input of the D flip-flop through the GPIO2 output pin. Then, the Q output of the D flip-flop outputs a high level, and the Q# output outputs a low level. (4) At this time, the RESET pin of the first chip is pulled high, and the first chip is released from the reset state; and the SEL pin of the channel switching chip is pulled low, the data channel of the non-volatile memory FLASH is disconnected from the CPU, and is connected to the main SPI interface of the first chip. The CPU then disconnects the data update of the non-volatile memory FLASH, and the upgrade operation is completed.

7. The upgrading method according to claim 6, characterized in that: In the step (2), the SEL pin of the channel switching switch chip is pulled high, the data channel of the non-volatile memory FLASH is disconnected from the first chip, and is connected to the main SPI interface of the CPU, which specifically refers to: the channel switching switch chip selects channel A and channel C to be connected according to the high level of the SEL pin, so that the data channel of the non-volatile memory FLASH is connected to the main SPI interface of the CPU; selects channel B to be in a high impedance state, so that the data channel of the non-volatile memory FLASH is disconnected from the first chip; in the step (4), the SEL pin of the channel switching switch chip is pulled low, the data channel of the non-volatile memory FLASH is disconnected from the CPU, and is connected to the main SPI interface of the first chip, which specifically refers to: the channel switching switch chip selects channel B and channel C to be connected according to the low level of the SEL pin, so that the data channel of the non-volatile memory FLASH is connected to the main SPI interface of the first chip; selects channel A to be in a high impedance state, so that the data channel of the non-volatile memory FLASH is disconnected from the CPU.

8. The upgrading method according to claim 6, characterized in that: Before step (1), the preset input terminal of the D flip-flop is powered on by default, that is, at a high level, by means of a resistor pull-up. The Q output terminal of the D flip-flop is forced to be a high level, and the Q# output terminal is forced to be a low level. At this time, the RESET pin of the first chip is pulled high, the first chip is released from the reset state, the SEL pin of the channel switching chip is pulled low, the data channel of the non-volatile memory FLASH is connected to the main SPI interface of the first chip, and the first chip executes a normal power-on loading process.

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