Program performance analysis method, device, medium, and product

Abstract

This invention relates to the field of computer technology and discloses a method, device, medium, and product for program performance analysis. The method includes: starting a user program; creating a sub-thread using the user program; and retrieving an idle target structure from a structure array; statistically analyzing asynchronous and synchronous task performance data within a set code interval and updating it to the target structure; using the sub-thread to detect the updated target structure data; calculating the average utilization rate of the board acceleration module during the start and end time periods of asynchronous operations, as well as the time consumption data from the start to the end time of synchronous operations; and obtaining the average utilization rate of the board acceleration module and the average transmission bandwidth throughout the entire user program execution process based on the data calculated by the sub-thread. This approach closely reflects actual execution scenarios, making the statistical data practical and flexible, more comprehensively reflecting the performance during the process, and achieving accurate program performance analysis.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, medium, and product for program performance analysis. Background Technology

[0002] In relevant technical solutions, performance analysis of programs generally relies on performance analysis tools provided by the board manufacturer. These tools can track the number of calls to the board's runtime and operator libraries, execution time, and other information throughout the user program's execution. The results are typically displayed in sequence using visualization tools. The runtime and operator information tracked by this tool comes from the board's Software Development Kit (SDK), meaning the tool can only track the calls to interfaces within the SDK provided by the board.

[0003] In addition to the tools provided by board manufacturers, some framework software offers other performance analysis tools that add specific performance statistics function code. However, their use cases are relatively limited. They only count the interface performance within the framework, and the results only include information such as the number of interface calls and logic processing time, but cannot collect data that reflects the board's performance. Summary of the Invention

[0004] The purpose of this invention is to provide a program performance analysis method, device, medium, and product that can fit the actual execution scenario, make the statistical data practical and flexible, more comprehensively reflect the performance situation in the process, and achieve accurate analysis of program performance.

[0005] To address the aforementioned technical problems, this invention provides a program performance analysis method, the method comprising:

[0006] Start the user program, create a sub-thread using the user program, and retrieve an idle target structure from the structure array;

[0007] Collect performance data of asynchronous tasks and synchronous tasks in a defined code range, and update the asynchronous task performance data and synchronous task performance data to the target structure;

[0008] The target structure data to be updated is detected by the sub-thread, and the average utilization rate of the board acceleration module during the time period when the asynchronous operation starts and ends is calculated, as well as the time consumption data from the start time to the end time of the synchronous operation.

[0009] Based on the average utilization and time consumption data calculated by the sub-thread, combined with the asynchronous task performance data and the synchronous task performance data, the average utilization and average transmission bandwidth of the board acceleration module during the entire execution process of the user program are obtained.

[0010] Firstly, the program performance analysis method provided by the present invention further includes:

[0011] The sub-thread records the idle time between two adjacent task operations, and according to the recorded idle time, a set number of idle time information is counted as potential optimization time intervals; the idle time information includes idle duration, idle start time, operation name and operation sequence number.

[0012] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, the asynchronous task performance data includes asynchronous execution time; the process of calculating the asynchronous execution time includes:

[0013] An asynchronous operation statistics interface is constructed using a structure containing a first constructor and a first destructor.

[0014] The asynchronous operation statistics interface is used to create and record events in the first constructor and the first destructor, respectively, so as to calculate the asynchronous execution time through the interface provided by the software development kit.

[0015] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, the performance data of the synchronization task includes the synchronization execution time; the process of calculating the synchronization execution time includes:

[0016] A structure containing a second constructor and a second destructor is used to construct the synchronization operation statistics interface;

[0017] The second constructor is called using the synchronous operation statistics interface to record the start time of the statistics, and the second destructor is called to record the end time of the statistics when leaving the scope of the statistics.

[0018] The synchronous execution time is calculated based on the start and end times of the statistical content.

[0019] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, while updating the asynchronous task performance data and synchronous task performance data to the target structure, it also includes:

[0020] When the user program writes updated data, the write operation wakes up the child thread that is in a blocked waiting state; when the user program performs a write operation, the child thread cannot perform a write operation at the same time.

[0021] When the user program has not written updated data, the sub-thread enters a blocked waiting state.

[0022] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, the process of the sub-thread detecting the updated target structure data includes:

[0023] If the sub-thread detects that the update is the start timer operation of an asynchronous operation, it queries the completion flag of the asynchronous operation end event in real time and calculates the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation.

[0024] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, if the sub-thread detects that the update is the start timer operation of an asynchronous operation, it queries the completion flag of the asynchronous operation end event in real time, and calculates the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation, including:

[0025] If the sub-thread detects that the user program has written an asynchronous operation event and finds that the event has started to execute in the asynchronous task sequence, it periodically and in real time detects and counts the utilization rate of the board acceleration module used by the sub-thread until the user program updates the end event data and finds that the asynchronous operation end event has been completed.

[0026] Based on the statistical utilization rate of the board acceleration module, calculate the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation.

[0027] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, the process of the sub-thread detecting the updated target structure data further includes:

[0028] If the sub-thread detects that the updated data is the end timer data of the synchronization operation, it calculates the time elapsed from the start time to the end time of the synchronization operation.

[0029] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, when the user program is operated by multiple processes, each process uses an accelerator card.

[0030] Each process corresponds to one sub-thread; each sub-thread stores the corresponding accelerator card device number to distinguish different board data.

[0031] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, the present invention further includes:

[0032] Create shared memory;

[0033] Correspondingly, after calculating the average utilization rate of the board acceleration module during the start and end time periods of asynchronous operations, and the time consumption data from the start time to the end time of synchronous operations, the following is also included:

[0034] The calculated average utilization and time consumption data, as well as the asynchronous task performance data and the synchronous task performance data, are stored in shared memory.

[0035] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, based on the average utilization and time consumption data calculated by the sub-thread, combined with the asynchronous task performance data and the synchronous task performance data, the average utilization and average transmission bandwidth of the board acceleration module during the entire execution process of the user program are obtained, including:

[0036] Using the operation time of each task operation saved by the sub-thread and the calculated average utilization rate, the average utilization rate of the board acceleration module during the entire execution process of the user program is calculated.

[0037] The average transmission bandwidth during the entire execution of the user program is calculated by using the amount of data transmitted in each data transmission operation and the time consumption data calculated by the sub-thread.

[0038] On the other hand, in the above-mentioned program performance analysis method provided by the present invention, the average utilization rate of the board acceleration module during the entire execution process of the user program is calculated by using the operation time of each task operation stored in the sub-thread and the calculated average utilization rate, including:

[0039] The average utilization rate of the board acceleration module is obtained by multiplying the operation time of each task operation saved by the sub-thread by the calculated average utilization rate and then dividing by the total operation time.

[0040] Correspondingly, using the amount of data transmitted in each data transmission operation and the time consumption data calculated by the sub-thread, the average transmission bandwidth during the entire execution of the user program is calculated, including:

[0041] The total amount of data transmitted in each data transmission operation is obtained based on the amount of data transmitted in each operation.

[0042] The average transmission bandwidth during the entire execution of the user program is obtained by dividing the total amount of data transmitted in the data transmission operation task by the time consumption data calculated by the sub-thread.

[0043] To address the aforementioned technical problems, the present invention also provides a program performance analysis device, the device comprising:

[0044] Memory, used to store computer programs;

[0045] A processor is used to implement the steps of the above-described program performance analysis method when executing the computer program.

[0046] To address the aforementioned technical problems, the present invention also provides a non-volatile storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the aforementioned program performance analysis method.

[0047] To address the aforementioned technical problems, the present invention also provides a computer program product, comprising a computer program / instructions, wherein the computer program / instructions, when executed by a processor, implement the steps of the aforementioned program performance analysis method.

[0048] As can be seen from the above technical solution, the program performance analysis method provided by the present invention includes: starting a user program, creating a sub-thread using the user program, and retrieving an idle target structure from a structure array; statistically analyzing the performance data of asynchronous tasks and synchronous tasks in a set code interval, and updating the asynchronous task performance data and synchronous task performance data into the target structure; using the sub-thread to detect the updated target structure data, calculating the average utilization rate of the board acceleration module during the time period of the start and end of the asynchronous operation, and the time consumption data from the start time to the end time of the synchronous operation; and obtaining the average utilization rate and average transmission bandwidth of the board acceleration module during the entire execution process of the user program based on the average utilization rate and time consumption data calculated by the sub-thread, combined with the asynchronous task performance data and synchronous task performance data.

[0049] The beneficial effects of this invention are that the above-mentioned program performance analysis method provided by this invention can perform performance data statistics based on a set code interval, which is more in line with the actual execution scenario. This results in smaller granularity of the statistical data, making it more practical and flexible, and enabling more refined performance analysis. It avoids the influence of other unrelated logical parts on the final statistical results. Moreover, it counts the performance data of asynchronous tasks and synchronous tasks, which can more comprehensively reflect the performance situation in the process. By using the structure data updated by the sub-thread to calculate the average utilization rate of the board acceleration module during the time period of the start and end of the asynchronous operation, as well as the time consumption data from the start time to the end time of the synchronous operation, the tool can calculate the average utilization rate and average transmission bandwidth of the board acceleration module during the entire program execution process. This enables accurate analysis of program performance and lays the foundation for program optimization.

[0050] In addition, the present invention also provides corresponding program performance analysis equipment, non-volatile storage media and products for program performance analysis methods, which have the same or corresponding technical features as the program performance analysis methods mentioned above, and have the same effects. Attached Figure Description

[0051] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A flowchart of a program performance analysis method provided in an embodiment of the present invention;

[0053] Figure 2 This is a schematic diagram of the logical architecture of each part of the program performance analysis method provided in the embodiments of the present invention;

[0054] Figure 3 A flowchart illustrating the specific process of statistical asynchronous time in the program performance analysis method provided in this embodiment of the invention;

[0055] Figure 4 This is a schematic diagram of the structure of the program performance analysis device provided in an embodiment of the present invention;

[0056] Figure 5 This is a schematic diagram of the structure of the program performance analysis device provided in an embodiment of the present invention. Detailed Implementation

[0057] Currently, performance analysis of AI programs generally relies on performance analysis tools provided by board manufacturers. These tools collect data on the user program's interactions with the board's runtime and operator libraries during execution, and the results are typically displayed sequentially using visualization tools. The runtime and operator information collected by these tools comes from the board's software development kit (SDK), meaning they only analyze interface calls within the SSD. Besides board manufacturer tools, some frameworks offer other performance analysis tools, such as the profiler functionality in PyTorch (an open-source deep learning framework for machine learning and deep learning). Users add performance statistics code before the Python code that needs to be analyzed. After program execution, the performance statistics section displays a summary of performance data, including the number of calls to each interface, total execution time, and maximum and minimum execution times. However, this method is limited to the PyTorch framework and requires Python code for the statistics, restricting its application scenarios. The results only include the number of interface calls and their times, but cannot provide data reflecting the board's overall performance.

[0058] To address the aforementioned technical problems, this invention provides a program performance analysis method. The technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this invention.

[0059] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Figure 1 A flowchart of the program performance analysis method provided in the embodiments of the present invention is shown below. Figure 1 As shown, the method includes the following steps:

[0060] S101. Start the user program, create a sub-thread using the user program, and retrieve an idle target structure from the structure array.

[0061] As can be understood, a structure refers to structured data composed of a group of data. The data type of a structure consists of a set of different data called members (or fields, or elements), where each member can have a different type. Structures are typically used to represent several related data items of different types. The structure array of this invention can contain structures of multiple data lengths and is used to implement data transfer between user programs and sub-threads.

[0062] Figure 2 This is a schematic diagram of the logical architecture of each part of the program performance analysis method provided in this embodiment of the invention. In implementation, as... Figure 2 As shown, the execution entity of this invention can be a program performance analysis tool. The user program is started through this tool, and can create sub-threads through an initialization function and retrieve idle target structures from the structure array. After the user program finishes execution or exits midway, the tool collects and processes the information collected by the sub-threads and displays it.

[0063] It should be noted that this invention can pre-call the statistical operation initialization interface for preparatory work such as child thread creation; it can also pre-add statistical interface functions. When the added statistical interface function is executed, the statistical interface function can obtain a free target structure from the structure array.

[0064] S102. Collect the performance data of asynchronous tasks and synchronous tasks in the specified code range, and update the performance data of asynchronous tasks and synchronous tasks to the target structure.

[0065] In implementation, this invention can add corresponding interfaces to any code segment requiring performance analysis to complete interface data collection. Furthermore, to specifically analyze the performance of local code segments, it provides statistical start and end interface functions to control the code range for statistical operations (i.e., the code range requiring performance analysis). Before executing step S102 to statistically analyze the asynchronous and synchronous task performance data within the defined code range, the invention can specifically include: adding statistical operation start and end control functions to the code range to be analyzed; using the statistical start and end interface functions to locally select the program code to determine the code range corresponding to the statistical operation. The statistical operation only counts the code performance within the statistical start and end range. Correspondingly, statistically analyzing the asynchronous and synchronous task performance data within the defined code range can specifically involve statistically analyzing the asynchronous and synchronous task performance data within the code range corresponding to the determined statistical operation. Compared to the board vendor's tools that perform all statistics from beginning to end, the patent's statistics have a smaller granularity, avoiding the influence of other unrelated logic on the final statistical results. Compared to the PyTorch framework's profiler statistical tool, the patent's content supports performance statistics across multiple intervals, making the statistical operation more flexible.

[0066] In practical applications, asynchronous task performance data can be understood as a summary of the performance of asynchronous operations, which may include asynchronous execution time, the name of the asynchronous task, and the size of data transfer. Synchronous task performance data can be understood as a summary of the performance of synchronous operations, which may include synchronous execution time, the name of the synchronous task, and the size of data transfer.

[0067] S103. Use a sub-thread to detect the updated target structure data, calculate the average utilization rate of the board acceleration module during the time period when the asynchronous operation starts and ends, and the time consumption data from the start time to the end time of the synchronous operation.

[0068] S104. Based on the average utilization and time consumption data calculated by the sub-threads, combined with the asynchronous task performance data and synchronous task performance data, obtain the average utilization and average transmission bandwidth of the board acceleration module during the entire user program execution process.

[0069] In practical applications, the aforementioned user program can be an artificial intelligence program. In the field of artificial intelligence, solutions generally consist of multiple components, including one or more models / algorithms, various dependency packages and training / pushing frameworks, and one or more accelerator cards. Together, these components constitute a complete artificial intelligence system to solve a specific problem. This invention can perform performance analysis on artificial intelligence programs.

[0070] The program performance analysis method provided in this embodiment of the invention can perform performance data statistics based on a set code interval, closely matching the actual execution scenario. This results in smaller granularity of the statistical data, making it more practical and flexible, enabling more refined performance analysis and avoiding the influence of other unrelated logical parts on the final statistical results. Furthermore, it statistically analyzes asynchronous and synchronous task performance data, providing a more comprehensive reflection of the performance situation during the process. By using the updated structure data detected by the sub-thread to calculate the average utilization rate of the board acceleration module during the start and end time periods of asynchronous operations, as well as the time consumption data from the start to the end time of synchronous operations, the tool can calculate the average utilization rate and average transmission bandwidth of the board acceleration module throughout the entire program execution process. This allows for accurate analysis of program performance and lays the foundation for program optimization.

[0071] It should be noted that in this invention, the program execution time for developers consists of two parts: time spent on the server side and time spent on asynchronous operations executed on the accelerator card. This invention provides a set of interfaces for data statistics (e.g., asynchronous operation statistics interface and synchronous operation statistics interface) to calculate asynchronous execution time (also known as asynchronous start and end time) and synchronous execution time (also known as synchronous start and end time), as well as the operation name of the task. Specifically, the interface for data transmission records the size of the data transmitted.

[0072] Furthermore, in a specific implementation, in the above-mentioned program performance analysis method provided in the embodiments of the present invention, step S102 in the process of statistical asynchronous execution time in asynchronous task performance data may specifically include: using a structure containing a first constructor and a first destructor to construct an asynchronous operation statistics interface; using the asynchronous operation statistics interface to create events and record events in the first constructor and the first destructor respectively, so as to calculate the asynchronous execution time through the interface provided by the software development kit.

[0073] It's important to note that an event is a method provided by the accelerator card for handling asynchronous operations on the board. In implementation, the asynchronous operation statistics interface can be understood as an interface for collecting asynchronous time; it can be a structure containing a constructor and a destructor. The statistics of asynchronous execution time rely on the event mechanism interface in the board's software development kit (SDK). An event is created in both the constructor and destructor, and a record operation is performed. Later, during data processing, the interface provided by the SSD is used to calculate the time between the two events, thus determining the asynchronous execution time of the task.

[0074] Furthermore, in a specific implementation, in the above-mentioned program performance analysis method provided in the embodiments of the present invention, step S102, in the process of statistically analyzing the synchronization execution time in the performance data of the synchronization task, may specifically include: constructing a synchronization operation statistics interface using a structure containing a second constructor and a second destructor; using the synchronization operation statistics interface to call the second constructor to record the start time of the statistics content, and calling the second destructor to record the end time of the statistics content when leaving the scope of the statistics content; and calculating the synchronization execution time based on the start time and end time of the statistics content.

[0075] In implementation, the synchronization operation statistics interface can be understood as an interface for collecting synchronization time. It can also be a structure containing a constructor and a destructor. Developers define this structure at the starting point where they need to collect synchronization execution time statistics. The constructor is then called to record the start time of the statistics, and the destructor is called when the statistics leave their scope to record the end time. Developers can adjust the scope using parentheses.

[0076] The synchronous execution time, asynchronous execution time, operation name, and data size are stored in a structure data type. The structure information is generated in real time during program execution. In order to closely reflect the actual timing scenario of the developer's program when performing performance statistics, this invention can process the generated target structure data in real time by creating a new thread.

[0077] Furthermore, in a specific implementation, in the above-mentioned program performance analysis method provided in the embodiments of the present invention, while executing step S102 to update the asynchronous task performance data and synchronous task performance data into the target structure, it may also include: when the user program writes updated data, the write operation wakes up the child thread that is in a blocked waiting state; when the user program performs a write operation, the child thread cannot perform a write operation at the same time; when the user program does not write updated data, the child thread enters a blocked waiting state.

[0078] In implementation, to avoid excessive processor resource consumption by child threads, this invention implements a structure data type that supports write wake-up operations and read-write mutual exclusion through semaphore and lock mechanisms. The function of this data type is as follows: when a program writes to update structure data, the write operation simultaneously wakes up other child threads that are blocked and waiting for data updates; other child threads cannot write simultaneously while the program is performing a write operation. When the user program has not written updated data, the child threads enter a blocked waiting state.

[0079] Furthermore, in a specific implementation, in the above-mentioned program performance analysis method provided in the embodiments of the present invention, step S103, in the process of the sub-thread detecting the updated target structure data, may specifically include: if the sub-thread detects that the update is the start timer operation of an asynchronous operation, querying the completion flag of the asynchronous operation end event in real time, and calculating the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation. This is how the utilization rate of the board resources is obtained.

[0080] In the above steps, if the child thread detects that the update is the start timer of an asynchronous operation, it queries the completion flag of the asynchronous operation's end event in real time and calculates the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation. Specifically, this may include: if the child thread detects that the user program has written an event to the asynchronous operation and finds that the event has started execution in the asynchronous task sequence, it periodically and in real time detects and counts the utilization rate of the board acceleration module used by the child thread until the user program updates the end event data and finds that the asynchronous operation's end event has been completed; based on the counted utilization rate of the board acceleration module, it calculates the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation.

[0081] In implementation, after the child thread is woken up, it detects an updated structure. If the update is the start timer for an asynchronous operation, meaning the user program has inserted an event to record the start time of asynchronous execution, the child thread will detect in real time that the event has been completed. At this point, the asynchronous operation begins to execute on the acceleration module. The child thread periodically monitors the utilization rate of the acceleration module of the acceleration card used by the child thread in real time, and simultaneously queries the completion flag of the asynchronous operation end event. When the asynchronous operation end event is completed, the asynchronous operation execution ends, the child thread stops the acceleration module utilization statistics, calculates the average utilization rate during that time period, and saves it.

[0082] Figure 3 This is a flowchart illustrating the specific process of statistical asynchronous time analysis in the program performance analysis method provided in this embodiment of the invention. In implementation, as... Figure 3 As shown, when the child thread detects that the user program has written the initial event of an asynchronous operation and finds that the event has started execution in the asynchronous task sequence, the child thread periodically collects the utilization rate of the board's hardware acceleration module until the user program updates the end event data and finds that the end event has completed execution. Afterward, the average utilization rate of the acceleration module during this process is calculated, and the child thread saves the utilization rate value for later use. If new data is updated, the above operation continues until all updated data is completed. If no new data is updated, the child thread enters a blocked waiting state until the next data update by the user program wakes it up.

[0083] Furthermore, in a specific implementation, in the above-mentioned program performance analysis method provided in the embodiments of the present invention, step S103 in the process of the sub-thread detecting the updated target structure data may also include: if the sub-thread detects that the updated data is the end timer data of the synchronization operation, calculating the time consumed from the start time to the end time of the synchronization operation.

[0084] In practice, if the child thread detects that the updated data is the end timer data of the synchronization operation, the child thread can calculate and save the time elapsed from the start time to the end time of the synchronization operation.

[0085] Furthermore, in specific implementations, in the above-described program performance analysis method provided in the embodiments of the present invention, such as... Figure 2 As shown, when a user program operates through multiple processes, each process uses one accelerator card; each process corresponds to one child thread, i.e. Figure 2 In the process, process 1 corresponds to sub-thread 1, and process N corresponds to sub-thread N; each sub-thread stores the corresponding accelerator card device number to distinguish different board data.

[0086] In implementation, for distributed AI scenarios, user programs can operate on multiple processes, each using an accelerator card. Each user process then creates a sub-thread as described above. Besides storing the aforementioned information, the sub-thread also stores the accelerator card device number used by the thread to distinguish between different cards. After creating the sub-thread, the program executes normally.

[0087] Furthermore, in specific implementations, the program performance analysis method provided in the embodiments of the present invention may further include: creating shared memory. The shared memory is created by the program performance analysis tool so that subsequent child threads can fill in and update statistical data, after which the tool starts the user program. The time consumption data, utilization rate, and other additional data stored in the structure calculated by the synchronous and asynchronous operations can all be processed and saved to the shared memory allocated to the child thread.

[0088] Correspondingly, after calculating the average utilization rate of the board acceleration module during the time period of the start and end of the asynchronous operation, and the time consumption data from the start time to the end time of the synchronous operation, it may also include: storing the calculated average utilization rate and time consumption data, as well as the asynchronous task performance data and the synchronous task performance data in shared memory.

[0089] like Figure 2As shown, each sub-thread and the tool complete data transfer through shared memory. Each sub-thread obtains and uses the corresponding shared memory space through the device number. After completing the data processing for each operation, the sub-threads can also summarize and process data for the same task. The sub-threads save the data corresponding to different tasks in the shared memory in real time according to the agreed format, using the task name. The saved information for each task name includes the total execution time of the corresponding operation (synchronous operation) and / or the total execution time of the asynchronous operation, the number of calls, and the proportion of time spent in the entire operation. This information serves as the performance summary data of the user program. If it is an operator operation, the average utilization rate and duration of each acceleration module are also saved. If it is a data transfer operation, the size of the data transferred each time is also saved.

[0090] After the program ends, the program performance analysis tool can obtain the calculation results saved by the sub-threads of each process from the shared memory. The calculation results will compile and output the statistical data of each operation. The statistical data includes the name of all synchronous or asynchronous operations called during the program execution, the total time, the number of calls, and other information.

[0091] Furthermore, in a specific implementation, in the above-mentioned program performance analysis method provided in the embodiments of the present invention, step S104 obtains the average utilization rate and average transmission bandwidth of the board acceleration module during the entire user program execution process based on the average utilization rate and time consumption data calculated by the sub-thread, combined with the asynchronous task performance data and synchronous task performance data. Specifically, it may include: calculating the average utilization rate of the board acceleration module during the entire user program execution process using the operation time of each task operation saved by the sub-thread and the calculated average utilization rate; and calculating the average transmission bandwidth during the entire user program execution process using the amount of data transmitted in each data transmission operation and the time consumption data calculated by the sub-thread.

[0092] The above steps utilize the operation time of each task operation saved by the sub-thread and the calculated average utilization rate to calculate the average utilization rate of the board acceleration module during the entire user program execution process. Specifically, this can include: multiplying the operation time of each task operation saved by the sub-thread by the calculated average utilization rate and then dividing by the total operation time to obtain the average utilization rate of the board acceleration module during the entire user program execution process.

[0093] In implementation, the tool calculates the average utilization rate of the board acceleration module after the program ends, which is used for performance evaluation of the user program. The average utilization rate formula can be: the time of each operation saved by the sub-thread multiplied by the average board utilization rate during the operation, divided by the total time of each operation. This average utilization rate reflects the average utilization rate of the board acceleration module during the execution of the user program; the higher the value, the better the performance evaluation.

[0094] In addition, the above steps utilize the amount of data transmitted in each data transmission operation and the time consumption data calculated by the sub-thread to calculate the average transmission bandwidth during the entire execution of the user program. Specifically, this may include: obtaining the total amount of data transmitted in the data transmission operation task based on the amount of data transmitted in each data transmission operation; and obtaining the average transmission bandwidth during the entire execution of the user program by dividing the total amount of data transmitted in the data transmission operation task by the time consumption data calculated by the sub-thread.

[0095] During implementation, the tool calculates the average bandwidth of the transmission operation after the program ends. This average bandwidth is used to evaluate the user program's transmission rate. The formula for calculating the average transmission bandwidth is: the total amount of data transmitted in the data transmission operation task divided by the total time of the data transmission operation task. A higher average transmission bandwidth value indicates better transmission efficiency.

[0096] Furthermore, in a specific implementation, the above-mentioned program performance analysis method provided in the embodiments of the present invention may also include: using a sub-thread to record the idle time between two adjacent task operations, and according to the recorded idle time size, statistically analyzing a set number of idle time information as potential optimization time intervals; the idle time information includes idle duration, idle start time, operation name, and operation sequence number.

[0097] In implementation, the performance evaluation content of this invention, in addition to the average utilization rate and average transmission bandwidth of the acceleration module mentioned above, can also include the idle time. To record the larger idle time intervals on both the server and board sides, this invention, besides processing the structure data of each operation in real time, can also calculate the idle time between the end of the last operation and the start of the next operation, i.e., using statistical data to obtain the duration of the task's idle time period. A longer idle time indicates potential performance optimization opportunities. Whether this idle time can be optimized requires developers to locate the corresponding code logic based on the idle time's location information and conduct targeted analysis. This invention can statistically analyze and save the idle interval information of a predetermined number (e.g., the first 10) based on the idle time length; specifically, it can record the duration of these 10 idle intervals, as well as the operation sequence number and operation name before and after them for location purposes, while simultaneously updating the first 10 idle data in real time.

[0098] It should be noted that all final results obtained by this invention can be saved in file format for data comparison and verification, and can be displayed on the execution terminal interface. The program can exit after the performance analysis tool outputs the final results.

[0099] In the above embodiments, the program performance analysis method has been described in detail. This invention also provides embodiments of a program performance analysis device and a program performance analysis equipment. It should be noted that this invention describes the embodiments of the device from two perspectives: one based on functional modules, and the other based on hardware.

[0100] Figure 4 This is a schematic diagram of the program performance analysis device provided in an embodiment of the present invention. This embodiment is based on the perspective of functional modules, such as… Figure 4 As shown, the device includes:

[0101] The program startup module 10 is used to start the user program, create a sub-thread using the user program, and retrieve an idle target structure from the structure array.

[0102] The data statistics and update module 11 is used to collect statistics on the performance data of asynchronous tasks and synchronous tasks in a set code range, and update the performance data of asynchronous tasks and synchronous tasks to the target structure.

[0103] The sub-thread control module 12 is used to detect updated target structure data using sub-threads, calculate the average utilization rate of the board acceleration module during the time period when the asynchronous operation starts and ends, and the time consumption data from the start time to the end time of the synchronous operation.

[0104] The data calculation module 13 is used to obtain the average utilization and average transmission bandwidth of the board acceleration module during the entire user program execution process, based on the average utilization and time consumption data calculated by the sub-thread, combined with the asynchronous task performance data and the synchronous task performance data.

[0105] In the program performance analysis device provided in this embodiment of the invention, the interaction of the four modules allows for performance data statistics based on a set code interval, tailored to the actual execution scenario. This results in smaller granularity of the statistical data, greater practicality and flexibility, and more refined performance analysis, avoiding the influence of other unrelated logic on the final statistical results. Furthermore, the statistics cover both asynchronous and synchronous task performance data, providing a more comprehensive reflection of the performance during the process. By utilizing the updated structure data detected by the sub-thread, the average utilization rate of the board acceleration module within the start and end time periods of asynchronous operations, as well as the time consumption data from the start to the end time of synchronous operations, is calculated. This enables the tool to calculate the average utilization rate and average transmission bandwidth of the board acceleration module throughout the entire program execution process, achieving accurate program performance analysis and laying the foundation for program optimization.

[0106] Since the embodiments of the apparatus and the method correspond to each other, please refer to the description of the embodiments in the method section for the apparatus embodiments, which will not be repeated here. Furthermore, it has the same beneficial effects as the program performance analysis method mentioned above.

[0107] Furthermore, in a specific implementation, the data statistics and update module 11 in the above-described program performance analysis device provided in this embodiment of the invention may specifically include:

[0108] The asynchronous execution time calculation unit is used to construct an asynchronous operation statistics interface using a structure containing a first constructor and a first destructor; the asynchronous operation statistics interface is used to create and record events in the first constructor and the first destructor respectively, so as to calculate the asynchronous execution time through the interface provided by the software development kit;

[0109] The synchronous execution time calculation unit is used to construct a synchronous operation statistics interface using a structure containing a second constructor and a second destructor; it uses the synchronous operation statistics interface to call the second constructor to record the start time of the statistics content, and calls the second destructor to record the end time of the statistics content when leaving the scope of the statistics content; and calculates the synchronous execution time based on the start time and end time of the statistics content.

[0110] Furthermore, in a specific implementation, the data statistics and update module 11 in the above-described program performance analysis device provided in this embodiment of the invention may further include:

[0111] The child thread wake-up unit is used to wake up a child thread that is in a blocked waiting state when the user program writes updated data; the child thread cannot write while the user program is performing a write operation; when the user program has not written updated data, the child thread enters a blocked waiting state.

[0112] Furthermore, in a specific implementation, in the program performance analysis device provided in the embodiments of the present invention, the sub-thread control module 12 can be specifically used to query the completion flag of the asynchronous operation end event in real time if the sub-thread detects that the update is the start timer operation of the asynchronous operation, and calculate the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation; if the sub-thread detects that the update is the end timer data of the synchronous operation, calculate the time consumption data from the start time to the end time of the synchronous operation.

[0113] Furthermore, in a specific implementation, in the program performance analysis device provided in the embodiments of the present invention, the data calculation module 13 can be specifically used to calculate the average utilization rate of the board acceleration module during the entire user program execution process by using the operation time of each task operation saved by the sub-thread and the calculated average utilization rate; and to calculate the average transmission bandwidth during the entire user program execution process by using the amount of data transmitted in each data transmission operation and the time consumption data calculated by the sub-thread.

[0114] Furthermore, in specific implementations, the program performance analysis apparatus provided in the embodiments of the present invention may further include:

[0115] The potential optimization time interval statistics module is used to record the idle time between two adjacent task operations using a sub-thread, and to count a set number of idle time information as potential optimization time intervals according to the size of the recorded idle time; the idle time information includes idle duration, idle start time, operation name and operation sequence number.

[0116] Figure 5 This is a schematic diagram of the program performance analysis device provided in an embodiment of the present invention. This embodiment is based on a hardware perspective, such as... Figure 5 As shown, the program performance analysis equipment includes:

[0117] Memory 20 is used to store computer programs;

[0118] The processor 21 is used to implement the steps of the program performance analysis method mentioned in the above embodiments when executing a computer program.

[0119] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0120] The memory 20 may include one or more non-volatile storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, can implement the relevant steps of the program performance analysis method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the aforementioned program performance analysis method.

[0121] In some embodiments, the program performance analysis device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26. Those skilled in the art will understand that... Figure 5 The structure shown does not constitute a limitation on the program performance analysis device and may include more or fewer components than illustrated. The program performance analysis device provided in this embodiment includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a program performance analysis method, with the same effect as above.

[0122] Finally, the present invention also provides an embodiment corresponding to a non-volatile storage medium. A computer program is stored on the non-volatile storage medium, and when executed by a processor, the computer program implements the steps described in the above method embodiments.

[0123] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks. The non-volatile storage medium provided by the present invention can implement the aforementioned program performance analysis method, with the same effect.

[0124] Finally, the present invention also provides an embodiment corresponding to a computer program product. The computer program product includes a computer program / instructions, which, when executed by a processor, implement the steps described in the above-described program performance analysis method embodiment. The computer program product provided by the present invention can implement the aforementioned program performance analysis method, achieving the same effects.

[0125] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0126] The above provides a detailed description of the program performance analysis method, apparatus, medium, and product provided by this invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A program performance analysis method, characterized in that, The method includes: Start the user program, create a sub-thread using the user program, and retrieve an idle target structure from the structure array; The system collects and updates asynchronous and synchronous task performance data within a defined code range, and then updates this data into a target structure. The asynchronous task performance data includes asynchronous execution time. The process of collecting the asynchronous execution time includes: constructing an asynchronous operation statistics interface using a structure containing a first constructor and a first destructor; creating and recording events in the first constructor and first destructor using the asynchronous operation statistics interface, so as to calculate the asynchronous execution time through an interface provided by a software development kit. The synchronous task performance data includes synchronous execution time. The process of collecting the synchronous execution time includes: constructing a synchronous operation statistics interface using a structure containing a second constructor and a second destructor; using the synchronous operation statistics interface to call the second constructor to record the start time of the statistics, and calling the second destructor to record the end time of the statistics when leaving the scope of the statistics; and calculating the synchronous execution time based on the start and end times of the statistics. The target structure data to be updated is detected by the sub-thread, and the average utilization rate of the board acceleration module during the time period when the asynchronous operation starts and ends is calculated, as well as the time consumption data from the start time to the end time of the synchronous operation. The average utilization rate of the board acceleration module is obtained by multiplying the operation time of each task operation saved by the sub-thread by the calculated average utilization rate and then dividing by the total operation time. The total amount of data transmitted in each data transmission operation is obtained based on the amount of data transmitted in each operation. The average transmission bandwidth during the entire execution of the user program is obtained by dividing the total amount of data transmitted in the data transmission operation task by the time consumption data calculated by the sub-thread.

2. The program performance analysis method according to claim 1, characterized in that, Also includes: The sub-thread records the idle time between two adjacent task operations, and according to the recorded idle time, a set number of idle time information is counted as potential optimization time intervals; the idle time information includes idle duration, idle start time, operation name and operation sequence number.

3. The program performance analysis method according to claim 1, characterized in that, While updating the target structure with asynchronous and synchronous task performance data, it also includes: When the user program writes updated data, the write operation wakes up the child thread that is in a blocked waiting state; when the user program performs a write operation, the child thread cannot perform a write operation at the same time. When the user program has not written updated data, the sub-thread enters a blocked waiting state.

4. The program performance analysis method according to claim 1, characterized in that, The process of the sub-thread detecting updated target structure data includes: If the sub-thread detects that the update is the start timer operation of an asynchronous operation, it queries the completion flag of the asynchronous operation end event in real time and calculates the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation.

5. The program performance analysis method according to claim 4, characterized in that, If the sub-thread detects that the update is the start timer operation of an asynchronous operation, it queries the completion flag of the asynchronous operation's end event in real time, and calculates the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation, including: If the sub-thread detects that the user program has written an asynchronous operation event and finds that the event has started to execute in the asynchronous task sequence, it periodically and in real time detects and counts the utilization rate of the board acceleration module used by the sub-thread until the user program updates the end event data and finds that the asynchronous operation end event has been completed. Based on the statistical utilization rate of the board acceleration module, calculate the average utilization rate of the board acceleration module within the time period of the start and end of the asynchronous operation.

6. The program performance analysis method according to claim 5, characterized in that, The process of the sub-thread detecting updated target structure data also includes: If the sub-thread detects that the updated data is the end timer data of the synchronization operation, it calculates the time elapsed from the start time to the end time of the synchronization operation.

7. The program performance analysis method according to claim 1, characterized in that, When the user program operates through multiple processes, each process uses one accelerator card; Each process corresponds to one sub-thread; each sub-thread stores the corresponding accelerator card device number to distinguish different board data.

8. The program performance analysis method according to claim 1, characterized in that, Also includes: Create shared memory; Correspondingly, after calculating the average utilization rate of the board acceleration module during the start and end time periods of asynchronous operations, and the time consumption data from the start time to the end time of synchronous operations, the following is also included: The calculated average utilization and time consumption data, as well as the asynchronous task performance data and the synchronous task performance data, are stored in shared memory.

9. A program performance analysis device, characterized in that, The device includes: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the program performance analysis method as described in any one of claims 1 to 8.

10. A non-volatile storage medium, characterized in that, The non-volatile storage medium stores a computer program, which, when executed by a processor, implements the steps of the program performance analysis method as described in any one of claims 1 to 8.

11. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by the processor, they implement the steps of the program performance analysis method as described in any one of claims 1 to 8.

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