Server and computing system
By introducing the extended connection between the head and the device group in the server, the comprehensive management of the device group is achieved, the problem of insufficient computing power of the existing server is solved, the computing power and scalability are improved, and it is suitable for high computing power requirements. Task.
Patent Information
- Application Number
- CN202411283569.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2024-12-20
AI Technical Summary
The existing server architecture is fixed in an all-in-one mode, and it is difficult to meet the high real-time computing needs inadequate computing power, especially in model training and inference environments to increase the computing cycle.
Design a server to achieve in-position detection, clock control and communication management of device groups through the expansion and removability of the head to at least two device groups, and to improve the in-position detection, clock control and communication management of device groups by using multiple connectors, controllers and clock controllers. Computational capability.
It improves the computing power of the server, is suitable for tasks with high real-time and high computing power, enhances the scalability of AI servers, saves computing resources, reduces energy consumption, and reduces costs and increases efficiency.
Smart Images
Figure CN119166558A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a server and a computing system. Background Art
[0002] At present, the server architecture is usually an all-in-one model, that is, the processor and peripheral PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) devices such as GPU form a whole, and the matching relationship is relatively fixed. The computing power of the server in the all-in-one model is fixed. When the server is used in model training and inference environments, the computing cycle may increase due to insufficient computing power, making it difficult to meet the needs of high real-time computing.
[0003] Therefore, how to improve server computing power is a problem that technical personnel in this field need to solve. Summary of the invention
[0004] In view of this, the purpose of this application is to provide a server and a computing system to improve the computing power of the server. The specific scheme is as follows:
[0005] In a first aspect, the present application provides a server, comprising: a head and at least two device groups;
[0006] The head comprises: a plurality of first connectors, and a first controller, a clock controller and a second controller connected to the plurality of first connectors;
[0007] The arbitrary device group includes: a plurality of computing devices and a plurality of second connectors; at least one second connector of the arbitrary device group is connected to at least one first connector in the head;
[0008] The first controller is used to: perform in-situ detection on a target device group among the at least two device groups;
[0009] The clock controller is used to: perform clock control on the target device group;
[0010] The second controller is used for: performing communication control with the target device group.
[0011] Optionally, the first connector connected to any second connector is used to: use multiple signal values as an identity sequence of the device group to which the current second connector belongs; the identity sequences of different device groups are different;
[0012] Correspondingly, the second connector is currently used to: strongly pull up the multiple signal values to obtain the identity identification sequence.
[0013] Optionally, the second connector is currently connected to a second baseboard management controller in the device group to which it belongs;
[0014] Accordingly, the second connector is currently used to: send the identity sequence to the second baseboard management controller;
[0015] Correspondingly, the second baseboard management controller is used to: perform a logical operation on the identity identification sequence to obtain a bus address of the device group to which the current second connector belongs; different device groups have different bus addresses.
[0016] Optionally, the second baseboard management controller is used to: calculate integer multiples of the identity identification sequence according to a preset strategy to obtain a bus address of a device group to which the current second connector belongs.
[0017] Optionally, the head comprises: at least one processor, the at least one processor being connected to at least one first connector;
[0018] Any processor of the at least one processor is configured to determine the number of first connectors connected to the current processor according to a bandwidth supported by a single first connector and a bandwidth supported by the current processor.
[0019] Optionally, any processor among the at least one processor is connected to four first connectors.
[0020] Optionally, the head further comprises: a first substrate management controller; the first substrate management controller is connected to the first controller, the clock controller and the second controller;
[0021] Accordingly, the first baseboard management controller is used to: send an in-situ detection control signal to the first controller; send a clock control signal to the clock controller; send a communication control signal to the second controller;
[0022] Accordingly, the first controller is used to: detect the power-on completion signal and the in-place signal of the target device group according to the in-place detection control signal, collect the device group information of the target device group that is already in place, and send the device group information to the first baseboard management controller;
[0023] Accordingly, the first baseboard management controller is used to: store the device group information;
[0024] Accordingly, the clock controller is used to: control the clock reset signal of each computing device in the target device group according to the clock control signal;
[0025] Correspondingly, the second controller is used to: perform communication control with the target device group according to the communication control signal.
[0026] In a second aspect, the present application provides a computing system, comprising: at least one server as described in any of the foregoing items.
[0027] Optionally, different servers communicate with each other via a switching device.
[0028] Optionally, the servers in the computing system constitute a distributed computing system.
[0029] It can be seen from the above scheme that the present application provides a server, comprising: a head and at least two device groups; the head comprises: multiple first connectors, and a first controller, a clock controller and a second controller connected to the multiple first connectors; any device group comprises: multiple computing devices and multiple second connectors; at least one second connector of any device group is connected to at least one first connector in the head; the first controller is used to: perform in-place detection on a target device group in the at least two device groups; the clock controller is used to: perform clock control on the target device group; the second controller is used to: perform communication control with the target device group.
[0030] It can be seen that the server provided by the present application consists of a head connected to at least two device groups, realizing the expandable and detachable connection between the head and the device group; and, the first controller, the clock controller and the second controller in the head perform on-site detection, clock control and communication control on each device group, realizing all-round management and control of the device group. Combining the architecture of the head and multiple device groups, the computing power of the server is improved, which is suitable for running tasks with high real-time and high computing power.
[0031] Correspondingly, a communication device, equipment and medium provided by the present application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0033] Figure 1 A schematic diagram of a server disclosed in this application;
[0034] Figure 2 A schematic diagram of the connection of upstream and downstream connectors in a server disclosed in the present application;
[0035] Figure 3 A schematic diagram of the connection between a first controller of a server disclosed in the present application and each device group;
[0036] Figure 4 A schematic diagram of the connection between a second controller of a server disclosed in the present application and each device group;
[0037] Figure 5 A schematic diagram of an electronic device disclosed in this application;
[0038] Figure 6 A server structure diagram provided for this application;
[0039] Figure 7 A terminal structure diagram provided for this application. DETAILED DESCRIPTION
[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other examples obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0041] At present, the server architecture is usually an all-in-one mode, that is, the processor and peripheral PCIe devices such as GPU form a whole, and the matching relationship is relatively fixed. The computing power of the server in the all-in-one mode is fixed. When the server is used in model training and reasoning environments, the computing cycle may increase due to insufficient computing power, making it difficult to meet the needs of high real-time computing. To this end, this application provides a server design solution that can improve the computing power of the server.
[0042] See also Figure 1 As shown, an embodiment of the present application discloses a server, including: a head and at least two device groups. The head includes: a plurality of first connectors, and a first controller, a clock controller, and a second controller connected to the plurality of first connectors; any device group includes: a plurality of computing devices and a plurality of second connectors; at least one second connector of any device group is connected to at least one first connector in the head. For example: two second connectors of a device group are connected to two first connectors in the head, then the device group communicates with the head through two connection lines. It can be seen that there is at least one connection line between a device group and the head. In this example, the first connector and the second connector can be CDFP (400 Gbps form-Factor Pluggable) connectors, then the connection line between the two is a CDFP cable, and each CDFP cable can transmit 1 group of x16 PCIe signals and management control signals. The CDFP connector is: a high-speed pluggable connector. CDFP is a protocol specification for hot-swappable modules.
[0043] The first controller is used to perform on-site detection on a target device group in at least two device groups; the clock controller is used to perform clock control on the target device group; and the second controller is used to perform communication control with the target device group.
[0044] In one embodiment, the first connector connected to any second connector is used to: use multiple signal values as the identity sequence of the device group to which the current second connector belongs; the identity sequences of different device groups are different; accordingly, the current second connector is used to: strongly pull up the multiple signal values to obtain the identity sequence. When using multiple signal values as the identity sequence of the device group to which the current second connector belongs, 3 signal values can be set, and the details can be referred to Table 2.
[0045] In one embodiment, the current second connector is connected to the second baseboard management controller in the device group to which it belongs; accordingly, the current second connector is used to: send an identity identification sequence to the second baseboard management controller; accordingly, the second baseboard management controller is used to: perform logical operations on the identity identification sequence to obtain the bus address of the device group to which the current second connector belongs; the bus addresses of different device groups are different.
[0046] In one implementation, the second baseboard management controller is used to: calculate integer multiples of the identity identification sequence according to a preset strategy to obtain a bus address of the device group to which the current second connector belongs.
[0047] In one embodiment, the head includes: at least one processor, at least one processor is connected to at least one first connector; any processor among the at least one processor is used to: determine the number of first connectors connected to the current processor based on the bandwidth size supported by a single first connector and the bandwidth size supported by the current processor.
[0048] In one implementation, any processor of the at least one processor is connected to four first connectors.
[0049] In one embodiment, the head also includes: a first baseboard management controller; the first baseboard management controller is connected to the first controller, the clock controller and the second controller; accordingly, the first baseboard management controller is used to: send an in-situ detection control signal to the first controller; send a clock control signal to the clock controller; send a communication control signal to the second controller; accordingly, the first controller is used to: detect the power-on completion signal and the in-situ signal of the target device group according to the in-situ detection control signal, and collect the device group information of the target device group that is already in place, and send the device group information to the first baseboard management controller; accordingly, the first baseboard management controller is used to: store the device group information; accordingly, the clock controller is used to: control the clock reset signal of each computing device in the target device group according to the clock control signal; accordingly, the second controller is used to: communicate and control with the target device group according to the communication control signal.
[0050] It can be seen that the server provided in this embodiment is composed of a head connected to at least two device groups, realizing the expandability and detachable connection between the head and the device group; and, the first controller, the clock controller and the second controller in the head perform on-site detection, clock control and communication control on each device group, realizing all-round management and control of the device group. Combining the architecture of the head and multiple device groups, the computing power of the server is improved, which is suitable for running tasks with high real-time requirements and high computing power.
[0051] See also Figure 2 , one head has 8 CDFP connectors, and every two CDFP connectors are connected to two CDFP connectors on a BOX (i.e., device group). Of course, the BOX end (i.e., device group end) can be expanded through PCIe Switch, and the BOX's upstream port may not correspond to the head one-to-one. The number of BOX's upstream ports (corresponding to the number of CDFP connectors) can be 8, 4, 2, or 1.
[0052] This example takes 8 cables coming out of the head end as an example. The 8 CDFP connectors on the head end correspond to CDFP0-CDFP7. The CDFP connectors on the BOX end are numbered starting from 0. When paired with 1 BOX, each BOX can be connected through 8 or fewer cables; when paired with 2 BOXes, each BOX can be connected through 4 or fewer cables; when paired with 4 BOXes, each BOX can be connected through 2 or fewer cables; when paired with 8 BOXes, each BOX is connected through 1 cable. For specific connections, refer to Table 1.
[0053] Table 1
[0054]
[0055] In Table 1, "BOX1 CDFP0" means: CDFP0 of BOX1 is connected to CDFP0 of the machine head; referring to the second row in the table, it can be seen that CDFP0~CDFP7 of BOX1 correspond to CDFP0~CDFP7 connected to the machine head respectively, that is, when there is a single BOX, 8 cables are connected between BOX1 and the machine head. Correspondingly, referring to the third row in the table, it can be seen that CDFP0~CDFP3 of BOX1 correspond to CDFP0, CDFP2, CDFP4 and CDFP6 connected to the machine head respectively; CDFP0~CDFP3 of BOX2 correspond to CDFP1, CDFP3, CDFP5 and CDFP7 connected to the machine head respectively, that is, when there are two BOXs, 4 cables are connected between BOX1 and the machine head; 4 cables are connected between BOX2 and the machine head. The rest is analogous and will not be repeated here. Among them, for each BOX, any line between it and the machine head can be set for configuring and managing the BOX.
[0056] As mentioned above, a single BOX can have 8, 4, 2, or 1 uplink ports; a dual BOX can have 4, 2, or 1 uplink ports; a 4BOX can have 2 or 1 uplink ports; and an 8BOX can have 1 uplink port.
[0057] In this example, three BOX ID pins are set in each CDFP cable at the head end, corresponding to three BOX ID signals. For details, see Table 2.
[0058] Table 2
[0059]
[0060] The BOX ID signal (i.e., the BOX identification sequence) shown in Table 2 is obtained by referring to the following: In the head, the BOX ID signal is directly pulled up and down. The signal with ID 0 is strongly pulled down at the head end, and the BOX cannot be strongly pulled up; the signal with ID 1 is weakly pulled down at the head end, and the BOX can be strongly pulled up. In the BOX, all three ID signals are strongly pulled up, so that the level of the ID signal can be accurately transmitted to the BOX, and leakage from the head to the BOX can be avoided.
[0061] Inside the BOX, the BOX ID signal is connected to the GPIO pin in each BOX's BMC (i.e., the second baseboard management controller) for the BOX to identify its own serial number: BOX ID. The BMC of the BOX can calculate the ID based on the obtained BOX ID information, such as multiplying the ID by 2, and obtain a calculation result as the respective I2C address (a 7-bit binary number) to ensure that the BMC I2C bus address of each BOX is different to prevent malfunctions due to address conflicts.
[0062] In addition, the Power Enable signal of the BOX, that is, the power-on signal, is given from the head end to the 8 CDFP connectors respectively, so that when the CDFP connector is connected to the BOX, a power-on signal can be given to the BOX.
[0063] See also Figure 3 , the Power Good signal and Present signal of the BOX, that is, the power-on completion signal and the in-position signal, are respectively sent by each BOX to the head through the CDFP cable, and the signal is transmitted to the head BMC through the IO Expander (i.e., the first controller). The head BMC (i.e., the first baseboard management controller) can confirm the mode of several BOXes in the current server through the number of BOXes in position and the number of BOXes that have been powered on, and transmit the information to the BOX's BMC. Specifically, it can be synchronized to the BMC of all BOXes for storage and information display. Among them, the BOX and the head detect each other's Present signal. The Power Good signal of the BOX is transmitted to the head after the BOX is powered on. After the BOX is powered on, the head sends a PCIe Reset signal to the BOX.
[0064] See also Figure 4 In order to realize the IPMB (Intelligent Platform Management BUS) communication function between the head and BOX BMC, the head BMC gives an I2C signal, which is divided into 8 I2C signals through the I2C Switch (second controller) inside the head and given to the BMC of the BOX to realize this function. Among them, I2CSwitch is used to realize data interaction between the head and the BOX, such as: transmitting task data to the BOX.
[0065] Correspondingly, the machine head BMC can also be connected to CPLD (Complex Programmable Logic Device), and the CPLD (i.e., clock controller) is connected to the 8 CDFP connectors of the machine head, thereby realizing: the control of the PCIe Reset signal and the 100M clock signal in the BOX. The PCIe Reset signal is given by the machine head to control the reset signal of PCIe devices such as GPU, network card, memory, and hard disk in the BOX. The 100M clock signal is usually required by PCIe devices such as GPU, and is given by the machine head ClockBuffer (clock buffer) to meet the BOX's clock signal requirements. Both signals need to be divided into 8 channels in the machine head and given to the corresponding 8 CDFP connectors.
[0066] It should be noted that a BOX can include: at least one computing device (such as GPU), network card, memory, hard disk and other PCIe devices. Therefore, a single BOX, that is, a single device group, can be used as an acceleration device, and multiple BOXes can be interconnected to form an acceleration pool; the acceleration pool can be connected to one or more heads.
[0067] It can be seen that in this embodiment, cables are arranged between the machine head and the BOX for interconnection, and the machine head can output up to 8 high-speed cables to interconnect multiple BOXes; inside the machine head, each high-speed cable is set with a three-digit BOX ID signal, and 8 cables correspond to 8 three-digit binary IDs, from 000 to 111; the BOX ID is directly pulled down in the machine head and pulled up in the BOX. After the BOX and the machine head confirm the wiring position, the unique BOX ID is confirmed. The IPMB communication between the machine head and each BOX is realized through the I2C signal of the machine head and the BOX's BMC. The BOX's BMC automatically calculates and generates different bus addresses through different BOX ID information; the BOX's Power Good signal and Present signal are given to the machine head through each cable and transmitted to the machine head BMC through the IO Expander. The BOX's Power Enable signal, PCIe Reset signal and 100M clock signal are obtained from the machine head through the cable, and the machine head can realize the corresponding functions of the BOX through the above three signals. This embodiment implements a one-master-multiple-slave server hardware architecture, where a single head can be used with multiple BOXs, and a single head is used to manage and control 1-8 BOX machines, meeting the AI server's needs for a flexible and large GPU computing cluster, and enhancing the scalability of the AI server. The server architecture based on this hardware design saves unnecessary complex computing resources, improves computing power density, reduces energy consumption, reduces costs and increases efficiency, and is low-carbon and environmentally friendly. Moreover, the multi-modular system composition facilitates later maintenance and replacement, reducing operation and maintenance costs.
[0068] A computing system provided in an embodiment of the present application is introduced below. The computing system described below can be referenced to other embodiments described in this document.
[0069] An embodiment of the present application discloses a computing system, including: at least one server of any of the foregoing items.
[0070] In one implementation, different servers communicate with each other via a switching device.
[0071] In one embodiment, the servers in the computing system form a distributed computing system.
[0072] The server in this embodiment includes: a head and at least two device groups; the head includes: multiple first connectors, and a first controller, a clock controller and a second controller connected to the multiple first connectors; any device group includes: multiple computing devices and multiple second connectors; at least one second connector of any device group is connected to at least one first connector in the head.
[0073] The first controller is used to perform on-site detection on a target device group in at least two device groups; the clock controller is used to perform clock control on the target device group; and the second controller is used to perform communication control with the target device group.
[0074] In one embodiment, the first connector connected to any second connector is used to: use multiple signal values as the identity sequence of the device group to which the current second connector belongs; the identity sequences of different device groups are different; accordingly, the current second connector is used to: strongly pull up the multiple signal values to obtain the identity sequence. When using multiple signal values as the identity sequence of the device group to which the current second connector belongs, 3 signal values can be set, and the details can be referred to Table 2.
[0075] In one embodiment, the current second connector is connected to the second baseboard management controller in the device group to which it belongs; accordingly, the current second connector is used to: send an identity identification sequence to the second baseboard management controller; accordingly, the second baseboard management controller is used to: perform logical operations on the identity identification sequence to obtain the bus address of the device group to which the current second connector belongs; the bus addresses of different device groups are different.
[0076] In one implementation, the second baseboard management controller is used to: calculate integer multiples of the identity identification sequence according to a preset strategy to obtain a bus address of the device group to which the current second connector belongs.
[0077] In one embodiment, the head includes: at least one processor, at least one processor is connected to at least one first connector; any processor among the at least one processor is used to: determine the number of first connectors connected to the current processor based on the bandwidth size supported by a single first connector and the bandwidth size supported by the current processor.
[0078] In one implementation, any processor of the at least one processor is connected to four first connectors.
[0079] In one embodiment, the head also includes: a first baseboard management controller; the first baseboard management controller is connected to the first controller, the clock controller and the second controller; accordingly, the first baseboard management controller is used to: send an in-situ detection control signal to the first controller; send a clock control signal to the clock controller; send a communication control signal to the second controller; accordingly, the first controller is used to: detect the power-on completion signal and the in-situ signal of the target device group according to the in-situ detection control signal, and collect the device group information of the target device group that is already in place, and send the device group information to the first baseboard management controller; accordingly, the first baseboard management controller is used to: store the device group information; accordingly, the clock controller is used to: control the clock reset signal of each computing device in the target device group according to the clock control signal; accordingly, the second controller is used to: communicate and control with the target device group according to the communication control signal.
[0080] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.
[0081] It can be seen that this embodiment provides a computing system that can support operations in larger-scale model training and reasoning scenarios.
[0082] An electronic device provided in an embodiment of the present application is introduced below, and the electronic device described below can be cross-referenced with other embodiments described herein. The electronic device can be any functional module in the aforementioned embodiments, such as: a first connector, a second connector, a first controller or a processor in a head, etc.
[0083] The present application discloses an electronic device, including:
[0084] Memory 501, used for storing computer programs;
[0085] The processor 502 is used to execute the computer program to implement the method disclosed in any of the above embodiments.
[0086] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing on-site detection on a target device group in at least two device groups.
[0087] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing clock control on the target device group.
[0088] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing communication control with the target device group.
[0089] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: using multiple signal values as an identity sequence of the device group to which the current second connector belongs; different device groups have different identity sequences.
[0090] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: multiple signal values are strongly pulled up to obtain an identity sequence. When multiple signal values are used as the identity sequence of the device group to which the current second connector belongs, three signal values may be set, as shown in Table 2.
[0091] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: sending an identity identification sequence to the second baseboard management controller.
[0092] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing a logical operation on the identity identification sequence to obtain the bus address of the device group to which the current second connector belongs; different device groups have different bus addresses.
[0093] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: calculating integer multiples of the identity identification sequence according to a preset strategy to obtain the bus address of the device group to which the current second connector belongs.
[0094] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: determining the number of first connectors connected to the current processor according to the bandwidth supported by a single first connector and the bandwidth supported by the current processor.
[0095] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: sending a presence detection control signal to the first controller; sending a clock control signal to the clock controller; and sending a communication control signal to the second controller.
[0096] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: detecting the power-on completion signal and the in-place signal of the target device group according to the in-place detection control signal, collecting the device group information of the target device group that is already in place, and sending the device group information to the first baseboard management controller.
[0097] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: storing device group information.
[0098] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: controlling the clock reset signal of each computing device in the target device group according to the clock control signal.
[0099] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing communication control with the target device group according to the communication control signal.
[0100] Furthermore, the present application also provides an electronic device. The electronic device can be Figure 6 The server shown can also be Figure 7 Terminal shown. Figure 6 and Figure 7 All of them are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams cannot be regarded as any limitation on the scope of use of the present application.
[0101] Figure 6 A schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the communication disclosed in any of the aforementioned embodiments.
[0102] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.
[0103] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.
[0104] The operating system is used to manage and control the hardware devices and computer programs on the server to realize the operation and processing of the data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs that can be used to complete the communication method disclosed in any of the aforementioned embodiments, computer programs can also further include computer programs that can be used to complete other specific tasks. In addition to data such as application update information, data can also include data such as application developer information.
[0105] Figure 7 A schematic diagram of the structure of a terminal provided in an embodiment of the present application, the terminal may specifically include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer, etc.
[0106] Generally, the terminal in this embodiment includes: a processor and a memory.
[0107] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.
[0108] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the communication method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application.
[0109] In some embodiments, the terminal may also include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.
[0110] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the terminal, and may include more or fewer components than those shown in the figure.
[0111] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be cross-referenced with other embodiments described herein.
[0112] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the communication method disclosed in the above-mentioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage method may be temporary storage or permanent storage.
[0113] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: performing clock control on the target device group.
[0114] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: performing communication control with the target device group.
[0115] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: using multiple signal values as an identity sequence of the device group to which the current second connector belongs; different device groups have different identity sequences.
[0116] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: multiple signal values are strongly pulled up to obtain an identity sequence. When multiple signal values are used as the identity sequence of the device group to which the current second connector belongs, three signal values may be set, and specific reference may be made to Table 2.
[0117] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: sending an identity identification sequence to the second baseboard management controller.
[0118] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: performing a logical operation on the identity identification sequence to obtain the bus address of the device group to which the current second connector belongs; different device groups have different bus addresses.
[0119] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: calculating integer multiples of the identity identification sequence according to a preset strategy to obtain the bus address of the device group to which the current second connector belongs.
[0120] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: determining the number of first connectors connected to the current processor according to the bandwidth supported by a single first connector and the bandwidth supported by the current processor.
[0121] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: sending a presence detection control signal to the first controller; sending a clock control signal to the clock controller; and sending a communication control signal to the second controller.
[0122] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps can be specifically implemented: detecting the power-on completion signal and the in-place signal of the target device group according to the in-place detection control signal, collecting the device group information of the target device group that is already in place, and sending the device group information to the first baseboard management controller.
[0123] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: storing device group information.
[0124] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: controlling the clock reset signal of each computing device in the target device group according to the clock control signal.
[0125] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: performing communication control with the target device group according to the communication control signal.
[0126] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be cross-referenced with other embodiments described in this document.
[0127] A computer program product comprises a computer program / instruction, which implements the steps of the aforementioned disclosed communication method when executed by a processor.
[0128] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.
[0129] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.
[0130] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A server, characterized in that: include: The machine head and at least two equipment groups; The head comprises: a plurality of first connectors, and a first controller, a clock controller and a second controller connected to the plurality of first connectors; The arbitrary device group includes: a plurality of computing devices and a plurality of second connectors; at least one second connector of the arbitrary device group is connected to at least one first connector in the head; The first controller is used to: perform in-situ detection on a target device group among the at least two device groups; The clock controller is used to: perform clock control on the target device group; The second controller is used for: performing communication control with the target device group.
2. The server according to claim 1, characterized in that: The first connector connected to any second connector is used to: use multiple signal values as an identity sequence of the device group to which the current second connector belongs; the identity sequences of different device groups are different; Correspondingly, the second connector is currently used to: strongly pull up the multiple signal values to obtain the identity identification sequence.
3. The server according to claim 2, characterized in that: The second connector is currently connected to the second baseboard management controller in the device group to which it belongs; Accordingly, the second connector is currently used to: send the identity sequence to the second baseboard management controller; Accordingly, the second baseboard management controller is used to: perform a logical operation on the identity identification sequence to obtain a bus address of the device group to which the current second connector belongs; Different device groups have different bus addresses.
4. The server according to claim 3, characterized in that: The second baseboard management controller is used to calculate the integer multiples of the identity identification sequence according to a preset strategy to obtain the bus address of the device group to which the current second connector belongs.
5. The server according to claim 1, characterized in that: The head includes: at least one processor, the at least one processor connected to at least one first connector; Any processor of the at least one processor is configured to determine the number of first connectors connected to the current processor according to a bandwidth supported by a single first connector and a bandwidth supported by the current processor.
6. The server according to claim 5, characterized in that: Any processor of the at least one processor is connected to four first connectors.
7. The server according to any one of claims 1 to 6, characterized in that: The head also includes: a first substrate management controller; the first substrate management controller is connected to the first controller, the clock controller and the second controller; Accordingly, the first baseboard management controller is used to: send an in-situ detection control signal to the first controller; send a clock control signal to the clock controller; send a communication control signal to the second controller; Accordingly, the first controller is used to: detect the power-on completion signal and the in-place signal of the target device group according to the in-place detection control signal, collect the device group information of the target device group that is already in place, and send the device group information to the first baseboard management controller; Accordingly, the first baseboard management controller is used to: store the device group information; Accordingly, the clock controller is used to: control the clock reset signal of each computing device in the target device group according to the clock control signal; Correspondingly, the second controller is used to: perform communication control with the target device group according to the communication control signal.
8. A computing system, characterized in that: include: At least one server as claimed in any one of claims 1 to 7.
9. The computing system according to claim 8, characterized in that: Different servers communicate with each other through switching devices.
10. The computing system according to claim 9, characterized in that The servers in the computing system constitute a distributed computing system.