Bus bandwidth allocation method and device, server, electronic equipment and storage medium

Abstract

The invention provides a bus bandwidth allocation method and device, a server, electronic equipment and a storage medium, and relates to the technical field of computers.The method comprises the steps that detection voltage is provided for bus equipment inserted into a bus equipment slot, and the switching frequency of the detection voltage is controlled; acquiring a switching frequency detection value of each data channel in the bus equipment slot; determining a bus bandwidth allocation value corresponding to the bus equipment based on the switching frequency detection value of each data channel; and allocating a bus bandwidth to the bus device based on the bus bandwidth allocation value. According to the method and the device provided by the invention, the bandwidth of the bus equipment can be accurately determined and automatic allocation is realized, so that the waste of bus resources is avoided.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a bus bandwidth allocation method, device, server, electronic device and storage medium. Background Art

[0002] The PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) interface on the server motherboard generally uses PCIe X8 slots and PCIe X16 slots to facilitate the later insertion of different types of expansion cards. Even if the gold finger on the expansion card is X2 or X4, it can still be inserted into the PCIe X8 slot or PCIe X16 slot.

[0003] At present, the bandwidth directly provided by the processor to the PCIe X8 slot and PCIe X16 slot is the maximum bandwidth. When an expansion card with a small number of data channels (Lane) is inserted, it cannot be effectively identified and the processor also allocates the maximum bandwidth, resulting in a waste of PCIe bus resources.

[0004] Therefore, how to achieve automatic bandwidth allocation for PCIe bus devices has become a technical problem that needs to be solved urgently in the industry. Summary of the invention

[0005] The present application provides a bus bandwidth allocation method, device, server, electronic device and storage medium, which are used to solve the technical problem of how to realize automatic bandwidth allocation of PCIe bus devices.

[0006] The present application provides a bus bandwidth allocation method, comprising: Providing a detection voltage to a bus device inserted into the bus device slot, and controlling a switching frequency of the detection voltage; Obtaining a switching frequency detection value of each data channel in the bus device slot; Determining a bus bandwidth allocation value corresponding to the bus device based on a switching frequency detection value of each data channel; A bus bandwidth is allocated to the bus device based on the bus bandwidth allocation value.

[0007] In some embodiments, providing a detection voltage to a bus device inserted into a bus device slot and controlling a switching frequency of the detection voltage includes: Sending a first voltage control instruction to a power supply device; the first voltage control instruction is used to control the power supply device to provide a detection voltage to the bus device; A switching frequency control instruction is sent to a power control device; the switching frequency control instruction is used to control the power control device to control the switching frequency of the detection voltage by setting the switching frequency.

[0008] In some embodiments, determining the bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel includes: Determining a switching frequency detection value of each data channel in the bus device slot and a channel position of each data channel; Determine the data channels whose channel positions are adjacent and whose switching frequency detection values ​​are consistent with the set switching frequency as the target data channels; Based on the number of the target data channels, a bus bandwidth allocation value corresponding to the bus device is determined.

[0009] In some embodiments, before providing a detection voltage to a bus device inserted into a bus device slot and controlling a switching frequency of the detection voltage, the method further includes: The detection voltage is determined based on the operating voltage of each bus device; the detection voltage is less than the operating voltage of each bus device.

[0010] In some embodiments, sending a switching frequency control instruction to a power control device includes: Determine the set switching frequency corresponding to each bus device; the set switching frequency corresponding to each bus device is different; Based on the set switching frequencies corresponding to the various bus devices, generating switching frequency control instructions corresponding to the various bus devices; Sending a switching frequency control instruction corresponding to each bus device to a power control device corresponding to each bus device, so that the power control device controls the switching frequency of the detection voltage of each bus device; Alternatively, generating a switching frequency control instruction corresponding to the current bus device; Sending a switching frequency control instruction corresponding to the current bus device to a power control device corresponding to the current bus device, so that the power control device controls the switching frequency of the detection voltage of the current bus device; When the bus bandwidth allocation value corresponding to the current bus device is determined, the current bus device is switched to a next bus device.

[0011] In some embodiments, allocating bus bandwidth to the bus device based on the bus bandwidth allocation value includes: Sending a second voltage control instruction to the power supply device; the second voltage control instruction is used to control the power supply device to provide an operating voltage to the bus device; When the bus device operates normally, a bus bandwidth is allocated to the bus device based on the bus bandwidth allocation value.

[0012] The present application provides a bus bandwidth allocation device, comprising: A voltage generating module, used for providing a detection voltage to a bus device inserted into the bus device slot, and controlling a switching frequency of the detection voltage; A frequency detection module, used to obtain a switching frequency detection value of each data channel in the bus device slot; A bandwidth determination module, used to determine a bus bandwidth allocation value corresponding to the bus device based on a switching frequency detection value of each data channel; The bandwidth allocation module is used to allocate bus bandwidth to the bus device based on the bus bandwidth allocation value.

[0013] The present application provides a server, including a processor, a power supply device, a power supply control device, and a bus device slot; The bus device slot is used to insert a bus device; The power supply device is used to provide a detection voltage for the bus device; The power supply control device is used to control the switching frequency of the detection voltage; The processor is connected to the power supply device, the power control device and the bus device slot, and is used to execute the bus bandwidth allocation method to allocate bus bandwidth to the bus device.

[0014] The present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the bus bandwidth allocation method is implemented when the processor executes the computer program.

[0015] The present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, and the computer program implements the bus bandwidth allocation method when executed by a processor.

[0016] The bus bandwidth allocation method, device, server, electronic device and storage medium provided in the present application provide a detection voltage to a bus device inserted into a bus device slot, and control the switching frequency of the detection voltage; obtain the switching frequency detection value of each data channel in the bus device slot; determine the bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel; allocate the bus bandwidth to the bus device based on the bus bandwidth allocation value; since detection voltages with different switching frequencies are provided to the bus device, the switching frequency of each data channel in the bus device slot is detected, and the number of data channels actually used by the bus device is determined by comparing the switching frequency detection values ​​of each data channel, and then the bus bandwidth allocation value is determined, so that the bandwidth of the PCIe bus device can be accurately determined and automatically allocated, avoiding the processor directly allocating the maximum bandwidth according to the bus device slot and avoiding the waste of PCIe bus resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 This is one of the flow charts of the bus bandwidth allocation method provided in this application.

[0020] Figure 2 It is a structural schematic diagram of the bus bandwidth allocation device provided in this application.

[0021] Figure 3 It is a schematic diagram of the structure of the server provided by this application.

[0022] Figure 4 This is the second flow chart of the bus bandwidth allocation method provided by this application.

[0023] Figure 5 This is a circuit connection diagram for bus bandwidth allocation provided by this application.

[0024] Figure 6 It is a circuit structure diagram of the power supply device provided in this application.

[0025] Figure 7 It is a schematic diagram of the structure of the electronic device provided by this application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second" etc. in the present application are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable in appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0028] PCIe is a high-speed serial computer expansion card standard used in servers, mainly for connecting the central processing unit (CPU) and various expansion cards, such as graphics cards, sound cards, and network adapters. Bandwidth refers to the amount of data that can be transmitted in a certain period of time, and is usually used to describe the performance of a network or data transmission path. Bus bandwidth refers to the amount of data that can be transmitted by the bus that connects the various components in a computer system. For example, the bandwidth of the PCIe bus determines the data transfer rate it can support and the communication efficiency between devices. The bandwidth of the PCIe bus is closely related to the version of the PCIe bus and the number of data channels (Lane).

[0029] In the related art, the bandwidth directly provided by the central processing unit to the PCIe X8 slot and the PCIe X16 slot is the maximum bandwidth. When an expansion card with a small number of data channels (Lane) is inserted, it cannot be effectively identified and the processor also allocates the maximum bandwidth, resulting in a waste of PCIe bus resources.

[0030] In view of the shortcomings of relevant technologies, Figure 1 This is one of the flow charts of the bus bandwidth allocation method provided by this application, such as Figure 1 As shown, the method includes step 110 , step 120 , step 130 and step 140 .

[0031] Step 110: Provide a detection voltage to the bus device inserted into the bus device slot, and control the switching frequency of the detection voltage.

[0032] Specifically, the execution subject of the bus bandwidth allocation method provided in the embodiment of the present application is a bus bandwidth allocation device. The device can be implemented by software, such as a bus bandwidth allocation program running in a processor of a server; or it can be a device for executing the bus bandwidth allocation method, such as a central processing unit, and a tablet computer, desktop computer or server containing the central processing unit.

[0033] The following embodiments take a server as an example to illustrate the bus bandwidth allocation method. The server uses a PCIe bus to connect the central processing unit and various bus devices. Bus devices refer to devices that support connection with the central processing unit through a bus, such as a network adapter, a storage controller, a graphics processor, a disk array control card, etc.

[0034] The server's motherboard is equipped with a bus device slot. The bus device is equipped with a specific number and arrangement of gold fingers (metal contact parts), and the bus device slot is equipped with a corresponding metal contact area. When the bus device is inserted into the slot, the gold fingers are in contact with the metal contact area, which enables the bus device to reliably communicate and transmit data with the motherboard.

[0035] The detection voltage is used to detect the bandwidth of the bus device. For example, when the bus device is under normal working voltage (such as 3.3 volts, 5 volts or 12 volts), the data channel (PCIe Lane) port on the device side is low level (0 volts) after power-on, and the host (Host) side initiates the electrical signal for communication. However, when the bus device is under abnormal working voltage (such as 1 volt), the circuit on the device side cannot work normally due to the low voltage. The data channel port on the device side will output a certain level to the outside through the connection circuit inside the device. In this state, the part between each data channel port of the device and the power supply (VCC) port of the device can be approximately regarded as a resistor with a large resistance value. Here, the abnormal working voltage can be used as the detection voltage.

[0036] Switching frequency refers to the frequency at which the power supply is turned on or off, usually expressed in Hertz (Hz).

[0037] When a bus device is inserted into a bus device slot of a running server (host), or when a server with a bus device already inserted is powered on, a processor in the server can send instructions to a power supply device to control the power supply device to provide a detection voltage to the bus device, and control the power supply control device to control the switching frequency of the detection voltage.

[0038] Step 120: Obtain the switching frequency detection value of each data channel in the bus device slot.

[0039] Specifically, a data channel (Lane) refers to a pair of differential lines of the physical layer transmission line of a device, which is used for bidirectional communication.

[0040] When providing the detection voltage to the bus device, since the bus device cannot work normally under the abnormal working voltage at this time, it only acts as a resistor, and the detection voltage will be output to the bus device slot through the bus device. The voltage of each data channel in the bus device slot and the switching frequency corresponding to the voltage can be detected to obtain the switching frequency detection value of each data channel.

[0041] Step 130: Determine a bus bandwidth allocation value corresponding to the bus device based on the switch frequency detection value of each data channel.

[0042] Specifically, according to the switching frequency detection value of each data channel, it can be determined which data channels are connected to the bus device and the number of data channels connected to the bus device.

[0043] According to the number of data channels connected to the bus device, the number of data channels actually used by the bus device can be determined, and then the bus bandwidth allocation value can be determined. The bus bandwidth allocation value is the bus bandwidth allocated by the processor to the bus device.

[0044] For example, when the bus is PCIe, the bus device slot is mainly divided into four slot specifications: X1, X4, X8, and X16. Different slot specifications indicate the physical size and bandwidth capabilities of the slot. X1 means that the physical size of the slot is a channel of 1 data channel, providing a bandwidth of 1 PCIe data channel (usually 500 megabytes per second, full-duplex). X4 means that the physical size of the slot is a channel of 4 data channels, providing a bandwidth of 4 PCIe data channels (usually 2 gigabits per second, full-duplex), and so on. A bus device slot is a PCIe X16 slot, which means that the bus device slot has 16 data channels (Lane). When a bus device is inserted into the slot, a detection voltage of 1 volt (V) is provided to the bus device, and its switching frequency is controlled to be 1 kilohertz (kHz). It can be detected that the switching frequency detection values ​​of 8 data channels are 1 kHz, and these 8 data channels are adjacent. It can be determined that the bus device uses 8 data channels, and the slot specification is X8, which needs to provide a bus bandwidth 8 times that of X1, that is, 4 gigabytes per second.

[0045] Step 140: Allocate bus bandwidth to the bus device based on the bus bandwidth allocation value.

[0046] Specifically, after determining the bus bandwidth allocation value, the processor in the server may allocate the bus bandwidth to the bus device.

[0047] It should be noted that, in the embodiment of the present application, the server motherboard may be configured with multiple bus device slots, the slot specifications of each bus device slot may be different, and the bus devices inserted into each bus device slot may also be different.

[0048] The bus bandwidth allocation method provided in the embodiment of the present application is also applicable to inserting different bus devices into the bus device slots, and allocating bus bandwidth to these bus devices respectively. Specifically, the switching frequency of the detection voltage can be controlled so that the switching frequency of the detection voltage of each bus device is different, and different bus devices can be distinguished by the switching frequency.

[0049] The bus bandwidth allocation method provided in the embodiment of the present application provides a detection voltage to a bus device inserted into a bus device slot, and controls the switching frequency of the detection voltage; obtains the switching frequency detection value of each data channel in the bus device slot; determines the bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel; allocates the bus bandwidth to the bus device based on the bus bandwidth allocation value; since detection voltages with different switching frequencies are provided to the bus device, the switching frequency of each data channel in the bus device slot is detected, and the number of data channels actually used by the bus device is determined by comparing the switching frequency detection values ​​of each data channel, and then the bus bandwidth allocation value is determined, so that the bandwidth of the PCIe bus device can be accurately determined and automatically allocated, avoiding the processor directly allocating the maximum bandwidth according to the bus device slot and avoiding the waste of PCIe bus resources.

[0050] It should be noted that each implementation method of the present application can be freely combined, the order can be changed, or it can be executed separately, and does not need to rely on or depend on a fixed execution order.

[0051] In some embodiments, providing a detection voltage to a bus device inserted into a bus device slot and controlling a switching frequency of the detection voltage includes: Sending a first voltage control instruction to the power supply device; the first voltage control instruction is used to control the power supply device to provide a detection voltage to the bus device; A switching frequency control instruction is sent to the power control device; the switching frequency control instruction is used to control the power control device to set the switching frequency of the switching frequency control detection voltage.

[0052] Specifically, the mainboard of the server generally includes a power supply device and a power supply control device, which are respectively connected to the processor in the mainboard.

[0053] The processor may send a first voltage control instruction to the power supply device. The first voltage control instruction is used to control the power supply device to provide a detection voltage to the bus device. The detection voltage may be lower than a normal operating voltage of the bus device, so that the bus device may be approximately regarded as a resistor with a larger resistance value.

[0054] The processor also sends a switching frequency control instruction to the power control device. The switching frequency control instruction is used to control the power control device to set the switching frequency of the detection voltage. The set switching frequency can be set as needed, for example, different bus devices are set with different set switching frequencies, so that the processor can simultaneously identify the bandwidth required by different bus devices in the bus device slot.

[0055] The bus bandwidth allocation method provided in the embodiment of the present application provides a detection voltage to the bus device by sending a first voltage control instruction to the power supply device; and controls the switching frequency of the detection voltage by sending a switching frequency control instruction to the power supply control device.

[0056] In some embodiments, determining a bus bandwidth allocation value corresponding to a bus device based on a switching frequency detection value of each data channel includes: Determine a switching frequency detection value of each data channel in a bus device slot and a channel position of each data channel; The data channels whose channel positions are adjacent and whose switching frequency detection values ​​are consistent with the set switching frequency are determined as target data channels; Based on the number of target data channels, a bus bandwidth allocation value corresponding to the bus device is determined.

[0057] Specifically, the switching frequency of the voltage of each data channel in the bus device slot can be detected to obtain a switching frequency detection value. The processor can set a channel frequency status register to store the switching frequency detection value of each data channel. The channel position refers to the physical position of the data channel on the slot.

[0058] The processor can obtain the switching frequency detection value of each data channel from the channel frequency status register, and compare the switching frequency detection values ​​of each data channel. If there are multiple data channels, these data channels meet the channel position adjacent, and the switching frequency detection value is consistent with the set switching frequency, then these data channels can be determined as target data channels. The target data channel is the data channel actually used by the bus device.

[0059] According to the number of target data channels, the number of data channels actually used can be determined, and then the bus bandwidth allocation value can be determined. For example, in a PCIe X16 slot, there are 8 data channels whose channel positions are closely adjacent, and the switch frequency detection values ​​of these 8 data channels are consistent with the set switch frequency, then it can be determined that these 8 data channels are the data channels actually used by the bus device, the slot specification is X8, and a bus bandwidth 8 times that of X1 needs to be provided.

[0060] The bus bandwidth allocation method provided in the embodiment of the present application determines the bus bandwidth allocation value corresponding to the bus device according to the number of data channels whose channel positions are adjacent and whose switching frequency detection values ​​are consistent with the set switching frequency, thereby improving the accuracy of determining the bus bandwidth allocation value.

[0061] In some embodiments, before providing a detection voltage to a bus device inserted into a bus device slot and controlling a switching frequency of the detection voltage, the method further includes: A detection voltage is determined based on the operating voltage of each bus device; the detection voltage is less than the operating voltage of each bus device.

[0062] Specifically, each bus device slot can be detected to obtain the working voltage of each bus device inserted into each bus device slot. When determining the detection voltage, a voltage value less than the working voltage of each bus device can be selected as the detection voltage. For example, if the working voltages of each bus device are 3.3 volts, 5 volts, and 12 volts, respectively, 1 volt can be selected as the detection voltage.

[0063] In the bus bandwidth allocation method provided in the embodiment of the present application, the detection voltage is lower than the operating voltage of each bus device, so that the voltage is only used to determine the bus bandwidth without affecting the normal operation of the bus devices.

[0064] In some embodiments, sending a switching frequency control instruction to a power control device includes: Determine the set switching frequency corresponding to each bus device; the set switching frequency corresponding to each bus device is different; Based on the set switching frequencies corresponding to the various bus devices, generating switching frequency control instructions corresponding to the various bus devices; Sending the switching frequency control instructions corresponding to each bus device to the power control device corresponding to each bus device, so that the power control device controls the switching frequency of the detection voltage of each bus device; Alternatively, generating a switching frequency control instruction corresponding to the current bus device; Sending a switching frequency control instruction corresponding to the current bus device to a power control device corresponding to the current bus device, so that the power control device controls the switching frequency of the detection voltage of the current bus device; When the bus bandwidth allocation value corresponding to the current bus device is determined, the current bus device is switched to the next bus device.

[0065] Specifically, the embodiments of the present application provide two methods for sending switching frequency control instructions to a power supply control device.

[0066] The first method is suitable for parallel detection of bus devices in bus device slots. The processor can set different set switching frequencies for each bus device, so that one set switching frequency is used to detect one bus device.

[0067] According to the set switching frequency corresponding to each bus device, a switching frequency control instruction corresponding to each bus device is generated, and these switching frequency control instructions are sent to the power control device corresponding to each bus device, so that the power control device controls the switching frequency of the detection voltage of each bus device.

[0068] The second method is suitable for sequentially detecting the bus devices in the bus device slots according to a certain detection sequence. In each detection, a corresponding detection time can be set to complete the detection within the detection time.

[0069] First, the current bus device in the current detection process is determined, and a switching frequency control instruction corresponding to the current bus device is generated. Since sequential detection is adopted in this method, no two bus devices are detected at the same time, so the switching frequencies corresponding to each bus device can be the same.

[0070] The switching frequency control instruction corresponding to the current bus device is sent to the power control device corresponding to the current bus device, so that the power control device controls the switching frequency of the detection voltage of the current bus device.

[0071] When the bus bandwidth allocation value corresponding to the current bus device is determined, the current bus device is switched to the next bus device. Through the above method, the bus bandwidth allocation value of each bus device is determined one by one according to a certain detection order.

[0072] The bus bandwidth allocation method provided in the embodiment of the present application can detect multiple bus devices simultaneously by setting different set switching frequencies, and can also sequentially detect each bus device according to a certain detection order, thereby improving the accuracy of determining the bus bandwidth allocation value.

[0073] In some embodiments, allocating bus bandwidth to bus devices based on the bus bandwidth allocation value includes: Sending a second voltage control instruction to the power supply device; the second voltage control instruction is used to control the power supply device to provide a working voltage to the bus device; When the bus device works normally, the bus bandwidth is allocated to the bus device based on the bus bandwidth allocation value.

[0074] Specifically, after determining the bus bandwidth allocation value of the bus device, the processor may send a second voltage control instruction to the power supply device, where the instruction is used to control the power supply device to provide an operating voltage to the bus device so that the bus device can operate normally.

[0075] When the bus device operates normally, the processor allocates bus bandwidth to the bus device according to the bus bandwidth allocation value, so that the allocated bus bandwidth can meet the needs of the bus device and avoid waste of PCIe bus resources.

[0076] The device provided in the embodiment of the present application is described below. The device described below and the method described above can be referenced to each other.

[0077] Figure 2 is a schematic diagram of the structure of the bus bandwidth allocation device provided by the present application, such as Figure 2 As shown, the device comprises: The voltage generating module 210 is used to provide a detection voltage to the bus device inserted into the bus device slot and control the switching frequency of the detection voltage; The frequency detection module 220 is used to obtain the switching frequency detection value of each data channel in the bus device slot; The bandwidth determination module 230 is used to determine the bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel; The bandwidth allocation module 240 is used to allocate bus bandwidth to bus devices based on the bus bandwidth allocation value.

[0078] The bus bandwidth allocation device provided in the embodiment of the present application provides a detection voltage to a bus device inserted into a bus device slot, and controls the switching frequency of the detection voltage; obtains the switching frequency detection value of each data channel in the bus device slot; determines the bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel; allocates the bus bandwidth to the bus device based on the bus bandwidth allocation value; since detection voltages with different switching frequencies are provided to the bus device, the switching frequency of each data channel in the bus device slot is detected, and the number of data channels actually used by the bus device is determined by comparing the switching frequency detection values ​​of each data channel, and then the bus bandwidth allocation value is determined, so that the bandwidth of the PCIe bus device can be accurately determined and automatically allocated, avoiding the processor directly allocating the maximum bandwidth according to the bus device slot and avoiding the waste of PCIe bus resources.

[0079] In some embodiments, the voltage generation module is used to: Sending a first voltage control instruction to the power supply device; the first voltage control instruction is used to control the power supply device to provide a detection voltage to the bus device; A switching frequency control instruction is sent to the power control device; the switching frequency control instruction is used to control the power control device to set the switching frequency of the switching frequency control detection voltage.

[0080] In some embodiments, the bandwidth determination module is configured to: Determine a switching frequency detection value of each data channel in a bus device slot and a channel position of each data channel; The data channels whose channel positions are adjacent and whose switching frequency detection values ​​are consistent with the set switching frequency are determined as target data channels; Based on the number of target data channels, a bus bandwidth allocation value corresponding to the bus device is determined.

[0081] In some embodiments, the voltage generating module is further configured to: A detection voltage is determined based on the operating voltage of each bus device; the detection voltage is less than the operating voltage of each bus device.

[0082] In some embodiments, the voltage generating module is specifically used for: Determine the set switching frequency corresponding to each bus device; the set switching frequency corresponding to each bus device is different; Based on the set switching frequencies corresponding to the various bus devices, generating switching frequency control instructions corresponding to the various bus devices; Sending the switching frequency control instructions corresponding to each bus device to the power control device corresponding to each bus device, so that the power control device controls the switching frequency of the detection voltage of each bus device; Alternatively, generating a switching frequency control instruction corresponding to the current bus device; Sending a switching frequency control instruction corresponding to the current bus device to a power control device corresponding to the current bus device, so that the power control device controls the switching frequency of the detection voltage of the current bus device; When the bus bandwidth allocation value corresponding to the current bus device is determined, the current bus device is switched to the next bus device.

[0083] In some embodiments, the bandwidth allocation module is specifically configured to: Sending a second voltage control instruction to the power supply device; the second voltage control instruction is used to control the power supply device to provide a working voltage to the bus device; When the bus device works normally, the bus bandwidth is allocated to the bus device based on the bus bandwidth allocation value.

[0084] Figure 3 It is a schematic diagram of the structure of the server provided by this application, such as Figure 3 As shown, the server 300 includes a processor 310 , a power supply device 320 , a power control device 330 , and a bus device slot 340 .

[0085] Bus device slot, used to insert bus devices.

[0086] Power supply device, used to provide detection voltage for bus devices.

[0087] A power control device is used to control the switching frequency of the detection voltage.

[0088] The processor is connected to the power supply device, the power control device and the bus device slot, and is used to execute the bus bandwidth allocation method in the above embodiment to allocate bus bandwidth to the bus device.

[0089] The server provided in the embodiment of the present application can accurately determine the bandwidth of the PCIe bus device and realize automatic allocation because the processor executes the bus bandwidth allocation method in the above embodiment, thereby avoiding the processor directly allocating the maximum bandwidth according to the bus device slot and avoiding the waste of PCIe bus resources.

[0090] Figure 4 This is the second flow chart of the bus bandwidth allocation method provided by this application, such as Figure 4 As shown, the method is applicable to the server and is implemented by the Basic Input Output System (BIOS). The server and the bus device use the PCIe bus, so the bus device can also be called a PCIe device. The specific steps include: Step 410: Insert the PCIe device into the PCIe device slot in the server mainboard.

[0091] After the PCIe device is inserted into the slot, the data channel (Lane) ports of all PCIe devices are connected to the data channel (Lane) ports of the root port (PCIe Root port) of the central processing unit (CPU) in the motherboard.

[0092] Step 420: Set the eFUSE chip corresponding to each PCIe device slot.

[0093] The switch chip is used to control the on and off of the power supply and output voltages of different frequencies. The switch chip can be an eFUSE (electronic Fuse, programmable electronic fuse) chip, etc.

[0094] Figure 5 is a circuit connection diagram of bus bandwidth allocation provided by this application, such as Figure 5 As shown, the circuit includes a central processing unit (CPU), a power supply device (DC / DC chip), a power control device (eFUSE chip) and a PCIe device slot.

[0095] The BIOS system code runs in the central processing unit, and the system management bus (SMBUS) of the central processing unit connects the power supply device and the switch chip. The BIOS generates switch signals of different frequencies by sending different switch commands to the power supply device and the switch chip connected to the MBUS bus.

[0096] Figure 6 is a circuit diagram of the power supply device provided by this application, such as Figure 6 As shown, U1 is a switching voltage regulator of a step-down power management monolithic integrated circuit, which can output a driving current of 3 amperes (A) and has good linear and load regulation characteristics. The fixed output versions are 3.3V, 5V, and 12V, which are adapted to the voltage used in the PCIe device slot. VIN is the power supply end, GND is the ground end, and 3.3V / 5V / 12V is the output end. In the middle, inductors L1 and L2, diodes D1, D2, and D3 are used for rectification and voltage regulation. Capacitors C1, C2, and C3 are used for filtering. The output end of the switching voltage regulator U1 is connected to resistor R1 to form a PCIe device slot power supply switch circuit, which identifies the BIOS and sends an on signal to the switch circuit. Switch S1 is a switch chip used to control the on and off of the power supply and output voltages of different frequencies.

[0097] Step 430: At the time of powering on, the BIOS uses the Inter-Integrated Circuit (IIC) interface to set the output voltage of the power supply device that supplies power to the PCIe device to 1V.

[0098] The power supply device may be a DC / DC (Direct Current / Direct Current) chip, which can convert a DC voltage into a DC voltage of different voltage levels.

[0099] Step 440, BIOS uses the integrated circuit bus interface to send an enable signal of different frequencies to each eFUSE chip, and each PCIe device will receive a 1V voltage power supply of different frequencies.

[0100] Step 450, BIOS reads the PCIe Lane frequency status register in the CPU, and if it obtains that adjacent Lanes on n CPUs have the same frequency start signal, the bandwidth of the device is recorded as Xn; for example, if BIOS reads that the same frequency start signal exists on Lanes connected to 4 CPU ends in one of the PCIe X16 device slots, the bandwidth of the device is recorded as X4.

[0101] The frequency signals obtained by all Lanes of a PCIe X16 and the device bandwidth information in the device slots are shown in Table 1.

[0102] Table 1 Device bandwidth information table

[0103] It can be clearly seen from the above table that after the BIOS is turned on, it reads that there are 4 identical frequency signals in the adjacent Lanes on the CPU, and directly allocates the PCIe bandwidth to X4. Any combination of PCIe devices can achieve the purpose of use.

[0104] Step 460, BIOS restores the DC / DC chip to normal level output and allocates the bandwidth required by each PCIe device. As shown in the above table, the bandwidth allocated by BIOS is X4. Combined with the independent power supply switch circuit or eFUSE chip of each PCIe device, the BIOS software detects the CPU PCIe lane frequency status register and obtains the same frequency start signal for adjacent Lanes on the CPU, thereby realizing automatic allocation of PCIe device bandwidth.

[0105] The method provided in the embodiment of the present application only needs to establish a PCIe device slot power supply switch circuit or install an eFUSE chip. After the BIOS identifies the PCIe device slot after startup, each switch circuit or eFUSE chip sends an enable signal of different frequencies. The total number of devices inserted into the PCIe device slot can be quickly confirmed, and then a total bandwidth value can be directly allocated. The specific slot can be identified with higher identification accuracy, and the bandwidth allocation is more accurate and quick, thereby improving the bandwidth allocation efficiency. It can achieve the effect of connecting multiple devices to one PCIe slot without being directly affected by the bandwidth.

[0106] Figure 7 is a schematic diagram of the structure of the electronic device provided by this application, such as Figure 7 As shown, the electronic device may include: a processor (Processor) 710, a communication interface (Communications Interface) 720, a memory (Memory) 730 and a communication bus (Communications Bus) 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic command in the memory 730 to execute the method described in the above embodiment, for example: Provide a detection voltage to a bus device inserted into a bus device slot, and control the switching frequency of the detection voltage; obtain a switching frequency detection value of each data channel in the bus device slot; determine a bus bandwidth allocation value corresponding to the bus device based on the switching frequency detection value of each data channel; and allocate bus bandwidth to the bus device based on the bus bandwidth allocation value.

[0107] In addition, the logical commands in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several commands to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program code.

[0108] The processor in the electronic device provided in the embodiment of the present application can call the logic instructions in the memory to implement the above method. Its specific implementation method is consistent with the implementation method of the aforementioned method and can achieve the same beneficial effects, which will not be repeated here.

[0109] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the methods provided in the above embodiments are implemented.

[0110] Its specific implementation is consistent with the aforementioned method implementation and can achieve the same beneficial effects, so it will not be repeated here.

[0111] An embodiment of the present application provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0112] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0113] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A bus bandwidth allocation method, It is characterized in that include: Providing a detection voltage to a bus device inserted into the bus device slot, and controlling a switching frequency of the detection voltage; Obtaining a switching frequency detection value of each data channel in the bus device slot; Determining a bus bandwidth allocation value corresponding to the bus device based on a switching frequency detection value of each data channel; A bus bandwidth is allocated to the bus device based on the bus bandwidth allocation value.

2. The bus bandwidth allocation method according to claim 1, It is characterized in that The method of providing a detection voltage to a bus device inserted into a bus device slot and controlling a switching frequency of the detection voltage comprises: Sending a first voltage control instruction to a power supply device; the first voltage control instruction is used to control the power supply device to provide a detection voltage to the bus device; A switching frequency control instruction is sent to a power control device; the switching frequency control instruction is used to control the power control device to control the switching frequency of the detection voltage by setting the switching frequency.

3. The bus bandwidth allocation method according to claim 2, It is characterized in that The determining, based on the switching frequency detection value of each data channel, the bus bandwidth allocation value corresponding to the bus device comprises: Determining a switching frequency detection value of each data channel in the bus device slot and a channel position of each data channel; Determine the data channels whose channel positions are adjacent and whose switching frequency detection values ​​are consistent with the set switching frequency as the target data channels; Based on the number of the target data channels, a bus bandwidth allocation value corresponding to the bus device is determined.

4. The bus bandwidth allocation method according to claim 2, It is characterized in that Before providing a detection voltage to the bus device inserted into the bus device slot and controlling a switching frequency of the detection voltage, the method further includes: The detection voltage is determined based on the operating voltage of each bus device; the detection voltage is less than the operating voltage of each bus device.

5. The bus bandwidth allocation method according to claim 2, It is characterized in that The sending of a switching frequency control instruction to the power supply control device comprises: Determine the set switching frequency corresponding to each bus device; the set switching frequency corresponding to each bus device is different; Based on the set switching frequencies corresponding to the various bus devices, generating switching frequency control instructions corresponding to the various bus devices; Sending a switching frequency control instruction corresponding to each bus device to a power control device corresponding to each bus device, so that the power control device controls the switching frequency of the detection voltage of each bus device; Alternatively, generating a switching frequency control instruction corresponding to the current bus device; Sending a switching frequency control instruction corresponding to the current bus device to a power control device corresponding to the current bus device, so that the power control device controls the switching frequency of the detection voltage of the current bus device; When the bus bandwidth allocation value corresponding to the current bus device is determined, the current bus device is switched to a next bus device.

6. The bus bandwidth allocation method according to any one of claims 1 to 5, It is characterized in that The allocating bus bandwidth to the bus device based on the bus bandwidth allocation value comprises: Sending a second voltage control instruction to the power supply device; the second voltage control instruction is used to control the power supply device to provide an operating voltage to the bus device; When the bus device operates normally, a bus bandwidth is allocated to the bus device based on the bus bandwidth allocation value.

7. A bus bandwidth allocation device, It is characterized in that include: A voltage generating module, used for providing a detection voltage to a bus device inserted into the bus device slot, and controlling a switching frequency of the detection voltage; A frequency detection module, used to obtain a switching frequency detection value of each data channel in the bus device slot; A bandwidth determination module, used to determine a bus bandwidth allocation value corresponding to the bus device based on a switching frequency detection value of each data channel; The bandwidth allocation module is used to allocate bus bandwidth to the bus device based on the bus bandwidth allocation value.

8. A server, It is characterized in that Includes a processor, a power supply device, a power control device, and a bus device slot; The bus device slot is used to insert a bus device; The power supply device is used to provide a detection voltage for the bus device; The power supply control device is used to control the switching frequency of the detection voltage; The processor is connected to the power supply device, the power control device and the bus device slot, and is used to execute the bus bandwidth allocation method according to any one of claims 1 to 6 to allocate bus bandwidth to the bus device.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, It is characterized in that When the processor executes the computer program, the bus bandwidth allocation method according to any one of claims 1 to 6 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, It is characterized in that When the computer program is executed by a processor, the bus bandwidth allocation method according to any one of claims 1 to 6 is implemented.

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