SPDK architecture multi-control storage expansion method and device based on memory sharing

Abstract

The embodiment of the invention discloses an SPDK architecture multi-control storage expansion method and device based on memory sharing. The method comprises the following steps: constructing interconnection links with other controllers; creating an original annular queue in the SPDK process, and mapping a mapping annular queue corresponding to the original annular queue in the SPDK processes of other controllers based on the interconnection link; and traversing and processing the queue data in the original annular queue. According to the embodiment of the invention, support of upper-layer communication protocols such as FC, ISCSI and NVMe-oF is not needed, conversion of block equipment is not needed, the opposite end is directly operated through the SPDK process, namely, annular queues mapped by other controllers are operated, and the SPDK process of the opposite end is treated as a thread of the SPDK process, so that inter-process communication is converted into inter-thread communication; the resource consumption is reduced, the communication speed is improved, and the operation of the SPDK is expanded from single-controller operation to multi-controller operation.

Description

Technical Field

[0001] One or more embodiments of this specification relate to communication technology, and more particularly, to a method and device for multi-control storage expansion of an SPDK architecture based on memory sharing. Background Art

[0002] The Storage Performance Development Kit (SPDK) provides a series of high-performance, scalable, user-mode tools and libraries. The current application scenarios of SPDK are mainly for block storage. It is driven by polling mode and uses a ring queue to process requests between threads. The request thread submits the request to the queue and continues to perform other work. The processing thread can check whether there are new requests submitted and process them by continuously polling or periodically polling the queue. The current storage system has developed from a single single-controller system to a multi-controller system. However, the current SPDK software can only run on a single machine, resulting in the communication between the controllers of the SPDK architecture can only be through FC, ISCSI, NVMe-oF and other communication protocols, mapping the storage device of one controller to another controller through the above protocols, so that the mapped storage device is used as a block device. These methods need to be processed by the block device layer, which increases the complexity of the structure, has high cost, slow transmission rate, high IO latency, and poor interoperability of SPDK software running between multiple controllers. Summary of the invention

[0003] In order to solve the above problems, one or more embodiments of this specification describe a method and device for multi-controller storage expansion in an SPDK architecture based on memory sharing.

[0004] According to a first aspect, a method for multi-controller storage expansion of an SPDK architecture based on memory sharing is provided, the method comprising: Building an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing for multiple controllers; An original circular queue is created in the SPDK process, and a mapped circular queue corresponding to the original circular queue is mapped in the SPDK processes of other controllers based on the interconnection link, and queue data of the original circular queue and the mapped circular queue that match each other are shared in real time; The queue data in the original circular queue is traversed and processed.

[0005] Preferably, the high-speed interconnection protocol is a non-transparent bridge protocol or a computational fast link protocol.

[0006] Preferably, the original ring queue is only provided with message dequeueing authority, and the mapped ring queue is only provided with message enqueueing authority.

[0007] Preferably, after creating the original ring queue in the SPDK process, the method further includes: Initialize the original ring queue.

[0008] Preferably, the traversing and processing the queue data in the original ring queue includes: The original circular queue is traversed in a continuous polling manner, and when queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

[0009] Preferably, the method further comprises: When a data write instruction is detected, a target mapping circular queue and a target write row corresponding to the data to be written are determined, and the data to be written is written to the target write row of the target mapping circular queue.

[0010] Preferably, the creating of the original ring queue in the SPDK process, and mapping the mapped ring queue corresponding to the original ring queue in the SPDK processes of other controllers based on the interconnection link, includes: When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are respectively mapped in the SPDK process of each remaining controller based on the interconnection link.

[0011] According to a second aspect, a SPDK architecture multi-control storage expansion device based on memory sharing is provided, the device comprising: A construction module, used to construct an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing on multiple controllers; A mapping module, used for creating an original circular queue in the SPDK process, mapping a mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link, and sharing queue data of the mutually matching original circular queue and mapped circular queue in real time; The traversal module is used to traverse and process the queue data in the original circular queue.

[0012] According to a third aspect, there is provided an electronic device, comprising a processor and a memory; The processor is connected to the memory; The memory is used to store executable program code; The processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the steps of the method provided in the first aspect or any possible implementation manner of the first aspect.

[0013] According to a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and the computer-readable storage medium stores instructions, which, when the instructions are executed on a computer or a processor, cause the computer or the processor to execute the method provided in the first aspect or any possible implementation of the first aspect.

[0014] The method and device provided in the embodiments of this specification do not require the support of upper-layer communication protocols such as FC, ISCSI, NVMe-oF, etc., nor do they require conversion of block devices. The opposite end is directly operated through the SPDK process, that is, the circular queues mapped by the other controllers are operated, and the SPDK process of the opposite end is regarded as its own thread for processing, thereby converting the communication between processes into communication between threads, reducing resource consumption, improving the communication speed, and extending the operation of SPDK from single-controller operation to multi-controller operation, thereby realizing multi-controller storage expansion under the SPDK architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a flowchart of a multi-controller storage expansion method in an SPDK architecture based on memory sharing in an embodiment of this specification.

[0017] Figure 2 It is a schematic diagram of the architecture of the interconnection link in one embodiment of this specification.

[0018] Figure 3 It is a schematic diagram of the principle of the mapping process of the original ring queue in one embodiment of this specification.

[0019] Figure 4 It is a structural diagram of a multi-control storage expansion device based on SPDK architecture with memory sharing in one embodiment of this specification.

[0020] Figure 5 It is a structural diagram of an electronic device in one embodiment of this specification. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0022] In the following introduction, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The following introduction provides multiple embodiments of the present application, and different embodiments can be replaced or combined, so the present application can also be considered to include all possible combinations of the same and / or different embodiments recorded. Therefore, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then the present application should also be considered to include embodiments containing one or more of all other possible combinations of A, B, C, and D, although the embodiment may not be clearly recorded in the following text.

[0023] The following description provides examples and does not limit the scope, applicability or examples set forth in the claims. Changes may be made to the functions and arrangements of the elements described without departing from the scope of the present application. Various processes or components may be appropriately omitted, substituted or added to each example. For example, the described method may be performed in an order different from the order described, and various steps may be added, omitted or combined. In addition, features described in some examples may be combined in other examples.

[0024] See also Figure 1 , Figure 1 1 is a flow chart of a method for multi-controller storage expansion based on memory sharing in an SPDK architecture provided in an embodiment of the present application. In an embodiment of the present application, the method includes: S101. Build interconnection links with other controllers based on a high-speed interconnection protocol that supports memory sharing.

[0025] The interconnection link is used to share memory mapping for multiple controllers.

[0026] The execution subject of this application may be a controller.

[0027] In the embodiments of this specification, there are multiple controllers in a multi-control system. In order to realize the multi-control storage expansion under the SPDK architecture, the controller first needs to directly build an interconnection link with the remaining controllers through a high-speed interconnection protocol that supports memory sharing, so as to realize the memory mapping sharing between multiple controllers through the interconnection link. High-speed protocols are commonly used in the storage field. Compared with upper-layer communication protocols such as FC, ISCSI, and NVMe-oF, they have the advantages of low overhead and high speed. The communication connection constructed by the memory mapping sharing method allows the controllers to be directly connected through the interconnection link, without the support of the upper-layer communication protocol, and without the conversion of block devices, which is more efficient. At the same time, such a memory sharing mapping method can also enable the controller to directly operate the data mapped by the remaining controllers through the SPDK process, so as to treat the SPDK processes of the remaining controllers as their own threads, and then transform the communication between processes into communication between threads, so that the operation of SPDK is extended from a single controller to multiple controllers. Among them, the high-speed interconnection protocol supporting memory sharing can use Non-Transparent Bridge (NTB), Compute Express Link (CXL), Unified Port Interface (UPI), etc. Among them, the remaining controllers refer to the controllers other than the controller itself in the multi-control system.

[0028] In one possible implementation, the high-speed interconnection protocol is a non-transparent bridge protocol or a computing fast link protocol.

[0029] In the embodiments of this specification, NTB (non-transparent bridge) technology is derived from the standard PCIe rules. Two hosts can forward PCIe transactions from one side of NTB to the other side through the address translation mechanism of NTB. This function enables communication between different hosts. With the help of the characteristics of NTB, the memory of other machines can also be mapped to this end to achieve memory sharing. CXL is a high-speed data transmission protocol that allows fast and reliable data transmission between different components within a computer system. It aims to solve bottleneck problems in high-performance computing, including memory capacity, memory bandwidth, and I / O latency. CXL technology not only provides high-speed transmission, but also supports memory sharing and virtualization, making the collaboration between controllers closer and more efficient. The interconnection link architecture built according to the non-transparent bridge protocol or the computing fast link protocol is as follows: Figure 2 As shown in the figure, multiple controllers can be interconnected through PCIE NTB links or CXL links. If PCIE NTB links are used, controllers can access the memory of other controllers through NTB. If CXL links are used, multiple controllers can simultaneously access the shared memory attached to the CXL links.

[0030] S102: Create an original ring queue in the SPDK process, and map a mapped ring queue corresponding to the original ring queue in the SPDK processes of other controllers based on the interconnection link.

[0031] The queue data of the original ring queue and the mapped ring queue that match each other are shared in real time.

[0032] In the embodiments of this specification, the controller will create an original circular queue in the SPDK process, and then share the original circular queue mapping created by itself to other controllers through the memory sharing mechanism of the interconnection link, so that there will also be a mapped circular queue corresponding to the original circular queue of this controller in the other controllers. They match each other, that is, the queue data of the original circular queue and the mapped circular queue, which essentially belong to a circular queue, are shared in real time through the interconnection link, so that the other controllers can read and write the mapped circular queue in their own SPDK process, and realize the process of operating the original circular queue of this controller with other controllers. The specific principle diagram of this process is shown in the figure. Figure 3 shown.

[0033] In one possible implementation, the original ring queue is only provided with a message dequeue permission, and the mapped ring queue is only provided with a message enqueue permission.

[0034] In the embodiments of the present specification, in order to prevent the current controller and another controller mapped with a mapped circular queue from reading and writing the same circular queue at the same time, that is, conflicts caused by reading and writing the same block of memory at the same time, only message dequeue permissions will be set in the original circular queue, and only message enqueue permissions will be set in the mapped circular queue. In this way, any controller can only read data from the original circular queue in its own SPDK, and write data from the mapped circular queue in its own SPDK.

[0035] In one possible implementation, the creating an original ring queue in the SPDK process, and mapping a mapped ring queue corresponding to the original ring queue in the SPDK processes of other controllers based on the interconnection link, includes: When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are respectively mapped in the SPDK process of each remaining controller based on the interconnection link.

[0036] In the embodiments of this specification, under normal circumstances, an original circular queue will only match one mapped circular queue, that is, an original circular queue will only form a mapped circular queue in one remaining controller for memory sharing. If a certain circular queue of this controller needs to be shared with multiple controllers, the controller will generate multiple original circular queues of the same type according to the number of remaining controllers that need to be shared, and map the mapped circular queues in each remaining controller through different original circular queues to ensure the independence of the same type of mapped circular queues in different remaining controllers without mutual interference.

[0037] In one possible implementation, after creating the original ring queue in the SPDK process, the method further includes: Initialize the original ring queue.

[0038] In the embodiments of this specification, after the original circular queue is created, the original circular queue needs to be initialized first. The specific process of initialization may include allocating memory space, setting the queue size, initializing control variables, marking the queue state, setting boundary conditions, initializing auxiliary variables, etc. Among them, allocating memory space refers to allocating enough memory to store the data structure of the circular queue, which usually includes the element array in the queue and the control variables (such as head pointer, tail pointer, etc.) that manage the queue state. Setting the queue size refers to determining the maximum capacity of the queue, that is, how many elements the queue can store at most. Usually, the size of the queue should be a power of 2, so as to simplify the management logic of the circular queue by bit operation. Initializing control variables refers to setting the initial values ​​of the head pointer (head) and the tail pointer (tail) of the queue. Marking the queue state refers to initializing the status flag of the queue, such as whether it is empty, whether it is full, etc. Setting boundary conditions is to construct the wrap-around logic after the queue head and tail pointers reach the end of the queue. Initializing auxiliary variables refers to initializing the counter that records the current number of elements in the queue.

[0039] S103: traverse and process the queue data in the original ring queue.

[0040] In the embodiments of this specification, through the above settings, each controller can operate the circular queues of other controllers to achieve mutual communication between controllers. During the communication process, corresponding data will be generated in the circular queue, and the controller will traverse the original circular queue to determine the queue data therein and process the queue data uniformly. The traversal process can choose regular traversal or irregular continuous real-time traversal according to actual conditions. The former may cause lag in data processing and have a higher delay, so the latter is generally preferred.

[0041] In one possible implementation, the traversing and processing queue data in the original ring queue includes: The original circular queue is traversed in a continuous polling manner, and when queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

[0042] In the embodiment of this specification, the controller will continuously traverse the original circular queue in a continuous polling manner. In the process of traversing the original circular queue, if queue data is found in the queue, the queue data will be dequeued first, that is, the queue data will be taken out, and the queue data will be processed after it is taken out, rather than directly processing the data in the queue, and it also avoids the residual processed data in the queue.

[0043] In one embodiment, the method further comprises: When a data write instruction is detected, a target mapping circular queue and a target write row corresponding to the data to be written are determined, and the data to be written is written to the target write row of the target mapping circular queue.

[0044] In the embodiment of this specification, when there are more than two controllers in the storage system, there will be different mapping ring queues mapped from different controllers in the SPDK process of one controller. When the user wants to write data through the controller, the controller will determine which mapping ring queue the current data to be written is to be written to according to the data write instruction, that is, determine the target mapping ring queue, and also determine the target write row, that is, the specific location in the write target mapping ring queue.

[0045] The following will be combined with the attached Figure 4 , the SPDK architecture multi-control storage expansion device based on memory sharing provided in the embodiment of the present application is introduced in detail. It should be noted that the attached Figure 4 The SPDK architecture multi-control storage expansion device based on memory sharing shown is used to execute the application Figure 1 For the convenience of explanation, only the part related to the embodiment of the present application is shown. For the specific technical details not disclosed, please refer to the present application. Figure 1 The embodiment shown.

[0046] See also Figure 4 , Figure 4 Schematic diagram of a multi-control storage expansion device based on SPDK architecture and memory sharing provided by an embodiment of the present application. Figure 4 As shown, the device comprises: A construction module 401 is used to construct an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing on multiple controllers; A mapping module 402 is used to create an original ring queue in the SPDK process, and map a mapped ring queue corresponding to the original ring queue in the SPDK processes of other controllers based on the interconnection link, and the queue data of the original ring queue and the mapped ring queue that match each other are shared in real time; The traversal module 403 is used to traverse and process the queue data in the original ring queue.

[0047] In one possible implementation, the high-speed interconnection protocol is a non-transparent bridge protocol or a computing fast link protocol.

[0048] In one possible implementation, the original ring queue is only provided with message dequeueing authority, and the mapped ring queue is only provided with message enqueueing authority.

[0049] In one possible implementation, the mapping module 402 is further configured to: Initialize the original ring queue.

[0050] In one possible implementation, the traversal module 403 is specifically used for: The original circular queue is traversed in a continuous polling manner, and when queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

[0051] In one embodiment, the device further comprises: The writing module is used to determine the target mapping circular queue and the target writing row corresponding to the data to be written when a data writing instruction is detected, and write the data to be written into the target writing row of the target mapping circular queue.

[0052] In one possible implementation, the mapping module 402 is specifically configured to: When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are respectively mapped in the SPDK process of each remaining controller based on the interconnection link.

[0053] Those skilled in the art can clearly understand that the technical solutions of the embodiments of the present application can be implemented with the help of software and / or hardware. The "unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array (FPGA), an integrated circuit (IC), etc.

[0054] Each processing unit and / or module of the embodiments of the present application may be implemented by an analog circuit that implements the functions described in the embodiments of the present application, or may be implemented by software that executes the functions described in the embodiments of the present application.

[0055] See also Figure 5 , which shows a schematic diagram of the structure of an electronic device involved in an embodiment of the present application, the electronic device can be used to implement Figure 1 The method in the embodiment shown. Figure 5 As shown, the electronic device 500 may include: at least one processor 501 , at least one network interface 504 , a user interface 503 , a memory 505 , and at least one communication bus 502 .

[0056] The communication bus 502 is used to realize the connection and communication between these components.

[0057] The user interface 503 may include a display screen (Display) and a camera (Camera). Optionally, the user interface 503 may also include a standard wired interface and a wireless interface.

[0058] The network interface 504 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0059] Among them, the processor 501 may include one or more processing cores. The processor 501 uses various interfaces and lines to connect various parts of the entire electronic device 500, and executes various functions and processes data of the electronic device 500 by running or executing instructions, programs, code sets or instruction sets stored in the memory 505, and calling data stored in the memory 505. Optionally, the processor 501 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 501 can integrate one or a combination of a central processing unit (Central Processing Unit, CPU), a graphics central processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communication. It can be understood that the above-mentioned modem may not be integrated into the processor 501, and it can be implemented separately through a chip.

[0060] Among them, the memory 505 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 505 includes a non-transitory computer-readable storage medium. The memory 505 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 505 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned method embodiments, etc.; the data storage area may store data involved in the above-mentioned method embodiments, etc. The memory 505 may optionally be at least one storage device located away from the aforementioned processor 501. As Figure 5 As shown, the memory 505 as a computer storage medium may include an operating system, a network communication module, a user interface module, and program instructions.

[0061] exist Figure 5 In the electronic device 500 shown, the user interface 503 is mainly used to provide an input interface for the user and obtain data input by the user; and the processor 501 can be used to call the SPDK architecture multi-control storage extension application based on memory sharing stored in the memory 505, and specifically perform the following operations: Building an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing for multiple controllers; An original circular queue is created in the SPDK process, and a mapped circular queue corresponding to the original circular queue is mapped in the SPDK processes of other controllers based on the interconnection link, and queue data of the original circular queue and the mapped circular queue that match each other are shared in real time; The queue data in the original circular queue is traversed and processed.

[0062] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0063] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0064] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0065] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0066] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0067] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0068] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program codes.

[0069] A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by entering a program to instruct related hardware, and the program may be stored in a computer-readable memory, which may include a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0070] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. A multi-controller storage expansion method for an SPDK architecture based on memory sharing, characterized in that: The method comprises: Building an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing for multiple controllers; An original circular queue is created in the SPDK process, and a mapped circular queue corresponding to the original circular queue is mapped in the SPDK processes of other controllers based on the interconnection link, and queue data of the original circular queue and the mapped circular queue that match each other are shared in real time; The queue data in the original circular queue is traversed and processed.

2. The method according to claim 1, characterized in that The high-speed interconnection protocol is a non-transparent bridge protocol or a computing fast link protocol.

3. The method according to claim 1, characterized in that The original ring queue is only provided with a message dequeueing authority, and the mapped ring queue is only provided with a message enqueueing authority.

4. The method according to claim 1, characterized in that: After the original ring queue is created in the SPDK process, the following steps are also included: Initialize the original ring queue.

5. The method according to claim 1, characterized in that The traversing and processing the queue data in the original ring queue includes: The original circular queue is traversed in a continuous polling manner, and when queue data exists in the original circular queue, the queue data is taken out from the original circular queue and processed.

6. The method according to claim 1, characterized in that The method further comprises: When a data write instruction is detected, a target mapping circular queue and a target write row corresponding to the data to be written are determined, and the data to be written is written to the target write row of the target mapping circular queue.

7. The method according to claim 1, characterized in that The creating of the original ring queue in the SPDK process, and mapping the mapped ring queue corresponding to the original ring queue in the SPDK processes of other controllers based on the interconnection link, includes: When there are more than two remaining controllers that need to share memory, the same number of original circular queues are created in the SPDK process based on the number of remaining controllers that need to share memory, and mapped circular queues corresponding to different original circular queues are respectively mapped in the SPDK process of each remaining controller based on the interconnection link.

8. A multi-control storage expansion device based on SPDK architecture with memory sharing, characterized in that: The device comprises: A construction module, used to construct an interconnection link with other controllers based on a high-speed interconnection protocol supporting memory sharing, wherein the interconnection link is used to perform memory mapping sharing on multiple controllers; A mapping module, used for creating an original circular queue in the SPDK process, mapping a mapped circular queue corresponding to the original circular queue in the SPDK processes of other controllers based on the interconnection link, and sharing queue data of the mutually matching original circular queue and mapped circular queue in real time; The traversal module is used to traverse and process the queue data in the original circular queue.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, wherein the computer-readable storage medium has instructions stored therein, and when the instructions are executed on a computer or a processor, the computer or the processor executes the steps of the method according to any one of claims 1 to 7.

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