Direct memory access controller, data handling method and chip

Abstract

The embodiment of the invention provides a direct memory access controller, a data handling method and a chip wherein the direct memory access controller comprises: a read controller, a write controller and a request state management module; the request state management module is used for at least recording an initial address of each address space, a request identifier of each request capable of being processed in each address space, a request state identifier corresponding to each request identifier and the initial address of the address space are determined based on a source address and a destination address of the data handling task; the read controller and the write controller configure a request state identifier corresponding to the request identifier of each request according to the execution condition of each request, and the request identifier indicates the address space where each request is located in the data handling task and the request arrangement position of the request in the indicated address space. According to the technical scheme provided by the embodiment of the invention, the hardware resource occupation amount of the direct memory access controller can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a direct memory access controller, a data transfer method, and a chip. Background Art

[0002] As the demand for computing power and storage of chips increases, the amount of data that the processor needs to process also increases. Correspondingly, the processor needs more computing power resources to move data. Therefore, in order to improve the data processing performance of the processor, the direct memory access (DMA) controller is used to implement the execution of data moving tasks, unloading the CPU from the task of data moving.

[0003] As data handling performance increases, the hardware resources required by DMA also increase accordingly. Therefore, in this context, how to provide a technical solution to reduce the hardware resource usage of a direct memory access controller has become a technical problem that those skilled in the art need to solve urgently. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a direct memory access controller, a data transfer method, and a chip to reduce the hardware resource usage of the direct memory access controller.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a direct memory access controller, including: a read controller, a write controller and a request status management module;

[0007] The request status management module is used to record at least the starting address of each address space of the direct memory access controller, and the request identifier of each request that can be processed in each address space, and the request status identifier corresponding to each request identifier, and the starting address of the address space is determined based on the source address and the destination address of the data transfer task;

[0008] The read controller and the write controller configure request status identifiers corresponding to request identifiers of each request according to the execution status of each request for the data transfer task, and the request identifier indicates the address space where each request in the data transfer task is located, and the request arrangement position of the request in the indicated address space.

[0009] In a second aspect, an embodiment of the present invention provides a data transfer method, which is applied to the direct memory access controller described in the first aspect, comprising:

[0010] Get data handling tasks;

[0011] According to the data handling task, the starting address of each address space, the request identifier of each request that can be processed in each address space, and the request status identifier corresponding to each request identifier are recorded in the request status management module of the direct memory access controller, and the starting address of the address space is determined based on the source address and the destination address of the data handling task;

[0012] Execute each request of the data handling task, and configure a request status identifier corresponding to the request identifier of each request according to the execution status of each request of the data handling task;

[0013] The request identifier indicates the address space where each request in the data transfer task is located, and the request arrangement position of the request in the indicated address space.

[0014] In a third aspect, an embodiment of the present invention provides a chip, comprising the direct memory access controller as described in the first aspect.

[0015] A direct memory access controller provided by an embodiment of the present invention includes: a read controller, a write controller and a request status management module; the request status management module is used to record at least the starting address of each address space of the direct memory access controller, and the request identifier of each request that can be processed in each address space, and the request status identifier corresponding to each request identifier, and the starting address of the address space is determined based on the source address and destination address of the data transfer task; the read controller and the write controller configure the request status identifier corresponding to each request identifier according to the execution status of each request of the data transfer task, and the request identifier indicates the address space where each request is located in the data transfer task, and the request arrangement position of the request in the indicated address space.

[0016] It can be seen that the technical solution provided by the embodiment of the present invention, by adding a request status management module in the direct memory access controller, on the one hand, uses the request status management module to record the execution status of each request of the data handling task, thereby avoiding the use of the read controller and the write controller to manage and record the requests executed by each, and can reduce the hardware resources occupied by the read controller and the write controller for managing and recording the execution status of each request; on the other hand, in the embodiment of the present invention, when recording the request execution status of each request, the request status management module only records the starting address of each address space, the request status identifier of each request, and the request identifier, thereby reducing the hardware resources occupied by the request status management module. Moreover, the starting address of the address space recorded in the request status management module is determined according to the source address and the destination address of the data handling task, and the request identifier can indicate the address space where the request is located and the specific location of the request in the address space; therefore, when the direct memory access controller processes each request in the data handling task, the read controller and the write controller can accurately configure the request status identifier of each request according to the starting address of the address space and the request identifier recorded by the request status management module to record the execution status of each request. It can be seen that the direct memory access controller provided by the embodiment of the present invention can enable the request management module to meet the normal working requirements of the direct memory access controller by only recording the starting address, request identifier and request status identifier of the above-mentioned address space. At the same time, since the request status management module does not need to record the addresses of all requests for the data transfer task, it only needs to record the starting address and request identifier of the address space to record the execution status of each request. Therefore, the hardware resource usage of the request management module can be reduced, thereby reducing the hardware resource usage of the direct memory access controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0018] Figure 1 is a schematic diagram of the structure of a direct memory access controller provided by an embodiment of the present invention;

[0019] Figure 2 This is a common structural diagram of a direct memory access controller provided by an embodiment of the present invention;

[0020] Figure 3a yes Figure 2 A schematic diagram of the recorded contents of the first read controller in the structure shown;

[0021] Figure 3b yes Figure 2 A schematic diagram of the recorded contents of the first write controller in the structure shown;

[0022] Figure 4 yes Figure 1 A schematic diagram of a record content of the request status management module in the structure shown;

[0023] Figure 5 is another structural diagram of a direct memory access controller provided by an embodiment of the present invention;

[0024] Figure 6 yes Figure 5 A schematic diagram of the recorded contents of the request status management module of the structure shown;

[0025] Figure 7 It is a flow chart of a data transfer method provided by an embodiment of the present invention;

[0026] Figure 8 It is a schematic diagram of the structure of a chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] As chip storage capacity and bandwidth grow, the CPU (central processing unit) needs to spend more computing resources on data transfer. In order to improve chip performance and unload the CPU from data transfer tasks, direct memory access (DMA) controllers that can implement direct memory access functions have emerged. Direct memory access controllers can receive CPU configuration information and parse the configuration information to obtain data transfer tasks to implement memory data transfer.

[0029] While the DMA controller is being used to move data, the CPU can handle other tasks. After the DMA controller completes the data moving task, it can notify the CPU through an interrupt or status flag, so the CPU only needs to prepare the configuration information of the data moving task and wait for the task to be completed.

[0030] The direct memory access controller can release the CPU from the heavy task of moving data to the memory. At the same time, the direct memory access controller is designed specifically for memory data movement, and it can complete the memory data movement task with better energy efficiency than the CPU.

[0031] Since the direct memory access controller inevitably has access delay when accessing the memory, the direct memory access controller cannot start working before the memory data is read. Therefore, in order to improve the efficiency of the direct memory access controller, the direct memory access controller generally issues multiple read requests to read the memory at the same time to avoid the direct memory access controller being idle due to waiting for the read memory data to return.

[0032] In order to identify the correspondence between the read response, read data, and the issued read request, the direct memory access controller generally maintains a read response queue and a write response queue in the direct memory access controller to record the request information for verifying the received response (read response and write response). At the same time, in order to avoid system congestion due to the read data not being processed in time, the direct memory access controller reserves storage space in the read controller of the direct memory access controller for storing read data before the read request is issued. When the delay of the read data is large or the design bandwidth of the direct memory access controller is large, the direct memory access controller needs to design a large read response queue and read data cache space, which requires a large amount of hardware resources.

[0033] Therefore, how to reduce the hardware resource usage of the direct memory access controller while ensuring the bandwidth performance of the direct memory access controller has become a technical problem that needs to be solved urgently.

[0034] Based on this, an embodiment of the present invention provides a direct memory access controller to solve the above technical problems.

[0035] Please refer to Figure 1 , Figure 1 It is a structural diagram of a direct memory access controller provided by an embodiment of the present invention.

[0036] like Figure 1 As shown, the direct memory access controller 1 includes: a read controller 11, a write controller 12 and a request status management module 13;

[0037] The request status management module 13 is used to record at least the starting address of each address space of the direct memory access controller 1, and the request identifier of each request that can be processed in each address space, and the request status identifier corresponding to each request identifier, and the starting address of the address space is determined based on the source address and destination address of the data transfer task;

[0038] The read controller 11 and the write controller 12 configure request status identifiers corresponding to request identifiers of each request according to the execution status of each request for the data transfer task, and the request identifier indicates the address space where each request in the data transfer task is located, and the request arrangement position of the request in the indicated address space.

[0039] The read controller 11 may execute a read request in a data transfer task, and the write controller 12 may execute a write request in a data transfer task.

[0040] For example, Figure 1 As shown, the read controller 11 can use the read interface module 110 to implement the sending of read requests, the receiving of read data, and the receiving of read responses; the write controller 12 can use the write interface module 120 to implement the sending of write requests and the receiving of write responses.

[0041] Each address space of the direct memory access controller 1 may be a space of each channel for implementing data transfer, wherein the channel may be a working thread of the direct memory access controller.

[0042] In the context of a DMA controller, a "worker thread" generally refers to the internal mechanisms or logic of the DMA controller that are responsible for managing and executing data transfer tasks.

[0043] It should be noted that these "worker threads" are not software threads in the traditional sense, but logic at the hardware level. They automatically perform data transfer tasks according to the design of the direct memory access controller.

[0044] The processable requests are the maximum number of requests that can be transmitted at one time in each address space. This can be determined based on the access delay and the bandwidth design of the direct memory access controller 1. For example, the processable requests may be 256, that is, a maximum of 256 requests can be transmitted at one time in one address space. Therefore, the size of the request space that can be covered by the content recorded by the request status management module 13 is equal to the maximum space that can be occupied by the processable requests of each address space of the direct memory access controller 1, thereby meeting the working requirements of the direct memory access controller 1.

[0045] The data transfer task is issued by the processor. The data transfer task can carry the source address and destination address of the data to be transferred and the amount of data to be transferred (data transfer amount), so as to determine the address space recorded in the request status management module 13 when executing the data transfer task, as well as the execution status of each request in the address space.

[0046] The request status management module 13 provides an implementation basis for recording the entire address space of the direct memory access controller 1 and the specific conditions of the requests processed by each address space. Among them, for the convenience of subsequent use, the request status management module 13 uses a request identifier to record which address space the request is executed by, because there are multiple requests that can be processed in an address space, so the request identifier is further used to indicate the specific arrangement position of the request in the address space indicated by it. In other words, there is a one-to-one correspondence between the request identifier and the request, and at the same time, a request status identifier is provided for each request identifier in the request status management module 13 to facilitate recording the execution status of the request determined by the request identifier. The starting address of the address space can make it so that it does not affect the execution of the data transfer task by the direct memory access controller 1. The request status management module 13 obtained based on the above-mentioned functional design can meet the use of the direct memory access controller 1, and at the same time, record the execution status of each request with a smaller hardware resource occupation.

[0047] When using the direct memory access controller 1 to perform a data transfer task, the configuration management module of the direct memory access controller 1 (discussed in detail below) can configure the request status management module 13 based on the data transfer task according to the specific transfer situation of the data transfer task, such as the data transfer volume and the source address and destination address of the transferred data, and complete the initialization of the request status management module 13, so that the read controller and the write controller can subsequently configure the request status identifier recorded in the request status management module 13 according to the execution situation of each request of the data transfer task, combined with the starting address of the address space and the request identifier.

[0048] Since the number of requests that can be processed by each address space of the direct memory access controller 1 can be known in advance according to the design requirements, that is, known, the size of the request space that can be covered by each address space can be determined, and the request status management module 13 records the execution status of the requests in each address space, so the starting address of each address space can be determined according to the source address and destination address of the data transfer task.

[0049] For example, the size of the request space that can be covered by each address space is 128KB, the data transfer amount of the data transfer task is 192KB, the source address is H00000000, and the destination address is H01000000, where H represents hexadecimal.

[0050] First, two address spaces allocated for the data transfer task are determined based on the data transfer volume of 192KB. The starting addresses of the first address space include: a starting read address directly determined based on the source address: H00000000, and a starting write address directly determined based on the destination address: H01000000.

[0051] The starting addresses of the second address space include: the starting read address obtained after an interval of 128KB (the requested space size that can be covered by the first address space) at the source address H00000000: H00020000, and the starting write address obtained after an interval of 128KB at the destination address H00000000: H01020000.

[0052] Among them, when calculating the starting address of the second address space, 128KB can be first converted into bytes (Byte), 128KB=128*1024B=13072B, and then 13072B is converted into hexadecimal: 20000. Since the source address is represented in an eight-bit format, the remaining bits are filled with "0" to obtain the starting address determined based on the source address in the second address space: H00020000.

[0053] Since the source address and destination address of the data handling task are determined according to the hardware system where the processor is located, for example, in a 64-bit system, the data length of the source address and the destination address is 64 bits, and in a 32-bit system, the data length of the source address and the destination address is 32 bits. Therefore, in the request status management module 13, only the starting address determined based on the source address and the destination address of each address space of the data handling task is recorded, and the request arrangement position of the request in the address space indicated by the request identifier of the request is combined, and the address of the request can be calculated without recording the addresses of all requests of the data handling task, thereby reducing the hardware resource usage of the request status management module 13.

[0054] The read controller (RDMA) 11 and the write controller (WDMA) 12 can configure the request status identifier corresponding to the request identifier in the request status management module 13 according to the execution status of their respective requests for data transfer tasks. Therefore, the read controller 11 and the write controller 12 can avoid using a large amount of hardware resources to record and manage requests in order to ensure the accuracy of request processing.

[0055] Please refer to Figure 2 , Figure 3a and Figure 3b , Figure 2 is a common structural diagram of a direct memory access controller provided by an embodiment of the present invention, Figure 3a yes Figure 2 A schematic diagram of a recorded content of the first read controller in the structure shown, Figure 3b yes Figure 2 A schematic diagram of recorded contents of the first write controller in the structure shown.

[0056] like Figure 2As shown, in a direct memory access controller, it usually includes a first configuration management module 01, a first data processing module 02, a first read controller (RDMA) 03 and a first write controller (WDMA) 04. The first configuration management module 01 can receive the configuration information of the CPU, parse the configuration information, and manage the operation of the entire direct memory access controller based on the data handling task obtained after the parsing. For example, it manages the direct memory access controller to start and end work, provides the first data processing module 02, the first read controller 03 and the first write controller 04 with the information required for operation, and exchanges status information with the CPU.

[0057] The first data processing module 02 can perform specified processing on the read data (memory data), such as performing CRC check on the read data.

[0058] The first read controller 03 is responsible for executing read requests in data transfer tasks, such as issuing read requests to read data from the address specified by the processor's data transfer task (starting from the source address until the address satisfies the data transfer amount of the data transfer task).

[0059] The first write controller 04 is responsible for executing write requests in data transfer tasks, for example, issuing write requests to write the read data to the address specified by the processor's data transfer task (starting from the destination address until the address satisfies the data transfer amount of the data transfer task).

[0060] The address and data length of the request (read request and write request) are obtained by the first configuration management module 01 by parsing the configuration information of the CPU.

[0061] Since there is inevitably access delay when the direct memory access controller accesses the memory (including data path delay within the system and internal delay of the memory, etc.), in order to ensure the bandwidth performance of the direct memory access controller, the first read controller 03 and the first write controller 04 will simultaneously issue multiple read requests and write requests.

[0062] Therefore, in order to be able to check the execution of each request, such as Figure 3a As shown, a read response queue with a depth of N and a read data cache with a depth of N need to be maintained in the first read controller 03 to store various read data, wherein the read response queue will record the address of each read request, the tag number of the read request, the priority and other information, and the depth N is the maximum number of read requests that can be issued simultaneously.

[0063] like Figure 3b As shown, the first write controller 04 needs to maintain a write response queue with a depth of M, in which the address of each write request, the mark number of the write request and other information are recorded. The depth M is the maximum number of write requests that can be issued simultaneously.

[0064] M and N are, for example, the maximum number of requests that can be processed by each address space as mentioned above, 256.

[0065] Therefore, in a commonly used direct memory access controller, the space of hardware resources that needs to be allocated for the read response queue and the write response queue in the first read controller 03 and the first write controller 04 can be: the number of requests that can be processed by each address space * the size of the request space that can be covered by each address space (the amount of read data carried by each request * the number of requests that can be processed by each address space). And it is necessary to allocate a read data cache of the same size as the read response queue in the first read controller 03.

[0066] Therefore, in order to meet the increasing data transfer volume in the data transfer task in the commonly used direct memory access controller, the corresponding hardware resources required in the first read controller 03 and the first write controller 04 are also increasing.

[0067] In the embodiment of the present invention, the request status management module 13 is used to manage and maintain the execution status of each request in the data transfer task, so that it is no longer necessary to allocate a large amount of hardware resources to the read controller 11 and the write controller 12 to maintain the execution status of the read request and the write request.

[0068] At the same time, since the request status management module 13 records the starting address of each address space, there is no need to record the address of each request in the data transfer task, and the request status identifier is used to indicate the execution status of each request, thereby reducing the space size of the hardware resources required by the request status management module 13.

[0069] In order to correctly execute the data transfer task, the request status identifier of each request is recorded. The request identifier is also recorded in the request status management module 13. Based on the request identifier and the starting address of the address space, the address space where the request is located, the request arrangement position in the address space and the request address of the request can be accurately determined, thereby ensuring the reliable execution of the data transfer task.

[0070] It can be seen that the technical solution provided by the embodiment of the present invention, by adding a request status management module 13 in the direct memory access controller 1, on the one hand, uses the request status management module 13 to record the execution status of each request of the data transfer task, thereby avoiding using the read controller 11 and the write controller 12 to manage and record the requests executed by each, and can reduce the hardware resources occupied by the read controller 11 and the write controller 12 for managing and recording the execution status of each request; on the other hand, in the embodiment of the present invention, the request status management module 13 only records the starting address of each address space, the request status identifier of each request and the request identifier when recording the request execution status of each request, thereby reducing the hardware resources occupied by the request status management module 13. Moreover, the starting address of the address space recorded in the request status management module 13 is determined according to the source address and the destination address of the data handling task, and the request identifier can indicate the address space where the request is located and the specific location of the request in the address space; therefore, when the direct memory access controller 1 processes each request in the data handling task, the read controller 11 and the write controller 12 can accurately configure the request status identifier of each request according to the starting address and the request identifier of the address space recorded by the request status management module 13 to record the execution status of each request. It can be seen that the direct memory access controller 1 provided by the embodiment of the present invention can enable the request management module 13 to meet the normal working requirements of the direct memory access controller 1 when only recording the starting address, request identifier and request status identifier of the above-mentioned address space; at the same time, since the request status management module 13 does not need to record the addresses of all requests of the data handling task, only recording the starting address and request identifier of the address space, the execution status of each request can be recorded, so the hardware resource occupation of the request management module 13 can be reduced, thereby reducing the hardware resource occupation of the direct memory access controller.

[0071] In one embodiment, in order to accurately record the execution status of each request and reduce the hardware resource usage of the request status management module 13, each request of the data handling task includes: a read request for reading data sequentially from a source address, and a write request for writing the read data sequentially from a destination address; the starting address includes a starting read address and a starting write address; the request identifier includes a request identifier of a read request and a request identifier of a write request, which is composed of a space address number of an address space and a number of a request arrangement position; the request status identifier includes a set of read request issuance identifiers, a read request completion identifier, a write request issuance identifier, and a write request completion identifier;

[0072] The read request and the write request for completing the data transfer task are a group of requests, and the request identifiers of the read request and the write request in the group of requests are the same.

[0073] The data transfer task carries the source address of the data transfer and the destination address of the data transfer, and includes the data transfer amount to be transferred by the task. Therefore, when the direct memory access controller 1 executes the data transfer task, it can start from the source address, read the data of the data transfer amount in sequence, and then write the read data in sequence according to the destination address, thereby completing the execution of the data transfer task.

[0074] To facilitate recording the execution status of each request, the request execution status of a group of requests is recorded in each address space. Since the data transfer task is to transfer data from one memory (source address) to another memory (destination address), the data transfer process includes two parts: reading from the source address and writing to the destination address. The read request and write request that complete the transfer of data are called a group of requests.

[0075] In a group of requests, the read request and the write request are located in the same address space (the address space of the address space is the same), and the request arrangement positions in the address space are the same, so the request identifiers are the same.

[0076] Since the read controller 11 and the write controller 12 will issue multiple read requests and write requests at the same time, in order to facilitate the recording of the execution status of each request, each group of requests is recorded as a basis in each address space, and the request status identifier of each request is configured based on the same request identifier of the read request and the write request in each group of requests.

[0077] In the process of executing the data transfer task, the configuration of the request status flag of each group is configured according to the specific execution conditions of the read controller 11 and the write controller 12. In the initial configuration, the request status flags of each request are uniformly configured, for example, all are configured to "0", indicating that neither the read request nor the write request has started to be executed.

[0078] When issuing a read request, the read controller 11 may carry a request identifier in the read request, so that the read controller 11 can determine the read request corresponding to the read data carried in the read response according to the request identifier of the read request carried in the returned read response.

[0079] The read data received by the write controller 12 is synchronously added with a request identifier, so that after issuing a write request, a write request issuance status identifier is configured according to the request identifier. When returning a write response, a write request completion status identifier is configured according to the request identifier of the write request carried in the write response.

[0080] The records of the request status management module 13 can be referred to Figure 4 , Figure 4 yes Figure 1 A schematic diagram of the record contents of the request status management module in the structure shown.

[0081] like Figure 4 As shown, the request status management module 13 records the request execution status of each request according to the number of address spaces of the direct memory access controller 1. It is assumed that the direct memory access controller 1 may include a total of K (determined by the designer based on design requirements) address spaces, and the request status management module 13 records each address space.

[0082] In the request status management module 13, the starting address of each address space and the request identifier of each processable request (composed of the space address number of the address space and the number of the request arrangement position in the address space) can be recorded. In some embodiments, information such as priority can also be recorded.

[0083] When recording each address space, the address space is divided into L request address spaces (L can be determined by the designer) based on the amount of data that each request can carry. Each request address space records the request execution status of a request in the address space. Each request address space contains 4 request status flags, which record the execution status of read requests and write requests, namely, the read request issuance flag, the read request completion flag, the write request issuance flag, and the write request completion flag.

[0084] Figure 4 The figure only shows four request status identifiers corresponding to each request identifier in each address space as an example. When recording the address space, the request status management module 13 also records the starting address and request identifier of the address space.

[0085] It can be seen that the request status management module 13 only records the starting address, 4 request status identifiers, and the request identifier of the processable request for each address space. Therefore, the hardware resource occupancy of the request status management module 13 is relatively low, and the hardware resource occupancy is reduced while managing the request execution status of the read controller 11 and the write controller 12.

[0086] After the request status management module 13 is configured, the read controller 11 and the write controller 12 can execute the data transfer task based on the configuration of the request status management module 13. In one embodiment, the read controller 11 and the write controller 12 configure the request status identifier corresponding to the request identifier of each request according to the execution status of each request for the data transfer task, including:

[0087] The read controller 11 configures a request status identifier corresponding to a request identifier of each read request according to the execution status of each read request of the data handling task;

[0088] Furthermore, the write controller 12 configures a request status identifier corresponding to the request identifier of each write request according to the execution status of each write request of the data transfer task.

[0089] The read controller 11 can detect the request status identifier configured as the second value in the request status management module 13, and then determine the request identifier corresponding to the request status identifier, determine the address of the read request based on the request identifier combined with the starting read address of the address space, and issue a read request carrying the request identifier to the corresponding address to read data.

[0090] The write controller 12 can also detect the request status identifier configured as the second value in the request status management module 13, and then determine the request identifier corresponding to the request status identifier, determine the address of the write request based on the request identifier combined with the starting write address of the address space, and issue a write request carrying the request identifier to write the read data to the address.

[0091] Please continue to refer to Figure 1 In one implementation, the read controller 11 may include a read data cache 111; the read controller 11 configures a request status identifier corresponding to a request identifier of each read request according to the execution status of each read request of the data handling task, including:

[0092] When issuing a read request for the data handling task, configuring a read request issuing identifier to a first value according to a request identifier of the read request;

[0093] And, when a read response is received and it is detected that there is free cache space in the read data cache 111, the read data carried by the read response is stored in the read data cache 111, and the read request completion flag is configured to the first value according to the request flag of the read request carried by the read response.

[0094] The request identifier of the read request may be determined by the address space where the read request is located and the request arrangement position.

[0095] The first value may be "1". When the read controller 11 completes sending of the read request, the read request sending flag is set to "1", indicating that the read request for this position has been sent.

[0096] The read response may carry the read data read based on the read request and the request identifier of the read request. After the read data is stored in the read data cache 111 , the read request completion identifier may be configured as “1”.

[0097] Please continue to refer to Figure 1 , in order to further reduce the hardware resource usage of the direct memory access controller 1, the read controller 11 further includes: a read retransmission management module 112;

[0098] The read retransmission management module 112 is used to discard the read data carried by the read response when detecting that there is no free cache space in the read data cache 111, and configure the read request issuance identifier to a second value according to the request identifier of the read request carried by the read response;

[0099] The cache space of the read data cache 111 is determined based on the amount of data that the read request can carry and the amount of address space.

[0100] The second value may be "0". When the read request issuance flag is "0", it indicates that the read request has not been issued. When the read request completion flag is "0", it indicates that the read request has not been completed.

[0101] When it is determined that the read data cache 111 is full, the read data is discarded through the design of the read retransmission management module 112, and the read request issuance flag corresponding to the request flag of the read request carried in the read response in the request status management module 13 is set to 0. This allows the subsequent read controller 11 to re-execute the read request based on the read request issuance flag configured as "0".

[0102] The use of the read retransmission management module 112 can provide a basis for implementing the read data cache 111 with lower hardware resource usage. Since the read data cached in the read data cache 111 is continuously received by the write controller 12 and written to the corresponding write address. Therefore, in the design with the read retransmission management module 112, the cache space of the read data cache 111 provided by the embodiment of the present invention can be designed with the number of address spaces and the amount of data that can be carried (read) by each read request as the minimum.

[0103] For example, the number of address spaces is 64, and the maximum amount of data that can be carried by each read request (the size of the read data) is 8*512 bits, then the cache space of the read data cache 111 is at least 8*512*64 bits. Of course, in order to ensure the reliable operation of the direct memory access controller, a certain amount of space can be reserved for the read data cache 111 to cope with emergencies. For example, the cache space of the read data cache 111 can be 2*8*512*64 bits.

[0104] Therefore, the design of the read retransmission management module 112 does not need to reserve a large amount of read data cache space in the read controller 11 in advance for each issued read request, thereby reducing the hardware resource usage of the read data cache 111 and greatly saving hardware resources.

[0105] To enable the direct memory access controller 1 to accurately perform the data transfer task of the processor, please continue to refer to Figure 1, the direct memory access controller 1 may further include: a configuration management module 15, configured to receive and parse the configuration information sent by the processor, obtain the parsed data handling task, and configure the request status management module 13 based on the data handling task;

[0106] The read retransmission management module 112 is further configured to send a read overflow error to the configuration management module 15 when detecting that there is no free cache space in the read data cache 111;

[0107] The configuration management module 15 is further used to count the number of times read overflow errors are issued, and adjust the rate at which the read controller 11 issues read requests based on the statistical value of the number of times.

[0108] The configuration management module 15 receives the configuration information of the CPU, and parses the configuration information to obtain a data handling task; the parsed data handling task includes: a source address of the read data, a destination address of the write data, and a data handling amount (data length).

[0109] The configuration management module 15 can configure the request status management module 13 based on the data transfer task, so that the read controller 11 and the write controller 12 can execute the data transfer task according to the configured request status management module 13 .

[0110] The read overflow error may indicate that the read data cache 111 cannot continue to store read data, so that the configuration management module 15 can dynamically adjust the rate at which the read controller 11 sends read requests based on the number of read overflow errors and flexibly adjust the working state of the read controller 11.

[0111] In one implementation, the configuration management module 15 is used to configure the request status management module 13 based on the data handling task, including:

[0112] Determine the amount of address space used according to the data transfer amount of the data transfer task, and determine the starting address of the address space based on the source address and destination address of the data transfer task;

[0113] And, for each determined address space, the request status identifier corresponding to a preset number of request identifiers is configured as a second value, and the preset number corresponds to the data handling amount.

[0114] Since the data handling volume is the amount of data to be handled in the data handling task, the number of requests for executing the corresponding amount of data handling and the number of address spaces used can be determined based on the data handling volume, and then each request identifier in each address space can be obtained.

[0115] During the initial configuration, the read controller 11 and the write controller 12 have not yet started to execute read requests and write requests. Therefore, in order to facilitate the read controller 11 and the write controller 12 to execute data transfer tasks at a clear and unified time, the configuration management module 15 configures the request status management module 13 according to the data transfer task, completes the initialization of the request status management module 13, and configures the request status identifiers corresponding to each determined request identifier to the second value, indicating that the data transfer task has not yet started.

[0116] Subsequently, the read controller 11 and the write controller 12 may accurately execute the data transfer task according to the initialization configuration of the request status management module 13 .

[0117] The data handling amount varies according to the data handling tasks, so the number of requests for the corresponding data amount to be handled is also different, and the number of address spaces is also different. One or more address spaces are allocated in the request state management module 13 according to the data handling amount of the data handling task, and the starting address of each address space is determined according to the source address and destination address in the data handling task. When the data handling amount in the handling task is less than the number of request identifiers preset as L in the address space, the four request state identifiers corresponding to the redundant request identifiers are all set to the first value (e.g., "1"), and the four request state identifiers corresponding to the remaining request identifiers that need to be used are all set to the second value (e.g., "0").

[0118] For example, take the data transfer amount of the data transfer task described in the above embodiment as 192KB, and the size of the space that can be covered by the address space as 256*8*512=128KB.

[0119] When the data transfer volume is 192KB, two address spaces of 128KB in size are required, wherein the second address space uses 192-128=64KB, that is, half of the space of the second address space is used.

[0120] When determining each request status identifier in the two determined address spaces, all the spaces in the first address space are to be used, and each request status identifier corresponding to all the request identifiers in the first address space is configured as the second value. Since only half of the space size is used in the second address space, the request status identifier corresponding to each request identifier in the first half of the space is configured as the second value, and the remaining request status identifiers are configured as the first value, so that the read controller 11 and the write controller 12 can accurately execute each request.

[0121] In order to flexibly and reliably adjust the rate at which the read requests of the read controller 11 are issued, in one embodiment, the write controller 12 is further configured to issue an idle state signal when it is determined that the idle time during which the write request is not executed exceeds a preset time;

[0122] The configuration management module 15 is further used to count the number of times read overflow errors are issued, and adjust the rate at which the read controller 11 issues read requests based on the statistical value of the number of times issued, including:

[0123] Counting the number of times read overflow errors are issued within the preset time, and determining a rate adjustment level based on the statistical value of the number of times issued, so as to slow down the rate at which the read controller 11 issues read requests based on the rate adjustment level;

[0124] The configuration management module 15 is further configured to increase the rate at which the read controller 11 issues read requests when no read overflow error is received within a preset time or when the idle state signal is received.

[0125] The preset time may be a predetermined unit time, such as 10ms. The number of read overflow errors received within the preset time may reflect the cache space of the read data cache 111. Therefore, the greater the number of read overflow errors received by the configuration management module 15 within the preset time, the higher the adjustment level, thereby adjusting the sending rate of the read controller 11 to be slower.

[0126] If the configuration management module 15 does not receive a read overflow error within the preset time, it means that there is enough cache space in the read data cache 111, so the rate of issuing read requests of the read controller 11 can be increased, thereby realizing flexible adjustment of the working state of the read controller 11.

[0127] The configuration management module 15 may also receive a status signal from the write controller 12. When the write controller 12 does not execute a write request within a preset time, it indicates that the write controller 12 is in an idle state. Therefore, the write controller may send an idle state signal to the configuration management module 15, so that the configuration management module 15 speeds up the rate at which the read requests of the read controller 11 are issued based on the received idle state signal.

[0128] In one implementation, when the write controller 12 sends an idle state signal, a signal line may be drawn from the write controller 12, and the idle state signal may be fed back directly to the configuration management module 15 based on the drawn signal line. Of course, in other implementations, the idle state signal may also be fed back to the configuration management module 15 through a status register used inside the write controller 12.

[0129] To facilitate the work of writing controller 12, please continue to refer to Figure 1 , the direct memory access controller 1 may further include: a data processing module 14, configured to transmit the read data read by the read controller 11 to the write controller 12;

[0130] The write controller 12 configures a request status identifier corresponding to a request identifier of each write request according to the execution status of each write request of the data transfer task, including:

[0131] When the read data is received, a write request is issued, and according to a request identifier of the read request corresponding to the read data, the write request issuance identifier is configured as a first value;

[0132] When a write response is received, the write request completion flag is configured as a first value according to the request flag of the write request carried in the write response.

[0133] Since when a data is transferred, i.e., a group of requests, the request identifier of the write request is the same as the request identifier of the read request, and the read data received by the write request is the data read by the read request in the group of requests, therefore, the request identifier of the read request corresponding to the read data can be directly used as the request identifier of the write request, thereby configuring the write request issuance identifier to be the first value, and the first value can be "1", indicating that the write request has been issued.

[0134] After receiving the write response, the write controller 12 sets the write request completion flag to "1" according to the request flag of the write request carried in the write response, indicating that the write request has been executed.

[0135] To ensure the correct execution of the write request, in one embodiment, the write controller 12 is configured to configure the write request completion flag to a first value according to the request flag of the write request carried in the write response when receiving the write response, including:

[0136] When it is determined that the status of the received write response is successful, the read data is successfully written into the destination address, and the write request completion flag is configured as the first value.

[0137] The status of the write response can indicate whether the read data is written successfully. Therefore, when the status of the write response is determined to be successful, it can be determined that the read data has been successfully written to the destination address. At this time, the write request completion flag can be configured to the first value, indicating that the execution of the write request has been successfully completed.

[0138] Since there is a situation where a write request fails, in one embodiment, the write controller 12 is also used to issue an error status signal when it is determined that the status of the received write response is a failure, and configure the write request completion flag, the write request issuance flag, the read request completion flag and the read request issuance flag to a second value according to the request flag of the write request carried by the write response.

[0139] Since the write request execution fails, it means that the data transfer of this group of requests is unsuccessful, so it needs to be re-executed. In order to facilitate the read controller 11 and the write controller 12 to re-execute the group of requests, the four request status identifiers under the request identifier of this group of requests can be configured as the second value based on the request identifier of the write request carried by the write response, so as to prompt the read controller 11 and the write controller 12 that the regrouped request belongs to the unexecuted request, so that it can be executed again.

[0140] In one implementation, the configuration management module 15 is further configured to send a data handling task processing completion signal when detecting that the request status identifiers corresponding to the request identifiers recorded by the request status management module 13 are all configured as the first value.

[0141] In the request status management module 13, when each request status identifier is configured as the first value, it means that the data transfer of each group of requests has been completed, that is, the execution of the data transfer task has been completed, and the configuration management module 15 is a module that interacts with the processor. Therefore, the configuration management module 15 can send a data transfer task processing completion signal to the processor to prompt the processor that the data transfer task has been completed.

[0142] In one implementation, the request status management module 13 is further configured to record the request processing priority corresponding to each request identifier.

[0143] The data processing module 14 can refer to Figure 1 , connecting the read controller 11 and the write controller 12, and used to realize data transmission between the read controller 11 and the write controller 12.

[0144] The record of request processing priority can meet the execution requirements of the request.

[0145] To facilitate understanding of the use of the direct memory access controller 1 provided in the embodiment of the present invention, the following is combined with Figure 5 and Figure 6 Provide explanation. Figure 5 is another structural diagram of a direct memory access controller provided by an embodiment of the present invention, Figure 6 yes Figure 5 A schematic diagram of the recorded contents of the request status management module of the structure shown.

[0146] It is assumed that the direct memory access controller 1 can support up to 64 independent channels (i.e., 64 address spaces), and each address space can process 256 requests. The direct memory access controller 1 is composed of a configuration management module 15, a data processing module 14, a read controller 11 (RDMA), a write controller 12 (WDMA), and a request status management module 13.

[0147] like Figure 5As shown, the configuration management module 15 communicates with the CPU through a slave interface (AXI, Advanced Xtensible Interface) with a data width of 32 bits. The CPU sends configuration information of the data transfer task to the configuration management module 15, and the configuration management module 15 feeds back the execution status of the data transfer task to the CPU through an interrupt.

[0148] RDMA and WDMA send requests (read requests and write requests) to the memory through the master interface (AXI) with a data width of 512 bits respectively. Each request can support a maximum data transfer volume (i.e., the amount of data that can be carried) of 8*512 bits. The RDMA internal cache space is at least 64*8*512 bits of read data cache 111, and of course, the preferred cache space can be 2*64*8*512 bits.

[0149] The direct memory access controller 1 can issue up to 64*256 read requests at a time, and each read request can read 8*512 bits of data. Figure 6 As shown, the request status management module 13 can record the execution status of each request in the 64 address spaces.

[0150] Among them, each address space can record the execution status of 256 requests (processable requests). Based on the above content, it can be known that each request can carry a maximum of 8*512 / 8=512B of data. Therefore, each address space can cover a request space size of (256*8*512) / 8=128KB, and the request status management module 13 can simultaneously record the execution status of requests corresponding to a maximum space size of (128KB*64) / 1024=8MB. Since the request status management module 13 only needs to record the starting address of the address space (for example, the starting read address 32 bits and the starting write address 32 bits determined based on the source address and the destination address of the data handling task), the priority (for example, 2 bits), the request identifier (the address space address number + the request arrangement position number, for example, 13 bits) and the request status identifier (4*256=1024 bits) when recording each address space, it can be obtained that the space size of 32+32+2+13+1024=1103 bits is only required to record each address space. Therefore, the space size required for the entire request status management module 13 to record all address spaces can be calculated as: 1103*64=70592 bits.

[0151] It can be seen that the hardware resources occupied by the request status management module 13 and the read data cache in the embodiment of the present invention are: 70592 bits + 64*8*512*2 bits = 594880 bits.

[0152] Compared to Figure 2 and Figure 3a as well as Figure 3b The hardware resources occupied by using the read controller and write controller to maintain each request are significantly reduced. For ease of understanding, the calculation process of the hardware resources occupied by the read data cache in the read controller is used as an example to illustrate:

[0153] The hardware resources occupied by the read data cache = (the number of requests that can be processed 256) * (the maximum amount of data that can be transmitted for each request (8*512 bits)) * (the number of address spaces 64) = 67108864 bits.

[0154] Figure 2 and Figure 3a as well as Figure 3b The first read controller also includes a read response queue equal to the hardware resources occupied by the read data cache, and the first write controller also includes a write response queue for maintaining write requests. Therefore, when the hardware resources occupied by the read data cache are much greater than the hardware resources occupied by the direct memory access controller provided in the embodiment of the present invention, Figure 2 and Figure 3a as well as Figure 3b The hardware resources occupied by the direct memory access controller shown are obviously high, so the direct memory access controller provided by the embodiment of the present invention can reduce the occupation of hardware resources while ensuring its normal operation.

[0155] Continue with Figure 5 Taking the structure shown as an example, when the CPU configuration information requires direct memory access controller 1 to execute a data transfer task of transferring a segment of 192KB of data, the source address of the data transfer task is H00000000 (H represents hexadecimal) and the destination address is H01000000.

[0156] The configuration management module 15 receives and analyzes the configuration information to obtain a data handling task. Since the data handling amount of the data handling task is 192KB and the space size that can be covered by one address space is 128KB, the data handling task is allocated to two address spaces.

[0157] Among them, the starting read address assigned to the first address space is H00000000, the starting write address is H01000000, and the 4-bit request status flags corresponding to the request identifiers of the 256 requests are all set to the second value "0". The starting read address assigned to the second address space is: H00000000+128KB=H00020000, the starting write address is: H01000000+128KB=H01020000, the 4-bit request status flags corresponding to the first 128 request identifiers are all set to the second value "0", and the 4-bit request status flags corresponding to the last 128 request identifiers are all set to the first value "1".

[0158] The following describes the execution of the read controller 11 and the write controller 12 by taking the ninth request group of the first address space as an example.

[0159] The read controller 11 detects the request status management module 13 and finds that the read request corresponding to the read request of the 9th request group has a read request issuance identifier of 0, so it prepares to issue the read request. The address of the read request is H00000800 (starting from the starting read address, calculate the address after the number of the request arrangement position: H00000000+H800). The length of the read request can be 256B, and the request identifier of the read request is expressed as H09 (space address number 0 of the address space + number 9 of the request arrangement position).

[0160] After issuing a read request, the read controller 11 sets the read request issuance flag to "1". When the read controller 11 receives a read response with a request flag of H09, if there is at least 256B of cache space left in the read data cache 111, the read response is received, the read data carried by the read response is stored in the read data cache 111, and the read request completion flag is set to 1. If there is less than 256B of cache space left in the read data cache 111, the read request is discarded, and its read request issuance flag is set to "0", and a read overflow error is issued to the configuration management module 15, waiting for the subsequent execution of the read request.

[0161] When the write controller 12 receives the read data with the identification number H09, the query request status management module 13 obtains the information of the corresponding write request, and calculates the address of the write request H01000800, and the write controller 12 issues a write request to the memory and sets the write request issuance flag to "1". When the write controller 12 receives the write response with the request identification number H09, the corresponding write request completion identifier is set to "1", and if the status of the write response is an error, an error status signal is reported to the configuration management module 15.

[0162] The configuration management module 15 counts the number of read overflow errors within a preset time each time it receives a read overflow error, and reduces the sending rate of the read request of the read controller 11 by 20% each time it receives a read overflow error.

[0163] If no read overflow error is received (ie, there is free cache space in the read data cache), the sending rate of the read request of the read controller 11 is increased by 20%.

[0164] The preset time may be 10 ms. That is, the time interval for the configuration management module 15 to adjust the sending rate of the read request of the read controller 11 is not shorter than 10 ms.

[0165] When the configuration management module 15 queries the request status management module 13 and finds that the request status flags of each request in the two recorded address spaces are all set to "1", it means that the data transfer task is completed. The configuration management module 15 notifies the CPU through an interrupt that the data transfer task has been completed.

[0166] An embodiment of the present invention further provides a data transport method, which is applied to the direct memory access controller as described in any of the above embodiments.

[0167] Please refer to Figure 7 , Figure 7 It is a flow chart of a data transfer method provided by an embodiment of the present invention.

[0168] like Figure 7 As shown, the method comprises the following steps:

[0169] Step S101, obtaining a data transfer task.

[0170] The data handling task is obtained by parsing the configuration information of the processor.

[0171] Step S102, according to the data handling task, configure the start address of each address space, the request identifier of each request that can be processed in each address space, and the request status identifier corresponding to each request identifier recorded in the request status management module of the direct memory access controller.

[0172] The starting address of the address space is determined based on the source address and destination address of the data transfer task.

[0173] Step S103, executing each request of the data transfer task, and configuring a request status identifier corresponding to the request identifier of each request according to the execution status of each request of the data transfer task.

[0174] The request identifier indicates the address space where each request in the data transfer task is located, and the request arrangement position of the request in the indicated address space.

[0175] In one embodiment, each request in the data handling task includes: a read request for sequentially reading data starting from a source address, and a write request for sequentially writing the read data starting from a destination address; the starting address includes a starting read address and a starting write address; the request identifier includes a request identifier of a read request and a request identifier of a write request, which is composed of a space address number of an address space and a number of a request arrangement position; the request status identifier includes a set of read request issuance identifiers, a read request completion identifier, a write request issuance identifier, and a write request completion identifier;

[0176] The read request and the write request for completing the data transfer task are a group of requests, and the request identifiers of the read request and the write request in the group of requests are the same.

[0177] Optionally, step S103 may include:

[0178] For the execution status of each read request of the data handling task, a request status identifier corresponding to the request identifier of each read request is configured;

[0179] And, for the execution status of each write request of the data transfer task, a request status identifier corresponding to the request identifier of each write request is configured.

[0180] Optionally, configuring the execution status of each read request of the data handling task with a request status identifier corresponding to the request identifier of each read request includes:

[0181] When issuing a read request for the data handling task, configuring a read request issuing identifier to a first value according to a request identifier of the read request;

[0182] And, when a read response is received and free cache space is detected, the read data carried by the read response is stored, and the read request completion flag is configured as a first value according to the request flag of the read request carried by the read response.

[0183] Optionally, configuring the execution status of each write request of the data handling task with a request status identifier corresponding to the request identifier of each write request includes:

[0184] When the read data is received, a write request is issued, and the write request issuance flag is configured as a first value according to a request flag of the read request corresponding to the read data;

[0185] When a write response is received, the write request completion flag is configured as a first value according to the request flag of the write request carried in the write response.

[0186] It can be seen that the technical solution provided by the embodiment of the present invention, by adding a request status management module in the direct memory access controller, on the one hand, uses the request status management module to record the execution status of each request of the data handling task, thereby avoiding the use of the read controller and the write controller to manage and record the requests executed by each, and can reduce the hardware resources occupied by the read controller and the write controller for managing and recording the execution status of each request; on the other hand, in the embodiment of the present invention, when recording the request execution status of each request, the request status management module only records the starting address of each address space, the request status identifier of each request, and the request identifier, thereby reducing the hardware resources occupied by the request status management module. Moreover, the starting address of the address space recorded in the request status management module is determined according to the source address and the destination address of the data handling task, and the request identifier can indicate the address space where the request is located and the specific location of the request in the address space; therefore, when the direct memory access controller processes each request in the data handling task, the read controller and the write controller can accurately configure the request status identifier of each request according to the starting address of the address space and the request identifier recorded by the request status management module to record the execution status of each request. It can be seen that the direct memory access controller provided by the embodiment of the present invention can enable the request management module to meet the normal working requirements of the direct memory access controller by only recording the starting address, request identifier and request status identifier of the above-mentioned address space. At the same time, since the request status management module does not need to record the addresses of all requests for the data transfer task, it only needs to record the starting address and request identifier of the address space to record the execution status of each request. Therefore, the hardware resource usage of the request management module can be reduced, thereby reducing the hardware resource usage of the direct memory access controller.

[0187] The present invention also provides a chip, please refer to Figure 8 , Figure 8 It is a schematic diagram of the structure of a chip provided by an embodiment of the present invention.

[0188] like Figure 8 As shown, the chip includes:

[0189] A direct memory access controller 1 as described in any one of the preceding embodiments.

[0190] It can be seen that the technical solution provided by the embodiment of the present invention, by adding a request status management module in the direct memory access controller, on the one hand, uses the request status management module to record the execution status of each request of the data handling task, thereby avoiding the use of the read controller and the write controller to manage and record the requests executed by each, and can reduce the hardware resources occupied by the read controller and the write controller for managing and recording the execution status of each request; on the other hand, in the embodiment of the present invention, when recording the request execution status of each request, the request status management module only records the starting address of each address space, the request status identifier of each request, and the request identifier, thereby reducing the hardware resources occupied by the request status management module. Moreover, the starting address of the address space recorded in the request status management module is determined according to the source address and the destination address of the data handling task, and the request identifier can indicate the address space where the request is located and the specific location of the request in the address space; therefore, when the direct memory access controller processes each request in the data handling task, the read controller and the write controller can accurately configure the request status identifier of each request according to the starting address of the address space and the request identifier recorded by the request status management module to record the execution status of each request. It can be seen that the direct memory access controller provided by the embodiment of the present invention can enable the request management module to meet the normal working requirements of the direct memory access controller by only recording the starting address, request identifier and request status identifier of the above-mentioned address space. At the same time, since the request status management module does not need to record the addresses of all requests for the data transfer task, it only needs to record the starting address and request identifier of the address space to record the execution status of each request. Therefore, the hardware resource usage of the request management module can be reduced, thereby reducing the hardware resource usage of the direct memory access controller.

[0191] Please continue to refer to Figure 8 , the chip may further include:

[0192] The processor 2 is used to send configuration information to the direct memory access controller 1.

[0193] Of course, the processor 2 may also receive a data transfer task processing completion signal returned by the direct memory access controller.

[0194] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0195] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A direct memory access controller, characterized in that: include: Read controller, write controller and request status management module; The request status management module is used to record at least the starting address of each address space of the direct memory access controller, and the request identifier of each request that can be processed in each address space, and the request status identifier corresponding to each request identifier, and the starting address of the address space is determined based on the source address and the destination address of the data transfer task; The read controller and the write controller configure request status identifiers corresponding to request identifiers of each request according to the execution status of each request for the data transfer task, and the request identifier indicates the address space where each request in the data transfer task is located, and the request arrangement position of the request in the indicated address space.

2. The direct memory access controller according to claim 1, wherein: Each request of the data handling task includes: a read request for sequentially reading data starting from a source address, and a write request for sequentially writing the read data starting from a destination address; the starting address includes a starting read address and a starting write address; the request identifier includes a request identifier of a read request and a request identifier of a write request, which is composed of a space address number of an address space and a number of a request arrangement position; the request status identifier includes a set of read request issuance identifiers, a read request completion identifier, a write request issuance identifier, and a write request completion identifier; The read request and the write request for completing the data transfer task are a group of requests, and the request identifiers of the read request and the write request in the group of requests are the same.

3. The direct memory access controller according to claim 2, characterized in that: The read controller and the write controller configure a request status identifier corresponding to the request identifier of each request according to the execution status of each request for the data handling task, including: The read controller configures a request status identifier corresponding to a request identifier of each read request according to the execution status of each read request of the data handling task; Furthermore, the write controller configures a request status identifier corresponding to the request identifier of each write request according to the execution status of each write request of the data transfer task.

4. The direct memory access controller according to claim 3, characterized in that: The read controller includes a read data cache; The read controller configures a request status identifier corresponding to a request identifier of each read request according to the execution status of each read request of the data handling task, including: When issuing a read request for the data handling task, configuring a read request issuing identifier to a first value according to a request identifier of the read request; And, when a read response is received and it is detected that there is free cache space in the read data cache, the read data carried by the read response is stored in the read data cache, and the read request completion flag is configured to a first value according to the request flag of the read request carried by the read response.

5. The direct memory access controller according to claim 4, characterized in that: The read controller also includes: a read retransmission management module; The read retransmission management module is used to discard the read data carried by the read response when detecting that there is no free cache space in the read data cache, and configure the read request issuance identifier to a second value according to the request identifier of the read request carried by the read response; The cache space of the read data cache is determined based on the amount of data that the read request can carry and the amount of address space.

6. The direct memory access controller according to claim 5, characterized in that: Also includes: A configuration management module, used to receive and parse the configuration information sent by the processor, obtain the parsed data handling task, and configure the request status management module based on the data handling task; The read retransmission management module is further configured to send a read overflow error to the configuration management module when detecting that there is no free cache space in the read data cache; The configuration management module is also used to count the number of times read overflow errors are issued, and adjust the rate at which the read controller issues read requests based on the statistical value of the number of times.

7. The direct memory access controller according to claim 6, characterized in that: The configuration management module is used to configure the request status management module based on the data handling task, including: Determine the amount of address space used according to the data transfer amount of the data transfer task, and determine the starting address of the address space based on the source address and destination address of the data transfer task; And, for each determined address space, the request status identifier corresponding to a preset number of request identifiers is configured as a second value, and the preset number corresponds to the data handling amount.

8. The direct memory access controller according to claim 7, wherein: The write controller is further configured to send an idle state signal when it is determined that the idle time during which the write request is not executed exceeds a preset time; The configuration management module is further used to count the number of times a read overflow error is issued, and adjust the rate at which the read controller issues a read request based on the statistical value of the number of times issued, including: Counting the number of times read overflow errors are issued within the preset time, and determining a rate adjustment level based on the statistical value of the number of times issued, so as to slow down the rate at which the read controller issues read requests based on the rate adjustment level; The configuration management module is further used to increase the rate at which the read controller issues read requests when no read overflow error is received within a preset time or when the idle state signal is received.

9. The direct memory access controller according to any one of claims 3 to 8, characterized in that: Also includes: A data processing module, used for transmitting the read data read by the read controller to the write controller; The write controller configures a request status identifier corresponding to a request identifier of each write request according to the execution status of each write request of the data handling task, including: When the read data is received, a write request is issued, and according to a request identifier of the read request corresponding to the read data, the write request issuance identifier is configured as a first value; When a write response is received, the write request completion flag is configured as a first value according to the request flag of the write request carried in the write response.

10. The direct memory access controller according to claim 9, characterized in that: The write controller is configured to configure the write request completion flag to a first value according to a request flag of the write request carried in the write response when receiving the write response, including: When it is determined that the status of the received write response is successful, the read data is successfully written into the destination address, and the write request completion flag is configured as the first value.

11. The direct memory access controller according to claim 10, characterized in that: The write controller is also used to issue an error status signal when it is determined that the status of the received write response is a failure, and configure the write request completion flag, the write request issuance flag, the read request completion flag and the read request issuance flag to a second value based on the request flag of the write request carried by the write response.

12. The direct memory access controller according to claim 11, wherein: The configuration management module is further configured to send a data handling task processing completion signal when detecting that the request status identifiers corresponding to the request identifiers recorded by the request status management module are all configured as the first value.

13. The direct memory access controller according to claim 12, wherein: The request status management module is also used to record the request processing priority corresponding to each request identifier.

14. A data transport method, characterized in that: A direct memory access controller as claimed in any one of claims 1 to 13, comprising: Get data handling tasks; According to the data handling task, the starting address of each address space, the request identifier of each request that can be processed in each address space, and the request status identifier corresponding to each request identifier are recorded in the request status management module of the direct memory access controller, and the starting address of the address space is determined based on the source address and the destination address of the data handling task; Execute each request of the data handling task, and configure a request status identifier corresponding to the request identifier of each request according to the execution status of each request of the data handling task; The request identifier indicates the address space where each request in the data transfer task is located, and the request arrangement position of the request in the indicated address space.

15. The data transfer method according to claim 14, wherein: Each request in the data handling task includes: a read request for sequentially reading data starting from a source address, and a write request for sequentially writing the read data starting from a destination address; the starting address includes a starting read address and a starting write address; the request identifier includes a request identifier of a read request and a request identifier of a write request, which is composed of a space address number of an address space and a number of a request arrangement position; the request status identifier includes a set of read request issuance identifiers, a read request completion identifier, a write request issuance identifier, and a write request completion identifier; The read request and the write request for completing the data transfer task are a group of requests, and the request identifiers of the read request and the write request in the group of requests are the same.

16. The data transfer method according to claim 15, wherein: The executing each request of the data handling task, and configuring a request status identifier corresponding to the request identifier of each request according to the execution status of each request of the data handling task, includes: For the execution status of each read request of the data handling task, a request status identifier corresponding to the request identifier of each read request is configured; And, for the execution status of each write request of the data transfer task, a request status identifier corresponding to the request identifier of each write request is configured.

17. The data transfer method according to claim 16, wherein: The execution status of each read request of the data handling task is configured with a request status identifier corresponding to the request identifier of each read request, including: When issuing a read request for the data handling task, configuring a read request issuing identifier to a first value according to a request identifier of the read request; And, when a read response is received and free cache space is detected, the read data carried by the read response is stored, and the read request completion flag is configured as a first value according to the request flag of the read request carried by the read response.

18. The data transfer method according to claim 16, wherein: The execution status of each write request of the data handling task is configured with a request status identifier corresponding to the request identifier of each write request, including: When the read data is received, a write request is issued, and the write request issuance flag is configured as a first value according to a request flag of the read request corresponding to the read data; When a write response is received, the write request completion flag is configured as a first value according to the request flag of the write request carried in the write response.

19. A chip, characterized in that: include: A direct memory access controller as claimed in any one of claims 1 to 13.

20. The chip according to claim 19, characterized in that Also includes: The processor is configured to send configuration information to the direct memory access controller.

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