Video acquisition and transmission method and device for converting 10-gigabit network to PCIe interface

Abstract

The invention relates to a video acquisition and transmission method and device for converting a 10-gigabit network into a PCIe (Peripheral Component Interconnect Express) interface. The method comprises the following steps: receiving a video stream through a double 10-gigabit network optical module, carrying out protocol analysis and preprocessing through an FPGA (Field Programmable Gate Array), realizing multi-path alternate reading and writing by utilizing DDR3 ping-pong cache, dynamically distributing the video stream to multiple devices through a three-path PCIe 3.0 * 4 interface and an XDMA (Extensible Direct Memory Access), and optimizing the transmission priority in combination with a load state. The device comprises two paths of SFP + optical modules, a Xilinx Virtex7 series FPGA chip (integrated with a 10-gigabit network MAC, a PCIe XDMA IP core and a DDR3 controller), three paths of PCIe 3.0 * 4 interfaces and an external DDR3 memory. The system has the advantages that the double 10-gigabit network input and multi-PCIe channel collaborative architecture breaks through the single-channel bandwidth bottleneck; the intelligent ping-pong cache and the AXI arbitration strategy reduce the data conflict risk; and dynamic bandwidth allocation optimizes real-time performance.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed video acquisition and interface conversion, and in particular to a video acquisition and transmission method and device for converting a 10 Gigabit Ethernet to a PCIe interface. Background Art

[0002] In existing video acquisition and transmission solutions, the measured bandwidth of Gigabit Ethernet is only 800 Mbps, and the theoretical bandwidth of the USB3.0 interface is only 5 Gbps. It is difficult to meet the real-time transmission requirements of 4K video signals, and there are problems such as insufficient bandwidth and low multi-channel data collaboration efficiency. Although 10 Gigabit Ethernet (10GbE) and PCIe interfaces each have high-bandwidth advantages, the existing technology lacks an efficient collaboration mechanism between the two; although 10 Gigabit Ethernet (10GbE) supports 10 Gbps transmission, its native interface cannot directly connect to the PCIe bus of computing devices and relies on complex relay protocol conversion; although the PCIe interface can provide a bandwidth of up to 64 GB / s, traditional video capture cards are limited by the single-channel transmission architecture and it is difficult to process multiple 10 Gigabit Ethernet inputs in parallel; and at present, most FPGA solutions use a single interface (such as only supporting 10 Gigabit Ethernet or PCIe), and do not implement dynamic resource allocation for multiple 10 Gigabit Ethernet inputs and multiple PCIe channel outputs.

[0003] Therefore, there is an urgent need for a solution for video acquisition and transmission from 10 Gigabit Ethernet to a PCIe interface, which is convenient for multi-channel video real-time processing scenarios that require high bandwidth and low latency, such as ultra-high-definition video transmission, AI vision analysis, medical image processing, etc. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides a video acquisition and transmission method for converting a 10 Gigabit Ethernet to a PCIe interface, including the following steps:

[0005] Step S1: Dual-channel 10 Gigabit Ethernet data acquisition: Receive 10 Gigabit Ethernet video streams through two optical modules, extract MAC layer data based on the 10 Gigabit Ethernet IP core embedded in the FPGA, parse the UDP protocol and extract the payload, decode the video stream data packets according to a custom protocol, and verify the packet order and integrity;

[0006] Step S2: Video preprocessing and caching: Perform bit-width conversion and color space conversion on the video stream data in the FPGA, divide the external DDR3 memory into two logical areas for ping-pong caching, and realize the alternating reading and writing of multi-channel video data to avoid data congestion;

[0007] Step S3: Multi-channel PCIe transmission: Synchronously transmit the preprocessed video stream to multiple computing devices through at least three PCIe interfaces using the XDMA method, and dynamically adjust the interrupt frequency and data allocation strategy according to the load status of the computing devices.

[0008] In an embodiment of the present invention, the custom protocol described in step S1 includes a synchronization header, total number of packets, current packet number, packet length, and checksum field, which are used for data packet parsing and integrity verification.

[0009] In an embodiment of the present invention, the data acquisition capture and parsing in step S1 specifically includes the following steps:

[0010] Step 1.1: Specific MAC layer data capture: Establish an external 10 Gigabit Ethernet link by configuring an optical module chip, and receive the MAC layer data stream in AXI-Stream format based on the Xilinx 10GEthernet Subsystem IP core;

[0011] Step 1.2: Specific UDP protocol stack parsing: Extract the IPv4 data packet from the MAC frame payload, verify the integrity of the IP header and obtain the source IP address and protocol type; Strip the UDP header to extract the source port number, data length, and payload;

[0012] Step 1.3: Custom protocol decoding: Parse the payload data according to the custom protocol format, which includes the custom protocol format and pixel data fields; Verify the packet sequence and integrity based on the fields therein.

[0013] In an embodiment of the present invention, the data processing in step S2 specifically includes the following steps:

[0014] Step 2.1: Bit width conversion and color space conversion: Convert the data width of the video data packet to the pixel width through a FIFO buffer to generate a line synchronization signal, a field synchronization signal, and valid data to restore the video timing; And according to the processing requirements of the backend computing device, convert the video data into a standard color space format, where the format includes at least one of RGB, YUV4:2:2, or YUV4:4:4;

[0015] Step 2.2: External memory ping-pong buffering: Allocate independent storage blocks for multi-channel DDR3 memories, and divide dual logical areas (BankA / B) in the physical address. Trigger the logical area switch based on the frame signal (VSYNC) to achieve alternating read and write operations; At the same time, arbitrate the concurrent access requests of multi-channel video data through the AXI Interconnect protocol to avoid storage conflicts.

[0016] In an embodiment of the present invention, the data transmission and distribution in step S3 specifically includes the following steps:

[0017] Step 3.1, PCIe Channel Initialization and XDMA IP Core Configuration: After the device is powered on, the FPGA initializes at least three PCIe 3.0 channels and configures independent XDMA IP cores corresponding to the number of channels; the configuration includes setting the link rate to 8.0 GT / s, the number of channels to x4, and the AXI Memory Mapped mode parameters;

[0018] Step 3.2, Interrupt Triggering and Load Awareness: The FPGA dynamically adjusts the interrupt signal frequency and data allocation priority by reading the GPU utilization rate or memory occupancy rate fed back by the computing device; within the video frame processing cycle, an interrupt signal is generated at the frame frequency to trigger the XDMA driver engine of the computing device to start data transmission;

[0019] Step 3.3, Direct Memory Access and Arbitration: Direct Memory Access (DMA) between 3 XDMA IP cores and the external DDR3 of the FPGA is implemented through the AXI_Stream protocol; a priority strategy is preset in the AXI Interconnect to arbitrate multiple DMA requests and avoid multi-channel data transmission conflicts.

[0020] The present invention also provides a video acquisition and transmission device for converting a 10 Gigabit Ethernet to a PCIe interface, customized based on the video acquisition and transmission method, including:

[0021] 10 Gigabit Ethernet Input Module: Integrating at least two SFP+ optical modules, supporting the 10G BASE-LR / SR standard, the transmit enable (TX_EN) of the optical module is connected to the IO port of the FPGA chip, and the other receive data (RXD) pins are connected to the FPGA GTX bank through high-speed differential signals for configuring the working mode of the optical module and receiving optical signals;

[0022] FPGA Processing Unit: The FPGA processing unit uses an Xilinx Virtex7 series chip, with three independent XDMA IP cores built-in, supporting multi-channel PCIe channel synchronous transmission, and is used to execute any of the above methods;

[0023] PCIe Output Module: It provides three PCIe 3.0×4 interfaces, and the PCIe output module is connected to the XDMA IP core through the PCIe hard core of the FPGA; and the XDMA IP core is connected to the DDR3 controller through the AXI Interconnect module, and a priority strategy is preset to arbitrate multiple DMA requests;

[0024] External memory module: Its configuration includes at least 4GB DDR3 chips, and data caching is achieved through the DDR3 controller of the FPGA. The physical address of DDR3 is divided into two logical banks (BankA / B), and bank switching is triggered by the frame synchronization signal (VSYNC) generated by the FPGA to implement the ping-pong caching mechanism. Multiple channels of video data access DDR3 concurrently through the AXI Interconnect protocol, and the FPGA allocates independent storage blocks to avoid read-write conflicts.

[0025] In an embodiment of the present invention, the status monitoring pins of the optical module (such as the optical power alarm LOS, link status LINK_UP) are connected to the FPGA IO pins to achieve real-time monitoring of the optical signal quality.

[0026] In an embodiment of the present invention, the FPGA processing unit incorporates the following functional modules:

[0027] 10 Gigabit Ethernet MAC IP core: Directly connected to the SerDes interface of the SFP+ optical module, receiving the MAC layer data stream in AXI-Stream format;

[0028] PCIe IP core: Configured with at least three independent XDMA IP cores, respectively bound to three PCIe 3.0×4 physical interfaces;

[0029] DDR3 controller: Connected to the external DDR3 memory through the AXI bus, supporting multi-channel concurrent access.

[0030] In an embodiment of the present invention, the reference clock (REFCLK) and differential signal pair (TX / RX) of each PCIe interface in the PCIe output module implement the physical layer link through the GTX transceiver of the FPGA.

[0031] In an embodiment of the present invention, after the various hardware components are connected, a specific control and status feedback link is formed. The FPGA processing unit communicates with the computing device through the configuration space (BAR space) of the PCIe interface, receiving the load status feedback of the computing device (including GPU utilization rate, memory occupancy rate); dynamically adjusts the interrupt signal frequency according to the feedback, and triggers the XDMA driver engine through the PCIe MSI (Message Signaled Interrupt) mechanism.

[0032] The above technical solutions of the present invention have the following advantages compared with the prior art:

[0033] 1. Dual 10 Gigabit Ethernet and Multi-PCIe Channel Cooperative Architecture: For the first time, it realizes the input of two 10GbE 10 Gigabit Ethernets and the output of three PCIe 3.0 x4s, supports the parallel acquisition and transmission of multiple ultra-high-definition videos (such as 4K@30Hz RGB), and breaks through the bandwidth bottleneck of traditional single-channel transmission.

[0034] 2. Intelligent Cache Mechanism Reduces the Risk of Data Conflict: By dividing the dual logical areas (BankA / B) in the DDR3 physical address and automatically switching the read and write operations through the frame signal (VSYNC), it realizes the alternating storage of multiple video data and avoids read and write conflicts. It uses the AXI Interconnect to achieve the concurrent access of multiple videos to DDR3, and combines the BRAM cache of the FPGA to preprocess the data, reducing the latency of the computing device accessing the external memory.

[0035] 3. Dynamic Bandwidth Allocation Optimizes Real-Time Performance: The FPGA triggers the XDMA driver engine through the interrupt signal according to the load status of the computing device, dynamically allocates the PCIe channel bandwidth, and preferentially transmits video streams with high real-time requirements (such as medical images or AI analysis data).

[0036] 4. It supports the independent transmission of three PCIe interfaces, meeting the differentiated requirements in multi-task scenarios. Description of the Drawings

[0037] In order to make the content of the present invention easier to be clearly understood, the following further details the present invention according to the specific embodiments of the present invention and in combination with the drawings.

[0038] Figure 1 It is the flowchart of the video acquisition and transmission method of the 10 Gigabit Ethernet to PCIe interface in the present invention;

[0039] Figure 2 It is the schematic diagram of the dual-channel 10 Gigabit Ethernet data acquisition process in the present invention;

[0040] Figure 3 It is the schematic diagram of the multi-video preprocessing and caching process in the present invention;

[0041] Figure 4 It is the schematic diagram of the multi-channel PCIe transmission process in the present invention;

[0042] Figure 5 It is the schematic diagram of the video acquisition and transmission device of the 10 Gigabit Ethernet to PCIe interface in the present invention. Detailed Embodiments

[0043] Embodiment 1

[0044] This embodiment provides a video acquisition and transmission method for the 10 Gigabit Ethernet to PCIe interface, including the following steps:

[0045] Step S1: Dual-channel 10 Gigabit Ethernet data acquisition: Receive 10 Gigabit Ethernet video streams through two optical modules, extract MAC layer data based on the 10 Gigabit Ethernet IP core embedded in the FPGA, and parse out UDP payload data through the UDP protocol. Distinguish the payload data of different channels according to the network port number, and then extract video stream data packets according to the self-defined protocol, and verify the packet sequence and integrity.

[0046] Step 1.1: MAC layer data capture: Establish a connection with the external 10 Gigabit Ethernet link by configuring the optical module chip, and then receive the MAC layer data stream in AXI-Stream format output by the IP core based on the Xilinx 10 Gigabit Ethernet Subsystem IP core.

[0047] Step 1.2: UDP protocol stack parsing: Extract IPv4 data packets from the MAC frame payload, verify the integrity of the IP header, and obtain the source IP address and protocol type; strip the UDP header and extract the source port number, data length, and payload.

[0048] Step 1.3: Custom protocol decoding: Parse the payload data according to the custom protocol format (synchronization frame header + total number of packets + current packet number + checksum + pixel data, etc.), extract video stream data packets, and verify the packet sequence and integrity.

[0049] Step S2: Video preprocessing and caching: Perform preprocessing such as bit-width conversion and color space conversion on the video stream data packets in the FPGA, and use an external DDR3 memory to implement ping-pong caching of the video stream data to avoid data congestion.

[0050] Step 2.1: Bit-width conversion and color space conversion. The bit-width conversion is implemented by using a FIFO cache to convert the data width of the video data packet to the pixel width, and generate line and field synchronization signals and valid data, thereby restoring the video timing; the color space conversion converts the video data to the standard color space RGB / YUV4:2:2 / YUV4:4:4 format according to the processing requirements of the backend computing device.

[0051] Step 2.2: External memory ping-pong caching: Mainly implement multi-channel DDR3 storage management. Each channel is allocated an independent storage block, and two logical areas are divided in the DDR3 physical address respectively. Switch the Bank according to the frame signal (VSYNC) to complete the alternating read and write operations; multiple video data access the DDR3 concurrently through the AXI Interconnect to avoid conflicts.

[0052] Step S3: Multi-channel PCIe transmission: Through 3 PCIe 3.0 x4 interfaces, in the XDMA mode, synchronously transmit the preprocessed multi-channel video streams stored in the external DDR3 memory to 3 computing devices.

[0053] Step 3.1, PCIe channel initialization and XDMA IP core configuration: After the device is powered on, the FPGA initializes the PCIe channel and configures 3 independent XDMA IP cores, completing parameter configurations such as link rate 8.0 GT / s, number of channels x4, and AXI MemoryMapped mode.

[0054] Step 3.2 Interrupt triggering and load awareness: The FPGA adjusts the interrupt frequency or data allocation strategy by reading its own processing status (such as GPU utilization rate, memory occupancy rate) fed back by the computing device. Under normal circumstances, an interrupt signal is generated at the video frame frequency. After receiving the interrupt signal, the computing device triggers the XDMA driver engine.

[0055] Step 3.3 Direct memory access and arbitration: The 3 XDMA IPs implement direct memory access (DMA) between the computing device and the external DDR3 of the FPGA through the AXI_Stream protocol. Strategies such as preset priorities are set in the AXI Interconnect to arbitrate multiple requests and avoid multiple request conflicts.

[0056] Specifically, Figure 1 The figure shows the flowchart of the video acquisition and transmission method for a 10 Gigabit Ethernet to PCIe interface. The input interface includes 2 SFP interfaces and 2 optical modules, and the output interface is 3 PCIe interfaces; the optical signal undergoes optoelectronic conversion through the optical module and then enters the FPGA. The MAC layer data is captured through the 10 Gigabit Ethernet IP core; the UDP payload data packet is extracted from the MAC layer data through the UDP protocol stack, and then the payload data is decoded according to the self-defined protocol to recover the extracted video stream data packet; the video stream data packet enters the video preprocessing module, and the data width of the video data packet is converted to the pixel width by using the FIFO line buffer method, and line and field synchronization signals and valid data are generated to recover the video timing; after color space transformation, the ping-pong buffer of multiple videos is realized by using the external DDR3 memory; at the same time, the PCIe channel completes initialization and XDMA IP core configuration, the FPGA senses the load status and adjusts the interrupt sending logic; the computing module receives the interrupt signal and calls the XDMA driver engine, arbitrates multiple requests through the AXI Interconnect, completes direct memory access, and avoids multiple request conflicts, thereby realizing the independent transmission of data to different computing devices through 3 PCIe interfaces.

[0057] Such as Figure 2As shown in the schematic diagram of the dual-channel 10 Gigabit Ethernet data acquisition process, first, the optical module is configured. The main configuration is to enable the optical module for two-way communication requirements and receive the status signal of the optical module simultaneously to determine whether there is an optical signal. After establishing a connection with the external 10 Gigabit Ethernet link, the MAC layer data is obtained through the 10 Gigabit Ethernet IP core embedded in the FPGA, and then the UDP payload data is parsed by the UDP protocol stack. According to the self-defined protocol, the payload data is decoded to restore the extracted video stream data packets, and the order and integrity of the data packets are verified.

[0058] As Figure 3 shown in the schematic diagram of the multi-channel video preprocessing and caching process, video preprocessing mainly realizes the bit-width conversion of pixel data in the FPGA. The data width of the video data packets is converted to the pixel width by using the FIFO line buffer method, and the line and field synchronization signals and valid data are generated to restore the video timing. Then, after color space transformation, it is written into the DDR3. Multi-channel video caching mainly realizes the storage management of multi-channel DDR3. Each channel is assigned an independent storage block, and two logical areas (BankA / B) are divided in the DDR3 physical address respectively. According to the frame end signal (VSYNC), the Bank is automatically switched to complete the alternating read and write operations. Concurrent access is achieved through the AXI Interconnect to avoid conflicts, and the ping-pong caching of multi-channel videos is realized by using the external DDR3 memory.

[0059] As Figure 4 shown in the schematic diagram of the multi-channel PCIe dynamic transmission process, first, after the device is powered on, the FPGA initializes the PCIe channels and configures 3 groups of independent XDMA IP cores to complete the configuration of parameters such as link rate 8.0GT / s, channel number x4, and MMP mode. The FPGA adjusts the interrupt frequency or data distribution strategy by reading its own processing status (such as GPU utilization rate, memory occupancy rate) fed back by the computing device. Under normal circumstances, an interrupt signal is generated at the video frame frequency. After receiving the interrupt signal, the computing device triggers the XDMA driver engine. The 3 XDMA IPs achieve direct memory access (DMA) between the computing device and the external DDR3 of the FPGA through the AXI_Stream protocol. Strategies such as preset priorities are set in the AXI Interconnect to arbitrate multiple requests and avoid conflicts of multiple requests, so as to realize the independent transmission of data from 3 PCIe interfaces to the computing device.

[0060] Embodiment 2

[0061] This embodiment provides a video acquisition and transmission device for converting 10 Gigabit Ethernet to a PCIe interface, customized based on the video acquisition and transmission method, including:

[0062] 10 Gigabit Ethernet Input Module: Integrates two SFP+ optical modules, supporting 10GBASE-LR / SR standards. The optical module uses Zhonghang Optoelectronics HTS3201A-AH-016YY-G, which is a low-power, high-performance single-fiber bidirectional pigtail type optical transceiver module with a transmission distance of 10Km, small size, light weight, and supports hot plugging. The control pins of the optical module are all connected to the FPGA chip, enabling configuration of transceiver functions, optical signal status flags, etc.

[0063] FPGA Processing Unit: Adopts Xilinx Virtex7-690T, with built-in 10 Gigabit Ethernet MAC, PCIe IP core, and DDR3 controller. Using Xilinx's Virtex7-690T, this chip supports configuration of two 10G Ethernet Subsystem IP cores and three PCIe 3.0 Integrated Block IP cores, and can support simultaneous transmission to a maximum of 3 computing devices.

[0064] PCIe Output Module: 3 PCIe 3.0×4 interfaces.

[0065] External Memory: 4GB DDR3, used for multi-channel video frame buffering.

[0066] The control pins of the optical module are all connected to the FPGA chip, enabling functions such as configuration of transceiver functions and monitoring of optical signal status flags.

[0067] The logic layer includes a protocol conversion layer and a data scheduling layer. The protocol conversion layer is, for example, the conversion of MAC layer data protocol to UDP protocol. The data scheduling layer is, for example, the FPGA controls multi-channel video writing to DDR3, and the FPGA drives XDMA to obtain multi-channel video data.

[0068] The hardware composition of this device also includes a power management circuit and an external serial communication circuit.

[0069] Specifically, Figure 5 It is a schematic diagram of the structure of a 10 Gigabit Ethernet to PCIe interface video acquisition and transmission device, mainly integrating two SFP+ optical modules, supporting 10G BASE-SR / LR standards. Additionally, it includes an FPGA chip, a power management unit, a DDR3 external storage chip, and a PCIe interface.

[0070] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation methods. For those of ordinary skill in the art, based on the above description, other different forms of changes or variations can be made. It is not necessary and impossible to enumerate all implementation methods here. And the obvious changes or variations derived therefrom are still within the protection scope of this invention.

Claims

1. A method for video acquisition and transmission from a 10 Gigabit Ethernet to a PCIe interface, characterized in that, It includes the following steps: Step S1: Dual-channel 10 Gigabit Ethernet data acquisition: Receive 10 Gigabit Ethernet video streams through two optical modules, extract MAC layer data based on the 10 Gigabit Ethernet IP core embedded in the FPGA, parse the UDP protocol and extract the payload, decode the video stream data packets according to the custom protocol, and verify the packet sequence and integrity; Step S2: Video preprocessing and caching: Perform bit-width conversion and color space conversion on the video stream data in the FPGA, divide the external DDR3 memory into two logical areas for ping-pong caching, and achieve alternating read and write of multi-channel video data; Step S3: Multi-channel PCIe transmission: Through at least three PCIe interfaces, synchronously transmit the preprocessed video streams to multiple computing devices in the XDMA mode, and dynamically adjust the interrupt frequency and data allocation strategy according to the load status of the computing devices.

2. The video acquisition and transmission method according to claim 1, wherein: The custom protocol described in Step S1 includes a synchronization header, total number of packets, current packet number, packet length, and checksum fields, which are used for packet parsing and integrity verification.

3. The video acquisition and transmission method according to claim 1, characterized in that: Specifically, the data acquisition capture and parsing in Step S1 include the following steps: Step 1.1: Specific MAC layer data capture: Establish an external 10 Gigabit Ethernet link by configuring the optical module chip, and receive the MAC layer data stream in AXI-Stream format based on the Xilinx 10GEthernet Subsystem IP core; Step 1.2: Specific UDP protocol stack parsing: Extract the IPv4 data packet from the MAC frame payload, verify the integrity of the IP header and obtain the source IP address and protocol type; strip the UDP header to extract the source port number, data length, and payload; Step 1.3: Custom protocol decoding: Parse the payload data according to the custom protocol format, including the custom protocol format and pixel data fields; Verify the packet sequence and integrity based on the fields therein.

4. The video acquisition and transmission method according to claim 1, wherein: Specifically, the data processing in Step S2 includes the following steps: Step 2.1: Bit-width conversion and color space conversion: Convert the data width of the video data packet to the pixel width through FIFO caching, generate line synchronization signals, field synchronization signals, and valid data to restore the video timing; and convert the video data to the standard color space format according to the processing requirements of the backend computing device, where the format includes at least one of RGB, YUV4:2:2, or YUV4:4:4; Step 2.2: External memory ping-pong caching: Allocate independent storage blocks for the multi-channel DDR3 memory, divide the physical address into two logical areas, trigger the logical area switch based on the frame signal, and achieve alternating read and write operations; at the same time, arbitrate the concurrent access requests of multi-channel video data through the AXI Interconnect protocol to avoid storage conflicts.

5. The video acquisition and transmission method according to claim 1, wherein: Specifically, the data transmission and allocation in Step S3 include the following steps: Step 3.1, PCIe Channel Initialization and XDMA IP Core Configuration: After the device is powered on, the FPGA initializes at least three PCIe 3.0 channels and configures independent XDMA IP cores corresponding to the number of channels; the configuration includes setting the link rate to 8.0 GT / s, the number of channels to x4, and the AXI Memory Mapped mode parameters; Step 3.2, Interrupt Triggering and Load Awareness: The FPGA dynamically adjusts the interrupt signal frequency and data allocation priority by reading the GPU utilization rate or memory occupancy rate fed back by the computing device; within the video frame processing cycle, an interrupt signal is generated at the frame frequency to trigger the XDMA driver engine of the computing device to start data transmission; Step 3.3, Direct Memory Access and Arbitration: Direct memory access between 3 XDMA IP cores and the external DDR3 of the FPGA is achieved through the AXI_Stream protocol; a priority strategy is preset in the AXI Interconnect to arbitrate multiple DMA requests and avoid multi-channel data transmission conflicts.

6. A video acquisition and transmission device that converts a 10 Gigabit Ethernet to a PCIe interface, customized based on the video acquisition and transmission method of claims 1 to 5, characterized in that, Including: 10 Gigabit Ethernet Input Module: Integrating at least two SFP+ optical modules, the transmit enable of the optical module is connected to the IO port of the FPGA chip, and the receive data pins are connected to the FPGA GTX bank through high-speed differential signals; FPGA Processing Unit: The FPGA processing unit uses a Xilinx Virtex7 series chip and has three independent XDMA IP cores built-in for executing the method described in any one of claims 1-4; PCIe Output Module: It provides three PCIe 3.0×4 interfaces, and the PCIe output module is connected to the XDMA IP core through the PCIe hard core of the FPGA; and the XDMA IP core is connected to the DDR3 controller through the AXI Interconnect module; External Memory Module: Its configuration includes at least 4GB DDR3 chips, and data caching is achieved through the DDR3 controller of the FPGA; the physical address of the DDR3 is divided into two logical areas, and the Bank switching is triggered by the frame synchronization signal generated by the FPGA to implement the ping-pong caching mechanism; multiple video data access the DDR3 concurrently through the AXI Interconnect protocol, and the FPGA allocates independent storage blocks to avoid read-write conflicts.

7. The video acquisition and transmission device according to claim 6, characterized in that: The status monitoring pin of the optical module is connected to the FPGA IO pin.

8. The video acquisition and transmission device according to claim 6, characterized in that: The FPGA processing unit has the following functional modules built-in: 10 Gigabit Ethernet MAC IP Core: Directly connected to the SerDes interface of the SFP+ optical module to receive the MAC layer data stream in AXI-Stream format; PCIe IP Core: Configuring at least three independent XDMA IP cores, respectively bound to three PCIe 3.0×4 physical interfaces; DDR3 Controller: Connected to the external DDR3 memory through the AXI bus, supporting multi-channel concurrent access.

9. The video acquisition and transmission device according to claim 6, wherein: The reference clock and differential signal pair of each PCIe interface in the PCIe output module implement the physical layer link through the GTX transceiver of the FPGA.

10. The video acquisition and transmission device according to claim 6, wherein: After the included various hardware components are connected, a specific control and status feedback link is formed. Among them, the FPGA processing unit communicates with the computing device through the configuration space of the PCIe interface, receives the load status feedback of the computing device, dynamically adjusts the interrupt signal frequency according to the feedback, and triggers the XDMA driver engine through the PCIe MSI mechanism.

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