Safe encryption and decryption circuit

Abstract

The invention discloses a safe encryption and decryption circuit, which comprises a safe storage array, a time sequence control module, a key line, a sensitive amplifier array, a phase inverter array, a switch control array, a write-in circuit and two refresh circuits, the secure storage array is used for storing to-be-encrypted data, XOR data and decrypted data and encrypting and decrypting the data, the secure storage array is realized by adopting a hardware multiplexing technology, the hardware overhead is reduced, when a key line needs to generate a key, the key line generates the key through the control of the time sequence control circuit, and the security of the key line is improved. When the key line is not needed, the time sequence control circuit is used for controlling power-off and zero clearing, and the key line adopts a dynamic key generation technology, so that the risk behavior of key storage is avoided, and the safety performance is relatively high; the method has the advantages of being small in hardware overhead and high in safety performance.

Description

Technical Field

[0001] The invention relates to a security encryption and decryption circuit, and in particular to a security encryption and decryption circuit. Background Art

[0002] Currently, a large amount of private data collected by the Internet of Things faces the risk of unauthorized access and theft. In order to improve the security of IoT data, researchers designed a secure encryption and decryption circuit.

[0003] The existing widely used security encryption and decryption circuit adopts the AES encryption circuit structure. In addition to the plaintext to be encrypted, the security encryption and decryption circuit also needs to input a 128-bit AES key, so the key needs to be specially stored and managed. The process is complicated and the key can be stolen by attackers at the slightest loophole, so the security is not high. In addition, when performing encryption and decryption operations, the plaintext and the key need to be XORed and decrypted, which requires additional hardware modules for XOR encryption and decryption operations, resulting in higher overall hardware costs. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a security encryption and decryption circuit with low hardware overhead and high security performance.

[0005] The technical solution adopted by the present invention to solve the above technical problems is: a secure encryption and decryption circuit, comprising a secure storage array, a timing control module, a key row, a sensitive amplifier array, an inverter array, a switch control array, a write circuit and two refresh circuits, the two refresh circuits are respectively referred to as a first refresh circuit and a second refresh circuit, the secure storage array is implemented by hardware multiplexing technology to reduce hardware resource overhead; when encryption is required, first, the timing control module controls the second refresh circuit to output a clear signal to refresh the secure storage array, and clears the state of the secure storage array, and then, when the data to be encrypted is transmitted to the write circuit, the write circuit, under the control of the timing control module, converts the data to be encrypted into two data with opposite phases and outputs them to the secure storage array, and the secure storage array stores the two data with opposite phases outputted thereto by the write circuit; then, the timing control module controls the first refresh circuit to output a precharge signal on the one hand to precharge the secure storage array, and controls the second refresh circuit to output a clear signal on the other hand to clear the key row Refresh, clear the state of the key row, then the timing control module controls the key row to generate a pair of keys with opposite phases and transmit them to the switch control array, the switch control array transmits the pair of keys transmitted by the key row to the secure storage array, the secure storage array performs an XOR operation on the pair of keys currently transmitted by the key row and two data with opposite phases already stored therein to obtain an XOR value of one bit, and transmits the XOR value to the sensitive amplifier array, the sensitive amplifier array performs an XOR operation on the pair of keys currently transmitted by the key row to the secure storage array under the timing control module. Under the control of the module, the XOR value outputted thereto is shaped, and the shaped XOR value is transmitted to the inverter array, the inverter array inverts the shaped XOR value, and the XOR value with opposite phase is transmitted to the switch control array, the switch control array transmits the shaped XOR value transmitted thereto by the sensitive amplifier array and the XOR value with opposite phase inverted and transmitted thereto by the inverter array to the secure storage array, and the secure storage array saves the shaped XOR value and the XOR value with opposite phase as encrypted data to realize encryption;When encrypted data has been stored in the secure storage array and needs to be decrypted, first, the timing control module controls the first refresh circuit to output a precharge signal to precharge the secure storage array, and controls the second refresh circuit to output a reset signal to refresh the key row and reset the key row to zero. Then, the timing control module controls the key row to generate a pair of keys with opposite phases and transmit them to the switch control array. The switch control array transmits the pair of keys transmitted by the key row to the secure storage array. The secure storage array performs an XOR operation on the pair of keys currently received and the encrypted data stored there, and obtains an initial value of one bit for transmission. To the sensitive amplifier array, the sensitive amplifier array, under the control of the timing control module, shapes the initial value, obtains the shaped initial value and transmits it to the inverter array, the inverter array inverts the shaped initial value, obtains the initial value with opposite phase and transmits it to the switch control array, the switch control array transmits both the one-bit initial value outputted by the sensitive amplifier array and the initial value with opposite phase outputted by the inverter array to the secure storage array, the secure storage array stores the one-bit initial value and the initial value with opposite phase, at this time, the pair of data stored in the secure storage array is consistent with the pair of data stored in the write circuit during encryption, thus realizing data decryption. ;

[0006] The write circuit has a group of input terminals, two groups of output terminals and a control terminal, wherein the group of input terminals is used to access four-bit binary data, and each group of output terminals is used to output four-bit binary data, and the input terminals are referred to as the first group of input terminals, the two groups of output terminals are referred to as the first group of output terminals and the second group of output terminals, and the control terminal is referred to as the first control terminal; the first refresh circuit has two input terminals and three groups of output terminals, wherein the two input terminals are referred to as the first input terminal and the second input terminal, respectively, and each group of output terminals is used to output four-bit binary data, and the three groups of output terminals are referred to as the first group of output terminals, the second group of output terminals and the third group of output terminals, respectively; the second refresh circuit has two input terminals and four groups of output terminals, wherein the two input terminals are referred to as Its first input terminal and second input terminal, and each group of its output terminals are used to output four-bit binary data, and its four groups of output terminals are respectively referred to as its first group of output terminals, second group of output terminals, third group of output terminals and fourth group of output terminals; the sensitive amplifier array has two input terminals, one group of input terminals and one group of output terminals, and its two input terminals are respectively referred to as its first input terminal and second input terminal, one group of its input terminals are used to access four-bit binary data, and its one group of input terminals are referred to as its first group of input terminals, and one group of its output terminals are used to output four-bit binary data, and its one group of its output terminals are referred to as its first group of output terminals; the safety storage array has five groups of input terminals and three groups of input and output terminals, each group of its input terminals is used to access four-bit binary data, and each group of its input and output terminals The key row has one input terminal, two input and output terminals and one control terminal, and one input terminal is called the first input terminal. Each input and output terminal is used to output four-bit binary data or access four-bit binary data. The five input terminals are respectively called the first input terminal, the second input terminal, the third input terminal, the fourth input terminal and the fifth input terminal, and the three input and output terminals are respectively called the first input and output terminals, the second input and output terminals and the third input and output terminals. The key row has one input terminal, two input and output terminals and one control terminal, and one input terminal is called the first input terminal. Each input and output terminal is used to output four-bit binary data or access four-bit binary data. The two input and output terminals are respectively called the first input and output terminals and the second input and output terminals, and the control terminal is called the first control terminal. The inverter array has one input terminal, two input and output terminals and one control terminal. The timing control module has ten output terminals, and the ten output terminals are respectively referred to as the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal, the sixth output terminal, the seventh output terminal, the eighth output terminal, the ninth output terminal and the tenth output terminal; the timing control module is used to control the coordinated work of the security storage array, the key row, the sensitive amplifier array, the inverter array, the switch control array, the write circuit and the two refresh circuits.The first output terminal, the second output terminal, the third output terminal, the fourth output terminal and the fifth output terminal of the timing control module are respectively used to output control signals, and the sixth output terminal, the seventh output terminal, the eighth output terminal, the ninth output terminal and the tenth output terminal of the timing control module are respectively used to output refresh signals. The control signal output by the first output terminal of the timing control module is recorded as ctrl0, the control signal output by the second output terminal is recorded as ctrl1, the control signal output by the third output terminal is recorded as ctrl2, the control signal output by the fourth output terminal is recorded as ctrl3, the control signal output by the fifth output terminal is recorded as ctrl4, the refresh signal output by the sixth output terminal is recorded as pre0, and the refresh signal output by the seventh output terminal is recorded as The refresh signal output by the eighth output terminal is recorded as pre1, the refresh signal output by the ninth output terminal is recorded as pre2, the refresh signal output by the tenth output terminal is recorded as pre3, and the refresh signal output by the tenth output terminal is recorded as pre4; the switch control array has two groups of input terminals, four groups of output terminals, two groups of input and output terminals and three control terminals, each group of input terminals is used to access four-bit binary data, each group of output terminals is used to output four-bit binary data, each group of input and output terminals is used to output four-bit binary data or access four-bit binary data, its two groups of input terminals are respectively referred to as the first group of input terminals and the second group of input terminals, its four groups of output terminals are respectively referred to as the first group of output terminals, the second group of output terminals, the third group of output terminals and the fourth group of output terminals, its two groups of input terminals are respectively referred to as the first group of output terminals, the second group of output terminals, the third group of output terminals and the fourth group of output terminals, its two groups of input terminals are respectively referred to as the first group of The input and output ends are respectively referred to as the first group of input and output ends and the second group of input and output ends, and the three control ends are respectively referred to as the first control end, the second control end and the third control end; the four bits of data to be encrypted are recorded as IN<0:3>, the first group of input ends of the write circuit is used to access the four bits of data to be encrypted IN<0:3>, the first group of output ends of the write circuit is used to output one of the two data with opposite phases, the second group of output ends of the write circuit is used to output the other of the two data with opposite phases, the first group of output ends of the write circuit is respectively connected to the first group of input and output ends of the security storage array, the first group of output ends of the second refresh circuit and the first group of output ends of the switch control array The second group of output ends of the write circuit are respectively connected to the second group of input and output ends of the safety storage array, the second group of output ends of the second refresh circuit and the second group of output ends of the switch control array, the first control end of the write circuit is connected to the first output end of the timing control module, the first input end of the first refresh circuit is connected to the sixth output end of the timing control module, the second input end of the first refresh circuit is connected to the seventh output end of the timing control module, the first input end of the first refresh circuit is connected to the sixth output end of the timing control module, and the second input end of the first refresh circuit is connected to the seventh output end of the timing control module,The first group of output ends of the first refresh circuit are respectively connected to the third group of input and output ends of the safety storage array and the first group of input ends of the sensitive amplifier array, the second group of output ends of the first refresh circuit are respectively connected to the fourth group of input ends of the safety storage array and the third group of output ends of the switch control array, the second group of output ends of the first refresh circuit are used to output a precharge signal, which is four-bit binary data, the third group of output ends of the first refresh circuit are respectively connected to the fifth group of input ends of the safety storage array and the fourth group of output ends of the switch control array, the third group of output ends of the first refresh circuit are used to output a precharge signal, which is four-bit binary data. The first input terminal of the second refresh circuit is connected to the eighth output terminal of the timing control module, the second input terminal of the second refresh circuit is connected to the tenth output terminal of the timing control module, the third group of output terminals of the second refresh circuit are respectively connected to the first group of input and output terminals of the key row and the first group of input and output terminals of the switch control array, the third group of output terminals of the second refresh circuit are used to output a reset signal, which is a four-bit binary data, the fourth group of output terminals of the second refresh circuit are respectively connected to the second group of input and output terminals of the key row and the second group of input and output terminals of the switch control array, the fourth group of output terminals of the second refresh circuit are used to output A reset signal, which is four-bit binary data, the first input end of the sense amplifier array is used to access an external threshold voltage compare, the first group of output ends of the sense amplifier array is used to output a shaped XOR value, the XOR value is four-bit binary data, the second input end of the sense amplifier array is connected to the ninth output end of the timing control module, the first group of output ends of the sense amplifier array are respectively connected to the first group of input ends of the inverter array and the first group of input ends of the switch control array, the first group of input ends of the safety storage array is used to access a four-bit voltage signal VDD<0:3>, the second group of input ends of the safety storage array is used to access a four-bit word line control The four-bit word line control signal WL<0:3> is used to control whether the security storage array stores the data BL<0:3> connected to its first input and output terminals and the data BLB<0:3> connected to its second input and output terminals. The four-bit word line control signal ctrl<0:3> is used to control whether the security storage array stores the data BL<0:3> connected to its fourth input terminal and the data BLB<0:3> connected to its fifth input terminal. The first control terminal of the key row is connected to the fifth output terminal of the timing control signal.The first input terminal of the key row is used to access the word line control signal XWL, and the word line control signal XWL is used to control the transmission of the key of the key row; the first group of output terminals of the inverter array is used to output the inverted and shaped XOR value, the first group of output terminals of the inverter array is connected to the first group of input terminals of the switch control array, the first control terminal of the switch control array is connected to the second output terminal of the timing control module, the second control terminal of the switch control array is connected to the third output terminal of the timing control module, and the fourth output terminal of the switch control array is connected to the timing control module.

[0007] The write circuit includes 4 first write units and 4 second write units, each of the first write units has an input end, an output end and a control end, each of the second write units has an input end, an output end and a control end, the control ends of the 4 first write units are connected to the control ends of the 4 second write units, and their connecting ends are the first control ends of the write circuit, the input end of the first first write unit is connected to the input end of the first second write unit, and its connecting end is the first input end of the write circuit, the input end of the second first write unit is connected to the input end of the second second write unit, and its connecting end is the second input end of the write circuit, the input end of the third first write unit is connected to the input end of the third second write unit, and its connecting end is the third input end of the write circuit, the input end of the fourth first write unit is connected to the input end of the fourth second write unit, and its connecting end is the fourth input end of the write circuit, and the first The first input end to the fourth input end constitute a first group of input ends of the write circuit, the output end of the first first write unit is the first output end of the write circuit, the output end of the second first write unit is the second output end of the write circuit, the output end of the third first write unit is the third output end of the write circuit, the output end of the fourth first write unit is the fourth output end of the write circuit, the first output end to the fourth output end of the write circuit constitute a first group of output ends of the write circuit, the output end of the first second write unit is the fifth output end of the write circuit, the output end of the second second write unit is the sixth output end of the write circuit, the output end of the third second write unit is the seventh output end of the write circuit, the output end of the fourth second write unit is the eighth output end of the write circuit, and the fifth output end to the eighth output end of the write circuit constitute a second group of output ends of the write circuit;Each of the first writing units includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube. The source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are all connected to the power supply voltage. The gate of the first PMOS tube is connected to the gate of the first NMOS tube, and the connection end thereof is the input end of the first writing unit. The drain of the first PMOS tube, the drain of the first NMOS tube, the gate of the fourth PMOS tube and the drain of the first NMOS tube are connected to the gate of the fourth PMOS tube. The gates of the three NMOS tubes are connected, the drain of the second PMOS tube, the gate of the third PMOS tube and the drain of the second NMOS tube are connected, the gate of the second PMOS tube, the gate of the second NMOS tube and the gate of the fourth NMOS tube are connected, and the connection end thereof is the control end of the first writing unit, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and the connection end thereof is the output end of the first writing unit, the source of the third NMOS tube is connected to the fourth NMOS The drain of the first NMOS tube is connected, the source of the first NMOS tube, the source of the second NMOS tube and the source of the fourth NMOS tube are all grounded; each of the second writing units includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube, the source of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the power supply voltage, the gate of the fifth PMOS tube, the gate of the fifth NMOS tube and the gate of the seventh NMOS tube are connected, and the connection end is the control end of the second writing unit, the fifth PMOS tube The drain of the sixth PMOS tube is connected to the drain of the fifth NMOS tube, the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube, the gate of the sixth NMOS tube is connected to the gate of the seventh PMOS tube, and the connection end thereof is the input end of the second writing unit, the source of the sixth NMOS tube is connected to the drain of the seventh PMOS tube, and the connection end thereof is the output end of the second writing unit, the drain of the sixth NMOS tube is connected to the drain of the seventh NMOS tube, and the source of the seventh NMOS tube and the source of the fifth NMOS tube are both grounded. ;

[0008] The first refresh circuit includes three first refresh units, each of which has an input end and a group of output ends, the input end of the first first refresh unit is the first input end of the first refresh circuit, the group of output ends of the first first refresh unit is the first group of output ends of the first refresh circuit, the input end of the second first refresh unit is connected to the input end of the third first refresh unit, and its connection end is the second input end of the first refresh circuit, the group of output ends of the second first refresh unit is the second group of output ends of the first refresh circuit, and the group of output ends of the third first refresh unit is the third group of output ends of the first refresh circuit; each of the first refresh units includes an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube and an eleventh PMOS tube, the source, The source of the ninth PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are all connected to the power supply voltage VDD, the gate of the eighth PMOS tube, the gate of the ninth PMOS tube, the gate of the tenth PMOS tube and the gate of the eleventh PMOS tube are connected, and their connection ends are the input ends of the first refresh unit, the drain of the eighth PMOS tube is the first output end of the first refresh unit, the drain of the ninth PMOS tube is the second output end of the first refresh unit, the drain of the tenth PMOS tube is the third output end of the first refresh unit, the drain of the eleventh PMOS tube is the fourth output end of the first refresh unit, and the first output end to the fourth output end of the first refresh unit constitute a group of output ends.

[0009] The second refresh circuit includes 4 second refresh units, each of which has an input end and a group of output ends. The input end of the first second refresh unit is connected to the input end of the second second refresh unit, and the connected end is the first input end of the second refresh circuit. The input end of the third second refresh unit is connected to the input end of the fourth second refresh unit, and the connecting end is the second input end of the second refresh circuit. A group of output ends of the first second refresh unit is the first group of output ends of the second refresh circuit. A group of output ends of the second second refresh unit is the second group of output ends of the second refresh circuit. A group of output ends of the third second refresh unit is the third group of output ends of the second refresh circuit. A group of output ends of the fourth second refresh unit is the fourth group of output ends of the second refresh circuit. Each of the second refresh units includes an eighth NMOS tube, a ninth NMOS tube, The tenth NMOS tube and the eleventh NMOS tube, the source of the eighth NMOS tube, the source of the ninth NMOS tube, the source of the tenth NMOS tube and the source of the eleventh NMOS tube are all grounded, the gate of the eighth NMOS tube, the gate of the ninth NMOS tube, the gate of the tenth NMOS tube and the gate of the eleventh NMOS tube are connected, and their connecting ends are the input ends of the second refresh unit, the drain of the eighth NMOS tube is the first output end of the second refresh unit, the drain of the ninth NMOS tube is the second output end of the second refresh unit, the drain of the tenth NMOS tube is the third output end of the second refresh unit, and the drain of the eleventh NMOS tube is the fourth output end of the second refresh unit, and the first output end to the fourth output end of the second refresh unit constitute a group of output ends.

[0010] The inverter array includes four inverters, each of which has an input end and an output end. The input end of the first inverter is the first input end of the inverter array, the input end of the second inverter is the second input end of the inverter array, the input end of the third inverter is the third input end of the inverter array, and the input end of the fourth inverter is the fourth input end of the inverter array. The first input end to the fourth input end of the inverter array constitute a first group of input ends, the output end of the first inverter is the first output end of the inverter array, the output end of the second inverter is the second output end of the inverter array, and the output end of the third inverter is the fourth input end of the inverter array. The third output end of the inverter array, the output end of the fourth inverter is the fourth output end of the inverter array, and the first output end to the fourth output end of the inverter array constitute its first group of output ends; each of the inverters includes a twelfth PMOS tube and a twelfth NMOS tube, the source of the twelfth PMOS tube is connected to the power supply voltage, the gate of the twelfth PMOS tube is connected to the gate of the twelfth NMOS tube, and the connection end thereof is the input end of the inverter, the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS tube, and the connection end thereof is the output end of the inverter, and the source of the twelfth NMOS tube is grounded.

[0011] The sensitive amplifier array includes four sensitive amplifiers, each of which has three input terminals and one output terminal, and the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal. The first input terminals of the four sensitive amplifiers are connected, and the connection terminal thereof is the first input terminal of the sensitive amplifier array. The second input terminals of the four sensitive amplifiers are connected, and the connection terminal thereof is the second input terminal of the sensitive amplifier array. The third input terminal of the first sensitive amplifier is the first input terminal of the sensitive amplifier array. The third input terminal of the second sensitive amplifier is the second input terminal of the sensitive amplifier array. The third input terminal of the third sensitive amplifier is the a third input end, the third input end of the fourth sensitive amplifier is the fourth input end of the sensitive amplifier array, the first input end to the fourth input end of the sensitive amplifier array constitute a first group of input ends, the output end of the first sensitive amplifier is the first output end of the sensitive amplifier array, the output end of the second sensitive amplifier is the second output end of the sensitive amplifier array, the output end of the third sensitive amplifier is the third output end of the sensitive amplifier array, the output end of the fourth sensitive amplifier is the fourth output end of the sensitive amplifier array, and the first output end to the fourth output end of the sensitive amplifier array constitute a first group of output ends of the sensitive amplifier array;Each of the sensitive amplifiers comprises a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and a seventeenth NMOS tube, the source of the thirteenth PMOS tube, the source of the fourteenth PMOS tube, the source of the fifteenth PMOS tube and the source of the sixteenth PMOS tube are all connected to the power supply voltage, the gate of the thirteenth PMOS tube, the gate of the sixteenth PMOS tube and the gate of the seventeenth NMOS tube are connected, and the connection end thereof is the second input end of the sensitive amplifier, the drain of the thirteenth PMOS tube, the drain of the fourteenth PMOS tube, the gate of the fifteenth PMOS tube, the drain of the thirteenth NMOS tube and the drain of the tenth The gates of the four NMOS are connected, and the connection end thereof is the output end of the sensitive amplifier, the drain of the fifteenth PMOS tube, the drain of the sixteenth PMOS tube, the gate of the fourteenth PMOS tube, the gate of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube are connected, the drain of the fifteenth NMOS tube is connected to the source of the thirteenth NMOS tube, the drain of the sixteenth NMOS tube is connected to the source of the fourteenth NMOS tube, the gate of the fifteenth NMOS tube is the first input end of the sensitive amplifier, the gate of the sixteenth NMOS tube is the third input end of the sensitive amplifier, the source of the fifteenth NMOS tube, the source of the sixteenth NMOS tube and the drain of the seventeenth NMOS tube are connected, and the source of the seventeenth NMOS tube is grounded. ;

[0012] The key row includes 4 key units, each of which has an input end, a control end and two input-output ends, the two input-output ends of which are respectively referred to as the first input-output end and the second input-output end, the input ends of the 4 key units are connected, and their connecting end is the first input end of the key row, the control ends of the 4 key units are connected, and their connecting end is the control end of the key row, the first input-output end of the first key unit is the first input-output end of the key row, the first input-output end of the second key unit is the second input-output end of the key row, and the first input-output end of the third key unit is the second input-output end of the key row. The third input-output end of the key row, the first input-output end of the fourth key unit is the fourth input-output end of the key row, the first input-output end to the fourth input-output end of the key row constitute the first group of input-output ends of the key row, the second input-output end of the first key unit is the fifth input-output end of the key row, the second input-output end of the second key unit is the sixth input-output end of the key row, the second input-output end of the third key unit is the seventh input-output end of the key row, the second input-output end of the fourth key unit is the eighth input-output end of the key row, and the key row The fifth input-output terminal to the eighth input-output terminal constitute the second group of input-output terminals of the key row; each of the key units includes a seventeenth PMOS tube, an eighteenth PMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube and a twenty-first NMOS tube, the source of the seventeenth PMOS tube is connected to the source of the eighteenth PMOS tube, and the connecting end is the control end of the key unit, the gate of the eighteenth NMOS tube is connected to the gate of the nineteenth NMOS tube, and the connecting end is the input end of the key row, the gate of the seventeenth PMOS tube, the gate of the twentieth NMOS tube, and the connecting end is the input end of the key row. The gate of the tube, the drain of the eighteenth PMOS tube, the drain of the twenty-first NMOS tube and the source of the nineteenth NMOS tube are connected, the gate of the eighteenth PMOS tube, the gate of the twenty-first NMOS tube, the drain of the seventeenth PMOS tube, the drain of the twentieth NMOS tube and the source of the eighteenth NMOS tube are connected, the drain of the eighteenth NMOS tube is the first input and output end of the key unit, the drain of the nineteenth NMOS tube is the second input and output end of the key unit, and the source of the twentieth NMOS tube and the source of the twenty-first NMOS tube are both grounded.

[0013] The switch control array includes three switch control units, each of which has a control end, a first group of input ends, a second group of input ends, a first group of output ends and a second group of output ends. The control end of the first switch control unit is the first control end of the switch control array, the control end of the second switch control unit is the second control end of the switch control array, the control end of the third switch control unit is the third control end of the switch control array, the first group of input ends of the first switch control unit is the first group of input ends of the switch control array, the second group of input ends of the first switch control unit is the second group of input ends of the switch control array, and the first group of output ends of the first switch control unit are respectively connected to the first group of input ends and The first group of input ends of the third switch control unit are connected, and its connection end is the first group of input and output ends of the switch control array, the second group of output ends of the first switch control unit are respectively connected to the second group of input ends of the second switch control unit and the second group of input ends of the third switch control unit, and its connection end is the second group of input and output ends of the switch control array, the first group of output ends of the second switch control unit are the first group of output ends of the switch control array, the second group of output ends of the second switch control unit are the second group of output ends of the switch control array, the first group of output ends of the third switch control unit are the third group of output ends of the switch control array, and the second group of output ends of the third switch control unit are the fourth group of output ends of the switch control array;Each of the switch control units includes 8 switch control circuits, each of which has a control end, an input end and an output end. The control ends of the 8 switch control circuits are connected, and their connection ends are the control ends of the switch control unit. The input end of the first switch control circuit is the first input end of the switch control unit, the input end of the second switch control circuit is the second input end of the switch control unit, the input end of the third switch control circuit is the third input end of the switch control unit, and the input end of the fourth switch control circuit is the fourth input end of the switch control unit. The first input end to the fourth input end of the switch control unit constitute its first group of input ends. The input end of the fifth switch control circuit is the fifth input end of the switch control unit, the input end of the sixth switch control circuit is the sixth input end of the switch control unit, the input end of the seventh switch control circuit is the seventh input end of the switch control unit, and the input end of the eighth switch control circuit is the eighth input end of the switch control unit. The fifth input end to the eighth input end of the unit constitute the second group of input ends of the switch control end element, the output end of the first switch control circuit is the first output end of the switch control unit, the output end of the second switch control circuit is the second output end of the switch control unit, the output end of the third switch control circuit is the third output end of the switch control unit, the output end of the fourth switch control circuit is the fourth output end of the switch control unit, the first output end to the fourth output end of the switch control unit constitute the first group of output ends of the switch control end element, the output end of the fifth switch control circuit is the fifth output end of the switch control unit, the output end of the sixth switch control circuit is the sixth output end of the switch control unit, the output end of the seventh switch control circuit is the seventh output end of the switch control unit, the output end of the eighth switch control circuit is the eighth output end of the switch control unit, and the fifth output end to the eighth output end of the switch control unit constitute the second group of output ends of the switch control end element;Each of the switch control circuits comprises a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-second NMOS tube and a twenty-third NMOS tube, the drain of the nineteenth PMOS tube is connected to the drain of the twenty-second NMOS tube, and the connection end thereof is the input end of the switch control circuit, the source of the nineteenth PMOS tube is connected to the source of the twenty-second NMOS tube, and the connection end thereof is the output end of the switch control circuit, the gate of the nineteenth PMOS tube, the gate of the twenty-third NMOS tube and the gate of the twentieth PMOS tube are connected, the source of the twentieth PMOS tube is connected to the power supply voltage, the drain of the twentieth PMOS tube, the drain of the twenty-third NMOS tube and the gate of the twenty-second NMOS tube are connected, and the connection end thereof is the control end of the switch control circuit, and the source of the twenty-third NMOS tube is grounded. ;

[0014] The safety storage array includes 16 safety storage units distributed in 4 rows and 4 columns, each of which has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a first input-output terminal, and a second input-output terminal. The first input terminals of the four safety storage units in the first row are connected, and their connection terminal is the first input terminal of the safety storage array. The first input terminals of the four safety storage units in the second row are connected, and their connection terminal is the second input terminal of the safety storage array. The first input terminals of the four safety storage units in the third row are connected, and their connection terminal is the third input terminal of the safety storage array. The first input terminals of the four safety storage units in the fourth row are connected, and their connection terminal is the safety storage array. The fourth input end of the full storage array, the first input end to the fourth input end of the safety storage array constitute the first group of input ends of the safety storage array, the second input ends of the four safety storage units in the first row are connected, and their connection end is the fifth input end of the safety storage array, the second input ends of the four safety storage units in the second row are connected, and their connection end is the sixth input end of the safety storage array, the second input ends of the four safety storage units in the third row are connected, and their connection end is the seventh input end of the safety storage array, the second input ends of the four safety storage units in the fourth row are connected, and their connection end is the eighth input end of the safety storage array, the fifth input end to the eighth input end of the safety storage array The third input terminals of the four safety storage units in the first row are connected to each other, and the connection terminal thereof is the ninth input terminal of the safety storage array. The third input terminals of the four safety storage units in the second row are connected to each other, and the connection terminal thereof is the tenth input terminal of the safety storage array. The third input terminals of the four safety storage units in the third row are connected to each other, and the connection terminal thereof is the eleventh input terminal of the safety storage array. The third input terminals of the four safety storage units in the fourth row are connected to each other, and the connection terminal thereof is the twelfth input terminal of the safety storage array. The ninth input terminal to the twelfth input terminal of the safety storage array constitute the third group of input terminals of the safety storage array. The fourth input terminals of the four safety storage units in the first row are connected to each other, and the connection terminal thereof is the twelfth input terminal of the safety storage array. The input ends of the four safety storage units in the second column are connected, and the connection end thereof is the thirteenth input end of the safety storage array, the fourth input ends of the four safety storage units in the third column are connected, and the connection end thereof is the fifteenth input end of the safety storage array, the fourth input ends of the four safety storage units in the fourth column are connected, and the connection end thereof is the sixteenth input end of the safety storage array, the thirteenth input end to the sixteenth input end of the safety storage array constitute a fourth group of input ends of the safety storage array, the fifth input ends of the four safety storage units in the first column are connected, and the connection end thereof is the seventeenth input end of the safety storage array,The fifth input terminals of the four safety storage units in the second column are connected, and the connection terminal thereof is the eighteenth input terminal of the safety storage array. The fifth input terminals of the four safety storage units in the third column are connected, and the connection terminal thereof is the nineteenth input terminal of the safety storage array. The fifth input terminals of the four safety storage units in the fourth column are connected, and the connection terminal thereof is the twentieth input terminal of the safety storage array. The seventeenth input terminal to the twentieth input terminal of the safety storage array constitute the fifth group of input terminals of the safety storage array. The first input-output terminals of the four safety storage units in the first column are connected, and the connection terminal thereof is the safety storage array. The first input and output end of the storage array and the first input and output ends of the four safety storage units in the second column are connected, and the connection end thereof is the second input and output end of the safety storage array, the first input and output ends of the four safety storage units in the third column are connected, and the connection end thereof is the third input and output end of the safety storage array, the first input and output ends of the four safety storage units in the fourth column are connected, and the connection end thereof is the fourth input and output end of the safety storage array, and the first input and output ends to the fourth input and output ends of the safety storage array constitute the first group of input and output ends of the safety storage array, and the four safety storage units in the first column are connected. The second input and output ends of the four safety storage units in the second column are connected, and the connection end thereof is the fifth input and output end of the safety storage array. The second input and output ends of the four safety storage units in the second column are connected, and the connection end thereof is the sixth input and output end of the safety storage array. The second input and output ends of the four safety storage units in the third column are connected, and the connection end thereof is the seventh input and output end of the safety storage array. The second input and output ends of the four safety storage units in the fourth column are connected, and the connection end thereof is the eighth input and output end of the safety storage array. The fifth input and output end to the eighth input and output end of the safety storage array constitute a The third input-output terminals of the four safety storage units in the first column are connected to each other, and the connection terminal thereof is the ninth input-output terminal of the safety storage array. The third input-output terminals of the four safety storage units in the second column are connected to each other, and the connection terminal thereof is the tenth input-output terminal of the safety storage array. The third input-output terminals of the four safety storage units in the third column are connected to each other, and the connection terminal thereof is the eleventh input-output terminal of the safety storage array. The third input-output terminals of the four safety storage units in the fourth column are connected to each other, and the connection terminal thereof is the twelfth input-output terminal of the safety storage array.The ninth input-output terminal to the twelfth input-output terminal of the safety storage array constitute a third group of input-output terminals of the safety storage array; each of the safety storage units includes a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-fourth NMOS tube, a twenty-fifth NMOS tube, a twenty-sixth NMOS tube, a twenty-seventh NMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube and a first capacitor, a source electrode of the twenty-first PMOS tube, a source electrode of the twenty-second PMOS tube, a source electrode of the twenty-fifth PMOS tube and a first capacitor. The sources of the twenty-sixth PMOS tube are connected, and the connection end is the first input end of the safety storage unit, the gate of the twenty-first PMOS tube, the gate of the twenty-sixth NMOS tube, the drain of the twenty-second PMOS tube, the source of the twenty-seventh NMOS tube, the source of the twenty-fifth NMOS tube and the source of the twenty-fourth PMOS tube are connected, the gate of the twenty-second PMOS tube, the gate of the twenty-seventh NMOS tube, the drain of the twenty-first PMOS tube, the source of the twenty-sixth NMOS tube, the source of the twenty-fourth NMOS tube and the source of the twenty-third PMOS tube are connected, and the twenty-fourth NMOS tube is connected. The gate of the S tube is connected to the gate of the twenty-fifth NMOS tube, and the connection end thereof is the second input end of the safety storage unit, the drain of the twenty-fourth NMOS tube is the first input-output end of the safety storage unit, the drain of the twenty-fifth NMOS tube is the second input-output end of the safety storage unit, the gate of the twenty-third PMOS tube, the source of the twenty-eighth NMOS tube and the drain of the twenty-fifth PMOS tube are connected, the gate of the twenty-fourth PMOS tube, the source of the twenty-ninth NMOS tube and the drain of the twenty-sixth PMOS tube are connected, and the drain of the twenty-eighth NMOS tube is the second input-output end of the safety storage unit. The fourth input terminal, the drain of the 29th NMOS tube is the fifth input terminal of the safety storage unit, the gate of the 28th NMOS tube, the gate of the 29th NMOS tube, the gate of the 25th PMOS tube and the gate of the 26th PMOS tube are connected, and the connection terminal is the third input terminal of the safety storage unit, the drain of the 23rd PMOS tube, the drain of the 24th PMOS tube and one end of the first capacitor are connected, and the connection terminal is the third input and output terminal of the safety storage unit, and the drain of the 26th NMOS tube, the drain of the 27th NMOS tube and the other end of the first capacitor are grounded.

[0015] Compared with the prior art, the advantage of the present invention is that a secure encryption and decryption circuit is formed by a secure storage array, a timing control module, a key row, a sensitive amplifier array, an inverter array, a switch control array, a write circuit and two refresh circuits. The secure storage array is used for the storage of data to be encrypted, the storage of XOR data, the storage of decrypted data and the encryption and decryption operations of data. The secure storage array is implemented by hardware multiplexing technology, which reduces hardware overhead. When the key row needs to generate a key, the key is generated by the control of the timing control circuit. When it is not needed, the key row is powered off and cleared by the control of the timing control circuit. The key row adopts a technology of dynamically generating keys, avoiding the risky behavior of storing keys, and has higher security performance. Therefore, the hardware overhead of the present invention is small and the security performance is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A block diagram of the security encryption and decryption circuit of the present invention;

[0017] Figure 2 A block diagram of a write circuit of the security encryption and decryption circuit of the present invention;

[0018] Figure 3 A circuit diagram of a first writing unit of a security encryption and decryption circuit of the present invention;

[0019] Figure 4 A circuit diagram of a second writing unit of the security encryption and decryption circuit of the present invention;

[0020] Figure 5 is a block diagram of a first refresh circuit of the security encryption and decryption circuit of the present invention;

[0021] Figure 6 A circuit diagram of a first refresh unit of the security encryption and decryption circuit of the present invention;

[0022] Figure 7 is a block diagram of a second refresh circuit of the security encryption and decryption circuit of the present invention;

[0023] Figure 8 A circuit diagram of a second refresh unit of the security encryption and decryption circuit of the present invention;

[0024] Fig. 9 A block diagram of an inverter array of a security encryption and decryption circuit of the present invention;

[0025] Fig.10 A circuit diagram of an inverter of a security encryption and decryption circuit of the present invention;

[0026] Fig.11 A block diagram of a sensitive amplifier array of a security encryption and decryption circuit of the present invention;

[0027] Fig.12A circuit diagram of a sensitive amplifier of the security encryption and decryption circuit of the present invention;

[0028] Fig.13 A block diagram of a key row of a security encryption and decryption circuit of the present invention;

[0029] Fig.14 A circuit diagram of a key row unit of a security encryption and decryption circuit of the present invention;

[0030] Fig.15 A block diagram of a switch control array of a security encryption and decryption circuit of the present invention;

[0031] Fig.16 A block diagram of a switch control circuit of the security encryption and decryption circuit of the present invention;

[0032] Fig.17 A circuit diagram of a switch control unit of the security encryption and decryption circuit of the present invention;

[0033] Fig.18 A block diagram of a secure storage array of a secure encryption and decryption circuit of the present invention;

[0034] Fig.19 A circuit diagram of a secure storage unit of the present invention;

[0035] Fig. 20 It is a functional simulation waveform diagram of the security encryption and decryption circuit of the present invention. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below with reference to the accompanying drawings.

[0037] Embodiment 1: Figure 1As shown, a secure encryption and decryption circuit includes a secure storage array, a timing control module, a key row, a sensitive amplifier array, an inverter array, a switch control array, a write circuit and two refresh circuits, the two refresh circuits are respectively referred to as a first refresh circuit and a second refresh circuit, the secure storage array is implemented by hardware multiplexing technology to reduce hardware resource overhead; when encryption is required, first, the timing control module controls the second refresh circuit to output a clear signal to refresh the secure storage array, and clears the state of the secure storage array, and then, when the data to be encrypted is transmitted to the write circuit, the write circuit, under the control of the timing control module, converts the data to be encrypted into two data with opposite phases and outputs them to the secure storage array, and the secure storage array stores the two data with opposite phases outputted thereto by the write circuit; then, the timing control module controls the first refresh circuit to output a precharge signal on the one hand to precharge the secure storage array, and controls the second refresh circuit to output a clear signal on the other hand to refresh the key row, The key row is cleared to zero state, and then the timing control module controls the key row to generate a pair of keys with opposite phases and transmits them to the switch control array. The switch control array transmits the pair of keys transmitted to it by the key row to the secure storage array. The secure storage array performs an XOR operation on the pair of keys transmitted to it by the current key row and two data with opposite phases already stored there, to obtain a one-bit XOR value, and transmits the XOR value to the sensitive amplifier array. Under the control of the timing control module, the sensitive amplifier array shapes the XOR value output thereto, and the shaped XOR value is transmitted to the inverter array. The inverter array inverts the shaped XOR value to obtain an XOR value with opposite phases and transmits it to the switch control array. The switch control array transmits the shaped XOR value transmitted to it by the sensitive amplifier array and the XOR value with opposite phases transmitted to it by the inverter array to the secure storage array. The secure storage array saves the shaped XOR value and the XOR value with opposite phases as encrypted data to achieve encryption.When encrypted data has been stored in the secure storage array and needs to be decrypted, first, the timing control module controls the first refresh circuit to output a precharge signal to precharge the secure storage array, and controls the second refresh circuit to output a reset signal to refresh the key row and reset the key row to zero. Then, the timing control module controls the key row to generate a pair of keys with opposite phases and transmit them to the switch control array. The switch control array transmits the pair of keys transmitted by the key row to the secure storage array. The secure storage array performs an XOR operation on the pair of keys currently received and the encrypted data stored there, and obtains an initial value of one bit and transmits it to the sensitive array. Amplifier array, under the control of the timing control module, the sensitive amplifier array shapes the initial value, obtains the shaped initial value and transmits it to the inverter array, the inverter array inverts the shaped initial value, obtains the initial value with opposite phase and transmits it to the switch control array, the switch control array transmits both the one-bit initial value outputted by the sensitive amplifier array and the initial value with opposite phase outputted by the inverter array to the security storage array, the security storage array stores the one-bit initial value and the initial value with opposite phase, at this time, the pair of data stored in the security storage array is consistent with the pair of data stored in the write circuit during encryption, thus realizing data decryption. ;

[0038] In this embodiment, the secure storage array is used for storing data to be encrypted, storing XOR data, storing decrypted data, and performing encryption and decryption operations on data. The secure storage array is implemented using hardware multiplexing technology, which reduces hardware overhead. When a key row needs to generate a key, the key row is generated through the control of a timing control circuit. When it is not needed, the key row is powered off and cleared through the control of the timing control circuit. The key row uses a technology for dynamically generating keys, which avoids the risk of storing keys and has higher security performance. Therefore, the hardware overhead is small and the security performance is high.

[0039] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the write circuit has a group of input terminals, two groups of output terminals and a control terminal, wherein the group of input terminals is used to access four-bit binary data, and each group of output terminals is used to output four-bit binary data, and the input terminals are referred to as the first group of input terminals, the two groups of output terminals are referred to as the first group of output terminals and the second group of output terminals, and the control terminal is referred to as the first control terminal; the first refresh circuit has two input terminals and three groups of output terminals, wherein the two input terminals are referred to as the first input terminal and the second input terminal, respectively, and each group of output terminals is used to output four-bit binary data, and the three groups of output terminals are referred to as the first group of output terminals, the second group of output terminals and the third group of output terminals, respectively; the second refresh circuit The invention has two input terminals and four groups of output terminals, wherein the two input terminals are respectively referred to as the first input terminal and the second input terminal, and each group of output terminals is used to output four-bit binary data, and the four groups of output terminals are respectively referred to as the first group of output terminals, the second group of output terminals, the third group of output terminals and the fourth group of output terminals; the sensitive amplifier array has two input terminals, one group of input terminals and one group of output terminals, wherein the two input terminals are respectively referred to as the first input terminal and the second input terminal, the one group of input terminals is used to access four-bit binary data, and the one group of input terminals is referred to as the first group of input terminals, and the one group of output terminals is used to output four-bit binary data, and the one group of output terminals is referred to as the first group of output terminals; the safety storage array has five groups of input terminals and three groups of input and output terminals, and each group of output terminals is referred to as the first group of output terminals. The input terminals are all used to access four-bit binary data, and each group of input and output terminals is used to output four-bit binary data or access four-bit binary data. The five groups of input terminals are respectively referred to as the first group of input terminals, the second group of input terminals, the third group of input terminals, the fourth group of input terminals and the fifth group of input terminals, and the three groups of input and output terminals are respectively referred to as the first group of input and output terminals, the second group of input and output terminals and the third group of input and output terminals; the key row has one input terminal, two groups of input and output terminals and one control terminal, and the one input terminal is referred to as the first input terminal, and each group of input and output terminals is used to output four-bit binary data or access four-bit binary data, and the two groups of input and output terminals are respectively referred to as the first group of input and output terminals and the second group of input and output terminals, and the control terminal is The first control terminal is called the first control terminal; the inverter array has a group of input terminals and a group of output terminals, wherein the group of input terminals is used to access four-bit binary data, and the group of output terminals are used to output four-bit binary data, wherein the group of input terminals is called the first group of input terminals, and the group of output terminals is called the first group of output terminals; the timing control module has ten output terminals, wherein the ten output terminals are respectively called the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal, the sixth output terminal, the seventh output terminal, the eighth output terminal, the ninth output terminal and the tenth output terminal; the timing control module is used to control the coordinated work of the security storage array, the key row, the sensitive amplifier array, the inverter array, the switch control array, the write circuit and the two refresh circuits,The first output terminal, the second output terminal, the third output terminal, the fourth output terminal and the fifth output terminal of the timing control module are respectively used to output control signals, and the sixth output terminal, the seventh output terminal, the eighth output terminal, the ninth output terminal and the tenth output terminal of the timing control module are respectively used to output refresh signals. The control signal output by the first output terminal of the timing control module is recorded as ctrl0, the control signal output by the second output terminal is recorded as ctrl1, the control signal output by the third output terminal is recorded as ctrl2, the control signal output by the fourth output terminal is recorded as ctrl3, the control signal output by the fifth output terminal is recorded as ctrl4, the refresh signal output by the sixth output terminal is recorded as pre0, the refresh signal output by the seventh output terminal is recorded as pre1, and the control signal output by the eighth output terminal is recorded as ctrl4. The refresh signal output by the ninth output terminal is recorded as pre2, the refresh signal output by the ninth output terminal is recorded as pre3, and the refresh signal output by the tenth output terminal is recorded as pre4; the switch control array has two groups of input terminals, four groups of output terminals, two groups of input-output terminals and three control terminals, each group of input terminals is used to access four-bit binary data, each group of output terminals is used to output four-bit binary data, each group of input-output terminals is used to output four-bit binary data or access four-bit binary data, its two groups of input terminals are respectively referred to as its first group of input terminals and the second group of input terminals, its four groups of output terminals are respectively referred to as its first group of output terminals, the second group of output terminals, the third group of output terminals and the fourth group of output terminals, its two groups of input-output terminals are respectively referred to as its first group of input-output terminals and the second group of input terminals. The first group of output ends of the write circuit are connected to the first group of input and output ends of the security storage array, the first group of output ends of the second refresh circuit and the first group of output ends of the switch control array, respectively; the second group of output ends of the write circuit are connected to the second group of input and output ends of the security storage array, the second group of output ends of the second refresh circuit and the switch control array, respectively; the second group of output ends of the write circuit are connected to the second group of input and output ends of the security storage array, the second group of output ends of the second refresh circuit and the switch control array, respectively. The first control terminal of the write circuit is connected to the first output terminal of the timing control module, the first input terminal of the first refresh circuit is connected to the sixth output terminal of the timing control module, the second input terminal of the first refresh circuit is connected to the seventh output terminal of the timing control module, the first input terminal of the first refresh circuit is connected to the sixth output terminal of the timing control module, the second input terminal of the first refresh circuit is connected to the seventh output terminal of the timing control module, the first group of output terminals of the first refresh circuit are respectively connected to the third group of input and output terminals of the safety storage array and the first group of input terminals of the sense amplifier array, the second group of output terminals of the first refresh circuit are respectively connected to the fourth group of input terminals of the safety storage array and the third group of output terminals of the switch control array,The second group of output ends of the first refresh circuit is used to output a precharge signal, which is four-bit binary data. The third group of output ends of the first refresh circuit are respectively connected to the fifth group of input ends of the security storage array and the fourth group of output ends of the switch control array. The third group of output ends of the first refresh circuit is used to output a precharge signal, which is four-bit binary data. The first input end of the second refresh circuit is connected to the eighth output end of the timing control module. The second input end of the second refresh circuit is connected to the tenth output end of the timing control module. The third group of output ends of the second refresh circuit are respectively connected to the first group of input and output ends of the key row and the first group of input and output ends of the switch control array. The third group of output ends of the second refresh circuit are used to The fourth group of output ends of the second refresh circuit are respectively connected to the second group of input and output ends of the key row and the second group of input and output ends of the switch control array. The fourth group of output ends of the second refresh circuit are used to output the reset signal, which is four-bit binary data. The first input end of the sensitive amplifier array is used to access the external threshold voltage compare (set according to actual use requirements). The first group of output ends of the sensitive amplifier array is used to output the shaped XOR value, which is four-bit binary data. The second input end of the sensitive amplifier array is connected to the ninth output end of the timing control module. The first group of output ends of the sensitive amplifier array are respectively connected to the first group of input ends of the inverter array. The first group of input terminals of the safety storage array are connected to the first group of input terminals of the switch control array, the first group of input terminals of the safety storage array are used to access the four-bit voltage signal VDD<0:3>, the second group of input terminals of the safety storage array are used to access the four-bit word line control signal WL<0:3>, and the third group of input terminals of the safety storage array are used to access the four-bit switch control signal ctrl<0:3>; the four-bit voltage signal VDD<0:3> is used to control the power on and power off of the safety storage array, the four-bit word line control signal WL<0:3> is used to control whether the safety storage array saves the data BL<0:3> accessed by the first input and output terminals and the data BLB<0:3> accessed by the second input and output terminals, and the four-bit word line control signal ctrl<0:3> is used to control whether the safety storage array saves the data BL<0:3> accessed by the first input and output terminals and the data BLB<0:3> accessed by the second input and output terminals. Control whether the secure storage array stores the data connected to its fourth input terminal and the data connected to its fifth input terminal. The first control terminal of the key row is connected to the fifth output terminal of the timing control signal. The first input terminal of the key row is used to access the word line control signal XWL. The word line control signal XWL is used to control the transmission of the key of the key row. The first group of output terminals of the inverter array is used to output the inverted and shaped XOR value. The first group of output terminals of the inverter array is connected to the first group of input terminals of the switch control array. The first control terminal of the switch control array is connected to the second output terminal of the timing control module. The second control terminal of the switch control array is connected to the third output terminal of the timing control module. The fourth output terminal of the switch control array is connected to the timing control module.

[0040] In this embodiment, when encryption is required, first, the eighth output terminal of the timing control module outputs a refresh signal pre2 to control the first group of output terminals and the second group of output terminals of the second refresh circuit to output a clear signal, so as to refresh the first group of input and output terminals and the second group of input and output terminals of the security storage array, and clear the state of the security storage array. Thereafter, when the data to be encrypted IN<0:3> is transmitted to the write circuit, the write circuit, under the control of the control signal ctrl0 output by the first output terminal of the timing control module, converts the data to be encrypted IN<0:3> into two data with opposite phases, and outputs them to the first group of input and output terminals and the second group of input and output terminals of the security storage array in a one-to-one correspondence. The security storage array The data connected to the first group of input and output terminals and the data connected to the second group of input and output terminals are stored; then, the timing control module outputs a refresh signal pre0 through the sixth output terminal and a refresh signal pre4 through the tenth output terminal. At this time, the first refresh circuit outputs a precharge signal through the first group of output terminals to precharge the third group of input and output terminals of the security storage array, and the second refresh circuit outputs a reset signal through the third group of output terminals and the fourth group of output terminals to refresh the first group of input and output terminals and the second group of input and output terminals of the key row, and reset the state of the key row. After that, the fifth output terminal of the timing control module outputs a control signal ctrl4 to control the key row to generate a pair of keys with opposite phases through the first group of input and output terminals and the second group of input and output terminals. The first group input and output terminals are transmitted to the first group input and output terminals and the second group input and output terminals of the switch control array in a one-to-one correspondence. The third output terminal of the timing control array outputs a control signal ctrl2 to control the switch control array, and the pair of keys transmitted to it by the key row is transmitted to the fourth group input and output terminals and the fifth group input and output terminals of the security storage array in a one-to-one correspondence through the third output terminal and the fourth output terminal of the security storage array. The security storage array performs an XOR operation on the currently received pair of keys and the two data with opposite phases already stored therein, and obtains an XOR value of one bit, which is transmitted to the first group input terminal of the sensitive amplifier array through the third group input and output terminal of the security amplifier array. The ninth output terminal of the timing control module outputs a refresh signal pre3, and the sensitive amplifier array receives the refresh signal pre3. Under the control of , the XOR value of one bit outputted thereto is shaped, and the shaped XOR value is transmitted to the first group of input ends of the inverter array through the first group of output ends thereof, the inverter array inverts the shaped XOR value to obtain the XOR value with opposite phase and transmits it to the second group of input ends of the switch control array through the first group of output ends thereof, the switch control array transmits the shaped XOR value transmitted thereto by the sensitive amplifier array and the XOR value with opposite phase inverted and transmitted thereto by the inverter array to the first group of input-output ends and the second group of input-output ends of the security storage array through the first group of output ends and the second group of output ends thereof in a one-to-one correspondence, and the security storage array stores the shaped XOR value and the XOR value with opposite phase as encrypted data to realize encryption;When encrypted data has been stored in the secure storage array and needs to be decrypted, first, the sixth output terminal of the timing control module outputs a refresh signal pre0 and the tenth output terminal outputs a refresh signal pre4. At this time, the first refresh circuit, under the control of the refresh signal pre0, outputs a precharge signal to the third input-output terminal of the secure storage array through its first output terminal to precharge the secure storage array. The second refresh circuit, under the control of the refresh signal pre4, first outputs a clear signal to refresh the key row through its third group of output terminals and fourth group of output terminals, and clears the state of the first group of input-output terminals and the second group of input-output terminals of the key row. Then, the fifth output terminal of the timing control module outputs a control signal ctrl4 to control the key row to generate a pair of keys with opposite phases, which are transmitted to the first group of input-output terminals and the second group of input-output terminals of the switch control array one-to-one through its first group of input-output terminals and the second group of input-output terminals. The third output terminal of the timing control array outputs a control signal ctrl2 to control the switch control array to transmit the pair of keys transmitted to it by the key row through its third group of output terminals and the fourth group of output terminals to the fourth group of input terminals and the fifth group of input terminals of the secure storage array. At the end, the security storage array performs an XOR operation on the pair of keys currently received and the encrypted data stored therein, obtains an initial value of one bit and transmits it to the first input end of the sensitive amplifier array. The sensitive amplifier array, under the control of the refresh signal pre3 outputted by the fourth output end of the timing control module, shapes the initial value, obtains the shaped initial value and transmits it to the first group of input ends of the inverter array through its first group of output ends. The inverter array inverts the shaped initial value, obtains the initial value with the opposite phase and transmits it to the second group of input ends of the switch control array through its first group of output ends. At the input end, the switch control array transmits the one-bit initial value outputted by the sensitive amplifier array and the initial value with opposite phase outputted by the inverter array to the first group of input and output ends and the second group of input and output ends of the security storage array through its first group of output ends and the second group of output ends in a one-to-one correspondence. The security storage array stores the one-bit initial value and the initial value with opposite phase currently received. At this time, the pair of data of the one-bit initial value and the initial value with opposite phase stored in the security storage array is consistent with the pair of data of the two data with opposite phase stored in encryption, thereby realizing data decryption. ;

[0041] Embodiment 3: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figures 2 to 4As shown, the write circuit includes 4 first write units and 4 second write units, each of the first write units has an input end, an output end and a control end, each of the second write units has an input end, an output end and a control end, the control ends of the 4 first write units are connected to the control ends of the 4 second write units, and their connecting ends are the first control ends of the write circuit, the input end of the first first write unit is connected to the input end of the first second write unit, and its connecting end is the first input end of the write circuit, the input end of the second first write unit is connected to the input end of the second second write unit, and its connecting end is the second input end of the write circuit, the input end of the third first write unit is connected to the input end of the third second write unit, and its connecting end is the third input end of the write circuit, the input end of the fourth first write unit is connected to the input end of the fourth second write unit, and its connecting end is the fourth input end of the write circuit. input end, the first input end to the fourth input end of the write circuit constitute a first group of input ends of the write circuit, the output end of the first first write unit is the first output end of the write circuit, the output end of the second first write unit is the second output end of the write circuit, the output end of the third first write unit is the third output end of the write circuit, the output end of the fourth first write unit is the fourth output end of the write circuit, the first output end to the fourth output end of the write circuit constitute a first group of output ends of the write circuit, the output end of the first second write unit is the fifth output end of the write circuit, the output end of the second second write unit is the sixth output end of the write circuit, the output end of the third second write unit is the seventh output end of the write circuit, the output end of the fourth second write unit is the eighth output end of the write circuit, and the fifth output end to the eighth output end of the write circuit constitute a second group of output ends of the write circuit;Each first writing unit includes a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3 and a fourth NMOS tube N4. The source of the first PMOS tube P1, the source of the second PMOS tube P2 and the source of the third PMOS tube P3 are all connected to the power supply voltage. The gate of the first PMOS tube P1 is connected to the gate of the first NMOS tube N1, and the connection end thereof is the input end of the first writing unit. The drain of the first PMOS tube P1, the drain of the first NMOS tube N1, the fourth PMOS tube N4 and the drain of the first NMOS tube N2 are connected to the gate of the first NMOS tube N3. The gate of P4 is connected to the gate of the third NMOS tube N3, the drain of the second PMOS tube P2, the gate of the third PMOS tube P3 and the drain of the second NMOS tube N2 are connected, the gate of the second PMOS tube P2, the gate of the second NMOS tube N2 and the gate of the fourth NMOS tube N4 are connected, and the connection end thereof is the control end of the first writing unit, the drain of the third PMOS tube P3 is connected to the source of the fourth PMOS tube P4, the drain of the fourth PMOS tube P4 is connected to the drain of the third NMOS tube N3, and the connection end thereof is the output end of the first writing unit, the source of the third NMOS tube N3 and the fourth NMOS tube N4 are connected. The drain of the first NMOS tube N1 is connected, the source of the second NMOS tube N2 and the source of the fourth NMOS tube N4 are all grounded; each second writing unit includes a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7, a fifth NMOS tube N5, a sixth NMOS tube N6 and a seventh NMOS tube N7, the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6 are both connected to the power supply voltage, the gate of the fifth PMOS tube P5, the gate of the fifth NMOS tube N5 and the gate of the seventh NMOS tube N7 are connected, and the connection end is the control end of the second writing unit, the fifth PMOS tube P5 is connected to the gate of the fifth NMOS tube N5 and the gate of the seventh NMOS tube N7, and the connection end is the control end of the second writing unit, and the fifth PMOS tube P5 is connected to the gate of the fifth NMOS tube N5 and the gate of the seventh NMOS tube N7. The drain of the S transistor P5, the gate of the sixth PMOS transistor P6 and the drain of the fifth NMOS transistor N5 are connected, the drain of the sixth PMOS transistor P6 and the source of the seventh PMOS transistor P7 are connected, the gate of the sixth NMOS transistor N6 and the gate of the seventh PMOS transistor P7 are connected, and the connection end thereof is the input end of the second writing unit, the source of the sixth NMOS transistor N6 is connected to the drain of the seventh PMOS transistor P7, and the connection end thereof is the output end of the second writing unit, the drain of the sixth NMOS transistor N6 is connected to the drain of the seventh NMOS transistor N7, and the source of the seventh NMOS transistor N7 and the source of the fifth NMOS transistor N5 are both grounded. ;

[0042] In this embodiment, the working principle of the write circuit is as follows: when the first control terminal of the write circuit is connected to a high level, and when four bits of signals to be encrypted are input to the first input terminal of the write circuit, a binary signal is input to the input terminal of each first write unit and the input terminal of each second write unit. In each first write unit, the binary signal is inverted twice through an inverter composed of a first NMOS tube and a first PMOS tube and an inverter composed of a fourth PMOS tube and a third NMOS tube. Finally, the output terminal of each first write unit outputs a signal identical to the binary signal connected to its input terminal. In each second write unit, the binary signal is inverted once through an inverter composed of a seventh PMOS tube and a sixth NMOS tube. Finally, the output terminal of each second write unit outputs a signal with a phase opposite to the binary signal connected to its input terminal, so that the write circuit converts the signal to be encrypted into two 4-bit binary signals with opposite phases for output.

[0043] Embodiment 4: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 5 and Figure 6 As shown, the first refresh circuit includes three first refresh units, each of which has an input end and a group of output ends, the input end of the first first refresh unit is the first input end of the first refresh circuit, the group of output ends of the first first refresh unit is the first group of output ends of the first refresh circuit, the input end of the second first refresh unit is connected to the input end of the third first refresh unit, and its connection end is the second input end of the first refresh circuit, the group of output ends of the second first refresh unit is the second group of output ends of the first refresh circuit, and the group of output ends of the third first refresh unit is the third group of output ends of the first refresh circuit; each first refresh unit includes an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth PMOS tube P10 and an eleventh PMOS tube P11, the eighth PMOS The source of the transistor P8, the source of the ninth PMOS transistor P9, the source of the tenth PMOS transistor P10 and the source of the eleventh PMOS transistor P11 are all connected to the power supply voltage VDD, the gate of the eighth PMOS transistor P8, the gate of the ninth PMOS transistor P9, the gate of the tenth PMOS transistor P10 and the gate of the eleventh PMOS transistor P11 are connected, and the connection end thereof is the input end of the first refresh unit, the drain of the eighth PMOS transistor P8 is the first output end of the first refresh unit, the drain of the ninth PMOS tube P9 is the second output end of the first refresh unit, the drain of the tenth PMOS tube P10 is the third output end of the first refresh unit, the drain of the eleventh PMOS tube P11 is the fourth output end of the first refresh unit, and the first output end to the fourth output end of the first refresh unit constitute a group of output ends thereof.

[0044] In this embodiment, the working principle of the first refresh circuit is: when the first input end of the first refresh circuit is connected to a low level, the input end of each first refresh unit is at a low level, at this time, the eighth PMOS tube P8, the ninth PMOS tube P9, the tenth PMOS tube P10 and the eleventh PMOS tube P11 therein are turned on, and a group of output ends of each first refresh unit will output a pre-charge signal, and when the first input end of the first refresh circuit is at a high level, the first refresh circuit does not work.

[0045] Embodiment 5: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figure 7 and Figure 8 As shown, the second refresh circuit includes 4 second refresh units, each of which has an input end and a group of output ends, the input end of the first second refresh unit is connected to the input end of the second second refresh unit, and the connected end is the first input end of the second refresh circuit, the input end of the third second refresh unit is connected to the input end of the fourth second refresh unit, and the connection end is the second input end of the second refresh circuit, a group of output ends of the first second refresh unit is the first group of output ends of the second refresh circuit, a group of output ends of the second second refresh unit is the second group of output ends of the second refresh circuit, a group of output ends of the third second refresh unit is the third group of output ends of the second refresh circuit, and a group of output ends of the fourth second refresh unit is the fourth group of output ends of the second refresh circuit; each second refresh unit includes an eighth NMOS tube N8, a ninth NMOS tube N9, The tenth NMOS tube N10 and the eleventh NMOS tube N11, the source of the eighth NMOS tube N8, the source of the ninth NMOS tube N9, the source of the tenth NMOS tube N10 and the source of the eleventh NMOS tube N11 are all grounded, the gate of the eighth NMOS tube N8, the gate of the ninth NMOS tube N9, the gate of the tenth NMOS tube N10 and the gate of the eleventh NMOS tube N11 are connected, and the connection end thereof is the input end of the second refresh unit, the drain of the eighth NMOS tube N8 is the first output end of the second refresh unit, the drain of the ninth NMOS tube N9 is the second output end of the second refresh unit, the drain of the tenth NMOS tube N10 is the third output end of the second refresh unit, the drain of the eleventh NMOS tube N11 is the fourth output end of the second refresh unit, and the first output end to the fourth output end of the second refresh unit constitute a group of output ends thereof.

[0046] In this embodiment, the working principle of the second refresh circuit is: when the first input terminal of the second refresh circuit is connected to a high level, the input terminal of each second refresh unit is a high level, at this time, the eighth NMOS tube N8, the ninth NMOS tube N9, the tenth NMOS tube N10 and the eleventh NMOS tube N11 therein are all turned on, and a group of output terminals of each second refresh unit will output a reset signal, and when the first input terminal of the second refresh circuit is a low level, the second refresh circuit does not work.

[0047] Embodiment 6: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Fig. 9 and Fig.10 As shown, the inverter array includes 4 inverters, each inverter has an input end and an output end, the input end of the first inverter is the first input end of the inverter array, the input end of the second inverter is the second input end of the inverter array, the input end of the third inverter is the third input end of the inverter array, the input end of the fourth inverter is the fourth input end of the inverter array, the first input end to the fourth input end of the inverter array constitute its first group of input ends, the output end of the first inverter is the first output end of the inverter array, the output end of the second inverter is the second output end of the inverter array, and the output end of the third inverter is the The third output end, the output end of the fourth inverter is the fourth output end of the inverter array, and the first output end to the fourth output end of the inverter array constitute its first group of output ends; each inverter includes a twelfth PMOS tube P12 and a twelfth NMOS tube N12, the source of the twelfth PMOS tube P12 is connected to the power supply voltage, the gate of the twelfth PMOS tube P12 is connected to the gate of the twelfth NMOS tube N12, and the connection end thereof is the input end of the inverter, the drain of the twelfth PMOS tube P12 is connected to the drain of the twelfth NMOS tube N12, and the connection end thereof is the output end of the inverter, and the source of the twelfth NMOS tube N12 is grounded.

[0048] Embodiment 7: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Fig.11 and Fig.12As shown, the sense amplifier array includes four sense amplifiers, each of which has three input terminals and one output terminal, and the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal, the first input terminals of the four sense amplifiers are connected, and the connection terminal thereof is the first input terminal of the sense amplifier array, the second input terminals of the four sense amplifiers are connected, and the connection terminal thereof is the second input terminal of the sense amplifier array, the third input terminal of the first sense amplifier is the first input terminal of the sense amplifier array, the third input terminal of the second sense amplifier is the second input terminal of the sense amplifier array, and the third input terminal of the third sense amplifier is the third input terminal of the sense amplifier array. The third input end of the sense amplifier array is the fourth input end of the sense amplifier array, the first input end to the fourth input end of the sense amplifier array constitute its first group of input ends, the output end of the first sense amplifier is the first output end of the sense amplifier array, the output end of the second sense amplifier is the second output end of the sense amplifier array, the output end of the third sense amplifier is the third output end of the sense amplifier array, the output end of the fourth sense amplifier is the fourth output end of the sense amplifier array, and the first output end to the fourth output end of the sense amplifier array constitute the first group of output ends of the sense amplifier array;Each sensitive amplifier includes a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a thirteenth NMOS tube N13, a fourteenth MOS tube N14, a fifteenth MOS tube N15, a sixteenth MOS tube N16 and a seventeenth MOS tube N17. The source of the thirteenth PMOS tube P13, the source of the fourteenth PMOS tube P14, the source of the fifteenth PMOS tube P15 and the source of the sixteenth PMOS tube P16 are all connected to the power supply voltage. The gate of the thirteenth PMOS tube P13, the gate of the sixteenth PMOS tube P16 and the gate of the seventeenth MOS tube N17 are connected, and the connection end thereof is the second input end of the sensitive amplifier. The drain of the thirteenth PMOS tube P13, the drain of the fourteenth PMOS tube P14, the gate of the fifteenth PMOS tube P15, the gate of the fifteenth PMOS tube P16 and the gate of the seventeenth MOS tube N17 are connected. The drain of the thirteenth NMOS tube N13 is connected to the gate of the fourteenth NMOS, and the connection end thereof is the output end of the sensitive amplifier, the drain of the fifteenth PMOS tube P15, the drain of the sixteenth PMOS tube P16, the gate of the fourteenth PMOS tube P14, the gate of the thirteenth NMOS tube N13 and the drain of the fourteenth MOS tube N14 are connected, the drain of the fifteenth MOS tube N15 is connected to the source of the thirteenth NMOS tube N13, the drain of the sixteenth MOS tube N16 is connected to the source of the fourteenth MOS tube N14, the gate of the fifteenth MOS tube N15 is the first input end of the sensitive amplifier, the gate of the sixteenth MOS tube N16 is the third input end of the sensitive amplifier, the source of the fifteenth MOS tube N15, the source of the sixteenth MOS tube N16 and the drain of the seventeenth MOS tube N17 are connected, and the source of the seventeenth MOS tube N17 is grounded.;

[0049] In this embodiment, the working principle of the sense amplifier array is as follows: when the second input terminal of the sense amplifier array is connected to a four-bit low-level signal, the second input terminal of each sense amplifier is connected to a one-bit low-level signal, at which time the thirteenth PMOS tube P13 and the sixteenth PMOS tube P16 are turned on, and the seventeenth NMOS tube N17 is turned off, and the sense amplifier performs a refresh operation, pre-charging the first input terminal and the third input terminal of the sense amplifier to a high level, and resetting the internal circuit state of the sense amplifier. When the second input terminal of the sense amplifier array is a four-bit high-level signal, each sense amplifier A high-level signal is connected to the second input terminal of the sense amplifier, at which time the thirteenth PMOS tube P13 and the sixteenth PMOS tube P16 are disconnected, and the seventeenth NMOS tube N17 is turned on. The voltage difference between the external threshold voltage compare connected to the first input terminal of the sense amplifier and the third input terminal of the sense amplifier is amplified, and after positive feedback and amplification by the inverter composed of the fourteenth PMOS tube P14 and the thirteenth NMOS tube N13 and the inverter composed of the fifteenth PMOS tube P15 and the fourteenth NMOS tube N14, a bit of data is output at the output terminal of the sense amplifier.

[0050] Embodiment 8: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Fig.13 and Fig.14As shown, the key row includes 4 key units, each of which has an input end, a control end and two input-output ends, and the two input-output ends are respectively referred to as the first input-output end and the second input-output end. The input ends of the 4 key units are connected, and their connecting end is the first input end of the key row. The control ends of the 4 key units are connected, and their connecting end is the control end of the key row. The first input-output end of the first key unit is the first input-output end of the key row, the first input-output end of the second key unit is the second input-output end of the key row, and the first input-output end of the third key unit is the first input-output end of the key row. The third input-output terminal of the key row, the first input-output terminal of the fourth key unit is the fourth input-output terminal of the key row, the first input-output terminal to the fourth input-output terminal of the key row constitute the first group of input-output terminals of the key row, the second input-output terminal of the first key unit is the fifth input-output terminal of the key row, the second input-output terminal of the second key unit is the sixth input-output terminal of the key row, the second input-output terminal of the third key unit is the seventh input-output terminal of the key row, the second input-output terminal of the fourth key unit is the eighth input-output terminal of the key row, and the fifth input-output terminal to the eighth input-output terminal of the key row constitute the first group of input-output terminals of the key row. The input and output ends constitute the second group of input and output ends of the key row; each key unit includes a seventeenth PMOS tube P17, an eighteenth PMOS tube P18, an eighteenth MOS tube N18, a nineteenth MOS tube N19, a twentieth MOS tube N20 and a twenty-first MOS tube N21, the source of the seventeenth PMOS tube P17 is connected to the source of the eighteenth PMOS tube P18, and the connection end is the control end of the key unit, the gate of the eighteenth MOS tube N18 is connected to the gate of the nineteenth MOS tube N19, and the connection end is the input end of the key row, the gate of the seventeenth PMOS tube P17, the twentieth MOS tube N20 and the twenty-first MOS tube N21 The gate of the eighteenth PMOS tube P18, the drain of the eighteenth MOS tube P18, the drain of the twenty-first MOS tube N21 and the source of the nineteenth MOS tube N19 are connected, the gate of the eighteenth PMOS tube P18, the gate of the twenty-first MOS tube N21, the drain of the seventeenth PMOS tube P17, the drain of the twentieth MOS tube N20 and the source of the eighteenth MOS tube N18 are connected, the drain of the eighteenth MOS tube N18 is the first input and output end of the key unit, the drain of the nineteenth MOS tube N19 is the second input and output end of the key unit, and the source of the twentieth MOS tube N20 and the source of the twenty-first MOS tube N21 are both grounded.

[0051] In this embodiment, the working principle of the key row is as follows: when the first control terminal of the key row is connected to a high-level data, at each key unit, due to the slight difference in the production process of the MOS tubes, the inverter formed by the seventeenth PMOS tube P17 and the twentieth NMOS tube N20 and the inverter formed by the eighteenth PMOS tube P18 and the twenty-first NMOS tube N21, these two pairs of inverters amplify the slight difference into a pair of data with opposite phases through positive feedback, when the first input terminal of the key row is connected to a high level, at each key unit, the eighteenth NMOS tube N18 and the nineteenth NMOS tube N19 are turned on, at this time, the first group of input and output terminals of the key row outputs one of the two data with opposite phases, and the second group of input and output terminals of the key row outputs the other of the two data with opposite phases.

[0052] Embodiment 9: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Figures 15 to 17As shown, the switch control array includes three switch control units, each of which has a control end, a first group of input ends, a second group of input ends, a first group of output ends and a second group of output ends, the control end of the first switch control unit is the first control end of the switch control array, the control end of the second switch control unit is the second control end of the switch control array, the control end of the third switch control unit is the third control end of the switch control array, the first group of input ends of the first switch control unit is the first group of input ends of the switch control array, the second group of input ends of the first switch control unit is the second group of input ends of the switch control array, and the first group of output ends of the first switch control unit are respectively connected to the first group of input ends and The first group of input ends of the third switch control unit are connected, and its connection end is the first group of input and output ends of the switch control array, the second group of output ends of the first switch control unit are respectively connected to the second group of input ends of the second switch control unit and the second group of input ends of the third switch control unit, and its connection end is the second group of input and output ends of the switch control array, the first group of output ends of the second switch control unit is the first group of output ends of the switch control array, the second group of output ends of the second switch control unit is the second group of output ends of the switch control array, the first group of output ends of the third switch control unit is the third group of output ends of the switch control array, and the second group of output ends of the third switch control unit is the fourth group of output ends of the switch control array;Each switch control unit includes 8 switch control circuits, each of which has a control end, an input end and an output end. The control ends of the 8 switch control circuits are connected, and their connection ends are the control ends of the switch control unit. The input end of the first switch control circuit is the first input end of the switch control unit, the input end of the second switch control circuit is the second input end of the switch control unit, the input end of the third switch control circuit is the third input end of the switch control unit, and the input end of the fourth switch control circuit is the fourth input end of the switch control unit. The first input end to the fourth input end of the switch control unit constitute its first group of input ends, and the input end of the fifth switch control circuit is the first input end of the switch control unit. The switch control unit comprises five input terminals, the input terminal of the sixth switch control circuit is the sixth input terminal of the switch control unit, the input terminal of the seventh switch control circuit is the seventh input terminal of the switch control unit, the input terminal of the eighth switch control circuit is the eighth input terminal of the switch control unit, the fifth input terminal to the eighth input terminal of the switch control unit constitute the second group of input terminals of the switch control terminal element, the output terminal of the first switch control circuit is the first output terminal of the switch control unit, the output terminal of the second switch control circuit is the second output terminal of the switch control unit, the output terminal of the third switch control circuit is the third output terminal of the switch control unit, the output terminal of the fourth switch control circuit is the fourth output terminal of the switch control unit, and the switch The first output end to the fourth output end of the control unit constitute a first group of output ends of the switch control end element, the output end of the fifth switch control circuit is the fifth output end of the switch control unit, the output end of the sixth switch control circuit is the sixth output end of the switch control unit, the output end of the seventh switch control circuit is the seventh output end of the switch control unit, the output end of the eighth switch control circuit is the eighth output end of the switch control unit, and the fifth output end to the eighth output end of the switch control unit constitute a second group of output ends of the switch control end element; each switch control circuit includes a nineteenth PMOS tube P19, a twentieth PMOS tube P20, a twenty-second MOS tube N22 and a twenty-third MOS tube N23, a nineteenth The drain of the PMOS tube P19 is connected to the drain of the 22nd MOS tube N22, and the connection end thereof is the input end of the switch control circuit, the source of the 19th PMOS tube P19 is connected to the source of the 22nd MOS tube N22, and the connection end thereof is the output end of the switch control circuit, the gate of the 19th PMOS tube P19, the gate of the 23rd MOS tube N23 and the gate of the 20th PMOS tube P20 are connected, the source of the 20th PMOS tube P20 is connected to the power supply voltage, the drain of the 20th PMOS tube P20, the drain of the 23rd MOS tube N23 and the gate of the 22nd MOS tube N22 are connected, and the connection end thereof is the control end of the switch control circuit, and the source of the 23rd MOS tube N23 is grounded.;

[0053] In this embodiment, the working principle of the switch control array is as follows: when the first control terminal of the switch control array is connected to a high-level data, at this time, in each switch control unit, the inverter composed of the twenty-third NMOS tube N2 and the twentieth PMOS tube P20 inverts the high-level data into a low-level data, the twenty-second NMOS tube N22 and the nineteenth PMOS tube P19 are turned on, and the first group of input and output terminals of the switch control array outputs the signal input by its first group of input terminals. When the first control terminal of the switch control array is connected to a low-level data, the switch control array does not work.

[0054] Embodiment 10: This embodiment is basically the same as Embodiment 2, except that: in this embodiment, Fig.18 and Fig.19As shown, the security storage array includes 16 security storage units distributed in 4 rows and 4 columns, each security storage unit has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a first input-output terminal, and a second input-output terminal. The first input terminals of the four security storage units in the first row are connected, and their connection terminal is the first input terminal of the security storage array. The first input terminals of the four security storage units in the second row are connected, and their connection terminal is the second input terminal of the security storage array. The first input terminals of the four security storage units in the third row are connected, and their connection terminal is the third input terminal of the security storage array. The first input terminals of the four security storage units in the fourth row are connected, and their connection terminal is the fourth input terminal of the security storage array. The first input end to the fourth input end of the safety storage array constitute a first group of input ends of the safety storage array, the second input ends of the four safety storage units in the first row are connected, and the connection end thereof is the fifth input end of the safety storage array, the second input ends of the four safety storage units in the second row are connected, and the connection end thereof is the sixth input end of the safety storage array, the second input ends of the four safety storage units in the third row are connected, and the connection end thereof is the seventh input end of the safety storage array, the second input ends of the four safety storage units in the fourth row are connected, and the connection end thereof is the eighth input end of the safety storage array, the fifth input end to the eighth input end of the safety storage array constitute a second group of input ends of the safety storage array, and the four safety storage units in the first row are connected. The third input terminals of the four security storage units in the second row are connected, and the connection terminal thereof is the ninth input terminal of the security storage array. The third input terminals of the four security storage units in the third row are connected, and the connection terminal thereof is the tenth input terminal of the security storage array. The third input terminals of the four security storage units in the third row are connected, and the connection terminal thereof is the eleventh input terminal of the security storage array. The third input terminals of the four security storage units in the fourth row are connected, and the connection terminal thereof is the twelfth input terminal of the security storage array. The ninth input terminal to the twelfth input terminal of the security storage array constitute the third group of input terminals of the security storage array. The fourth input terminals of the four security storage units in the first column are connected, and the connection terminal thereof is the thirteenth input terminal of the security storage array. The fourth input terminals of the four security storage units in the second column are connected, and the connection terminal thereof is the thirteenth input terminal of the security storage array. The fourth input terminals of the four security storage units in the third column are connected, and their connection end is the fourteenth input terminal of the security storage array, the fourth input terminals of the four security storage units in the fourth column are connected, and their connection end is the sixteenth input terminal of the security storage array, the thirteenth input terminal to the sixteenth input terminal of the security storage array constitute a fourth group of input terminals of the security storage array, the fifth input terminals of the four security storage units in the first column are connected, and their connection end is the seventeenth input terminal of the security storage array, the fifth input terminals of the four security storage units in the second column are connected, and their connection end is the eighteenth input terminal of the security storage array, and the fifth input terminals of the four security storage units in the third column are connected,The first input and output terminals of the four safety storage units in the first column are connected, and the connection terminal thereof is the nineteenth input terminal of the safety storage array. The fifth input terminals of the four safety storage units in the fourth column are connected, and the connection terminal thereof is the twentieth input terminal of the safety storage array. The seventeenth input terminal to the twentieth input terminal of the safety storage array constitute the fifth group of input terminals of the safety storage array. The first input and output terminals of the four safety storage units in the first column are connected, and the connection terminal thereof is the first input and output terminal of the safety storage array. The first input and output terminals of the four safety storage units in the second column are connected, and the connection terminal thereof is the second input and output terminal of the safety storage array. The first input and output terminals of the four safety storage units in the third column are connected, and the connection terminal thereof is the third input and output terminal of the safety storage array. The first input and output terminals of the four safety storage units in the fourth column are connected, and the connection terminal thereof is the third input and output terminal of the safety storage array. The first input-output end to the fourth input-output end of the safety storage array constitute a first group of input-output ends of the safety storage array. The second input-output ends of the four safety storage units in the first column are connected, and the connecting end thereof is the fifth input-output end of the safety storage array. The second input-output ends of the four safety storage units in the second column are connected, and the connecting end thereof is the sixth input-output end of the safety storage array. The second input-output ends of the four safety storage units in the third column are connected, and the connecting end thereof is the seventh input-output end of the safety storage array. The second input-output ends of the four safety storage units in the fourth column are connected, and the connecting end thereof is the eighth input-output end of the safety storage array. The fifth input-output terminal to the eighth input-output terminal of the full storage array constitute the second group of input-output terminals of the safety storage array, the third input-output terminals of the four safety storage units in the first column are connected, and the connection terminal thereof is the ninth input-output terminal of the safety storage array, the third input-output terminals of the four safety storage units in the second column are connected, and the connection terminal thereof is the tenth input-output terminal of the safety storage array, the third input-output terminals of the four safety storage units in the third column are connected, and the connection terminal thereof is the eleventh input-output terminal of the safety storage array, the third input-output terminals of the four safety storage units in the fourth column are connected, and the connection terminal thereof is the twelfth input-output terminal of the safety storage array, and the ninth input-output terminal to the twelfth input-output terminal of the safety storage array constitute the safety storage array. a third group of input and output terminals of the storage array; each security storage unit includes a twenty-first PMOS tube P21, a twenty-second PMOS tube P22, a twenty-third PMOS tube P23, a twenty-fourth PMOS tube P24, a twenty-fifth PMOS tube P25, a twenty-sixth PMOS tube P26, a twenty-fourth MOS tube N24, a twenty-fifth MOS tube N25, a twenty-sixth MOS tube N26, a twenty-seventh MOS tube N27, a twenty-eighth MOS tube N28, a twenty-ninth MOS tube N29 and a first capacitor C1, a source of the twenty-first PMOS tube P21, a source of the twenty-second PMOS tube P22, a source of the twenty-fifth PMOS tube P25 and a source of the twenty-sixth PMOS tube P26 are connected,The connection end is the first input end of the security storage unit, the gate of the twenty-first PMOS tube P21, the gate of the twenty-sixth MOS tube N26, the drain of the twenty-second PMOS tube P22, the source of the twenty-seventh MOS tube N27, the source of the twenty-fifth MOS tube N25 and the source of the twenty-fourth PMOS tube P24 are connected, the gate of the twenty-second PMOS tube P22, the gate of the twenty-seventh MOS tube N27, the drain of the twenty-first PMOS tube P21, the source of the twenty-sixth MOS tube N26, the source of the twenty-fourth MOS tube N24 and the source of the twenty-third PMOS tube P23 are connected, the gate of the twenty-fourth MOS tube N24 and the gate of the twenty-fifth MOS tube N25 are connected, and the connection end is the second input end of the security storage unit, the drain of the twenty-fourth MOS tube N24 is the first input and output end of the security storage unit, the drain of the twenty-fifth MOS tube N25 is the second input and output end of the security storage unit, and the drain of the twenty-third PMOS tube P23 is the second input and output end of the security storage unit. The gate, the source of the twenty-eighth MOS tube N28 and the drain of the twenty-fifth PMOS tube P25 are connected, the gate of the twenty-fourth PMOS tube P24, the source of the twenty-ninth MOS tube N29 and the drain of the twenty-sixth PMOS tube P26 are connected, the drain of the twenty-eighth MOS tube N28 is the fourth input terminal of the security storage unit, the drain of the twenty-ninth MOS tube N29 is the fifth input terminal of the security storage unit, the gate of the twenty-eighth MOS tube N28, the gate of the twenty-ninth MOS tube N29, the gate of the twenty-fifth PMOS tube P25 and the gate of the twenty-sixth PMOS tube P26 are connected, and the connection end is the third input terminal of the security storage unit, the drain of the twenty-third PMOS tube P23, the drain of the twenty-fourth PMOS tube P24 and one end of the first capacitor C1 are connected, and the connection end is the third input and output terminal of the security storage unit, the drain of the twenty-sixth MOS tube N26, the drain of the twenty-seventh MOS tube N27 and the other end of the first capacitor C1 are all grounded.

[0055] In this embodiment, the working principle of the security storage array is as follows: when the first input terminal and the second input terminal of the security storage unit in a row of the security storage array are both connected to a high level, in each security storage unit of the row, the inverter formed by the twenty-first PMOS tube P21 and the twenty-sixth NMOS tube P26 and the inverter formed by the twenty-second PMOS tube P22 and the twenty-seventh NMOS tube N27 store the signals on the first input-output terminal and the second input-output terminal of each security storage unit of the row. At this time, the first capacitor C1 has been charged to the power supply voltage VDD through the pre-charge signal output by the first refresh circuit, so that the third input terminal of each security storage unit in the row is a high level signal. At this time, the data of the fourth input terminal and the fifth input terminal of each security storage unit in the row controls the on and off of the twenty-fifth PMOS tube P25 and the twenty-sixth PMOS tube P26, so that the first capacitor C1 and the stored signal form a discharge loop to realize data storage.

[0056] To verify the performance of the security encryption and decryption circuit of the present invention, Spectre is used to perform functional simulation on the security encryption and decryption circuit of the present invention at the standard voltage of 1.2V of TSMC 65nm process. The functional simulation waveform of the security encryption and decryption circuit of the present invention is shown in FIG. Fig. 20 Analysis Fig. 20 It can be seen that the security encryption and decryption circuit of the present invention has correct functional logic and can realize effective data encryption and decryption functions.

Claims

1. A secure encryption and decryption circuit, characterized in that The invention comprises a secure storage array, a timing control module, a key row, a sense amplifier array, an inverter array, a switch control array, a write circuit, and two refresh circuits, which are respectively referred to as a first refresh circuit and a second refresh circuit. The secure storage array is implemented using hardware multiplexing technology to reduce hardware resource overhead. When encryption is required, first, the timing control module controls the second refresh circuit to output a reset signal to refresh the security storage array, and resets the state of the security storage array. Afterwards, when the data to be encrypted is transmitted to the write circuit, the write circuit, under the control of the timing control module, converts the data to be encrypted into two data with opposite phases and outputs them to the security storage array. The security storage array stores the two data with opposite phases outputted thereto by the write circuit. Then, the timing control module controls the first refresh circuit to output a precharge signal to precharge the security storage array, and controls the second refresh circuit to output a reset signal to refresh the key row and reset the state of the key row. Afterwards, the timing control module controls the key row to generate a pair of keys with opposite phases and transmits them to the switch control array. The switch control array The pair of keys transmitted by the key row is transmitted to the secure storage array. The secure storage array performs an XOR operation on the pair of keys currently transmitted by the key row and two data with opposite phases already stored therein to obtain a one-bit XOR value, and transmits the XOR value to the sense amplifier array. Under the control of the timing control module, the sense amplifier array shapes the XOR value output thereto, and the shaped XOR value is transmitted to the inverter array. The inverter array inverts the shaped XOR value to obtain an XOR value with opposite phase, which is transmitted to the switch control array. The switch control array transmits both the shaped XOR value transmitted by the sense amplifier array and the XOR value with opposite phases inverted and transmitted thereto by the inverter array to the secure storage array. The secure storage array stores the shaped XOR value and the XOR value with opposite phases as encrypted data to achieve encryption. When encrypted data has been stored in the secure storage array and needs to be decrypted, first, the timing control module controls the first refresh circuit to output a precharge signal to precharge the secure storage array, and controls the second refresh circuit to output a reset signal to refresh the key row and reset the state of the key row. Then, the timing control module controls the key row to generate a pair of keys with opposite phases and transmit them to the switch control array. The switch control array transmits the pair of keys transmitted by the key row to the secure storage array. The secure storage array performs an XOR operation on the pair of keys it currently receives and the encrypted data stored therein to obtain an initial value of one bit for transmission. To the sensitive amplifier array, the sensitive amplifier array, under the control of the timing control module, shapes the initial value, obtains the shaped initial value and transmits it to the inverter array. The inverter array inverts the shaped initial value to obtain an initial value with an opposite phase and transmits it to the switch control array. The switch control array transmits both the one-bit initial value output by the sensitive amplifier array and the initial value with an opposite phase output by the inverter array to the secure storage array. The secure storage array stores the one-bit initial value and the initial value with an opposite phase. At this time, the pair of data stored in the secure storage array is consistent with the pair of data stored in the write circuit during encryption, thereby achieving data decryption.

2. The security encryption and decryption circuit according to claim 1, characterized in that The write circuit has a group of input terminals, two groups of output terminals and a control terminal, wherein the group of input terminals is used to receive four-bit binary data, and each group of output terminals is used to output four-bit binary data, and the input terminals are referred to as the first group of input terminals, the two groups of output terminals are referred to as the first group of output terminals and the second group of output terminals, and the control terminal is referred to as the first control terminal; the first refresh circuit has two input terminals and three groups of output terminals, wherein the two input terminals are referred to as the first input terminal and the second input terminal, and each group of output terminals is used to output four-bit binary data, and the three groups of output terminals are referred to as the first group of output terminals, the second group of output terminals and the third group of output terminals; the second refresh circuit has two input terminals and three groups of output terminals, wherein the two input terminals are referred to as the first input terminal and the second input terminal, and each group of output terminals is used to output four-bit binary data, and the three groups of output terminals are referred to as the first group of output terminals, the second group of output terminals and the third group of output terminals; The circuit has two input terminals and four groups of output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, each group of output terminals is used to output four-bit binary data, and the four groups of output terminals are respectively referred to as the first group of output terminals, the second group of output terminals, the third group of output terminals, and the fourth group of output terminals; the sense amplifier array has two input terminals, one group of input terminals, and one group of output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the one group of input terminals is used to receive four-bit binary data, and the one group of input terminals is referred to as the first group of input terminals, the one group of output terminals is used to output four-bit binary data, and the one group of output terminals is referred to as the first group of output terminals; The secure storage array has five groups of input terminals and three groups of input and output terminals, each of which is used to receive four-bit binary data, and each of which is used to output four-bit binary data or receive four-bit binary data. The five groups of input terminals are respectively referred to as the first group of input terminals, the second group of input terminals, the third group of input terminals, the fourth group of input terminals, and the fifth group of input terminals, and the three groups of input and output terminals are respectively referred to as the first group of input and output terminals, the second group of input and output terminals, and the third group of input and output terminals; the key row has one input terminal, two groups of input and output terminals, and one control terminal, the one input terminal is referred to as the first input terminal, each of which is used to output four-bit binary data or receive four-bit binary data, and the two groups of input terminals are referred to as the first input terminal. The output ends are respectively referred to as the first group of input and output ends and the second group of input and output ends, and the control end is referred to as the first control end; the inverter array has a group of input ends and a group of output ends, wherein the group of input ends is used to access four-bit binary data, and the group of output ends are used to output four-bit binary data, wherein the group of input ends is referred to as the first group of input ends, and the group of output ends is referred to as the first group of output ends; the timing control module has ten output ends, wherein the ten output ends are respectively referred to as the first output end, the second output end, the third output end, the fourth output end, the fifth output end, the sixth output end, the seventh output end, the eighth output end, the ninth output end and the tenth output end; the timing control module is used to control the security storage array, the The key row, the sense amplifier array, the inverter array, the switch control array, the write circuit and the two refresh circuits work in coordination, the first output end, the second output end, the third output end, the fourth output end and the fifth output end of the timing control module are respectively used to output control signals, the sixth output end, the seventh output end, the eighth output end, the ninth output end and the tenth output end of the timing control module are respectively used to output refresh signals, the control signal output by the first output end of the timing control module is recorded as ctrl0, the control signal output by the second output end is recorded as ctrl1, the control signal output by the third output end is recorded as ctrl2, the control signal output by the fourth output end is recorded as ctrl3, and the control signal output by the sixth output end is recorded as ctrl4. The control signal output by the fifth output terminal is recorded as ctrl4, the refresh signal output by the sixth output terminal is recorded as pre0, the refresh signal output by the seventh output terminal is recorded as pre1, the refresh signal output by the eighth output terminal is recorded as pre2, the refresh signal output by the ninth output terminal is recorded as pre3, and the refresh signal output by the tenth output terminal is recorded as pre4; the switch control array has two groups of input terminals, four groups of output terminals, two groups of input and output terminals and three control terminals, each group of input terminals is used to receive four-bit binary data, each group of output terminals is used to output four-bit binary data, and each group of input and output terminals is used to output four-bit binary data or receive four-bit binary data. The two groups of input terminals are respectively referred to as the first group of input terminals and the second group of input terminals.Its four groups of output terminals are respectively referred to as its first group of output terminals, its second group of output terminals, its third group of output terminals and its fourth group of output terminals, its two groups of input and output terminals are respectively referred to as its first group of input and output terminals and its second group of input and output terminals, and its three control terminals are respectively referred to as its first control terminal, its second control terminal and its third control terminal; the four bits of data to be encrypted are recorded as IN<0:3>, the first group of input terminals of the write circuit is used to access the four bits of data to be encrypted IN<0:3>, the first group of output terminals of the write circuit is used to output one of two data with opposite phases, the second group of output terminals of the write circuit is used to output the other of the two data with opposite phases, and the first group of output terminals of the write circuit are respectively connected to the The first group of input and output terminals of the safety storage array, the first group of output terminals of the second refresh circuit and the first group of output terminals of the switch control array are connected, the second group of output terminals of the write circuit are respectively connected to the second group of input and output terminals of the safety storage array, the second group of output terminals of the second refresh circuit and the second group of output terminals of the switch control array, the first control terminal of the write circuit is connected to the first output terminal of the timing control module, the first input terminal of the first refresh circuit is connected to the sixth output terminal of the timing control module, the second input terminal of the first refresh circuit is connected to the seventh output terminal of the timing control module, and the first control terminal of the first refresh circuit is connected to the seventh output terminal of the timing control module. An input end of the first refresh circuit is connected to the sixth output end of the timing control module, a second input end of the first refresh circuit is connected to the seventh output end of the timing control module, a first group of output ends of the first refresh circuit are respectively connected to the third group of input and output ends of the safety storage array and the first group of input ends of the sense amplifier array, a second group of output ends of the first refresh circuit are respectively connected to the fourth group of input ends of the safety storage array and the third group of output ends of the switch control array, a second group of output ends of the first refresh circuit are used to output a precharge signal, which is a four-bit binary data, a third group of output ends of the first refresh circuit are respectively connected to the safety The fifth group of input terminals of the storage array is connected to the fourth group of output terminals of the switch control array. The third group of output terminals of the first refresh circuit is used to output a precharge signal, which is four-bit binary data. The first input terminal of the second refresh circuit is connected to the eighth output terminal of the timing control module. The second input terminal of the second refresh circuit is connected to the tenth output terminal of the timing control module. The third group of output terminals of the second refresh circuit is respectively connected to the first group of input and output terminals of the key row and the first group of input and output terminals of the switch control array. The third group of output terminals of the second refresh circuit is used to output a clear signal, which is four-bit binary data.The fourth group of output ends of the second refresh circuit are respectively connected to the second group of input and output ends of the key row and the second group of input and output ends of the switch control array. The fourth group of output ends of the second refresh circuit is used to output a clear signal, which is four-bit binary data. The first input end of the sense amplifier array is used to receive an external threshold voltage compare. The first group of output ends of the sense amplifier array is used to output a shaped exclusive OR value, which is four-bit binary data. The second input end of the sense amplifier array is connected to the ninth output end of the timing control module. The first group of output ends of the sense amplifier array is respectively connected to the first group of input ends of the inverter array and the first group of input ends of the switch control array. The first group of input ends of the security storage array is used to receive a four-bit voltage signal VDD<0:3>. The second group of input ends of the security storage array is used to receive a four-bit word line control signal WL<0:3>. The third group of input ends of the security storage array is used to receive a four-bit switch control signal ctrl<0:3>. The four-bit voltage signal VDD<0:3> is used to control the The secure storage array is powered on and off. The four-bit wordline control signal WL<0:3> is used to control whether the secure storage array stores the data BL<0:3> connected to its first input / output terminal and the data BLB<0:3> connected to its second input / output terminal. The four-bit wordline control signal ctrl<0:3> is used to control whether the secure storage array stores the data connected to its fourth input terminal and the data connected to its fifth input terminal. The first control terminal of the key row is connected to the fifth output terminal of the timing control signal. The first input terminal of the key row is used to receive the wordline control signal XWL, which is used to control the transmission of the key in the key row. The first group of output terminals of the inverter array is used to output the inverted and shaped XOR value. The first group of output terminals of the inverter array is connected to the first group of input terminals of the switch control array. The first control terminal of the switch control array is connected to the second output terminal of the timing control module. The second control terminal of the switch control array is connected to the third output terminal of the timing control module. The switch control array is connected to the fourth output terminal of the timing control module.

3. The security encryption and decryption circuit according to claim 2, characterized in that The write circuit includes 4 first write units and 4 second write units, each first write unit has an input end, an output end and a control end, each second write unit has an input end, an output end and a control end, the control ends of the 4 first write units are connected to the control ends of the 4 second write units, and their connection ends are the first control end of the write circuit, the input end of the first first write unit is connected to the input end of the first second write unit, and its connection end is the first input end of the write circuit, the input end of the second first write unit is connected to the input end of the second second write unit, and its connection end is the second input end of the write circuit, the input end of the third first write unit is connected to the input end of the third second write unit, and its connection end is the third input end of the write circuit, the input end of the fourth first write unit is connected to the input end of the fourth second write unit, and its connection end is the fourth input end of the write circuit, and the first The first input end to the fourth input end constitute a first group of input ends of the write circuit, the output end of the first first write unit is the first output end of the write circuit, the output end of the second first write unit is the second output end of the write circuit, the output end of the third first write unit is the third output end of the write circuit, the output end of the fourth first write unit is the fourth output end of the write circuit, the first output end to the fourth output end of the write circuit constitute a first group of output ends of the write circuit, the output end of the first second write unit is the fifth output end of the write circuit, the output end of the second second write unit is the sixth output end of the write circuit, the output end of the third second write unit is the seventh output end of the write circuit, the output end of the fourth second write unit is the eighth output end of the write circuit, and the fifth output end to the eighth output end of the write circuit constitute a second group of output ends of the write circuit; Each of the first writing units includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube. The source of the first PMOS tube, the source of the second PMOS tube and the source of the third PMOS tube are all connected to the power supply voltage. The gate of the first PMOS tube is connected to the gate of the first NMOS tube, and the connection end thereof is the input end of the first writing unit. The drain of the first PMOS tube, the drain of the first NMOS tube, the gate of the fourth PMOS tube and the gate of the third NMOS tube are connected. The drain of the second PMOS tube, The gate of the third PMOS tube is connected to the drain of the second NMOS tube, the gate of the second PMOS tube, the gate of the second NMOS tube and the gate of the fourth NMOS tube are connected, and the connection end thereof is the control end of the first write unit, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube, and the connection end thereof is the output end of the first write unit, the source of the third NMOS tube is connected to the drain of the fourth NMOS tube, and the source of the first NMOS tube, the source of the second NMOS tube and the source of the fourth NMOS tube are all grounded; Each of the second write units includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to a power supply voltage. The gate of the fifth PMOS transistor, the gate of the fifth NMOS transistor, and the gate of the seventh NMOS transistor are connected, and their connection ends serve as the control end of the second write unit. The drain of the fifth PMOS transistor, the gate of the sixth PMOS transistor, and the drain of the fifth NMOS transistor are connected. The drain of the sixth PMOS transistor and the source of the seventh PMOS transistor are connected. The gate of the sixth NMOS transistor and the gate of the seventh PMOS transistor are connected, and their connection ends serve as the input end of the second write unit. The source of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor, and their connection ends serve as the output end of the second write unit. The drain of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor. The source of the seventh NMOS transistor and the source of the fifth NMOS transistor are both grounded.

4. The security encryption and decryption circuit according to claim 2, characterized in that The first refresh circuit includes three first refresh units, each of which has an input end and a group of output ends. The input end of the first first refresh unit is the first input end of the first refresh circuit, the group of output ends of the first first refresh unit is the first group of output ends of the first refresh circuit, the input end of the second first refresh unit is connected to the input end of the third first refresh unit, and the connection end thereof is the second input end of the first refresh circuit, the group of output ends of the second first refresh unit is the second group of output ends of the first refresh circuit, and the group of output ends of the third first refresh unit is the third group of output ends of the first refresh circuit; Each of the first refresh units includes an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube and an eleventh PMOS tube. The source of the eighth PMOS tube, the source of the ninth PMOS tube, the source of the tenth PMOS tube and the source of the eleventh PMOS tube are all connected to the power supply voltage VDD. The gate of the eighth PMOS tube, the gate of the ninth PMOS tube, the gate of the tenth PMOS tube and the gate of the eleventh PMOS tube are connected, and their connection ends are the input ends of the first refresh unit. The drain of the eighth PMOS tube is the first output end of the first refresh unit. The drain of the ninth PMOS tube is the second output end of the first refresh unit. The drain of the tenth PMOS tube is the third output end of the first refresh unit. The drain of the eleventh PMOS tube is the fourth output end of the first refresh unit. The first output end to the fourth output end of the first refresh unit constitute a group of its output ends.

5. The security encryption and decryption circuit according to claim 2, characterized in that The second refresh circuit includes four second refresh units, each of which has an input end and a group of output ends. The input end of the first second refresh unit is connected to the input end of the second second refresh unit, and the connected end is the first input end of the second refresh circuit. The input end of the third second refresh unit is connected to the input end of the fourth second refresh unit, and the connection end is the second input end of the second refresh circuit. The group of output ends of the first second refresh unit is the first group of output ends of the second refresh circuit. The group of output ends of the second second refresh unit is the second group of output ends of the second refresh circuit. The group of output ends of the third second refresh unit is the third group of output ends of the second refresh circuit. The group of output ends of the fourth second refresh unit is the fourth group of output ends of the second refresh circuit. Each of the second refresh units includes an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube and an eleventh NMOS tube. The source of the eighth NMOS tube, the source of the ninth NMOS tube, the source of the tenth NMOS tube and the source of the eleventh NMOS tube are all grounded. The gate of the eighth NMOS tube, the gate of the ninth NMOS tube, the gate of the tenth NMOS tube and the gate of the eleventh NMOS tube are connected, and their connection ends are the input ends of the second refresh unit. The drain of the eighth NMOS tube is the first output end of the second refresh unit, the drain of the ninth NMOS tube is the second output end of the second refresh unit, the drain of the tenth NMOS tube is the third output end of the second refresh unit, and the drain of the eleventh NMOS tube is the fourth output end of the second refresh unit. The first output end to the fourth output end of the second refresh unit constitute a group of its output ends.

6. The security encryption and decryption circuit according to claim 2, characterized in that The inverter array includes four inverters, each having an input and an output. The input of the first inverter is the first input of the inverter array, the input of the second inverter is the second input of the inverter array, the input of the third inverter is the third input of the inverter array, and the input of the fourth inverter is the fourth input of the inverter array. The first to fourth inputs of the inverter array constitute a first group of inputs. The output of the first inverter is the first output of the inverter array, the output of the second inverter is the second output of the inverter array, the output of the third inverter is the third output of the inverter array, and the output of the fourth inverter is the fourth output of the inverter array. The first to fourth outputs of the inverter array constitute a first group of outputs. Each of the inverters includes a twelfth PMOS transistor and a twelfth NMOS transistor. The source of the twelfth PMOS transistor is connected to the power supply voltage. The gate of the twelfth PMOS transistor is connected to the gate of the twelfth NMOS transistor, and the connection end thereof serves as the input end of the inverter. The drain of the twelfth PMOS transistor is connected to the drain of the twelfth NMOS transistor, and the connection end thereof serves as the output end of the inverter. The source of the twelfth NMOS transistor is grounded.

7. The security encryption and decryption circuit according to claim 2, characterized in that The sense amplifier array includes four sense amplifiers, each sense amplifier has three input terminals and one output terminal, and the three input terminals are respectively referred to as the first input terminal, the second input terminal and the third input terminal. The first input terminals of the four sense amplifiers are connected, and the connection terminal thereof is the first input terminal of the sense amplifier array. The second input terminals of the four sense amplifiers are connected, and the connection terminal thereof is the second input terminal of the sense amplifier array. The third input terminal of the first sense amplifier is the first input terminal of the sense amplifier array. The third input terminal of the second sense amplifier is the second input terminal of the sense amplifier array. The third input terminal of the third sense amplifier is the the third input end, the third input end of the fourth sense amplifier is the fourth input end of the sense amplifier array, the first input end to the fourth input end of the sense amplifier array constitute a first group of input ends thereof, the output end of the first sense amplifier is the first output end of the sense amplifier array, the output end of the second sense amplifier is the second output end of the sense amplifier array, the output end of the third sense amplifier is the third output end of the sense amplifier array, the output end of the fourth sense amplifier is the fourth output end of the sense amplifier array, and the first output end to the fourth output end of the sense amplifier array constitute a first group of output ends of the sense amplifier array; Each of the sensitive amplifiers includes a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor. The source of the thirteenth PMOS transistor, the source of the fourteenth PMOS transistor, the source of the fifteenth PMOS transistor, and the source of the sixteenth PMOS transistor are all connected to the power supply voltage. The gate of the thirteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth NMOS transistor are connected, and the connection end thereof is the second input end of the sensitive amplifier. The drain of the thirteenth PMOS transistor, the drain of the fourteenth PMOS tube, the gate of the fifteenth PMOS tube, the drain of the thirteenth NMOS tube, and the drain of the tenth The gates of the four NMOS transistors are connected, and the connection end thereof serves as the output end of the sense amplifier. The drain of the fifteenth PMOS transistor, the drain of the sixteenth PMOS transistor, the gate of the fourteenth PMOS transistor, the gate of the thirteenth NMOS transistor, and the drain of the fourteenth NMOS transistor are connected. The drain of the fifteenth NMOS transistor is connected to the source of the thirteenth NMOS transistor. The drain of the sixteenth NMOS transistor is connected to the source of the fourteenth NMOS transistor. The gate of the fifteenth NMOS transistor serves as the first input end of the sense amplifier. The gate of the sixteenth NMOS transistor serves as the third input end of the sense amplifier. The source of the fifteenth NMOS transistor, the source of the sixteenth NMOS transistor, and the drain of the seventeenth NMOS transistor are connected. The source of the seventeenth NMOS transistor is grounded.

8. The security encryption and decryption circuit according to claim 2, characterized in that The key row includes four key units, each of which has an input end, a control end, and two input and output ends. The two input and output ends are respectively referred to as the first input and output end and the second input and output end. The input ends of the four key units are connected, and their connection end is the first input end of the key row. The control ends of the four key units are connected, and their connection end is the control end of the key row. The first input and output end of the first key unit is the first input and output end of the key row. The first input and output end of the second key unit is the second input and output end of the key row. The first input and output end of the third key unit is the third input and output end of the key row. The fourth key unit is connected to the first input and output end of the key row. The first input-output end of the first key unit is the fourth input-output end of the key row, the first input-output end to the fourth input-output end of the key row constitute the first group of input-output ends of the key row, the second input-output end of the second key unit is the sixth input-output end of the key row, the second input-output end of the third key unit is the seventh input-output end of the key row, the second input-output end of the fourth key unit is the eighth input-output end of the key row, and the fifth input-output end to the eighth input-output end of the key row constitute the second group of input-output ends of the key row; Each of the key units includes a seventeenth PMOS tube, an eighteenth PMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube, and a twenty-first NMOS tube. The source of the seventeenth PMOS tube is connected to the source of the eighteenth PMOS tube, and the connection end is the control end of the key unit. The gate of the eighteenth NMOS tube is connected to the gate of the nineteenth NMOS tube, and the connection end is the input end of the key row. The gate of the seventeenth PMOS tube, the gate of the twentieth NMOS tube, and the drain of the eighteenth PMOS tube are connected. The gate of the 18th PMOS tube, the gate of the 21st NMOS tube, the drain of the 17th PMOS tube, the drain of the 20th NMOS tube and the source of the 18th NMOS tube are connected. The drain of the 18th NMOS tube is the first input and output terminal of the key unit, the drain of the 19th NMOS tube is the second input and output terminal of the key unit, and the source of the 20th NMOS tube and the source of the 21st NMOS tube are both grounded.

9. The secure encryption and decryption circuit according to claim 2, characterized in that The switch control array includes three switch control units, each of which has a control end, a first group of input ends, a second group of input ends, a first group of output ends, and a second group of output ends. The control end of the first switch control unit is the first control end of the switch control array, the control end of the second switch control unit is the second control end of the switch control array, and the control end of the third switch control unit is the third control end of the switch control array. The first group of input ends of the first switch control unit is the first group of input ends of the switch control array, the second group of input ends of the first switch control unit is the second group of input ends of the switch control array, and the first group of output ends of the first switch control unit is connected to the first group of input ends and the second group of output ends of the second switch control unit, respectively. The first group of input terminals of the third switch control unit are connected, and the connection terminals thereof are the first group of input and output terminals of the switch control array. The second group of output terminals of the first switch control unit are connected to the second group of input terminals of the second switch control unit and the second group of input terminals of the third switch control unit, respectively, and the connection terminals thereof are the second group of input and output terminals of the switch control array. The first group of output terminals of the second switch control unit are the first group of output terminals of the switch control array, and the second group of output terminals of the second switch control unit are the second group of output terminals of the switch control array. The first group of output terminals of the third switch control unit are the third group of output terminals of the switch control array, and the second group of output terminals of the third switch control unit are the fourth group of output terminals of the switch control array. Each of the switch control units includes 8 switch control circuits, each of which has a control end, an input end, and an output end. The control ends of the 8 switch control circuits are connected, and their connection ends are the control ends of the switch control unit. The input end of the first switch control circuit is the first input end of the switch control unit, the input end of the second switch control circuit is the second input end of the switch control unit, the input end of the third switch control circuit is the third input end of the switch control unit, and the input end of the fourth switch control circuit is the fourth input end of the switch control unit. The first input end to the fourth input end of the switch control unit constitute its first group of input ends. The input end of the fifth switch control circuit is the fifth input end of the switch control unit, the input end of the sixth switch control circuit is the sixth input end of the switch control unit, the input end of the seventh switch control circuit is the seventh input end of the switch control unit, and the input end of the eighth switch control circuit is the eighth input end of the switch control unit. The fifth to eighth input terminals of the unit constitute the second group of input terminals of the switch control end unit, the output terminal of the first switch control circuit is the first output terminal of the switch control unit, the output terminal of the second switch control circuit is the second output terminal of the switch control unit, the output terminal of the third switch control circuit is the third output terminal of the switch control unit, the output terminal of the fourth switch control circuit is the fourth output terminal of the switch control unit, the first to fourth output terminals of the switch control unit constitute the first group of output terminals of the switch control end unit, the output terminal of the fifth switch control circuit is the fifth output terminal of the switch control unit, the output terminal of the sixth switch control circuit is the sixth output terminal of the switch control unit, the output terminal of the seventh switch control circuit is the seventh output terminal of the switch control unit, the output terminal of the eighth switch control circuit is the eighth output terminal of the switch control unit, and the fifth to eighth output terminals of the switch control unit constitute the second group of output terminals of the switch control end unit; Each of the switch control circuits includes a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-second NMOS transistor, and a twenty-third NMOS transistor. The drain of the nineteenth PMOS transistor is connected to the drain of the twenty-second NMOS transistor, and the connection end thereof is the input end of the switch control circuit. The source of the nineteenth PMOS transistor is connected to the source of the twenty-second NMOS transistor, and the connection end thereof is the output end of the switch control circuit. The gate of the nineteenth PMOS transistor, the gate of the twenty-third NMOS transistor, and the gate of the twentieth PMOS transistor are connected. The source of the twentieth PMOS transistor is connected to the power supply voltage. The drain of the twentieth PMOS transistor, the drain of the twenty-third NMOS transistor, and the gate of the twenty-second NMOS transistor are connected, and the connection end thereof is the control end of the switch control circuit. The source of the twenty-third NMOS transistor is grounded.

10. The secure encryption and decryption circuit according to claim 2, characterized in that The security storage array includes 16 security storage units distributed in 4 rows and 4 columns, each of which has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a first input-output terminal, and a second input-output terminal. The first input terminals of the four security storage units in the first row are connected, and their connection terminal is the first input terminal of the security storage array. The first input terminals of the four security storage units in the second row are connected, and their connection terminal is the second input terminal of the security storage array. The first input terminals of the four security storage units in the third row are connected, and their connection terminal is the third input terminal of the security storage array. The first input terminals of the four security storage units in the fourth row are connected, and their connection terminal is the security storage array. The fourth input end of the full storage array, the first input end to the fourth input end of the safety storage array constitute the first group of input ends of the safety storage array, the second input ends of the four safety storage units in the first row are connected, and their connection end is the fifth input end of the safety storage array, the second input ends of the four safety storage units in the second row are connected, and their connection end is the sixth input end of the safety storage array, the second input ends of the four safety storage units in the third row are connected, and their connection end is the seventh input end of the safety storage array, the second input ends of the four safety storage units in the fourth row are connected, and their connection end is the eighth input end of the safety storage array, the fifth input end to the eighth input end of the safety storage array The third input terminals of the four safety storage units in the first row are connected, and the connection terminal thereof is the ninth input terminal of the safety storage array. The third input terminals of the four safety storage units in the second row are connected, and the connection terminal thereof is the tenth input terminal of the safety storage array. The third input terminals of the four safety storage units in the third row are connected, and the connection terminal thereof is the eleventh input terminal of the safety storage array. The third input terminals of the four safety storage units in the fourth row are connected, and the connection terminal thereof is the twelfth input terminal of the safety storage array. The ninth input terminal to the twelfth input terminal of the safety storage array constitute the third group of input terminals of the safety storage array. The fourth input terminals of the four safety storage units in the first column are connected, and the connection terminal thereof is the tenth input terminal of the safety storage array. The input ends of the four safety storage units in the second column are connected, and their connection end is the thirteenth input end of the safety storage array. The fourth input ends of the four safety storage units in the third column are connected, and their connection end is the fourteenth input end of the safety storage array. The fourth input ends of the four safety storage units in the fourth column are connected, and their connection end is the fifteenth input end of the safety storage array. The fourth input ends of the four safety storage units in the fourth column are connected, and their connection end is the sixteenth input end of the safety storage array. The thirteenth to sixteenth input ends of the safety storage array constitute a fourth group of input ends of the safety storage array. The fifth input ends of the four safety storage units in the first column are connected, and their connection end is the seventeenth input end of the safety storage array.The fifth input terminals of the four safety storage units in the second column are connected, and the connection terminal thereof is the eighteenth input terminal of the safety storage array. The fifth input terminals of the four safety storage units in the third column are connected, and the connection terminal thereof is the nineteenth input terminal of the safety storage array. The fifth input terminals of the four safety storage units in the fourth column are connected, and the connection terminal thereof is the twentieth input terminal of the safety storage array. The seventeenth to twentieth input terminals of the safety storage array constitute the fifth group of input terminals of the safety storage array. The first input and output terminals of the four safety storage units in the first column are connected, and the connection terminal thereof is the first input and output terminal of the safety storage array. The first input and output terminals of the four safety storage units in the second column are connected, and the connection terminal thereof is the second input and output terminal of the safety storage array. The first input and output terminals of the four safety storage units in the third column are connected, and the connection terminal thereof is the third input and output terminal of the safety storage array. The first input and output terminals of the four safety storage units in the fourth column are connected, and the connection terminal thereof is the fourth input and output terminal of the safety storage array. The first input and output terminals to the fourth input and output terminals of the safety storage array constitute the first group of input and output terminals of the safety storage array. The second input and output terminals of the four safety storage units in the first column are connected, and the connection terminal thereof is the safety storage array. The fifth input and output end of the full storage array is connected to the second input and output ends of the four safety storage units in the second column, and the connection end thereof is the sixth input and output end of the safety storage array. The second input and output ends of the four safety storage units in the third column are connected to each other, and the connection end thereof is the seventh input and output end of the safety storage array. The second input and output ends of the four safety storage units in the fourth column are connected to each other, and the connection end thereof is the eighth input and output end of the safety storage array. The fifth input and output ends to the eighth input and output ends of the safety storage array constitute the second group of input and output ends of the safety storage array. The third input and output ends of the four safety storage units in the first column are connected to each other. The third input and output terminals of the four security storage units in the second column are connected, and their connection terminal is the ninth input and output terminal of the security storage array. The third input and output terminals of the four security storage units in the third column are connected, and their connection terminal is the tenth input and output terminal of the security storage array. The third input and output terminals of the four security storage units in the fourth column are connected, and their connection terminal is the twelfth input and output terminal of the security storage array. The ninth input and output terminals to the twelfth input and output terminals of the security storage array constitute a third group of input and output terminals of the security storage array. Each of the security storage units includes a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-fourth NMOS transistor, a twenty-fifth NMOS transistor, a twenty-sixth NMOS transistor, a twenty-seventh NMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth NMOS transistor and a first capacitor. The source of the twenty-first PMOS transistor, the source of the twenty-second PMOS transistor, the source of the twenty-fifth PMOS transistor and the source of the twenty-sixth PMOS transistor are connected, and the connection end is the first input end of the security storage unit. The gate of the twenty-first PMOS tube, the gate of the twenty-sixth NMOS tube, the drain of the twenty-second PMOS tube, the source of the twenty-seventh NMOS tube, the source of the twenty-fifth NMOS tube and the source of the twenty-fourth PMOS tube are connected; the gate of the twenty-second PMOS tube, the gate of the twenty-seventh NMOS tube, the drain of the twenty-first PMOS tube, the source of the twenty-sixth NMOS tube, the source of the twenty-fourth NMOS tube and the source of the twenty-third PMOS tube are connected; the gate of the twenty-fourth NMOS tube and the gate of the twenty-fifth NMOS tube are connected; The connection end is the second input end of the security storage unit, the drain of the twenty-fourth NMOS tube is the first input-output end of the security storage unit, the drain of the twenty-fifth NMOS tube is the second input-output end of the security storage unit, the gate of the twenty-third PMOS tube, the source of the twenty-eighth NMOS tube and the drain of the twenty-fifth PMOS tube are connected, the gate of the twenty-fourth PMOS tube, the source of the twenty-ninth NMOS tube and the drain of the twenty-sixth PMOS tube are connected, the drain of the twenty-eighth NMOS tube is the fourth input end of the security storage unit, and the gate of the twenty-third PMOS tube, the source of the twenty-ninth NMOS tube and the drain of the twenty-sixth PMOS tube are connected. The drain of the ninth NMOS transistor is the fifth input terminal of the security storage unit. The gate of the twenty-eighth NMOS transistor, the gate of the twenty-ninth NMOS transistor, the gate of the twenty-fifth PMOS transistor, and the gate of the twenty-sixth PMOS transistor are connected, and the connection end is the third input terminal of the security storage unit. The drain of the twenty-third PMOS transistor, the drain of the twenty-fourth PMOS transistor, and one end of the first capacitor are connected, and the connection end is the third input and output terminal of the security storage unit. The drain of the twenty-sixth NMOS transistor, the drain of the twenty-seventh NMOS transistor, and the other end of the first capacitor are all grounded.

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