Design optimization method and system for integrated circuit layout

Abstract

The invention discloses a design optimization method and system for an integrated circuit layout, and relates to the technical field of integrated circuits, the system can accurately identify current density abnormal regions through a concentrated region analysis module, and calculates electromigration tolerance coefficients Drxs according to signal interconnection situation data in the regions, a signal interference coefficient Xgxs is constructed through a layout design analysis module in combination with a material state and attribute data, a trade-off evaluation index Qgzs is obtained through a trained risk prediction model, and the series of steps ensure that the balance state between electromigration tolerance and signal integrity is accurately evaluated. Finally, the optimization management module compares the Qgzs with a preset evaluation threshold value Q, and whether the current design reaches a balance state or not can be accurately judged. And if not, the system automatically sends out an optimization command, and optimization adjustment is carried out aiming at the electromigration tolerance and the signal integrity.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a design optimization method and system for an integrated circuit layout. Background Art

[0002] In the wide field of integrated circuit design and optimization, layout design is a key link. The design of integrated circuit layout involves multi-level metal layer layout, wire arrangement, and power and ground arrangement. Specifically, there is often a contradiction between electromigration tolerance and signal integrity. For example, in order to improve electromigration tolerance, designers may increase the width or thickness of the wire, which can effectively reduce the current density and avoid material migration and wire damage caused by electromigration. However, it may also lead to a larger wire crossing area, thereby increasing signal interference. Since the two conflict in design goals, how to find a balance between electromigration tolerance and signal integrity is a major challenge in integrated circuit layout design.

[0003] Current integrated circuit design optimization methods have some obvious deficiencies in dealing with the contradiction between electromigration tolerance and signal integrity optimization. Traditional design optimization methods often focus on optimizing a single aspect, ignoring the importance of balancing different requirements in the overall design. For example, many existing systems may focus on optimizing electromigration tolerance in the early stages of design, while ignoring the signal integrity issues that may be introduced, resulting in the final design having the potential for serious signal interference. Similarly, some methods may focus on improving signal integrity while ignoring the requirements for electromigration tolerance, which may lead to early failure of wires in high current density areas.

[0004] Therefore, in the design, it is necessary to seek a relatively good balance point through simulation analysis so that the circuit can achieve a balance between performance and reliability. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a design optimization method and system for an integrated circuit layout, which solves the problems in the above-mentioned background technology.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: a design optimization system for integrated circuit layout, including a simulation module, a data acquisition module, a data processing module, a centralized area analysis module, a layout design analysis module and an optimization management module;

[0007] The simulation module is used to establish a physical model of the integrated circuit using simulation software;

[0008] The data acquisition module is used to perform simulation test on the integrated circuit layout according to the physical model to monitor and obtain relevant signal interconnection status data information, and at the same time, to acquire relevant material status data information and relevant material property data information of the integrated circuit layout according to the physical model;

[0009] The data processing module is used to pre-process the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, construct a layout data set, and combine the dimensionless processing technology to unify the units of the relevant data information in the layout data set;

[0010] The centralized area analysis module is used to extract the current density Dmd in the relevant signal interconnection situation data information, identify the current density abnormal area in the integrated circuit layout based on the current density Dmd value, and construct the electromigration tolerance coefficient Drxs through the relevant signal interconnection situation data information in the current density abnormal area;

[0011] The layout design analysis module is used to construct a signal interference coefficient Xgxs according to relevant material state data information and relevant material property data information, and obtain a trade-off evaluation index Qgzs in combination with a trained layout design risk prediction model;

[0012] The optimization management module is used to pre-set an evaluation threshold Q, and compare and analyze the evaluation threshold Q with the trade-off evaluation index Qgzs to measure the balance between electromigration tolerance and signal integrity in the current physical model.

[0013] Preferably, the simulation module is used to establish a physical model in the simulation software that is consistent with the actual manufacturing process, wherein the physical model includes the geometric structure of the circuit, the electrical, thermal and mechanical properties of the conductor material, and defines the working environment conditions of the physical model, including temperature and working voltage;

[0014] The geometric structure of the circuit includes the circuit layout, metal layers, contact holes and through holes.

[0015] Preferably, the data acquisition module includes a collection unit and a monitoring unit;

[0016] The acquisition unit is used to acquire and record relevant material status data information and relevant material attribute data information of the integrated circuit layout in the physical model, wherein the relevant material status data information includes the number of metal layers n in the physical model, the width Dk of the corresponding metal layer, the spacing Dxj between adjacent metal layers, the signal strength Xhqd of the corresponding metal layer, the length Dc of the corresponding metal layer, and the spacing Djj between the wire and the bottom line in the corresponding area in the physical model;

[0017] The relevant material attribute data information includes the electrical conductivity Ddz of the conductor material and the magnetic permeability Cdz of the conductor material in the corresponding area in the physical model;

[0018] The monitoring unit is used to monitor the relevant signal interconnection status data information of the integrated circuit in real time, wherein the relevant signal interconnection status data information includes the current density Dmd, the roughness of the wire surface and the number of hot spots Rds in the corresponding area in the physical model.

[0019] Preferably, the data processing module includes a preprocessing unit and an integration unit;

[0020] The preprocessing unit is used to preprocess the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, and the preprocessing includes removing noise, filling missing values ​​and data smoothing operations;

[0021] The integration unit is used to aggregate data information from different sources, construct a layout data set after aggregation, and transmit the layout data set to the cloud platform. At the same time, combined with dimensionless processing technology, the units of related data information in the layout data set are unified so that the range of related data information in the layout data set falls between 0 and 1.

[0022] Preferably, the centralized area analysis module includes a preliminary identification unit and a risk analysis unit;

[0023] The preliminary identification unit is used to extract features from the relevant signal interconnection situation data information to obtain the current density Dmd in the corresponding area. The current density Dmd is obtained by the following formula: Among them, I represents the current value, and Jmj represents the cross-sectional area of ​​the wire;

[0024] Based on the current density Dmd in several groups of regions, and combined with the statistical averaging algorithm, the average current density is obtained and the standard deviation of the current density, σDmd, based on the average current density and the standard deviation σDmd of the current density, and set the abnormal limit value V, which is obtained by the following method: Where k is a constant;

[0025] Identify the abnormal current density areas in the integrated circuit layout, the details are as follows:

[0026] If the current density Dmd in the corresponding area exceeds the abnormal limit V, the corresponding area will be identified as an abnormal current density area;

[0027] If the current density Dmd in the corresponding area does not exceed the abnormal limit value V, the corresponding area will be identified as not being an abnormal current density area.

[0028] Preferably, the risk analysis unit is used to extract the relevant signal interconnection situation data information in the current density abnormal area from the relevant signal interconnection situation data information of the integrated circuit, and construct the electromigration tolerance coefficient Drxs in the current density abnormal area by dimensionlessly processing the current density Dmd and the number of hot spots Rds, which is specifically obtained according to the following formula:

[0029]

[0030] Wherein, Ccd represents the roughness of the conductor surface, α and β are weight values, and C represents the first correction constant.

[0031] Preferably, the layout design analysis module includes a signal analysis unit and a comprehensive analysis unit;

[0032] The signal analysis unit is used to obtain the metal layer cross-degree Jjcd according to the relevant material state data information and the relevant signal interconnection situation data information, which is specifically obtained in the following manner:

[0033]

[0034] Where i = 1, 2, 3, ..., n, n represents the number of metal layers, Dc i Expressed as the length of the i-th metal layer, Dk i Expressed as the width of the i-th metal layer, Dxj ij It is expressed as the distance from the i-th metal layer to the adjacent j-th metal layer, Xhqd i It is represented as the signal strength of the i-th metal layer;

[0035] According to the relevant material property data information and combined with the metal layer cross-degree Jjcd, the signal interference coefficient Xgxs is constructed, which is obtained in the following way:

[0036]

[0037] Wherein, Djj represents the distance between the conductor and the bottom line in the current density anomaly area, Ddz represents the electrical conductivity of the conductor material in the current density anomaly area, Cdz represents the magnetic permeability of the conductor material in the current density anomaly area, a1, a2, a3 and a4 are all weight values, and P represents the second correction constant.

[0038] Preferably, the comprehensive analysis unit is used to input the electromigration tolerance coefficient Drxs in the current density abnormal area and the signal interference coefficient Xgxs in the corresponding area into the trained layout design risk prediction model to calculate the trade-off evaluation index Qgzs, which is specifically obtained in the following manner:

[0039]

[0040] Preferably, the optimization management module includes a comparison and analysis unit and an optimization unit;

[0041] The comparison and analysis unit is used to compare and analyze the trade-off evaluation index Qgzs with the evaluation threshold Q to measure the balance between electromigration tolerance and signal integrity in the current physical model. The specific analysis content is as follows:

[0042] If the trade-off evaluation index Qgzs=the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are in a balanced state;

[0043] If the trade-off evaluation index Qgzs is greater than the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are not in a balanced state, and a first optimization command will be issued at this time;

[0044] If the trade-off evaluation index Qgzs is less than the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are not in a balanced state, and a second optimization command will be issued at this time;

[0045] The optimization unit is used to receive the optimization command issued by the comparison and analysis unit, and take optimization measures according to the received optimization command. The specific contents are as follows:

[0046] If the No. 1 optimization command is issued, the wire size will be adjusted in the abnormal current density area, and the wire width and thickness will be increased by 5% at a time until the electromigration tolerance and signal integrity in the physical model are in a balanced state. The adjustment operation will be stopped, and a heat dissipation layer will be added in the hot spot area.

[0047] If the No. 2 optimization command is issued, a shielding layer or shielding wire will be introduced in the abnormal current density area to isolate the interference source, and the wire size will be adjusted in the abnormal current density area, reducing the wire width and thickness by 5% of the original at a time until the electromigration tolerance and signal integrity in the physical model are in a balanced state and the adjustment operation is stopped.

[0048] A design optimization method for an integrated circuit layout comprises the following steps:

[0049] Step 1: Use simulation software to establish a physical model of the integrated circuit;

[0050] Step 2: According to the physical model, the integrated circuit layout is simulated and tested to monitor and obtain relevant signal interconnection status data information, and at the same time, the relevant material status data information and relevant material property data information of the integrated circuit layout are collected and obtained according to the physical model;

[0051] Step 3: pre-process the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, construct a layout data set, and combine the dimensionless processing technology to unify the units of the relevant data information in the layout data set;

[0052] Step 4: extract the current density Dmd in the relevant signal interconnection situation data information, identify the abnormal current density area in the integrated circuit layout based on the current density Dmd value, and construct the electromigration tolerance coefficient Drxs through the relevant signal interconnection situation data information in the abnormal current density area;

[0053] Step 5: construct the signal interference coefficient Xgxs according to the relevant material status data information and the relevant material attribute data information, and obtain the trade-off evaluation index Qgzs by combining the trained layout design risk prediction model;

[0054] Step 6: pre-set an evaluation threshold Q, and compare and analyze the evaluation threshold Q with the trade-off evaluation index Qgzs to measure the balance between electromigration tolerance and signal integrity in the current physical model.

[0055] The present invention provides a design optimization method and system for integrated circuit layout, which has the following beneficial effects:

[0056] (1) The system can accurately identify the abnormal current density areas through the centralized area analysis module, and calculate the electromigration tolerance coefficient Drxs based on the signal interconnection status data in these areas. Through the layout design analysis module, combined with the material state and property data, the signal interference coefficient Xgxs is constructed, and the trade-off evaluation index Qgzs is obtained through the trained risk prediction model. This series of steps ensures an accurate evaluation of the balance between electromigration tolerance and signal integrity. Finally, the optimization management module can accurately determine whether the current design has reached a balanced state by comparing Qgzs with the preset evaluation threshold Q. If it is not balanced, the system will automatically issue an optimization command to optimize and adjust the electromigration tolerance and signal integrity. This intelligent optimization management further effectively avoids the conflicts and incoordination problems that may occur in the traditional design process, thereby improving the reliability and performance of the design and ensuring the long-term stable operation of the integrated circuit.

[0057] (2) By calculating the metal layer cross-degree Jjcd, the system can quantify the cross-complexity of the metal layer in the circuit and the signal transmission density, so as to more accurately evaluate the potential problems of signal interference. Secondly, the comprehensive analysis unit uses the metal layer cross-degree Jjcd and related material property data information to construct the signal interference coefficient Xgxs, so as to reduce signal interference in the later optimization design. In short, the calculated metal layer cross-degree Jjcd and signal interference coefficient Xgxs can reveal potential problems and signal integrity risks in the design, thereby providing a scientific basis for adjustment and optimization. This precise analysis not only improves the reliability of the circuit design, but also enhances the overall performance of the system.

[0058] (3) The trade-off evaluation index Qgzs is calculated to quantify the relationship between electromigration risk and signal integrity. The comparison analysis unit compares the trade-off evaluation index Qgzs with the evaluation threshold to accurately measure the balance between electromigration tolerance and signal integrity. This comparison can accurately identify whether optimization is needed in the system, thereby improving the reliability and stability of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A block diagram of a design optimization system for an integrated circuit layout of the present invention;

[0060] Figure 2 The present invention is a schematic flow chart of a design optimization method for an integrated circuit layout. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] Example 1

[0063] See also Figure 1 , the present invention provides a design optimization system for integrated circuit layout, including a simulation module, a data acquisition module, a data processing module, a centralized area analysis module, a layout design analysis module and an optimization management module;

[0064] The simulation module is used to establish a physical model of the integrated circuit using simulation software;

[0065] The data acquisition module is used to perform simulation test on the integrated circuit layout according to the physical model to monitor and obtain relevant signal interconnection status data information, and at the same time, to acquire relevant material status data information and relevant material property data information of the integrated circuit layout according to the physical model;

[0066] The data processing module is used to pre-process the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, construct a layout data set, and combine the dimensionless processing technology to unify the units of the relevant data information in the layout data set;

[0067] The centralized area analysis module is used to extract the current density Dmd in the relevant signal interconnection situation data information, identify the current density abnormal area in the integrated circuit layout based on the current density Dmd value, and construct the electromigration tolerance coefficient Drxs through the relevant signal interconnection situation data information in the current density abnormal area;

[0068] The layout design analysis module is used to construct a signal interference coefficient Xgxs according to relevant material state data information and relevant material property data information, and obtain a trade-off evaluation index Qgzs in combination with a trained layout design risk prediction model;

[0069] The optimization management module is used to pre-set an evaluation threshold Q, and compare and analyze the evaluation threshold Q with the trade-off evaluation index Qgzs to measure the balance between electromigration tolerance and signal integrity in the current physical model.

[0070] During the operation of this system, the system includes multiple groups of modules, which can further effectively improve the accuracy and reliability of integrated circuit layout design. Specifically, the simulation module uses simulation software to establish a physical model to ensure a high degree of simulation of the actual circuit behavior in the design stage; the data acquisition module obtains data information such as signal interconnection status, material status and properties through simulation testing, providing a sufficient data basis for subsequent analysis; the data processing module ensures the consistency and comparability of data through preprocessing and dimensionless processing technology, thereby building a more comprehensive and accurate layout data set; the centralized area analysis module can identify electromigration risk areas based on abnormal values ​​of current density, and generate electromigration tolerance coefficient Drxs, providing key indicators for electromigration analysis; the optimization management module provides an effective optimization path by comparing the weighted evaluation index Qgzs with the preset threshold, further ensuring a relatively good balance between electromigration tolerance and signal integrity. In short, the beneficial effect of this system is that it can accurately predict and optimize the relationship between electromigration tolerance and signal integrity during the integrated circuit design stage, reduce the risk of electromigration and signal interference problems in circuit design, thereby extending the service life of the integrated circuit and improving its overall performance. Through the application of this system, designers can more effectively deal with the contradiction between electromigration and signal integrity optimization in integrated circuits, thereby improving design efficiency and long-term reliability of circuits.

[0071] Example 2

[0072] Please refer to Figure 1 Specifically: the simulation module is used to establish a physical model that is consistent with the actual manufacturing process in the simulation software, wherein the physical model includes the geometric structure of the circuit, the electrical, thermal and mechanical properties of the conductor material, ensuring that the simulation model can accurately reflect the actual performance of the material, and defining the working environment conditions of the physical model, including temperature and working voltage, to provide accurate simulation conditions to simulate the actual working state;

[0073] The geometric structure of the circuit includes the circuit layout, metal layers, contact holes and through holes.

[0074] The data acquisition module includes a collection unit and a monitoring unit;

[0075] The acquisition unit is used to acquire and record relevant material status data information and relevant material attribute data information of the integrated circuit layout in the physical model, wherein the relevant material status data information includes the number of metal layers n in the physical model, the width Dk of the corresponding metal layer, the spacing Dxj between adjacent metal layers, the signal strength Xhqd of the corresponding metal layer, the length Dc of the corresponding metal layer, and the spacing Djj between the wire and the bottom line in the corresponding area in the physical model;

[0076] The relevant material attribute data information includes the electrical conductivity Ddz of the conductor material and the magnetic permeability Cdz of the conductor material in the corresponding area in the physical model;

[0077] The monitoring unit is used to monitor the relevant signal interconnection status data information of the integrated circuit in real time, wherein the relevant signal interconnection status data information includes the current density Dmd, the roughness of the wire surface and the number of hot spots Rds in the corresponding area in the physical model.

[0078] The width Dk of the corresponding metal layer, the spacing Dxj between adjacent metal layers, the length Dc of the corresponding metal layer, and the spacing Djj between the wire and the bottom line mentioned above can be monitored and obtained through an optical microscope;

[0079] The signal strength Xhqd of the corresponding metal layer can be monitored and obtained by an oscilloscope;

[0080] The conductivity Ddz of the conductor material can be monitored and obtained by a conductivity meter;

[0081] The magnetic permeability Cdz of the conductor material can be monitored and obtained by a magnetic permeability tester;

[0082] The data processing module includes a preprocessing unit and an integration unit;

[0083] The preprocessing unit is used to preprocess the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, and the preprocessing includes noise removal, missing value filling and data smoothing operations, wherein the missing value filling methods include mean filling, median filling, interpolation filling and regression filling;

[0084] The integration unit is used to aggregate data information from different sources, construct a layout data set after aggregation, and transmit the layout data set to the cloud platform. At the same time, combined with dimensionless processing technology, the units of related data information in the layout data set are unified so that the range of related data information in the layout data set falls between 0 and 1.

[0085] In this embodiment, first, the simulation module can establish a physical model in the simulation software that is highly consistent with the actual manufacturing process, including the geometric structure of the circuit, the electrical, thermal and mechanical properties of the conductor material, so that the simulation model can not only accurately reflect the actual performance of the material, but also define accurate working environment conditions, such as temperature and working voltage, so as to provide a reliable basis for simulating the actual working state. The geometric structure of the circuit describes the layout, metal layer, contact hole and through hole of the circuit in detail, providing comprehensive data support for accurate simulation. Secondly, the data acquisition module comprehensively collects the relevant material state and attribute information of the integrated circuit layout through the acquisition unit and the monitoring unit. The acquisition unit records the number of layers, width, adjacent layer spacing, signal strength, length and spacing between the wire and the bottom line of the metal layer, and the monitoring unit monitors the current density, the roughness of the wire surface and the number of hot spots in real time. The comprehensive collection of this information ensures the accurate understanding of the internal state of the integrated circuit, and provides a detailed data basis for subsequent data processing and optimization. The data processing module removes noise, fills missing values ​​and smoothes the data collected through the preprocessing unit to ensure the accuracy and integrity of the data. Methods for filling missing values ​​include mean filling, median filling, interpolation filling and regression filling, which improve the reliability of the data. The integration unit aggregates data from different sources, constructs a layout data set, and transmits it to the cloud platform. Combined with dimensionless processing technology, the integration unit unifies the data range between 0 and 1, which not only improves the data processing efficiency, but also enhances the accuracy of data analysis. Overall, the system can effectively optimize the design of integrated circuit layouts, improve the reliability and performance of the design, and provide strong support for electromigration tolerance and signal integrity optimization through precise modeling, multi-dimensional data acquisition and advanced data processing technology.

[0086] Example 3

[0087] Please refer to Figure 1 ,Specifically: the centralized area analysis module includes a preliminary identification unit and a risk analysis unit;

[0088] The preliminary identification unit is used to extract features from the relevant signal interconnection situation data information to obtain the current density Dmd in the corresponding area. The current density Dmd is obtained by the following formula: Among them, I represents the current value, and Jmj represents the cross-sectional area of ​​the wire;

[0089] Based on the current density Dmd in several groups of regions, and combined with the statistical averaging algorithm, the average current density is obtained and the standard deviation of the current density, σDmd, based on the average current density and the standard deviation σDmd of the current density, and set the abnormal limit value V, which is obtained by the following method: Where k is a constant; it usually takes a value of 1-3, corresponding to different confidence levels, and the specific value is set by the user (according to actual conditions);

[0090] Identify the abnormal current density areas in the integrated circuit layout, the details are as follows:

[0091] If the current density Dmd in the corresponding area exceeds the abnormal limit V, the corresponding area will be identified as an abnormal current density area;

[0092] If the current density Dmd in the corresponding area does not exceed the abnormal limit value V, the corresponding area will be identified as not being an abnormal current density area.

[0093] The risk analysis unit is used to extract the relevant signal interconnection situation data information in the current density abnormal area from the relevant signal interconnection situation data information of the integrated circuit, and construct the electromigration tolerance coefficient Drxs in the current density abnormal area by dimensionlessly processing the current density Dmd and the number of hot spots Rds, which is specifically obtained according to the following formula:

[0094]

[0095] In the formula, Ccd represents the roughness of the conductor surface, α and β are weight values, wherein 0<α≤1, 0<β≤1, and α+β=1, and C represents the first correction constant.

[0096] The roughness Ccd of the conductor surface mentioned above can be monitored and obtained by a profilometer;

[0097] The number of hot spots Rds refers to the phenomenon that the temperature of a specific area in an integrated circuit is significantly higher than that of other areas due to reasons such as excessive current density, concentrated power consumption or uneven heat dissipation. This phenomenon is particularly common in semiconductor chips, integrated circuits and high-density circuit boards. The number of hot spots Rds can be obtained by monitoring with an infrared thermal imager.

[0098] In this embodiment, the preliminary identification unit can accurately obtain the current density Dmd of each area by extracting the features of the relevant signal interconnection situation data information. Further, the average current density and its standard deviation are calculated by the statistical averaging algorithm, so as to set the abnormal limit. This process can effectively identify the abnormal current density area, which helps to timely discover the possible electromigration risk area. Secondly, the risk analysis unit further analyzes the relevant signal interconnection situation data information in the abnormal current density area. Through the dimensionless processing technology, the electromigration tolerance coefficient Drxs is constructed. This analysis method can comprehensively consider the roughness of the wire surface and its weight value, and accurately evaluate the electromigration tolerance. This process not only provides a quantitative analysis of the electromigration risk, but also provides a scientific basis for the evaluation and optimization of the electromigration risk by determining the electromigration tolerance coefficient Drxs. In general, the effective integration of these functions can significantly improve the ability to identify abnormal current density areas and evaluate electromigration risks in integrated circuit layout design. It ensures that potential electromigration problems can be discovered and corrected in time during the design stage, thereby improving the reliability and stability of the integrated circuit and optimizing the balance between electromigration tolerance and signal integrity during the design process.

[0099] Example 4

[0100] Please refer to Figure 1 ,Specifically: the layout design analysis module includes a signal analysis unit and a comprehensive analysis unit;

[0101] The signal analysis unit is used to obtain the metal layer cross-degree Jjcd according to the relevant material state data information and the relevant signal interconnection situation data information, which is specifically obtained in the following manner:

[0102]

[0103] Where i = 1, 2, 3, ..., n, n represents the number of metal layers, Dc i Expressed as the length of the i-th metal layer, Dk i Expressed as the width of the i-th metal layer, Dxj ij It is expressed as the distance from the i-th metal layer to the adjacent j-th metal layer, Xhqd i It is represented as the signal strength of the i-th metal layer;

[0104] According to the relevant material property data information and combined with the metal layer cross-degree Jjcd, the signal interference coefficient Xgxs is constructed, which is obtained in the following way:

[0105]

[0106] Wherein, Djj represents the distance between the conductor and the bottom line in the current density anomaly area, Ddz represents the electrical conductivity of the conductor material in the current density anomaly area, Cdz represents the magnetic permeability of the conductor material in the current density anomaly area, a1, a2, a3 and a4 are all weight values, among which, 0<a1≤1, 0<a2≤1, 0<a3≤1, 0<a4≤1, and a1+a2+a3+a4=1, and P represents the second correction constant.

[0107] In this embodiment, the signal analysis unit evaluates the complexity and potential interference of signal transmission by calculating the cross-degree Jjcd of the metal layer. This formula can accurately evaluate the cross-degree of each metal layer and help identify those areas where the signal transmission path is complex and may cause signal interference. This analysis can effectively reveal the source of signal interference in the integrated circuit, thereby providing a basis for improving the design. Secondly, the comprehensive analysis unit uses the metal layer cross-degree Jjcd and related material property data information to construct the signal interference coefficient Xgxs. This coefficient takes into account a variety of factors and can further accurately reflect the impact of signal interference on circuit performance. In general, the integration and functions of these modules enable the integrated circuit layout design optimization system to deeply analyze and optimize the signal transmission and interference problems in the circuit, so as to effectively identify and solve problems that may affect circuit performance, improve design quality and enhance the overall performance of the system.

[0108] Example 5

[0109] Please refer to Figure 1 Specifically: the comprehensive analysis unit is used to input the electromigration tolerance coefficient Drxs in the current density abnormal area and the signal interference coefficient Xgxs in the corresponding area into the trained layout design risk prediction model to calculate the trade-off evaluation index Qgzs, which is obtained specifically in the following way:

[0110]

[0111] The optimization management module includes a comparison and analysis unit and an optimization unit;

[0112] The comparison and analysis unit is used to compare and analyze the trade-off evaluation index Qgzs with the evaluation threshold Q to measure the balance between electromigration tolerance and signal integrity in the current physical model. The specific analysis content is as follows:

[0113] If the trade-off evaluation index Qgzs=the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are in a balanced state;

[0114] If the trade-off evaluation index Qgzs is greater than the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are not in a balanced state, and a first optimization command will be issued at this time;

[0115] If the trade-off evaluation index Qgzs is less than the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are not in a balanced state, and a second optimization command will be issued at this time;

[0116] The optimization unit is used to receive the optimization command issued by the comparison and analysis unit, and take optimization measures according to the received optimization command. The specific contents are as follows:

[0117] If the No. 1 optimization command is issued, the wire size will be adjusted in the abnormal current density area, and the wire width and thickness will be increased by 5% at a time until the electromigration tolerance and signal integrity in the physical model are in a balanced state. The adjustment operation will be stopped, and a heat dissipation layer will be added in the hot spot area to effectively reduce the local temperature, thereby reducing the electromigration problem caused by high temperature;

[0118] If the No. 2 optimization command is issued, a shielding layer or shielding wire will be introduced in the abnormal current density area to isolate the interference source and further improve the signal quality. The wire size will be adjusted in the abnormal current density area, and the width and thickness of the wire will be reduced by 5% of the original at a time until the electromigration tolerance and signal integrity in the physical model are in a balanced state. The adjustment operation will be stopped to reduce the capacitive coupling effect between parallel traces and reduce signal crosstalk.

[0119] In this embodiment, the Drxs in the abnormal current density area and the signal interference coefficient Xgxs in the corresponding area are input into the trained layout design risk prediction model through the comprehensive analysis unit, and the calculated trade-off evaluation index Qgzs can accurately evaluate the balance between electromigration tolerance and signal integrity. The comparison analysis unit can effectively measure the risk status of the current design by comparing the trade-off evaluation index Qgzs with the evaluation threshold, and issue corresponding optimization commands according to the actual situation to ensure the pertinence and effectiveness of the design optimization. Optimization command No. 1: When the trade-off evaluation index Qgzs is greater than the evaluation threshold Q, the system will take measures to increase the width and thickness of the wire, and add a heat dissipation layer in the hot spot area. This adjustment can effectively increase the electromigration tolerance of the wire, while reducing the local temperature, improving the reliability of the design, and reducing the electromigration problem caused by high temperature. Optimization command No. 2: When the trade-off evaluation index Qgzs < the evaluation threshold Q, the system will introduce a shielding layer or shielding wire to isolate the interference source, further improve the signal quality, and reduce the width and thickness of the wire. This adjustment helps reduce the capacitive coupling effect between parallel traces, reduces signal crosstalk, and thus improves signal integrity. The system can automatically trigger optimization measures based on the real-time calculated evaluation index Qgzs and preset thresholds, reduce manual intervention, and improve the efficiency and accuracy of the design process. By automatically adjusting the wire size and introducing shielding measures, the system can dynamically adapt to changes in the design, ensure the balance between electromigration tolerance and signal integrity in the design process, and reduce the risk of design failure. These optimization measures ensure that the integrated circuit design effectively responds to electromigration and signal interference problems, and improves the overall performance and reliability of the integrated circuit.

[0120] Example 6

[0121] Please refer to Figure 1 and Figure 2 , specifically: A design optimization method for an integrated circuit layout, comprising the following steps,

[0122] Step 1: Use simulation software to establish a physical model of the integrated circuit;

[0123] Step 2: According to the physical model, the integrated circuit layout is simulated and tested to monitor and obtain relevant signal interconnection status data information, and at the same time, the relevant material status data information and relevant material property data information of the integrated circuit layout are collected and obtained according to the physical model;

[0124] Step 3: pre-process the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, construct a layout data set, and combine the dimensionless processing technology to unify the units of the relevant data information in the layout data set;

[0125] Step 4: extract the current density Dmd in the relevant signal interconnection situation data information, identify the abnormal current density area in the integrated circuit layout based on the current density Dmd value, and construct the electromigration tolerance coefficient Drxs through the relevant signal interconnection situation data information in the abnormal current density area;

[0126] Step 5: construct the signal interference coefficient Xgxs according to the relevant material status data information and the relevant material attribute data information, and obtain the trade-off evaluation index Qgzs by combining the trained layout design risk prediction model;

[0127] Step 6: pre-set an evaluation threshold Q, and compare and analyze the evaluation threshold Q with the trade-off evaluation index Qgzs to measure the balance between electromigration tolerance and signal integrity in the current physical model.

[0128] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A design optimization system for integrated circuit layout, Features: It includes simulation module, data acquisition module, data processing module, centralized area analysis module, layout design analysis module and optimization management module; The simulation module is used to establish a physical model of the integrated circuit using simulation software; The data acquisition module is used to perform simulation test on the integrated circuit layout according to the physical model to monitor and obtain relevant signal interconnection status data information, and at the same time, to acquire relevant material status data information and relevant material property data information of the integrated circuit layout according to the physical model; The data processing module is used to pre-process the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, construct a layout data set, and combine the dimensionless processing technology to unify the units of the relevant data information in the layout data set; The centralized area analysis module is used to extract the current density Dmd in the relevant signal interconnection situation data information, identify the current density abnormal area in the integrated circuit layout based on the current density Dmd value, and construct the electromigration tolerance coefficient Drxs through the relevant signal interconnection situation data information in the current density abnormal area; The layout design analysis module is used to construct a signal interference coefficient Xgxs according to relevant material state data information and relevant material property data information, and obtain a trade-off evaluation index Qgzs in combination with a trained layout design risk prediction model; The optimization management module is used to pre-set an evaluation threshold Q, and compare and analyze the evaluation threshold Q with the trade-off evaluation index Qgzs to measure the balance between electromigration tolerance and signal integrity in the current physical model.

2. The integrated circuit layout design optimization system according to claim 1, Features: The simulation module is used to establish a physical model in the simulation software that is consistent with the actual manufacturing process, wherein the physical model includes the geometric structure of the circuit, the electrical, thermal and mechanical properties of the conductor material, and defines the working environment conditions of the physical model, including temperature and working voltage; The geometric structure of the circuit includes the circuit layout, metal layers, contact holes and through holes.

3. The integrated circuit layout design optimization system according to claim 1, Features: The data acquisition module includes a collection unit and a monitoring unit; The acquisition unit is used to acquire and record relevant material status data information and relevant material attribute data information of the integrated circuit layout in the physical model, wherein the relevant material status data information includes the number of metal layers n in the physical model, the width Dk of the corresponding metal layer, the spacing Dxj between adjacent metal layers, the signal strength Xhqd of the corresponding metal layer, the length Dc of the corresponding metal layer, and the spacing Djj between the wire and the bottom line in the corresponding area in the physical model; The relevant material attribute data information includes the electrical conductivity Ddz of the conductor material and the magnetic permeability Cdz of the conductor material in the corresponding area in the physical model; The monitoring unit is used to monitor the relevant signal interconnection status data information of the integrated circuit in real time, wherein the relevant signal interconnection status data information includes the current density Dmd, the roughness of the wire surface and the number of hot spots Rds in the corresponding area in the physical model.

4. The integrated circuit layout design optimization system according to claim 1, Features: The data processing module includes a preprocessing unit and an integration unit; The preprocessing unit is used to preprocess the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, and the preprocessing includes removing noise, filling missing values ​​and data smoothing operations; The integration unit is used to aggregate data information from different sources, construct a layout data set after aggregation, and transmit the layout data set to the cloud platform. At the same time, combined with dimensionless processing technology, the units of related data information in the layout data set are unified so that the range of related data information in the layout data set falls between 0 and 1.

5. The integrated circuit layout design optimization system according to claim 3, Features: The centralized area analysis module includes a preliminary identification unit and a risk analysis unit; The preliminary identification unit is used to extract features from the relevant signal interconnection situation data information to obtain the current density Dmd in the corresponding area; Based on the current density Dmd in several groups of regions, and combined with the statistical averaging algorithm, the average current density is obtained and the standard deviation of the current density, σDmd, based on the average current density and the standard deviation σDmd of the current density, and set the abnormal limit value V, which is obtained by the following method: Where k is a constant; Identify the abnormal current density areas in the integrated circuit layout, the details are as follows: If the current density Dmd in the corresponding area exceeds the abnormal limit V, the corresponding area will be identified as an abnormal current density area; If the current density Dmd in the corresponding area does not exceed the abnormal limit value V, the corresponding area will be identified as not being an abnormal current density area.

6. The integrated circuit layout design optimization system according to claim 5, Features: The risk analysis unit is used to extract the relevant signal interconnection situation data information in the current density abnormal area from the relevant signal interconnection situation data information of the integrated circuit, and construct the electromigration tolerance coefficient Drxs in the current density abnormal area by dimensionlessly processing the current density Dmd and the number of hot spots Rds, which is specifically obtained according to the following formula: Wherein, Ccd represents the roughness of the conductor surface, α and β are weight values, and C represents the first correction constant.

7. The integrated circuit layout design optimization system according to claim 6, Features: The layout design analysis module includes a signal analysis unit and a comprehensive analysis unit; The signal analysis unit is used to obtain the metal layer cross-degree Jjcd according to the relevant material state data information and the relevant signal interconnection situation data information, which is specifically obtained in the following manner: Where i = 1, 2, 3, ..., n, n represents the number of metal layers, Dc i Expressed as the length of the i-th metal layer, Dk i Expressed as the width of the i-th metal layer, Dxj ij It is expressed as the distance from the i-th metal layer to the adjacent j-th metal layer, Xhqd i It is represented as the signal strength of the i-th metal layer; According to the relevant material property data information and combined with the metal layer cross-degree Jjcd, the signal interference coefficient Xgxs is constructed, which is obtained in the following way: Where Djj represents the distance between the conductor and the bottom line in the abnormal current density area, Ddz represents the conductivity of the conductor material in the abnormal current density area, Cdz represents the magnetic permeability of the conductor material in the abnormal current density area, and a 1 、a 2 、a 3 and a 4 are all weight values, and P represents the second correction constant.

8. The integrated circuit layout design optimization system according to claim 7, Features: The comprehensive analysis unit is used to input the electromigration tolerance coefficient Drxs in the current density abnormal area and the signal interference coefficient Xgxs in the corresponding area into the trained layout design risk prediction model to calculate the trade-off evaluation index Qgzs, which is specifically obtained in the following manner:

9. The integrated circuit layout design optimization system according to claim 1, Features: The optimization management module includes a comparison and analysis unit and an optimization unit; The comparison and analysis unit is used to compare and analyze the trade-off evaluation index Qgzs with the evaluation threshold Q to measure the balance between electromigration tolerance and signal integrity in the current physical model. The specific analysis content is as follows: If the trade-off evaluation index Qgzs=the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are in a balanced state; If the trade-off evaluation index Qgzs is greater than the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are not in a balanced state, and a first optimization command will be issued at this time; If the trade-off evaluation index Qgzs is less than the evaluation threshold Q, it indicates that the electromigration tolerance and signal integrity in the current physical model are not in a balanced state, and a second optimization command will be issued at this time; The optimization unit is used to receive the optimization command issued by the comparison and analysis unit, and take optimization measures according to the received optimization command. The specific contents are as follows: If the No. 1 optimization command is issued, the wire size will be adjusted in the abnormal current density area, and the wire width and thickness will be increased by 5% at a time until the electromigration tolerance and signal integrity in the physical model are in a balanced state. The adjustment operation will be stopped, and a heat dissipation layer will be added in the hot spot area. If the No. 2 optimization command is issued, a shielding layer or shielding wire will be introduced in the abnormal current density area to isolate the interference source, and the wire size will be adjusted in the abnormal current density area, reducing the wire width and thickness by 5% of the original at a time until the electromigration tolerance and signal integrity in the physical model are in a balanced state and the adjustment operation is stopped.

10. A method for optimizing the design of an integrated circuit layout, used to implement the system for optimizing the design of an integrated circuit layout as claimed in any one of claims 1 to 9. Features: The following steps are included: Step 1: Use simulation software to establish a physical model of the integrated circuit; Step 2: According to the physical model, the integrated circuit layout is simulated and tested to monitor and obtain relevant signal interconnection status data information, and at the same time, the relevant material status data information and relevant material property data information of the integrated circuit layout are collected and obtained according to the physical model; Step 3: pre-process the relevant signal interconnection situation data information, relevant material status data information and relevant material attribute data information obtained in the data acquisition module, construct a layout data set, and combine the dimensionless processing technology to unify the units of the relevant data information in the layout data set; Step 4: extract the current density Dmd in the relevant signal interconnection situation data information, identify the abnormal current density area in the integrated circuit layout based on the current density Dmd value, and construct the electromigration tolerance coefficient Drxs through the relevant signal interconnection situation data information in the abnormal current density area; Step 5: construct the signal interference coefficient Xgxs according to the relevant material status data information and the relevant material attribute data information, and obtain the trade-off evaluation index Qgzs by combining the trained layout design risk prediction model; Step 6: pre-set an evaluation threshold Q, and compare and analyze the evaluation threshold Q with the trade-off evaluation index Qgzs to measure the balance between electromigration tolerance and signal integrity in the current physical model.

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