Silicon-based liquid crystal chip control system and method

Abstract

The invention provides a silicon-based liquid crystal chip control system and method, and the system comprises a data buffering module which is used for converting an external video signal into a digital image signal and storing the digital image signal; the data adjusting module is connected with the data buffering module and is used for performing data rearrangement on the digital image signal to obtain a rearranged digital signal; and the data driving module is connected with the data adjusting module, and is used for generating a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearrangement digital signal, and outputting the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip. According to the silicon-based liquid crystal chip control system and the silicon-based liquid crystal chip control method, the video signal is decoded based on the FPGA, so that a function of bridging the video stream to the LCoS signal is realized, and the requirements of resolution and high refresh rate of the silicon-based liquid crystal chip are met.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal on silicon (LCoS) drive control, and in particular to a liquid crystal on silicon chip control system and method. Background Art

[0002] LCoS microdisplay technology has many applications in the display field. It has the advantages of high frame rate, high resolution and small size. LCoS is developed from liquid crystal display technology LCD, and is favored by people because of its mature production line and low cost. In early applications, LCoS was mainly used for laser projection, display and holographic projection. Based on LCoS technology, wavelength display switches can switch any wavelength channel received at the input port to any output port. Today, the development of LCoS technology has changed the optical communication and display industries, providing flexible and reliable solutions for various applications.

[0003] LCoS devices are mainly used as amplitude modulation devices and phase modulation devices. Amplitude modulation LCOS devices are mainly used for video and image display, and phase modulation LCOS devices are suitable for holographic projection and optical fields. Existing general-resolution display control systems are difficult to meet the special resolution and high refresh rate requirements of LCoS chips. Therefore, designing a processing system for high-definition images or video streams is an important task. A reliable processing system can provide a stable data stream for the display chip while being able to implement some real-time algorithms for image processing. Especially for those more complex algorithms, the flexibility and high efficiency of the system platform are very important. Generally speaking, it is difficult to use CPU to efficiently process high-speed video streams. Compared with GPU and ASIC, FPGA can customize the algorithms and functions of data streams according to requirements. FPGA can not only use parallelization and pipeline for data processing, but also has advantages in energy efficiency. Compared with GPU, the ability to work without an additional host makes FPGA suitable for embedded systems to meet image processing needs. In most applications using LCoS, the resolution of the chip is not high, and the requirements for the control system are relatively simple. However, in the face of growing data and special high-resolution specifications, traditional processing equipment seems powerless.

[0004] In summary, in the LCoS chip control system, a general-purpose processor is often required to control the chip drive. Traditional CPUs and GPUs can complete the control function, but they also have some disadvantages. For example, the CPU has weak processing capabilities for image data, and the GPU consumes too much power and is not suitable for edge application scenarios. For control systems designed with FPGA, high resolution and high refresh rate are bottlenecks for driving LCoS. Summary of the invention

[0005] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a silicon-based liquid crystal chip control system and method, which decodes the video signal based on FPGA, realizes the video stream to LCoS signal bridging function, and meets the resolution and high refresh rate requirements of silicon-based liquid crystal chips.

[0006] In a first aspect, the present invention provides a silicon-based liquid crystal chip control system, which is applied to FPGA, and the system includes: a data buffer module, which is used to convert an external video signal into a digital image signal and store it; a data adjustment module, which is connected to the data buffer module and is used to rearrange the digital image signal and obtain the rearranged digital signal; a data driving module, which is connected to the data adjustment module and is used to generate a control signal and a clock signal of the silicon-based liquid crystal chip based on the rearranged digital signal, and output the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip.

[0007] In an implementation of the first aspect, the data buffer module includes a frame data parsing module, a frame data storage module and a storage control module;

[0008] The frame data parsing module is used to convert the external video signal into the digital image signal;

[0009] The frame data storage module is connected to the frame data analysis module and is used to store the digital image signal;

[0010] The storage control module is connected to the frame data analysis module and the frame data storage module, and is used to control the read frame sequence number, write frame sequence number, frame data storage position and storage bit width of the frame data storage module.

[0011] In an implementation of the first aspect, the frame data storage module includes a storage space of three frame image size on the FPGA to implement a three-level frame cache, and the write frame sequence number always precedes the read frame sequence number.

[0012] In an implementation manner of the first aspect, the data buffer module obtains the external video signal through an HDMI interface.

[0013] In an implementation of the first aspect, the data adjustment module includes a row data buffer module, a data rearrangement module, a rearrangement data buffer module, and a data adjustment control module;

[0014] The row data buffer module is used to access the data buffer module to acquire and store the digital image signal;

[0015] The data rearrangement module is connected to the row data buffer module, and is used to pack and rearrange the digital image signal, and obtain the rearranged digital signal so that the rearranged digital signal satisfies the input sequence of the silicon-based liquid crystal chip;

[0016] The rearranged data buffer module is connected to the data rearrangement module and is used to store the rearranged digital signal;

[0017] The data adjustment control module is connected to the row data buffer module, the data rearrangement module and the rearranged data buffer module, and is used to control data access of the row data buffer module, data rearrangement of the data rearrangement module and data storage of the rearranged data buffer module.

[0018] In an implementation of the first aspect, the data rearrangement module uses a pipeline operation to rearrange the packaged digital image signal into multiple groups of parallel-structured rearranged digital signals.

[0019] In an implementation of the first aspect, the data driving module includes a driving control module, a data parsing module, a driving signal generating module and a data alignment module;

[0020] The drive control module is connected to the data parsing module, the drive signal generating module and the data alignment module, and is used to control the data parsing module, the drive signal generating module and the data alignment module;

[0021] The data parsing module is used to access the data adjustment module to obtain the rearranged digital signal;

[0022] The driving signal generating module is connected to the data analyzing module and is used to generate a control signal and a clock signal of a liquid crystal on silicon chip based on the rearranged digital signal;

[0023] The data alignment module is connected to the driving signal generation module, and is used for aligning the digital image signal, the clock signal and the control signal with the clock and then outputting them to the liquid crystal on silicon chip.

[0024] In an implementation manner of the first aspect, the data alignment module outputs a signal through a high-speed external interface.

[0025] In an implementation manner of the first aspect, the control signal includes a row drive signal and a field drive signal.

[0026] In a second aspect, the present invention provides a method for controlling a liquid crystal on silicon chip, which is applied to an FPGA. The method comprises the following steps:

[0027] Based on the data buffer module, the external video signal is converted into a digital image signal and stored;

[0028] Rearranging the digital image signal based on the data adjustment module to obtain a rearranged digital signal;

[0029] A data-based driving module generates a control signal and a clock signal for a liquid crystal on silicon chip according to the rearranged digital signal, and outputs the digital image signal, the clock signal and the control signal to the liquid crystal on silicon chip.

[0030] As described above, the control system and method of the liquid crystal on silicon chip of the present invention have the following beneficial effects:

[0031] (1) By using FPGA to decode the video signal and realize the video stream to LCoS signal bridging function, the problem that the existing resolution display control system is difficult to meet the special resolution and high refresh rate of the LCoS chip is solved;

[0032] (2) It can ensure the full resolution and image structure integrity of the output to the LCoS driver at high refresh rates, and meet the needs of edge application scenarios;

[0033] (3) The configurable parameter design can independently control the data rate and clock frequency output to the silicon-based liquid crystal chip to meet the data and control requirements of the silicon-based liquid crystal chip with different functions;

[0034] (4) Low power consumption, high real-time performance, and fast processing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram showing the structure of a liquid crystal on silicon chip control system in one embodiment of the present invention;

[0036] Figure 2 It is a schematic diagram showing the operation flow of a liquid crystal on silicon chip control system in one embodiment of the present invention;

[0037] Figure 3 Shown is a schematic diagram of the read and write sequence number of the data buffer module of the present invention in one embodiment;

[0038] Figure 4 It is a schematic diagram showing a data reordering mechanism of the present invention in one embodiment;

[0039] Figure 5 Shown is a flow chart of a control system of a liquid crystal on silicon chip in one embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0041] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0042] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0043] The control system and method of the silicon-based liquid crystal chip of the present invention decodes the video signal based on FPGA, realizes the video stream to LCoS signal bridging function through data buffering and data rearrangement, and can convert the video data into control signals and data signals for the silicon-based liquid crystal chip in real time, thereby meeting the resolution and high refresh rate requirements of the silicon-based liquid crystal chip.

[0044] The silicon-based liquid crystal chip control system of the present invention is applied to FPGA. Figure 1 and Figure 2 As shown, in one embodiment, the liquid crystal on silicon chip control system of the present invention includes a data buffer module 1 , a data adjustment module 2 and a data driving module 3 .

[0045] The data buffer module 1 is used to convert the external video signal into a digital image signal and store it. Wherein, the data buffer module 1 obtains the external video signal through an HDMI interface, and the external video signal is an HDMI signal.

[0046] In one embodiment, the data buffer module includes a frame data parsing module 11, a frame data storage module 12 and a storage control module 13. The frame data parsing module 11 is used to convert the external video signal into the digital image signal. In one embodiment, the frame data parsing module 11 converts the external video HDMI signal into a multi-bit width digital image signal in a specific format and video image control signals such as field synchronization VS, line synchronization HS, and data enable DataEn. The input frame rate is 60Hz, and the image resolution of the color digital image signal is 1920x1080. The frame data storage module 12 is connected to the frame data parsing module 11 and is used to store the digital image signal. Among them, the frame data storage module 12 includes an on-chip memory. The storage control module 13 is connected to the frame data parsing module 11 and the frame data storage module 12, and is used to realize the control of the read frame number, write frame number, frame data storage position and storage bit width of the frame data storage module. Among them, the storage control module 13 samples and caches the digital image signal by controlling the current read frame number R_Num and the current write frame number W_Num. The frame data storage module 12 opens up a space of three frames of image size in the DDR on the FPGA to realize a three-level frame buffer, and through the control of the three-level frame buffer and R_Num and W_Num, the write frame number W_Num is always prior to the read frame number R_Num, thereby satisfying that the write data rate is less than the read data rate. Figure 3 As shown, under the control of the read frame number R_Num and the write frame number W_Num, W_Num is always the previous level of R_Num.

[0047] The data adjustment module 2 is connected to the data buffer module 1 and is used to rearrange the data of the digital image signal to obtain a rearranged digital signal.

[0048] In one embodiment, the data adjustment module 2 includes a row data buffer module 21, a data rearrangement module 22, a rearranged data buffer module 23 and a data adjustment control module 24. The row data buffer module 21 is used to access the data buffer module, obtain and store the digital image signal. Wherein, the row data buffer module 21 accesses the digital image signal in the frame data storage module 12 through the on-chip memory and the on-chip high-speed bus according to the control signal generated by the data adjustment control module 24, and moves it to the row data buffer 21. The data rearrangement module 22 is connected to the row data buffer module 21, and is used to package and rearrange the digital image signal, and obtain the rearranged digital signal so that the rearranged digital signal meets the input order of the silicon-based liquid crystal chip. Wherein, the data rearrangement uses a pipeline operation to rearrange the packaged digital image signal in batches into multiple groups of parallel structures of the rearranged digital signal. It should be noted that the rearranged digital signal is a plurality of parallel groups, wherein the groups can be configured separately to meet the application requirements of different scenarios. The data rearrangement buffer module 23 is connected to the data rearrangement module 22, and is used to store the rearranged digital signal according to the signal scheduling of the data adjustment control module 24. Specifically, in the row data buffer module 21, the frame data storage module 12 is accessed through the control signal and the AXI on-chip high-speed bus, and the digital image signal with the corresponding sequence number is obtained according to the read frame sequence number R_Num. The storage control module 13 encodes four pixels into a group, that is, 40 bits are transmitted as a burst packet. The data rearrangement module 22 makes the data meet the order of output to the silicon-based liquid crystal chip, that is, a row of data will be divided into four equal parts and rearranged. Figure 4 As shown, the packed data is re-divided into four groups through data rearrangement and is stored in four on-chip Block Rams respectively.

[0049] The data driving module 3 is connected to the data adjusting module 2, and is used to generate a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearranged digital signal, and output the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip.

[0050] In one embodiment, the data driving module 3 includes a driving control module 31, a data parsing module 32, a driving signal generating module 33 and a data alignment module 34. The driving control module 31 is connected to the data parsing module 32, the driving signal generating module 33 and the data alignment module 34, and is used to control the data parsing module 32, the driving signal generating module 33 and the data alignment module 34. The data parsing module 32 is used to access the data adjustment module 2 to obtain the rearranged digital signal. Wherein, the data parsing module 32 accesses the rearranged data buffer module 23 through a high-speed bus according to the signal generated by the driving control module 31, and transports the rearranged digital signal to the driving signal generating module 33. The driving signal generating module 33 is connected to the data parsing module 32, and is used to generate a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearranged digital signal. Wherein, the control signal includes a row driving signal and a field driving signal. The data alignment module 34 is connected to the drive signal generation module 33, and is used to align the digital image signal, the clock signal and the control signal with the clock and then output them to the silicon-based liquid crystal chip. Preferably, the data alignment module 34 converts the digital image signal and the clock signal into corresponding differential signals, and outputs the differential signals and the control signals to the silicon-based liquid crystal chip through a high-speed external interface such as an LVDS interface. The maximum frequency of the clock signal output to the silicon-based liquid crystal chip is 250MHz, the maximum single pixel accuracy is 10bit, the number of output channels is 13 channels, and the total transmission rate is 5.75Gbps.

[0051] For the traditional 1080p@60Hz resolution video stream control system, the system processing speed is 356MB / s. The video stream output specification processed by the present invention is 1620p@120Hz, and the system processing speed is 593MB / s. It can be seen that the silicon-based liquid crystal chip control system of the present invention can process high-speed video streams more efficiently, and different control cores can be designed according to different input resolutions to meet the function of real-time processing.

[0052] The control method of the silicon-based liquid crystal chip of the present invention is applied to FPGA. Figure 5 As shown, in one embodiment, the LCS chip control method of the present invention includes steps S1 to S3.

[0053] Step S1: converting an external video signal into a digital image signal based on a data buffer module and storing the signal.

[0054] Specifically, in one embodiment, the data buffer module includes a frame data parsing module, a frame data storage module and a storage control module. The frame data parsing module converts the external video signal into the digital image signal. The frame data storage module stores the digital image signal. The storage control module implements the control of the read frame number, write frame number, frame data storage position and storage bit width of the frame data storage module.

[0055] Step S2: Rearrange the digital image signal based on the data adjustment module to obtain a rearranged digital signal.

[0056] Specifically, the data adjustment module includes a row data buffer module, a data rearrangement module, a rearranged data buffer module and a data adjustment control module. The row data buffer module accesses the data buffer module to obtain and store the digital image signal. The data rearrangement module packages and rearranges the digital image signal, and obtains the rearranged digital signal so that the rearranged digital signal meets the input sequence of the silicon-based liquid crystal chip. The rearranged data buffer module stores the rearranged digital signal according to the signal scheduling of the data adjustment control module.

[0057] Step S3: generating a control signal and a clock signal of a liquid crystal on silicon chip according to the rearranged digital signal based on a data driving module, and outputting the digital image signal, the clock signal and the control signal to the liquid crystal on silicon chip.

[0058] Specifically, the data driving module includes a driving control module, a data parsing module, a driving signal generating module and a data alignment module. The driving control module controls the data parsing module, the driving signal generating module and the data alignment module. The data parsing module obtains the rearranged digital signal. The driving signal generating module generates a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearranged digital signal. The data alignment module aligns the digital image signal, the clock signal and the control signal with the clock and outputs them to the silicon-based liquid crystal chip.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A liquid crystal on silicon chip control system, applied to FPGA, characterized in that: The system comprises: A data buffer module is used to convert external video signals into digital image signals and store them; A data adjustment module, connected to the data buffer module, for rearranging the digital image signal to obtain a rearranged digital signal; A data driving module is connected to the data adjustment module and is used to generate a control signal and a clock signal of a silicon-based liquid crystal chip based on the rearranged digital signal, and output the digital image signal, the clock signal and the control signal to the silicon-based liquid crystal chip.

2. The liquid crystal on silicon chip control system according to claim 1, characterized in that: The data buffer module includes a frame data parsing module, a frame data storage module and a storage control module; The frame data parsing module is used to convert the external video signal into the digital image signal; The frame data storage module is connected to the frame data analysis module and is used to store the digital image signal; The storage control module is connected to the frame data analysis module and the frame data storage module, and is used to control the read frame sequence number, write frame sequence number, frame data storage position and storage bit width of the frame data storage module.

3. The liquid crystal on silicon chip control system according to claim 2, characterized in that: The frame data storage module includes a storage space of three frame sizes on the FPGA to implement a three-level frame cache, and the write frame sequence number always precedes the read frame sequence number.

4. The liquid crystal on silicon chip control system according to claim 1, characterized in that: The data buffer module obtains the external video signal through the HDMI interface.

5. The liquid crystal on silicon chip control system according to claim 1, characterized in that: The data adjustment module includes a row data buffer module, a data rearrangement module, a rearrangement data buffer module and a data adjustment control module; The row data buffer module is used to access the data buffer module to acquire and store the digital image signal; The data rearrangement module is connected to the row data buffer module, and is used to pack and rearrange the digital image signal, and obtain the rearranged digital signal so that the rearranged digital signal satisfies the input sequence of the silicon-based liquid crystal chip; The rearranged data buffer module is connected to the data rearrangement module and is used to store the rearranged digital signal; The data adjustment control module is connected to the row data buffer module, the data rearrangement module and the rearranged data buffer module, and is used to control data access of the row data buffer module, data rearrangement of the data rearrangement module and data storage of the rearranged data buffer module.

6. The liquid crystal on silicon chip control system according to claim 5, characterized in that: The data rearrangement module adopts pipeline operation to rearrange the packed digital image signal into multiple groups of parallel structured rearranged digital signals.

7. The liquid crystal on silicon chip control system according to claim 1, characterized in that: The data driving module includes a driving control module, a data parsing module, a driving signal generating module and a data alignment module; The drive control module is connected to the data parsing module, the drive signal generating module and the data alignment module, and is used to control the data parsing module, the drive signal generating module and the data alignment module; The data parsing module is used to access the data adjustment module to obtain the rearranged digital signal; The driving signal generating module is connected to the data analyzing module and is used to generate a control signal and a clock signal of a liquid crystal on silicon chip based on the rearranged digital signal; The data alignment module is connected to the driving signal generation module, and is used for aligning the digital image signal, the clock signal and the control signal with the clock and then outputting them to the liquid crystal on silicon chip.

8. The liquid crystal on silicon chip control system according to claim 7, characterized in that: The data alignment module outputs signals through a high-speed external interface.

9. The liquid crystal on silicon chip control system according to claim 1, characterized in that: The control signal includes a row driving signal and a field driving signal.

10. A method for controlling a liquid crystal on silicon chip, applied to FPGA, characterized in that: The method comprises the following steps: Based on the data buffer module, the external video signal is converted into a digital image signal and stored; Rearranging the digital image signal based on the data adjustment module to obtain a rearranged digital signal; A data-based driving module generates a control signal and a clock signal for a liquid crystal on silicon chip according to the rearranged digital signal, and outputs the digital image signal, the clock signal and the control signal to the liquid crystal on silicon chip.

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