Source driver, display device, and source driving method

Abstract

The present application discloses a source driver, a display device and a source driving method. The source driver provides a plurality of source driving signals to the display panel through a plurality of source lines, and the display panel also receives a common voltage signal through a common electrode line. The source driver includes: a voltage detection circuit, which detects the voltage state of the low-voltage driving signal to output a state characterization signal; a logic circuit, which generates a control signal according to the state characterization signal and the backlight enable signal; an output selection circuit, which connects a plurality of source lines and a common electrode line, and selects to output the source driving signal and the common voltage signal to the display panel or output the ground voltage to the display panel according to the control signal. The output selection circuit outputs the source driving signal and the common voltage signal to the display panel according to the control signal only when the state characterization signal is valid and the backlight enable signal is valid. In order to control the timing of the low-voltage driving signal, the source driving signal and the common voltage signal during the startup process, the white flickering of the screen is improved.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal display technology, and in particular to a source driver, a display device and a source driving method. Background Art

[0002] Display devices have been widely used in mobile terminals and display panels due to their advantages such as good display quality, small size and low power consumption. Figure 1 The timing waveform diagram of the main signals of the existing display device during the power-on process is shown in FIG. Figure 1 As shown, during the power-on process, the input signal VIN first goes high to indicate the power-on action. The clock signal CLK is then pulled low, the potential of the low-voltage drive signal VGL drops, the common voltage signal Vcom begins to rise, and the data signal to be written to the pixel electrode or the source drive signal Source also begins to rise. This means that the timing of the source drive signal, the low-voltage drive signal, and the common voltage signal must be consistent during the power-on process. However, in actual applications, it is possible that the source drive signal Source is output before the clock signal CLK is pulled low. This high-level low-voltage drive signal VGL causes the thin-film transistors (TFTs) in the pixel array of the display panel to be partially turned off. This creates a voltage difference between the source drive signal Source and the common voltage signal Vcom. This voltage difference can further mischarge the pixel cells, resulting in afterimages and flickering, such as white flash during power-on. Existing display devices are unable to effectively address this issue. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide a source driver, a display device and a source driving method to solve the problems of the prior art.

[0004] According to one aspect of the present invention, a source driver is provided, which provides multiple source drive signals to a display panel through multiple source lines, and the display panel also receives a common voltage signal through a common electrode line, wherein the source driver includes: a voltage detection circuit, which detects the voltage state of the low-voltage drive signal received by the source driver to output a state characterization signal; a logic circuit, which generates a control signal according to the received state characterization signal and a backlight enable signal; and an output selection circuit, which connects the multiple source lines and the common electrode line, and selects to output the source drive signal and the common voltage signal to the display panel or output the ground voltage to the display panel according to the control signal, wherein the output selection circuit outputs the source drive signal and the common voltage signal to the display panel according to the control signal when the state characterization signal is valid and the backlight enable signal is valid.

[0005] Optionally, when the state representation signal is invalid and / or the backlight enable signal is invalid, the output gating circuit outputs the ground voltage to the display panel according to the control signal.

[0006] Optionally, the state characterization signal is valid when the low-voltage drive signal is at a low level, and the state characterization signal is invalid when the low-voltage drive signal is at a high level; the backlight enable signal is valid when the backlight enable signal is at a high level, and invalid when the backlight enable signal is at a low level.

[0007] Optionally, the voltage detection circuit compares the low-voltage drive signal with a reference voltage to generate the state characterization signal, wherein the state characterization signal is valid when the low-voltage drive signal is less than the reference voltage, and the state characterization signal is invalid when the low-voltage drive signal is greater than the reference voltage.

[0008] Optionally, the voltage detection circuit includes: a charge pump, whose input terminal receives the power supply voltage, and whose output terminal is grounded through a first resistor and a second resistor connected in series; a voltage follower, whose positive input terminal is connected to the intermediate node between the first resistor and the second resistor, whose reverse input terminal is connected to the output terminal, and whose voltage at the intermediate node is used as the reference voltage; a comparator, whose positive input terminal is connected to the output terminal of the voltage follower, receives the reference voltage, whose reverse input terminal receives the low-voltage drive signal, and whose output terminal generates the state characterization signal.

[0009] Optionally, the logic circuit includes a NAND gate, the first input terminal and the second input terminal of the NAND gate respectively receive the status characterization signal and the backlight enable signal, and the output terminal outputs the control signal; the voltage detection circuit includes a NOR gate, the first input terminal and the second input terminal of the NOR gate respectively receive the low-level signal and the low-voltage drive signal, and the output terminal outputs the status characterization signal.

[0010] Optionally, the output selection circuit includes: a plurality of first switching tubes, wherein the first ends of the plurality of first switching tubes are respectively connected to a plurality of source lines in a one-to-one correspondence, the second ends of the plurality of first switching tubes are all grounded through a third resistor, and the control ends of the plurality of first switching tubes all receive the control signal; and a second switching tube, wherein the first end of the second switching tube is connected to the common electrode line, the second end of the second switching tube is grounded through a fourth resistor, and the control end of the second switching tube receives the control signal.

[0011] Optionally, the output selection circuit includes: multiple first switches, which are connected to multiple source lines one by one, and the control ends of the multiple first switches all receive the control signal to output the source drive signal or the ground voltage to the display panel through the source line according to the control signal; and a second switch, which is connected to the common electrode line, and the control end of the second switch receives the control signal to output the source drive signal or the ground voltage to the display panel through the common electrode line according to the control signal.

[0012] According to another aspect of the present invention, a display device is provided, comprising: a display panel, the display panel including a pixel array, the pixel array including a plurality of pixel units arranged in an array; a gate driver, connected to a plurality of rows of pixel units via a plurality of gate lines, and providing gate drive signals to the pixel units; the above-mentioned source driver, connected to a plurality of columns of pixel units via a plurality of source lines, and providing source drive signals to the pixel units; and a common voltage generating circuit, connected to a plurality of pixel units via a common electrode line, and providing a common voltage to the pixel units.

[0013] According to another aspect of the present invention, a source driving method is provided, comprising: detecting a voltage state of a low-voltage driving signal received by a source driver to output a state characterizing signal; generating a control signal based on the received state characterizing signal and a backlight enable signal; when the state characterizing signal is valid and the backlight enable signal is valid, outputting the source driving signal and the common voltage signal to the display panel through a plurality of source lines and a common electrode line, respectively, according to the control signal; and when the state characterizing signal is invalid and / or the backlight enable signal is invalid, outputting a ground voltage to the display panel through a plurality of source lines and a common electrode line according to the control signal.

[0014] The source driver, display device, and source drive method provided by the present invention detect the valid states of the low-voltage drive signal VGL and the backlight enable signal LED-EN during the startup process, and accordingly generate a control signal to control the operating state of the output gating circuit. Based on the state of the control signal, the output gating circuit can select whether to output the source drive signal and the common voltage signal to the display panel via the source line and the common electrode line, respectively, or to output the ground voltage to the display panel via the source line and the common electrode line. Furthermore, the source drive signal and the common voltage signal are only output to the display panel to display the image normally when both the state-representing signal (the low-voltage drive signal) and the backlight enable signal are valid. Thus, during the startup process, the output timing of the source drive signal and the common voltage signal can be controlled based on the level states of the low-voltage drive signal and the backlight enable signal, ensuring that the timing of the source drive signal, the low-voltage drive signal, and the common voltage signal are consistent during the startup process. That is, the source drive signal and the common voltage signal are output only after the low-voltage drive signal becomes valid, and the source drive signal and the common voltage signal are output simultaneously, thereby avoiding problems such as white flickering during startup.

[0015] Furthermore, when either the low-voltage drive signal or the backlight enable signal is not in a valid state, a ground voltage is output to the display panel, rendering the display screen black. This ensures that the screen remains black during both the startup preparation phase and the shutdown discharge phase, disconnecting the source drive signal and the common voltage signal to prevent them from affecting the screen display, thereby suppressing problems such as screen flickering during startup.

[0016] Furthermore, different circuit forms can be used to implement the source driver's gated output function. For example, different components such as switching tubes or single-pole double-throw switches can be used to implement the output gate circuit to control the signal received by the display panel. Comparators or NOR gates can also be used to implement the voltage detection circuit to accurately detect the status of the low-voltage drive signal. This allows for a variety of implementations of the overall circuit and a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0018] Figure 1 The following diagram shows the timing waveforms of the main signals of the existing display device during the startup process;

[0019] Figure 2 shows a schematic structural block diagram of a display device according to an embodiment of the present invention;

[0020] Figure 3 shows a schematic structural block diagram of a source driver according to an embodiment of the present invention;

[0021] Figure 4ashows a schematic circuit diagram of a source driver according to a first embodiment of the present invention;

[0022] Figure 4b shows a schematic circuit diagram of a source driver according to a second embodiment of the present invention;

[0023] Figure 5 shows a schematic waveform diagram of various signals of the source driver when working according to an embodiment of the present invention;

[0024] Figure 6 FIG. 4 shows a schematic flow chart of a source driving method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0026] It should be understood that when describing a device structure, when a layer or region is referred to as being "on" or "above" another layer or region, this may mean that it is directly above the other layer or region, or that other layers or regions are located between it and the other layer or region. Furthermore, if the device is flipped over, the layer or region will be "below" or "beneath" the other layer or region. To describe a situation where a layer or region is directly above another layer or region, this document will use the expressions "A is directly above B" or "A is above and adjacent to B."

[0027] The present invention improves the traditional display driving circuit and provides another source driver, a display driving circuit and a display device including the source driver. Figure 2-Figure 5 introduce.

[0028] Figure 2 FIG. 1 shows a schematic structural block diagram of a display device according to an embodiment of the present invention. Figure 2As shown, the display device 200 includes a display panel 100, a common voltage generating circuit 400, a gate driver 300, a source driver 200, and a timing controller 500. The display panel 100 includes a pixel array, which includes a plurality of pixel units 101 arranged in an array. The pixel array also includes common electrode lines Vc1-Vcn, multiple scan lines G1-Gn, and multiple data lines S1-Sm. Each pixel unit 101 is formed at the intersection of a corresponding scan line and a data line, thereby forming n rows by m columns of pixel units 101. Each pixel unit 101 includes a TFT (thin-film transistor), a pixel capacitor Cc, and a storage capacitor Cs. The gate of the thin-film transistor (TFT) in each pixel unit 101 is connected to the corresponding scan line to receive a gate drive signal. The source of the thin-film transistor (TFT) in each pixel unit 101 is connected to the corresponding data line to receive source drive signals sc1-scm. A first end of the pixel capacitor Cc (i.e., the pixel electrode) and a first end of the storage capacitor Cs (i.e., the storage electrode) are connected to the drain of the thin film transistor TFT. A second end of the pixel capacitor Cc and a second end of the storage capacitor Cs are connected to the common electrode line Vc1-Vcn to receive a common voltage signal Vcom. Where n and m are both natural numbers greater than 0.

[0029] The gate driver 300 is connected to multiple horizontal gate lines (G1-Gn) within the display panel 100 and provides multiple gate drive signals to enable pixel cells 101. The source driver 200 is connected to multiple vertical source lines (S1-Sm) within the display panel 100 and provides multiple source drive signals (sc1-scm) to enable grayscale voltages, thereby controlling the brightness of the pixel cells 101. The time required for the display panel 100 to display a complete image is one image frame. During each image frame, all scan lines are scanned and grayscale voltages are applied to all data lines to display a complete image. The timing controller 500 (TCON) is connected to the gate driver 300 and source driver 200, respectively, to provide multiple drive signals to each. The gate driver 300 sequentially drives the multiple scan lines of the pixel array based on the drive signals provided by the timing controller 500, enabling the thin-film transistors (TFTs) in each pixel cell 101 within the pixel array. The source driver 200 provides a plurality of source driving data to the pixel array according to the driving signals provided by the timing controller 500, so that the selected pixel units 101 receive the corresponding source driving signals. The common voltage generating circuit 400 is connected to one end of the common electrode lines Vc1-Vcn on the pixel array to provide a common voltage signal Vcom.

[0030] In this embodiment, the source driver 200 receives a power supply voltage VCC, a low-voltage drive signal VGL, and a backlight enable signal LED-EN. The power supply voltage VCC is used to provide power to the source driver 200. The low-voltage drive signal VGL gradually drops to a low level after power-on. When the backlight enable signal LED-EN is valid, it indicates that the backlight source is ready. Then, the source drive signal and the common voltage signal Vcom both become valid and start to display data. Figure 3-Figure 5 The source driver 200 is introduced.

[0031] Figure 3 FIG. 1 shows a schematic structural block diagram of a source driver according to an embodiment of the present invention. Figure 4a FIG. 4 shows a schematic circuit diagram of a source driver according to a first embodiment of the present invention, Figure 4b FIG. 2 shows a schematic circuit diagram of a source driver according to a second embodiment of the present invention.

[0032] Combine Figure 3-4b The source driver 200 includes a voltage detection circuit 210, a logic circuit 220, an output selection circuit 230 and a source drive signal generating circuit 240. The voltage detection circuit 210 detects the voltage state of the low-voltage drive signal VGL received by the source driver 200 and outputs a state characterization signal Vs. The low-voltage drive signal VGL is a low-level signal when the display panel 100 is operating normally, and is a high-level signal at the moment the display panel 100 is shut down. It is valid at a low level and invalid at a high level. The logic circuit 220 generates a control signal Vctrl based on the received state characterization signal Vs and the backlight enable signal LED-EN. The backlight enable signal LED-EN represents the state of the backlight source. The backlight enable signal LED-EN is valid when it is at a high level and invalid when it is at a low level. The output gating circuit 230 is connected to a plurality of source lines and common electrode lines and, based on a control signal Vctrl, selects to output source drive signals sc1-scm and a common voltage signal Vcom to the display panel 100 via the source lines and the common electrode lines, respectively, or outputs a ground voltage GND to the display panel 100 via the source lines and the common electrode lines. Furthermore, when the low-voltage drive signal VGL is at a low level, the state-indicating signal Vs is valid; when the low-voltage drive signal VGL is at a high level, the state-indicating signal Vs is invalid. When the state-indicating signal Vs is valid and the backlight enable signal LED-EN is valid, the output gating circuit 230 outputs the source drive signals sc1-scm and the common voltage signal Vcom to the display panel 100 based on the control signal Vctrl. When the state-indicating signal Vs is invalid and / or the backlight enable signal LED-EN is invalid, the output gating circuit 230 outputs the ground voltage GND to the display panel 100 based on the control signal Vctrl.

[0033] like Figure 4a As shown, in one embodiment, the voltage detection circuit 210 compares the low-voltage drive signal VGL with the reference voltage Vref to generate a state-characterizing signal Vs. When the low-voltage drive signal VGL is less than the reference voltage Vref, the state-characterizing signal Vs is valid; when the low-voltage drive signal VGL is greater than the reference voltage Vref, the state-characterizing signal Vs is invalid. Since the low-voltage drive signal VGL is valid at a low level, the reference voltage Vref can be set to a low level or slightly higher than the valid level of the low-voltage drive signal VGL. For example, it can be set to 0V or above. The voltage detection circuit 210 may specifically include a charge pump 211, a resistor divider network, a voltage follower U1, and a comparator U2. The input of the charge pump 211 receives the supply voltage VCC, and the output is connected to ground via a first resistor R1 and a second resistor R2 connected in series. The positive input of the voltage follower U1 is connected to the middle node between the first resistor R1 and the second resistor R2, and the negative input is connected to its own output, with the voltage at the middle node serving as the reference voltage Vref. The comparator U2 has a positive input terminal connected to the output terminal of the voltage follower U1 to receive the reference voltage Vref, a negative input terminal to receive the low-voltage drive signal VGL, and an output terminal to generate a state representation signal Vs.

[0034] Logic circuit 220 includes, for example, a NAND gate U3. A first input terminal and a second input terminal of NAND gate U3 receive the status signal Vs and the backlight enable signal LED-EN, respectively. An output terminal of NAND gate U3 outputs the control signal Vctrl. According to the truth table of NAND gate U3, a low-level control signal Vctrl is output only when both the status signal Vs and the backlight enable signal LED-EN are active, i.e., at a high level.

[0035] The source drive signal generating circuit 240 includes multiple voltage followers to output multiple source signals sc1-scm. Of course, the source drive signal generating circuit 240 may also include other modules, such as control logic, P2P receiver, data buffer, shift register, level shifter, digital-to-analog converter (DAC), and output buffer, etc., which will not be detailed here.

[0036] In this embodiment, the output gating circuit 230 may include a plurality of first switching transistors Q11, Q12, ..., Q1m, and a second switching transistor Q2. The first ends of the plurality of first switching transistors Q11-Q1m are connected to a plurality of source lines S1-Sm, respectively. The second ends of the plurality of first switching transistors Q11-Q1m are grounded via a third resistor R3, and the control ends of the plurality of first switching transistors Q11-Q1m receive a control signal Vctrl. The first end of the second switching transistor Q2 is connected to the common electrode lines Vc1-Vcn, the second end of the second switching transistor Q2 is grounded via a fourth resistor R4, and the control end of the second switching transistor Q2 receives a control signal Vctrl. The first and second ends are either source or drain terminals, and the third resistor R3 and the fourth resistor R4 are both current-limiting resistors. Thus, through the above circuit connection, when it is detected that both the state-indicating signal Vs and the backlight enable signal LED-EN are valid, a valid control signal Vctrl is output, causing the plurality of first and second switches to be turned off. The output selection circuit 230 outputs the source drive signals sc1-scm to the display panel 100 through the multiple source lines S1-Sm and the common voltage signal Vcom to the display panel 100 through the common electrode lines Vc1-Vcn, thereby displaying a normal image. The effective control signal Vctrl is a low-level signal. When it is detected that either the state representative signal Vs or the backlight enable signal LED-EN is invalid, the output control signal Vctrl is invalid, that is, the output control signal Vctrl is a high-level control signal, which closes the multiple first switches and the second switches, causing the display panel 100 to receive the ground voltage GND through the multiple source lines and the common electrode line, thereby displaying a black image.

[0037] like Figure 4b As shown, in another embodiment, the common voltage generating circuit 400, the display panel 100, the logic circuit 220, the voltage detection circuit 210 and the source driving signal generating circuit 240 can be connected to Figure 4a The embodiments are completely consistent and will not be described in detail here. The difference is that in this embodiment, the output gating circuit 230 includes multiple first switches Q11-Q1m and one second switch Q2. The multiple first switches Q11-Q1m are connected to the multiple source lines S1-Sm in a one-to-one correspondence. The control terminals of the multiple first switches Q11-Q1m receive the control signal Vctrl to output the source drive signals sc1-scm or the ground voltage GND to the display panel 100 through the source lines S1-Sm according to the control signal Vctrl. The second switch Q2 is connected to the common electrode lines Vc1-Vcn. The control terminals of the second switch Q2 receive the control signal Vctrl to output the source drive signals sc1-scm or the ground voltage GND to the display panel 100 through the common electrode lines Vc1-Vcn according to the control signal Vctrl.

[0038] In this embodiment, both the first and second switches can be single-pole double-throw switches, or circuit components having similar functions to single-pole double-throw switches. The first switches Q11-Q1m can selectively output source signals sc1-scm or ground voltage GND to corresponding source lines S1-Sm. Similarly, the second switch Q2 can selectively output common voltage signal Vcom or ground voltage GND to corresponding common electrode lines vc1-Vcn.

[0039] Furthermore, in other embodiments, the voltage detection circuit 210 can replace the comparator U2 with a NOR gate, wherein the first and second input terminals of the NOR gate receive a low-level reference voltage Vref and a low-voltage drive signal VGL, respectively. When the low-voltage drive signal VGL is a low-level signal, the NOR gate outputs a high-level state-representing signal Vs, indicating that the low-voltage drive signal VGL is valid. The other circuit components and operating principles are exactly the same as described above. Alternatively, in another embodiment, the voltage detection circuit 210 can be directly replaced by a NOR gate, that is, the voltage detection circuit 210 includes a NOR gate, wherein the first and second input terminals of the NOR gate receive a low-level signal and the low-voltage drive signal VGL, respectively, and the output terminal outputs the state-representing signal Vs. When the low-voltage drive signal VGL is a low-level signal, the valid state-representing signal Vs is output.

[0040] Of course, these are only some examples of the source driver 200 that may be implemented by the present invention and are not intended to limit the present invention. In practical applications, other circuit elements may be substituted according to the above ideas.

[0041] Figure 5 FIG. 4 shows a schematic waveform diagram of various signals of a source driver in operation according to an embodiment of the present invention.

[0042] like Figure 5As shown, at time t1, the input voltage VIN rises, indicating power-on. At time t2, the low-voltage drive signal VGL begins to fall below the reference voltage Vref, or in other words, begins to transition to a low-level signal, entering the power-on preparation phase. During the time period t2-t3, because the backlight enable signal LED-EN is low, the source drive signal Source and the common voltage signal Vcom are both at the ground voltage GND, resulting in a black display. At time t3, the backlight enable signal LED-EN transitions to a high level, and the control signal Vctrl becomes active, causing the display panel 100 to begin receiving valid common voltage signal Vcom and source drive signal Source (i.e., sc1-scm). During the time period t3-t4, the display is normal, with normal display. At time t4, the backlight enable signal LED-EN returns to a low-level state, beginning the shutdown discharge phase. During the time period t4-t5, the source drive signal Source and the common voltage signal Vcom are both at the ground voltage GND, resulting in a black display. At time t5, the low-voltage driving signal VGL becomes high level, and the thin-film transistors TFT are all turned off, officially shutting down.

[0043] Figure 6 FIG. 4 shows a schematic flow chart of a source driving method according to an embodiment of the present invention.

[0044] The present invention further provides a source driving method, which is applicable to the source driver of the above embodiment and specifically includes steps S101 - S104 .

[0045] In step S101 , the voltage state of the low-voltage driving signal received by the source driver is detected to output a state characterization signal.

[0046] In this step, the voltage detection circuit 210 receives the low-voltage drive signal VGL and detects its level to output the state-representing signal Vs. When the low-voltage drive signal VGL is at a low level, the corresponding state-representing signal Vs is valid; when the low-voltage drive signal VGL is at a high level, the corresponding state-representing signal Vs is invalid.

[0047] In step S102 , a control signal is generated according to the received state representation signal and the backlight enable signal.

[0048] In this step, the active state of the backlight enable signal LED-EN is also detected. The backlight enable signal LED-EN is inactive when at a low level and active when at a high level. The logic circuit 220 generates a control signal Vctrl according to the state characterizing signal VGL and the backlight enable signal LED-EN.

[0049] In step S103 , when the state characterizing signal is valid and the backlight enabling signal is valid, the source driving signal and the common voltage signal are output to the display panel through the plurality of source lines and the common electrode lines respectively according to the control signal.

[0050] In this step, when it is detected that the status characterization signal Vs and the backlight enable signal LED-EN are both valid, a valid control signal Vctrl is output, so that the output selection circuit 230 outputs the source drive signals sc1-scm through multiple source lines S1-Sm to the display panel 100, and outputs the common voltage signal Vcom through the common electrode lines Vc1-Vcn to the display panel 100, displaying a normal picture.

[0051] In step S104 , when the state representation signal is invalid and / or the backlight enable signal is invalid, the ground voltage is output to the display panel through the plurality of source lines and the common electrode line according to the control signal.

[0052] In this step, when it is detected that either the state representation signal Vs or the backlight enable signal LED-EN is invalid, an invalid control signal Vctrl is output, so that the display panel 100 receives the ground voltage GND through multiple source lines and common electrode lines, thereby displaying a black screen.

[0053] Since this source driving method is applicable to the above-mentioned source driver, the specific working principle will not be described here in detail.

[0054] In summary, the source driver, display device, and source drive method provided by the present invention detect the valid states of the low-voltage drive signal VGL and the backlight enable signal LED-EN during the startup process, and accordingly generate a control signal to control the operating state of the output gating circuit. Based on the state of the control signal, the output gating circuit can select whether to output the source drive signal and the common voltage signal to the display panel via the source line and the common electrode line, respectively, or to output the ground voltage to the display panel via the source line and the common electrode line. Furthermore, the source drive signal and the common voltage signal are only output to the display panel to display the image normally when both the state-representing signal (the low-voltage drive signal) and the backlight enable signal are valid. Thus, during the startup process, the output timing of the source drive signal and the common voltage signal can be controlled based on the level states of the low-voltage drive signal and the backlight enable signal, ensuring that the timing of the source drive signal, the low-voltage drive signal, and the common voltage signal are consistent during the startup process. That is, the source drive signal and the common voltage signal are output only after the low-voltage drive signal is valid, and the source drive signal and the common voltage signal are output simultaneously, thereby avoiding problems such as white flickering during startup.

[0055] Furthermore, when either the low-voltage drive signal or the backlight enable signal is not in a valid state, a ground voltage is output to the display panel, rendering the display screen black. This ensures that the screen remains black during both the startup preparation phase and the shutdown discharge phase, disconnecting the source drive signal and the common voltage signal to prevent them from affecting the screen display, thereby suppressing problems such as screen flickering during startup.

[0056] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0057] Finally, it should be noted that: according to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments described. Obviously, based on the above description, many modifications and changes can be made. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention. This specification selects and specifically describes this embodiment in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A source driver provides a plurality of source driving signals to a display panel through a plurality of source lines, wherein the display panel also receives a common voltage signal through a common electrode line, The source driver includes: a voltage detection circuit for detecting a voltage state of a low-voltage driving signal received by the source driver and outputting a state characterization signal; a logic circuit, generating a control signal according to the received state representation signal and the backlight enable signal; and an output gating circuit, connected to the plurality of source lines and the common electrode line, and selectively outputting the source driving signal and the common voltage signal to the display panel or outputting the ground voltage to the display panel according to the control signal; Wherein, when the state characterizing signal is valid and the backlight enabling signal is valid, the output gating circuit outputs the source driving signal and the common voltage signal to the display panel according to the control signal, The voltage detection circuit comprises: A charge pump, wherein an input terminal receives a supply voltage and an output terminal is grounded via a first resistor and a second resistor connected in series; a voltage follower having a positive input terminal connected to an intermediate node between the first resistor and the second resistor, a negative input terminal connected to an output terminal, and using the voltage of the intermediate node as a reference voltage; The comparator has a positive input terminal connected to the output terminal of the voltage follower, receives the reference voltage, a negative input terminal receives the low-voltage drive signal, and an output terminal generates the state representation signal.

2. The source driver according to claim 1, wherein: The output gating circuit outputs the ground voltage to the display panel according to the control signal when the status representation signal is invalid and / or the backlight enable signal is invalid.

3. The source driver according to claim 2, wherein: The state characterizing signal is valid when the low-voltage driving signal is at a low level, and invalid when the low-voltage driving signal is at a high level; the backlight enabling signal is valid when the backlight enabling signal is at a high level, and invalid when the backlight enabling signal is at a low level.

4. The source driver according to claim 3, wherein: When the low-voltage driving signal is less than the reference voltage, the state characterizing signal is valid; when the low-voltage driving signal is greater than the reference voltage, the state characterizing signal is invalid.

5. The source driver according to claim 3, wherein: The logic circuit includes a NAND gate, wherein a first input terminal and a second input terminal of the NAND gate receive the state representation signal and the backlight enable signal respectively, and an output terminal outputs the control signal; The voltage detection circuit includes a NOR gate, wherein a first input terminal and a second input terminal of the NOR gate receive a low-level signal and the low-voltage driving signal respectively, and an output terminal outputs the state representation signal.

6. The source driver according to claim 1, wherein: The output gating circuit comprises: a plurality of first switching transistors, wherein first ends of the plurality of first switching transistors are connected to a plurality of source lines in a one-to-one correspondence, second ends of the plurality of first switching transistors are grounded via a third resistor, and control ends of the plurality of first switching transistors receive the control signal; and A second switch tube, wherein a first end of the second switch tube is connected to the common electrode line, a second end of the second switch tube is grounded via a fourth resistor, and a control end of the second switch tube receives the control signal.

7. The source driver according to claim 1, wherein: The output gating circuit comprises: a plurality of first switches connected to the plurality of source lines in a one-to-one correspondence, wherein control ends of the plurality of first switches receive the control signal to output the source drive signal or the ground voltage to the display panel through the source line according to the control signal; and The second switch is connected to the common electrode line, and the control end of the second switch receives the control signal to output the source driving signal or the ground voltage to the display panel through the common electrode line according to the control signal.

8. A display device comprising: A display panel, the display panel comprising a pixel array, the pixel array comprising a plurality of pixel units arranged in an array; A gate driver, connected to a plurality of rows of pixel units via a plurality of gate lines, and providing a gate drive signal to the pixel units; The source driver according to any one of claims 1 to 7, wherein a plurality of source lines are connected to a plurality of columns of pixel units to provide source drive signals to the pixel units; as well as The common voltage generating circuit is connected to a plurality of pixel units through common electrode lines and provides a common voltage to the pixel units.

9. A source driving method, applied to the source driver according to any one of claims 1 to 7, the source driving method comprising: detecting a voltage state of a low-voltage driving signal received by a source driver, and representing the signal with an output state; generating a control signal according to the received state characterization signal and the backlight enable signal; When the state characterizing signal is valid and the backlight enabling signal is valid, outputting a source driving signal and a common voltage signal to the display panel through a plurality of source lines and a common electrode line respectively according to the control signal; as well as When the state representation signal is invalid and / or the backlight enable signal is invalid, the ground voltage is output to the display panel through a plurality of source lines and common electrode lines according to the control signal.

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