Column strobe signal control circuit

Abstract

A column selection signal control circuit is provided. The circuit includes a plurality of triggers enabled by a clock signal and outputs a control signal related only to the system operating frequency. The control signal output by the trigger is compared with the delayed control signal through a delay comparison circuit. According to the output of a logic AND gate, an output signal with a pulse width less than or equal to the original control signal is obtained, so as to reduce the pulse width of the column selection signal under the low-frequency working condition of the system. In this way, while eliminating the influence of the process, voltage and temperature on the opening time of the column selection signal, the power consumption caused by the continuous operation of the sense amplifier when the system is working at a low frequency is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor chip storage technology, and in particular to a column selection signal control circuit which eliminates the influence of process, voltage and temperature on the column selection pulse width and changes it according to the system operating frequency. Background Art

[0002] The data in the computer is represented by binary 1 or 0. The memory stores data in the following way: for a storage unit in the storage array, when the capacitor therein is sensed to have a charge, it can be used to represent a binary 1, otherwise, it can be used to represent a binary 0. On this basis, the read operation of the memory is essentially to sense and determine whether there is a charge in the capacitor of a storage unit in the storage array, or to sense the charge difference between the capacitor and the bit line, while the write operation of the memory is to recharge and discharge the array of storage units by means of a refresh circuit.

[0003] The storage device contains a large number of storage cells, which are distributed in rows and columns to form a storage array. In order to distinguish and represent these storage cells, the system configures row addresses and column addresses for the storage array. The row and column addresses point to the row or column accessed by a data read or write operation, respectively. At the same time, the row address and column address uniquely point to a storage cell in the array.

[0004] At the beginning of a read / write operation, the row address and column address must be activated first. The row address is used to select the row for the read / write operation, and the column address is used to select the column corresponding to the read / write operation. When the column address is activated, the bit line is connected to the data input and output of the storage array and shares the charge between the two. After a read / write operation is completed, the data in the storage array is refreshed to wait for the next data read / write operation.

[0005] According to the storage array structure and data reading and writing method described above, it is easy to understand that in order to ensure the accuracy of data reading and writing in the computer, it should always be required to map between data and address, that is, the address signal and the data signal are always synchronized. As mentioned above, when the column address is activated, the bit line can be connected to the storage array and share the charge. Therefore, the pulse width of the column selection signal CSL (that is, the activation or opening time of the selection signal) is particularly important. The pulse width and signal activation time should correspond to the data signal.

[0006] Under the prior art, the pulse width of the column selection signal is generally controlled by a delay circuit. The function of the delay circuit is to achieve a fixed delay time for the system. Through the fixed time delay signal output by the delay circuit, the pulse width of the column selection signal is maintained within the same turn-on duration and turn-on interval. However, memories (such as DRAM) often need to be able to support operation at different operating frequencies. In theory, the system requires that at different operating frequencies, the turn-on time and duration of the selection signal remain consistent with the delay time output by the delay circuit. But at the same time, another problem is that the components that implement the delay circuit (such as a delay circuit composed of an even number of inverters) are susceptible to changes in process, voltage and temperature during execution, which will cause the delay time output by the delay circuit under different PVT environments to not always be the same, and the fluctuation of the delay time output by the delay circuit directly affects the turn-on and maintenance duration of the selection signal, which ultimately causes a mismatch between the selection address and the data.

[0007] Therefore, the control method of the selection signal following the technology should be improved to solve the above-mentioned technical problems of the prior art. Summary of the invention

[0008] In view of this, the present invention provides a method for solving at least one of the above problems.

[0009] In order to solve the above technical problems, the present invention provides a column selection signal control circuit, which includes at least one trigger, which uses the read and write commands as data input; a clock signal, which is a control signal that changes in response to the system frequency, and the clock signal is used as an enable signal and is connected to the enable end of the trigger, wherein the trigger outputs a selection start signal according to the clock signal, and the selection start signal is connected to the column decoder, so that the column decoder outputs a column selection signal according to the selection start signal.

[0010] As a more preferred embodiment of the present scheme, there is one column address signal and one read / write command signal, and is used to output a column selection signal through a column decoder, wherein the control circuit also includes at least two triggers, the previous stage trigger uses the read / write command as data input, and the output of the previous stage trigger is used as the input of the next stage trigger, wherein the two triggers respectively output two signals, defined as a first signal and a second signal, the first signal and the second signal are connected to a logic gate "OR" to obtain a first control signal, and the first control signal is connected to a column decoder so that the column decoder outputs a column selection signal according to the first control signal.

[0011] As a more preferred embodiment of the present invention, a delay comparison circuit is further included, the output of which is used as the input of the column decoder. The delay comparison circuit is formed by a delay circuit and a comparison circuit. The delay circuit delays the first control signal to obtain a second control signal. The comparison circuit compares the first control signal and the second control signal to output a third control signal whose pulse width is less than or equal to the first control signal. The comparison circuit includes a logic gate "AND", and the two inputs of the logic gate "AND" are respectively the first control signal and the second control signal after the first control signal is delayed.

[0012] As a further preferred embodiment of the present invention, the delay circuit includes a first delay unit and a second delay unit, and a logic NAND gate configured between the output of the first delay unit and the input of the second delay unit, the input of the first delay unit is the first control signal, and the first delay unit delays the first control signal according to a preset delay time; one input of the logic NAND gate is the first control signal, and the other input is the input of the first delay unit, the logic NAND gate outputs a first delay signal, the first delay signal serves as the input of the second delay unit, and the output of the second delay unit is the second control signal.

[0013] Compared with the prior art, the beneficial technical effects achieved by implementing the present invention are:

[0014] This solution first uses a counter counting method to replace the existing delay circuit method to generate a column selection signal with a fixed opening time. In particular, the final control signal output is related to the operating frequency, avoiding a series of problems caused by the change in the opening time of the column selection signal due to the influence of the working environment on the components. At the same time, in order to solve the power consumption problem caused by the long-term opening of the sense amplifier when the system works at a low frequency, a delay comparison circuit is introduced to reduce the pulse width of the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is an equivalent circuit diagram, showing an equivalent circuit structure of using a delay circuit to realize column selection signal start control in the prior art;

[0016] Figure 2 is a timing diagram showing Figure 1 The following conventional structure shows the timing of the start of the selection signal:

[0017] Figure 3 is a timing diagram showing Figure 1 The conventional structure shown shows the timing of the strobe signal being turned on in a fast environment;

[0018] Figure 4is a timing diagram showing Figure 1 The conventional structure shown shows the timing of the strobe signal being turned on in a slow environment;

[0019] Figure 5 is a curve diagram showing a state in which the strobe signal is extended under a slow environment, resulting in an IO line data reading error during continuous read and write operations;

[0020] Figure 6 is a schematic diagram showing an equivalent structure of a delay circuit in the prior art;

[0021] Figure 7 is a schematic diagram showing an equivalent circuit structure of the column selection signal control circuit in the second embodiment of the present invention;

[0022] Figure 8 is a timing diagram showing Figure 7 In the second embodiment shown, the clock signal count is used to control the timing of the CSL start signal;

[0023] Fig. 9 is a schematic diagram showing an equivalent circuit structure of the column gating control circuit described in the third embodiment of the present invention;

[0024] Fig.10 is a schematic diagram showing an equivalent circuit structure of the column selection signal control circuit described in the fourth embodiment of the present invention;

[0025] Fig.11 is a timing diagram showing Fig.10 In the fourth embodiment shown, a clock signal count is used to control the timing of the CSL start signal in the high frequency working state;

[0026] Fig.12 is a timing diagram showing Fig.10 In the fourth embodiment shown, the clock signal count is used to control the timing of the CSL start signal under low frequency operation. DETAILED DESCRIPTION

[0027] First, taking an existing column selection signal architecture as an example, the corresponding relationship between the column selection signal and the column address is explained. Figure 1 , Figure 1 An existing column strobe signal framework structure is shown. The equivalent circuit structure shown in the figure includes two paths, namely the column address path and the read-write command path. The read-write command path includes an SR latch, the data input of the latch is the read-write command, and its enable input is the read-write command delay signal output after the read-write command is delayed by the delay circuit. When the read-write command delay signal enables the SR latch, the read-write command is output to form a column strobe enable signal. The column strobe enable signal enables the column decoder, and the column decoder decodes the column address and outputs the final column strobe signal.

[0028] The timing of the above process is as follows Figure 2 The waveform shown, Figure 2 The arrow in the figure indicates the time interval between the first high level of the read / write command and the first high level of the read / write command delay signal. It can be seen that, ideally, when the subsequent signal arrives, the delay time controlled and maintained by the delay circuit always maintains the same length. Figure 2 , Figure 1 The circuit shown in Figure 2 During the time period shown, two column selection signals are output, which are defined as CSL0 and CSL1. It can be seen that CSL0 and CSL1 correspond to the first level fluctuation and the second level fluctuation of the column selection start signal (the level rises from low and then decreases from high), and the pulse width of CSL0 and CSL1 is consistent with the start time of the column selection signal. At the same time, the start time and start duration of each column selection signal, or the pulse width of each column selection signal output by the circuit, corresponds to each column address output on the column address line. In this way, the mapping between the column selection signal and the column address is realized.

[0029] However, as mentioned above, the components in the delay circuit will be affected by PVT (process, voltage and temperature), which may cause the delay time of the same delay circuit in different environments to have deviations in the turn-on time and / or turn-on duration. For ease of explanation, in the following text, the environment in which the delay time of the delay circuit output is prolonged is referred to as a "slow environment", and the environment in which the delay time of the delay circuit output is shortened is referred to as a "fast environment". In these environments, the timing or data of the read and write operations may have different degrees of read and write errors.

[0030] For example, Figure 3 and Figure 4 , respectively, the timing of the following strobe pulse widths in the fast and slow environments, and Figure 2 Same, Figure 3 and Figure 4 The arrow in the middle is also used to indicate the time interval from the first high level of the read / write command to the first high level of the read / write command delay signal. Figure 3 and Figure 4 It can be seen that the timing of the read and write commands and column addresses in the two environments remains the same, but the delay time is significantly different. Figure 2 and Figure 3In a "fast environment", the too fast delay time interval causes the read and write command delay signals to arrive faster in timing. Compared with the situation in a normal environment, under the influence of the fast delay signal, the column enable signal can only be maintained for a short time. Therefore, during the time when the column enable signal is turned on, the storage array cannot read all the data completely. Figure 2 and Figure 4 In a "slow environment", the long delay time causes the read and write command delay signals to arrive later in the timing. Figure 1 , the width of the CSL start signal output by the SR latch is further lengthened. The consequences of the further lengthening of the pulse width of the CSL start signal can be seen in Figure 5 , Figure 5 The curve in FIG. 1 shows that the strobe signal is extended in a slow environment, resulting in an IO line data reading error during a continuous read operation. Figure 2 Look again Figure 5 , the figure includes the same two column selection signals, which are still CSL0 and CSL1. As mentioned above, when the column selection address is activated, the bit line can be connected to the data input and output of the storage array and share the charge between the two, that is, when the high level of CSL0 and CSL1 arrives, the IO line is activated and connected to the bit line. Looking back at the previous explanation of the data reading and writing part, since the essence of the read and write operation is the induction charge difference, after the data read and write operation is completed, the IO line still needs a certain amount of time to restore the original potential in order to arrive the next read and write instruction. If the column selection signal is turned on for too long, the time available to restore the IO line potential will be compressed, and it is very likely that the IO line will not be restored to its proper potential, which will lead to the following result. Figure 5 In the situation shown in the figure, the dotted line delineates the mapping relationship between the bit line and the IO line when the selection signal is turned on. It can be seen that when the selection signal CSL0 is turned on, the bit line 0 is interconnected with the input and output line IO. Since the column selection signal is extended, the IO line lacks sufficient time to recover to the initial low level. In this way, at the end of the pulse width of the selection signal CSL0, the IO line is already connected to the bit line 1. Therefore, when the selection signal CSL1 is turned on, the IO line is still connected to the bit line 1. In this way, the data of the bit line 1 will be overwritten by the IO line during the time when CSL1 is turned on. In other words, data reading and writing errors occur during the time when CSL1 is turned on. Therefore, according to Figures 3 to 5 From the presented timing and status, it is obvious that during the read and write operations, a column selection signal that is too long or too short is not desirable.

[0031] Figure 6The schematic diagram shows the equivalent structure of the common delay circuit in the prior art. As shown in the figure, an even number of inverters are sequentially combined to form a chain delay circuit. When the signal passes through each inverter, it can be regarded as charging and discharging the input gate capacitor of the next inverter. Therefore, after charging step by step, the signal is delayed. Therefore, the preferred embodiment of the present invention first realizes that the reason for the above technical problems is that it is impossible to eliminate the influence of the delay circuit components due to factors such as process, voltage and temperature, and the delay time generated is extended or shortened.

[0032] However, even if other delay circuits known in the prior art are used, such as a delay circuit with an even number of inverters in series with resistors, or an even number of inverters in series with a parallel combination of capacitors, the aforementioned components are still affected by environmental factors. Therefore, an improvement idea that is more easily thought of by those skilled in the art is to provide a technical means to generate a fixed delay time without being affected by PVT.

[0033] Embodiments of the present invention will be described below with reference to the accompanying drawings. It will be appreciated by those skilled in the art that the described embodiments may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the drawings and description are illustrative in nature and are not intended to limit the scope of protection of the claims. In addition, in this specification, the drawings are not drawn to scale and the same reference numerals represent the same parts.

[0034] It should be noted that the expressions “first” and “second” used in the embodiments of the present invention are intended to distinguish two non-identical entities with the same name or non-identical parameters. It can be seen that “first” and “second” are only for the convenience of expression and should not be understood as limitations on the embodiments of the invention. The subsequent embodiments will not explain this one by one.

[0035] Embodiment 1

[0036] In the field of memory chips (mainly DRAM), in order to prevent the device from being affected by environmental changes, the technical means for generating fixed delays can also be implemented in a digital way. The expectation of the preferred embodiment of the present invention is that when the chip is at different operating frequencies, the turn-on time of the memory chip column selection signal can always maintain the same turn-on duration, or the column selection signal pulse width maintains a consistent width at different operating frequencies of the chip. For the above-mentioned same duration and consistent width, the preferred embodiment adopts the means of clock signal counting to implement.

[0037] The counting means may be any one or more of the various digital counters commonly seen in the technical field, and both the adding counter and the subtracting counter that can realize counting should be applied thereto. For example, in the Chinese invention patent with the authorization announcement number CN116758965B, a flip-flop (D flip-flop) is shown that triggers the jump according to the clock signal to output a pulse signal to trigger the cycle counting. When such a flip-flop is applied to the first embodiment of the present invention, the read-write command signal is connected to the data input end of the flip-flop, and enabled by a clock signal to output a control signal delayed by the clock signal, and the control signal is used as the start signal of the column selection and connected to the column address decoder, so that the column decoder decodes the column address signal and outputs the final column selection address.

[0038] Define one output of the trigger as the first signal, then in essence, the signal pulse width of the first signal should be one cycle of the clock signal (tCK). The clock signal selected in Example 1 is a variable control signal corresponding to the system operating frequency. In other words, the length of one cycle of the clock signal will change with the change of the system operating frequency. Figure 5 After the data read and write operation is completed, the IO line still needs a certain amount of time to restore the original potential in order to facilitate the arrival of the next read and write instruction. Under this premise, in this embodiment, a pulse width of the first signal also needs to reserve time for the IO line to restore its original potential. Therefore, the first embodiment is more often used in the low-frequency working scenario of the system.

[0039] Embodiment 2

[0040] Since the first embodiment is more suitable for low-frequency working scenarios, the present invention provides a better second embodiment. Figure 7 , Figure 7 FIG. 1 is a schematic diagram showing an equivalent circuit structure of the column selection signal control circuit in the second embodiment of the present invention, referring to FIG. Figure 7 Compare Figure 1 Compared with the existing circuit, the path from the column address to the column decoder has not changed, while the read-write command path has been improved from the original single SR latch to two serially connected D flip-flops (D flip-flops). For the convenience of explanation, according to the order of arrival of the read-write command and the clock signal, the two D flip-flops are defined as the first flip-flop and the second flip-flop respectively. The data input of the first flip-flop is the output of the first flip-flop of the read-write command, which is used as the data input of the second flip-flop. At the same time, the enable terminals of the first flip-flop and the second flip-flop are connected to the same clock signal. On this basis, the output of the first flip-flop is defined as the first signal, and the output of the second flip-flop is defined as the second signal. In this embodiment, the first signal and the second signal are connected to the logic gate "OR", and the output of the logic gate "OR" is used as a new column selection (CSL) start signal.

[0041] Figure 8 is a timing diagram showing Figure 7 In the second embodiment shown, the clock signal count is used to control the timing of the CSL start signal. Figure 2 Compare Figure 8 In the second embodiment, the same read / write command signal and column address signal are selected. As shown in the figure, when the first rising edge of the clock signal arrives, the read / write command is set low, and the first trigger and the second trigger have no output at this time, and signal 1 and signal 2 are set low. When the first high level of the read / write command arrives, the clock signal is set low at this moment, and the first trigger and the second trigger still have no output at this time, and signal 1 and signal 2 are still set low.

[0042] With the arrival of the second high level of the clock signal, since the D flip-flop is edge triggered (rising edge or falling edge), that is, the signal will only be transferred from the input end (D end) of the D flip-flop to the output end (Q end) at the rising edge or falling edge, otherwise the flip-flop state will not change. Therefore, for the first flip-flop, at this moment, there is input at its input end, and the enable end is at the rising edge, and the input read and write commands at the input end are written, but at this time, the first flip-flop has not yet transferred its output to the second flip-flop. At the same moment, although it is enabled by the clock signal together with the first flip-flop, since there is no input at the input end, the second flip-flop has no output at this time. Therefore, when the second high level of the clock signal arrives, signal 1 is set high and signal 2 is set low. Moreover, due to the aforementioned characteristics of the D flip-flop, this signal state will be maintained throughout the second clock cycle of the clock signal. When the third high level of the clock signal arrives, the read and write commands are set low, and the data in the first trigger is output through the output terminal (Q terminal) and input to the data terminal (D terminal) of the second trigger. Under the influence of this input, the second trigger outputs signal 2. In contrast to the state at the second high level of the clock signal, signal 1 is set low and signal 2 is set high at this time. Similarly, this output state will be maintained throughout the third clock cycle of the clock signal.

[0043] Combining two adjacent clock cycles of the clock signal, it is not difficult to see that the pulse width, or the holding time, of signal 1 and signal 2 is a complete cycle of the clock signal (tCK). Since the logic gate "OR" is used, as long as one of signal 1 and signal 2 is set high, the output result of the logic OR is high. Figure 8 As shown, the pulse widths of the two column selection signals CSL0 and CSL1 are respectively two complete clock cycles (tCK). In other words, the duration for which the column selection address is activated is always maintained at two complete clock cycles.

[0044] It should be understood that the selection signal control method provided in Example 2, since the signal turn-on time is always related to the clock period of the clock signal, and the period of the clock signal is the inverse of the system operating frequency, the turn-on time generated by this method will only change adaptively with the system operating frequency, and will not be affected by the process, voltage and temperature.

[0045] It should be noted that in the second embodiment, the opening time of the column selection signal is two complete clock cycles of the clock signal, which coincides with the number of D flip-flops used in the circuit. Therefore, in other preferred embodiments of the present invention, those skilled in the art, based on the premise of knowing the second embodiment, should be able to combine a column selection signal with a wider pulse width by adding more D flip-flops according to the design requirements of the circuit delay in accordance with the same idea as the second embodiment. For example, when four D flip-flops connected in series are selected, the opening time of the column selection signal generated by the circuit should be four complete clock cycles of the clock signal. However, it should be noted that the interval between the arrival of the read-write command and the first opening time of the column selection signal should still be half a clock cycle. In other words, in the design based on the second embodiment, the time interval between the appearance of the read-write instruction and the activation of the column selection signal is still fixed.

[0046] Embodiment 3

[0047] In fact, the selection of the number of D flip-flops will also take into account factors such as usage habits. For example, the tCCD time of the storage array refers to the minimum interval between two consecutive reads (or two consecutive writes). Looking back at the above content, it is known that within this tCCD time, a series of operations need to be completed, including CSL opening, the second-stage sense amplifier (SSA) amplifying data, CSL closing, and IO line and SSA resetting the potential. The tCCD time of a common storage array is usually 4 tCKs, so the selection of two flip-flops to achieve a pulse width of 2tCK can leave 2tCKs of equal length to facilitate operations such as resetting the potential. When the current storage array (such as DDR4) allows a tCCD greater than 4tCK, more D flip-flops can naturally be selected to form a longer column enable opening time.

[0048] Fig. 9 FIG. 1 is a schematic diagram showing an equivalent circuit structure of the column gating control circuit in the third embodiment of the present invention, see FIG. Fig. 9, in this embodiment, three triggers are included. Looking back at the second embodiment, the third embodiment adds a trigger on the basis of the second embodiment, which is defined as the third trigger, and the added third trigger is also enabled by the same clock signal, and uses the output of the second trigger of the previous stage as the input of the third trigger, and outputs a signal 3. In order to compare the first to third signals output by the three triggers, the input end of the logic gate "or" selected in the third embodiment is connected to the first to third signals at the same time, so that a CSL start signal with a pulse width of 3 tCK can be combined.

[0049] Embodiment 4

[0050] Through the first to third embodiments, the preferred embodiment of the present invention has realized the fixed delay time between the read and write commands and the column strobe signal, and the fixed start time of the column strobe signal at different operating frequencies of the system by means of timer counting. However, through long-term practice and experiments, the preferred embodiment of the present invention has realized that, based on the structure of the first embodiment, although the technical purpose of the present invention has been achieved, it will face new problems.

[0051] When the memory reads and writes data, it also needs to rely on two-stage sense amplifiers to achieve this. This is because the voltage values ​​maintained by the capacitors in the bit lines, word lines, and storage cells are usually very low. In order to facilitate the comparison of the voltage difference and output the data after obtaining the voltage difference, it is necessary to amplify the voltage difference of the differential data through the sense amplifier and the subsequent inductive amplifier circuit before reading. As mentioned earlier, when the column address is activated, the bit line can be connected to the storage array and share the charge. Then, during the actual reading operation, the amplified storage cell charge on the bit line is shared with the IO line, and further amplified by the second-stage sense amplifier (SSA) to meet the data transmission requirements.

[0052] In this framework, looking back Figure 8 It should be understood that when the column address needs to be read, the CSL start signal needs to be maintained for two clock cycles, but this also means that during the period when the column selection signal is turned on, the sense amplifier is always in working state. It is conceivable that as the system operating frequency decreases, the clock cycle at low frequency will be extended. Then, based on the circuit structure of the second embodiment, the turn-on time of the column selection signal will also be extended accordingly with the clock cycle, so the second sense amplifier will also need to maintain the execution state for a longer working period. Considering the frequency of addressing, accessing, reading and writing of the storage device, this will obviously bring about unavoidable power consumption problems.

[0053] In response to this problem, the fourth embodiment of the present invention realizes that the key to the above problem is that under the architecture of the first to third embodiments, the turn-on time of the column enable signal is directly related to the system operating frequency, and is only related to the operating frequency, which will cause the turn-on time of the column enable signal to fluctuate significantly with the change of the system operating frequency. Considering the power consumption problem, the technical idea of ​​the fourth embodiment is that since the second embodiment can work stably at high frequency and there is no power consumption problem, it only needs to solve its problem at low frequency. At low frequency, it only needs to introduce additional means to try to shorten the turn-on time of the column enable signal to reduce the power consumption problem.

[0054] Fig.10 Schematic diagram showing the equivalent circuit structure of the column selection signal control circuit in the fourth embodiment of the present invention. Figure 7 Compare Fig.10 , Embodiment 4 adds a delay unit between the logic gate "OR" and the column encoder based on the circuit of Embodiment 2. As shown in the figure, the delay unit includes two delay circuits and two logic gates, which are consistent with Embodiment 2. For the convenience of explanation, in Embodiment 4, according to the transmission direction of the signal and the order of arrival of the signal, the two delay circuits are defined as the first delay circuit and the second delay circuit, respectively, wherein the first delay circuit is relatively close to the original logic gate "OR" in the direction of signal transmission, and the second delay circuit is relatively close to the original column encoder. The two logic gates include a logic "NAND" gate and a logic gate "AND", the logic "NAND" gate is located between the first and second delay circuits, and the logic gate "AND" is located between the second delay circuit and the column encoder.

[0055] Compared to Figure 7 In the circuit of the fourth embodiment, four signals are introduced, which are respectively defined as signal 3 to signal 6. Specifically, Fig.10 , signal 3 is the original CSL start signal, which is the output of the logic gate "OR". Signal 3 is used as the input of the first delay circuit, the input of the logic "NAND" gate, and the input of the logic gate "AND". Signal 4 is the output of the second delay circuit, signal 5 is the output of the logic "NAND" gate, and also serves as the input of the second delay circuit, signal 6 is the output of the second delay circuit, and the other output of the logic gate "AND".

[0056] Looking back at the idea of ​​solving the technical problem of the fourth embodiment, since there is no need to modify the control method of the second embodiment, the output result of the original control circuit at high frequency can be retained, and at low frequency, the column selection signal output by the original circuit is delayed and output again through the delay circuit, which can achieve the technical purpose of shortening the opening time of the column selection signal to reduce power consumption. Therefore, under the guidance of this idea, it is only necessary to set the logic gate "AND" to compare the two column selection signals generated at a certain working frequency, and select the one with relatively less opening time as the last output column selection signal. Therefore, in the circuit, the signal 3 of the same part of the output as the second embodiment will be used as one input of the logic gate "AND" to compare with the delay generated by the delay circuit. In the comparison with the signal 4, through the logic "NAND" gate, the output signal 5 in the output process is a signal that will only output a low level when the signal 3 and the signal 4 are both kept at a high level, and is always set to a high level in other states. In the comparison between signal 3 and signal 6, through the logic "AND" gate, the output column selection signal is only high when signal 3 and signal 6 are both kept at high level, that is, the column selection is activated. In other words, the output logic of the circuit structure shown in the fourth embodiment is to always select a signal with a relatively short turn-on time (a relatively small signal pulse width) as the output when the system operating frequency is low, thereby solving the power consumption problem of the sense amplifier always being executed due to the long turn-on time of the column selection signal.

[0057] In addition, for the delay circuit used in the fourth embodiment, the delay circuit disclosed in the preferred embodiment of the present invention can be selected as follows: Figure 6 The existing structure shown may also select other existing structures disclosed in the present invention, including an even number of inverters in series with resistors, or an even number of inverters in series with a parallel combination capacitor, or other delay circuits known or should be known to those skilled in the art, such as an oscillator formed by sequentially connecting an odd number of adjustable delay units as inverters disclosed in the Chinese invention patent with authorization announcement number CN116614114B. Here, all applicable delay units and delay circuits are no longer listed, and those skilled in the art should know how to choose from the above-mentioned prior art means according to the application scenario and delay requirements.

[0058] Fig.11 and Fig.12 The timing states of the equivalent circuit shown in the fourth embodiment under high frequency and low frequency are shown respectively. Fig.11 In high frequency state, Fig.12 The solid arrows in the two figures are used to represent the delay time between the first rising edge of signal 3 and the first rising edge of signal 4 under high and low frequencies, and the delay time between the first rising edge of signal 5 and the first rising edge of signal 6 output at the final output. Fig.11 and Fig.12 It can be seen that in the high-frequency working state, the output maintenance time (pulse width) of the read and write commands and column addresses is shorter than that of the low-frequency working state of the system. Another manifestation in the timing of the attached figure is that when the system works at high frequency, the distance between the two adjacent high levels of the read and write commands and column addresses will be smaller. Conversely, when the system works at low frequency, the interval between the two will be longer.

[0059] Look first Fig.11 Since signal 3 is not delayed by the delay circuit, signal 3 with a shorter on time is always output when compared with signal 4 and signal 5. Therefore, the pulse width of the column selection signal outputted finally is consistent with that of signal 3. In other words, at a high frequency, the column selection signal outputted by embodiment 4 is the same as that of embodiment 2. Fig.12 , compared to Fig.11 In the high-frequency scenario shown, in the low-frequency state, the longer pulse width of the read and write command will make the pulse width of signal 3 correspondingly wider. On the other hand, after the delay of the two-way delay circuit, the change from signal 4 to signal 6 is that the signal opening time is getting longer and longer. Therefore, if the signal 3 is still output, the column selection signal is kept for a long time, which will cause the aforementioned power consumption problem of the sense amplifier. Therefore, by passing the signal 3 and the signal 6 through the logic gate "AND", the signal pulse width can be effectively reduced to achieve the technical effect of reducing the power consumption of the system. It is worth mentioning that although the two-way delay circuit in the fourth embodiment always keeps the working state and generates some power consumption, the power consumption of the delay circuit can be ignored compared with the power consumption of the second-stage sense amplifier (SSA). This is because the delay circuit itself is a logic circuit, and there is no leakage of the sense amplifier. More importantly, the amplification of one bit of data requires a second-level sense amplifier for amplification, and the number of bits involved in a read operation is often dozens or even hundreds, which means that the number of SSAs turned on at the same time will also reach the same number, and the power consumption of the delay circuit and the power consumption of the SSA that keeps working longer are not on the same order of magnitude.

[0060] In the fourth embodiment of the present invention and more preferred embodiments of the present invention based on the fourth embodiment, the circuit output shown in the fourth embodiment is always output in a form roughly consistent with signal 3 when the system operating frequency is higher than a certain specific value, and when the system operating frequency is reduced to below the specific value, it will be output as the logical AND result of signal 3 and signal 6. Obviously, when those skilled in the art know the fourth embodiment and set the specific value, they should also know how to adjust the delay configuration of the delay circuit according to the guidance of the first to fourth embodiments after fully understanding the performance of the target storage array and the SPEC (semiconductor product technical specification) requirements to be met, such as specifically configuring the tCCD, tWR, etc. of the storage array.

[0061] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the attached claims.

Claims

1. A column strobe signal control circuit, the circuit comprising a column address signal and a read / write command signal, and used to output a column strobe signal through a column decoder, wherein: The control circuit also includes At least two triggers, the trigger at the preceding stage uses the read / write command as data input, and the output of the trigger at the preceding stage is used as the input of the trigger at the succeeding stage, and outputs a first signal and a second signal respectively, and the first signal and the second signal are connected to a logic gate "OR" to obtain a first control signal; A clock signal, which is a control signal that changes in response to the system frequency, and the clock signal is used as an enable signal and is connected to the enable terminal of the trigger, wherein: The trigger outputs a gate enable signal according to the clock signal, and the gate enable signal is connected to the column decoder, so that the column decoder outputs a column gate signal according to the gate enable signal. It also includes a delay comparison circuit, the output of which serves as the input of the column decoder. The delay comparison circuit is formed by combining a delay circuit and a comparison circuit. The delay circuit delays the first control signal to obtain a second control signal. The comparison circuit compares the first control signal and the second control signal to output a third control signal whose pulse width is less than or equal to the first control signal. The comparison circuit includes a logic gate "AND", and the two inputs of the logic gate "AND" are the first control signal and the second control signal respectively.

2. The column selection signal control circuit according to claim 1, wherein: The delay circuit includes a first delay unit and a second delay unit, and a logic NAND gate configured between an output of the first delay unit and an input of the second delay unit. The input of the first delay unit is the first control signal, and the first delay unit delays the first control signal according to a preset delay time; One input of the logic NAND gate is the first control signal, and the other input is the input of the first delay unit. The logic NAND gate outputs a first delayed signal, which serves as the input of the second delay unit. The output of the second delay unit is the second control signal.

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