Semiconductor memory and electronic device

Abstract

The invention relates to a semiconductor memory and an electronic device. The semiconductor memory includes: a plurality of memory blocks; the array substrate comprises a plurality of memory blocks, at least one column gating control circuit, each column gating control circuit is coupled with at least two memory blocks in the plurality of memory blocks, each memory block is coupled with one column gating control circuit, and the memory blocks coupled with the same column gating control circuit share one column gating control circuit; the column gating control circuit is used for receiving a selection signal of each memory block coupled with the column gating control circuit, and generating a corresponding memory block control signal based on the selection signal of each memory block; and the storage blocks are used for receiving the corresponding storage block control signals and executing read / write operation in response to the storage block control signals. The occupied area of the column selection control circuit in the semiconductor memory can be saved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a semiconductor memory and an electronic device. Background Art

[0002] Low Power Double Data Rate SDRAM (LPDDR) is a low-power memory communication standard developed by the Joint Electron Device Engineering Council (JEDEC) for portable electronic terminals. It can be simply divided into five generations: LPDDR, LPDDR2, LPDDR3, LPDDR4 (including LPDDR4X) and LPDDR5. The number of storage blocks in LPDDR5 is twice that of LPDDR4, which results in the number of related circuits in LPDDR5 being doubled, which takes up a lot of area. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor memory and electronic device that can save occupied area.

[0004] In a first aspect, a semiconductor memory is provided, the semiconductor memory comprising:

[0005] Multiple storage blocks;

[0006] At least one column gating control circuit, each of the column gating control circuits is coupled to at least two of the plurality of storage blocks, each of the storage blocks is coupled to one column gating control circuit, and each of the storage blocks coupled to the same column gating control circuit shares one column gating control circuit;

[0007] The column gating control circuit is used to receive the selection signal of each of the storage blocks coupled thereto, and generate a corresponding storage block control signal based on the selection signal of each of the storage blocks;

[0008] The storage block is used to receive the corresponding storage block control signal and perform a read / write operation in response to the storage block control signal.

[0009] In one embodiment, the column gating control circuit comprises:

[0010] A merging circuit, used for receiving the selection signals of the respective storage blocks coupled to the column gating control circuit, and merging the received selection signals of the respective storage blocks to generate a total selection signal;

[0011] a delay control circuit connected to the merging circuit and configured to generate a total control signal based on the received total selection signal;

[0012] an identification generating circuit, configured to receive selection signals of the respective storage blocks coupled to the column gating control circuit, and generate a storage block identification signal based on the received selection signals of the respective storage blocks;

[0013] A separation circuit is connected to the delay control circuit and the identification generation circuit respectively, and is used to generate storage block control signals corresponding to each storage block coupled to the column selection control circuit based on the received total control signal and the storage block identification signal.

[0014] In one embodiment, each of the column enable control circuits is arranged adjacent to each of the coupled storage blocks; the storage blocks coupled to the same column enable control circuit are arranged adjacent to each other in the first direction and / or the second direction, so that the control signal transmission distance between the column enable control circuit and each of the coupled storage blocks is the same, and the first direction and the second direction intersect.

[0015] In one embodiment, the storage blocks coupled to each of the column enable control circuits include a first storage block and a second storage block, and the column enable control circuit is located between the coupled first storage block and the second storage block.

[0016] In one embodiment, the first storage block, the column gating control circuit coupled to the first storage block, and the second storage block coupled to the column gating control circuit are sequentially spaced apart along the first direction.

[0017] In one embodiment, the semiconductor memory includes a plurality of the column enable control circuits, and the first storage blocks and the second storage blocks respectively coupled to the plurality of the column enable control circuits, the plurality of the column enable control circuits are arranged in sequence and spaced apart along the second direction, the plurality of the first storage blocks respectively coupled to the column enable control circuits are arranged in sequence and spaced apart along the second direction, and the plurality of the second storage blocks respectively coupled to the column enable control circuits are arranged in sequence and spaced apart along the second direction.

[0018] In one embodiment, the first direction is a row direction, and the second direction is a column direction.

[0019] In one embodiment, the merging circuit comprises:

[0020] An OR gate, wherein the first input end of the OR gate is used to receive the selection signal of the first storage block, the second input end of the OR gate is used to receive the selection signal of the second storage block, and the output end of the OR gate is used to output the total selection signal.

[0021] In one embodiment, the identification generating circuit includes:

[0022] RS latch, the first input end of the RS latch is used to receive the selection signal of the first storage block, the second input end of the RS latch is used to receive the selection signal of the second storage block, and the positive output end and / or the negative output end of the RS latch is used to output the storage block identification signal.

[0023] In one embodiment, the overall control signal includes a plurality of overall control sub-signals, and the storage block control signal corresponding to each storage block also includes a plurality of storage block control sub-signals; the separation circuit includes a plurality of separation sub-circuits, and the plurality of separation sub-circuits correspond one-to-one to the plurality of overall control sub-signals and the plurality of storage block control sub-signals respectively;

[0024] Each of the separation sub-circuits is connected to the delay control circuit and the identification generation circuit respectively, and is used to generate a corresponding storage block control sub-signal based on the received storage block identification signal and a corresponding general control sub-signal.

[0025] In one embodiment, each of the separation sub-circuits comprises:

[0026] A NOT gate, wherein an input end of the NOT gate receives the storage block identification signal;

[0027] a first AND gate, wherein a first input terminal of the first AND gate is connected to an output terminal of the NOT gate, a second input terminal of the first AND gate is used to receive a corresponding one of the general control sub-signals, and an output terminal of the first AND gate is used to output a storage block control sub-signal corresponding to the first storage block;

[0028] A second AND gate, wherein the first input terminal of the second AND gate is connected to the input terminal of the NOT gate, the second input terminal of the second AND gate is used to receive a corresponding one of the total control sub-signals, and the output terminal of the second AND gate is used to output a storage block control sub-signal corresponding to the second storage block.

[0029] In one embodiment, the separation circuit comprises:

[0030] A third AND gate, wherein a first input terminal of the third AND gate is connected to the inverting output terminal of the RS latch, a second input terminal of the third AND gate is connected to the delay control circuit, and an output terminal of the third AND gate is used to output a control signal of the first storage block;

[0031] A fourth AND gate, wherein a first input terminal of the fourth AND gate is connected to the positive phase output terminal of the RS latch, a second input terminal of the fourth AND gate is connected to the delay control circuit, and an output terminal of the fourth AND gate is used to output a control signal of the second storage block.

[0032] In one embodiment, the storage block includes a storage cell array and an error correction and detection circuit; the multiple general control sub-signals include multiple array general control sub-signals and multiple ECC general control sub-signals, and the multiple storage block control sub-signals include multiple array control sub-signals and multiple ECC control sub-signals; the storage cell array performs read / write data operations based on the array control sub-signals, and the error correction and detection circuit performs error correction and detection operations on the read / write data based on the ECC control sub-signals.

[0033] In one embodiment, the storage block control sub-signal includes an enable signal of a data reading circuit in the storage cell array, an enable signal of a data writing circuit in the storage cell array, and an enable signal of the error correction and detection circuit.

[0034] In a second aspect, an electronic device is provided, the electronic device comprising the semiconductor memory provided in the first aspect.

[0035] In the semiconductor memory and electronic device, since the column gating control circuit is coupled to at least two storage blocks among the plurality of storage blocks, each storage block is coupled to a column gating control circuit, and each storage block coupled to the same column gating control circuit shares a column gating control circuit, compared with each storage block using a different column gating control circuit, the number of column gating control circuits can be reduced, and the occupied area can be saved. Moreover, the column gating control circuit receives the selection signal of each storage block coupled thereto, and generates a corresponding storage block control signal based on the selection signal of each storage block, and the storage block receives the corresponding storage block control signal, and performs a read / write operation in response to the storage block control signal, which has the same effect as each storage block using a different column gating control circuit. It can be seen that the semiconductor memory and electronic device reduce the number of column gating control circuits and save the occupied area on the basis of realizing the separate control of each storage block. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1It is a schematic diagram of the structure of a semiconductor memory in the related art;

[0038] Figure 2 A schematic diagram of the structure of a semiconductor memory according to an embodiment;

[0039] Figure 3 is a structural block diagram of a column selection control circuit according to an embodiment;

[0040] Figure 4 A timing diagram of various signals in a column selection control circuit according to an embodiment;

[0041] Figure 5 is a structural schematic diagram of a merging circuit according to an embodiment;

[0042] Figure 6 Schematic diagram of the structure of an RS latch according to an embodiment;

[0043] Figure 7 is a schematic structural diagram of an RS latch according to another embodiment;

[0044] Figure 8 is a schematic structural diagram of a separation circuit according to an embodiment;

[0045] Fig. 9 is a schematic structural diagram of a separation circuit according to another embodiment;

[0046] Fig.10 FIG. 1 is a schematic diagram of the structure of a column selection control circuit according to an embodiment.

[0047] Description of reference numerals:

[0048] 101, storage block, 102, column gating control circuit;

[0049] 201, storage block, 202, column gating control circuit;

[0050] 10. Merging circuit, 11. OR gate;

[0051] 20. Delay control circuit;

[0052] 30. a logo generating circuit, 31. a first NOR gate, 32. a second NOR gate, 33. a first NAND gate, 34. a second NAND gate;

[0053] 40. Separation circuit, 41. NOT gate, 42. First AND gate, 43. Second AND gate, 44. Third AND gate, 45. Fourth AND gate. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0057] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0059] JEDEC requires LPDDR5 to have 16 memory blocks, twice as many as LPDDR4. Figure 1 Schematic diagram of the structure of a semiconductor memory in the related art, such as Figure 1 As shown, each storage block 101 is independently provided with a column enable control circuit 102 for coupling, and 16 storage blocks 101 are provided with 16 column enable control circuits 102 in total. The 16 column enable control circuits 102 occupy a lot of area.

[0060] Based on the above situation, the present application provides a semiconductor memory and an electronic device, in which a column enable control circuit is coupled to at least two storage blocks among a plurality of storage blocks, and each memory coupled to the same column enable control circuit shares a column enable control circuit, thereby reducing the number of column enable control circuits and saving occupied area.

[0061] Figure 2 FIG. 1 is a schematic diagram of the structure of a semiconductor memory according to an embodiment of the present invention. Figure 2 As shown, the semiconductor storage circuit includes a plurality of storage blocks 201 and at least one column gating control circuit 202. Each column gating control circuit 202 is coupled to at least two storage blocks 201 among the plurality of storage blocks 201, each storage block 201 is coupled to one column gating control circuit 202, and each storage block 201 coupled to the same column gating control circuit 202 shares one column gating control circuit 202. The column gating control circuit 202 is used to receive the selection signal of each storage block 201 coupled thereto, and to generate a corresponding storage block control signal based on the selection signal of each storage block 201. The storage block 201 is used to receive the corresponding storage block control signal, and to perform a read / write operation in response to the storage block control signal.

[0062] The column selection control circuit 202 in the semiconductor memory is coupled to at least two of the multiple memory blocks, each memory block is coupled to a column selection control circuit, and each memory coupled to the same column selection control circuit shares a column selection control circuit. Compared with each memory using a different column selection control circuit, the number of column selection control circuits can be reduced, and the occupied area can be saved. Moreover, the column selection control circuit receives the selection signal of each memory block coupled thereto, and generates a corresponding memory block control signal based on the selection signal of each memory block. The memory block receives the corresponding memory block control signal, and performs a read / write operation in response to the memory block control signal, which is the same as the effect of each memory using a different column selection control circuit. It can be seen that the semiconductor memory reduces the number of column selection control circuits and saves the occupied area on the basis of realizing the separate control of each memory block.

[0063] by Figure 2 For example, the semiconductor storage circuit includes 16 storage blocks 201 and 8 column gating control circuits 202. Each column gating control circuit 202 is coupled to two storage blocks 201, each storage block 201 is coupled to one column gating control circuit 202, and two storage blocks 201 coupled to the same column gating control circuit 202 share one column gating control circuit 202. In this way, 16 storage blocks 201 are provided with a total of 8 column gating control circuits 202, and Figure 1 A total of 16 column enable control circuits 102 are provided in the 16 storage blocks 101, and the number of column enable control circuits is reduced by half, and the occupied area is also reduced by half.

[0064] Alternatively, if Figure 2As shown, each column gating control circuit is arranged adjacent to each coupled storage block. The storage blocks coupled to the same column gating control circuit are arranged adjacent to each other in the first direction and / or the second direction, so that the control signal transmission distance between the column gating control circuit and each coupled storage block is the same, and the first direction and the second direction intersect.

[0065] In the above embodiments, the storage blocks coupled to the same column enable control circuit are arranged adjacent to each other in the first direction and / or the second direction so that the control signal transmission distance between the column enable control circuit and each storage block coupled thereto is the same. This ensures that the multiple storage blocks that share a column enable control circuit have the same path to the column enable control circuit, thereby avoiding different transmission delays of storage block control signals due to different paths, thereby ensuring the stability of signal transmission when sharing the same column enable control circuit.

[0066] Or Figure 2 For example, the two storage blocks 201 coupled to each column strobe control circuit 202 are respectively a first storage block and a second storage block, and the column strobe control circuit 202 is located between the coupled first storage block and the second storage block.

[0067] In the above embodiment, each column enable control circuit is coupled to two storage blocks and is located between the two storage blocks, so as to facilitate the realization of the same control signal transmission distance between the column enable control circuit and the two storage blocks coupled thereto, thereby ensuring the stability of signal transmission when sharing the same column enable control circuit.

[0068] Accordingly, the semiconductor memory includes a plurality of column strobe control circuits 202 , and a first memory block and a second memory block to which the plurality of column strobe control circuits 202 are respectively coupled.

[0069] For example, Figure 2 As shown, the first storage block, the column gating control circuit 202 coupled to the first storage block, and the second storage block coupled to the column gating control circuit 202 are sequentially arranged in intervals along the first direction A. The first direction A may be a row direction.

[0070] The plurality of column strobe control circuits 202 are sequentially spaced apart along the second direction B, the first storage blocks coupled to the plurality of column strobe control circuits 202 are sequentially spaced apart along the second direction B, and the second storage blocks coupled to the plurality of column strobe control circuits 202 are sequentially spaced apart along the second direction B. The second direction B may be a column direction.

[0071] In the above embodiments, a plurality of column enable control circuits, a plurality of first storage blocks, and a plurality of second storage blocks are respectively arranged in sequence along one direction, and each column enable control circuit and its coupled first storage block and second storage block are arranged in sequence along another direction, so as to facilitate the realization of the same control signal transmission distance between the column enable control circuit and the two storage blocks coupled thereto, thereby ensuring the stability of signal transmission when sharing the same column enable control circuit.

[0072] Figure 3 FIG. 1 is a structural block diagram of a column selection control circuit according to an embodiment of the present invention. Figure 3 As shown, in one embodiment, the column gating control circuit 202 includes a merging circuit 10, a delay control circuit 20, an identification generating circuit 30 and a separation circuit 40. The merging circuit 10 is used to receive the selection signals of the respective storage blocks 201 coupled to the column gating control circuit 202, and merge the received selection signals of the respective storage blocks 201 to generate a total selection signal. The delay control circuit 20 is connected to the merging circuit 10, and is used to generate a total control signal based on the received total selection signal. The identification generating circuit 30 is used to receive the selection signals of the respective storage blocks 201 coupled to the column gating control circuit 202, and is used to generate a storage block identification signal based on the received selection signals of the respective storage blocks 201. The separation circuit 40 is connected to the delay control circuit 20 and the identification generating circuit 30, respectively, and is used to generate a storage block control signal corresponding to each storage block 201 coupled to the column gating control circuit 202 based on the received total control signal and the storage block identification signal.

[0073] In the above embodiment, the merging circuit first merges the selection signals of the storage blocks coupled to the column gating control circuit into a total selection signal, and then the delay control circuit generates a total control signal based on the total selection signal, and finally the separation circuit separates the total control signal into storage block control signals corresponding to the storage blocks coupled to the column gating control circuit. Compared with the case where the selection signals of the storage blocks coupled to the column gating control circuit each generate corresponding storage block control signals, the number of delay control circuits is reduced from multiple to one, which can effectively save the occupied area of ​​the entire circuit. In addition, the identification generation circuit receives the selection signals of the storage blocks coupled to the column gating control circuit, and generates a storage block identification signal based on the received selection signals of the storage blocks. In this way, when the separation circuit separates the total control signal into the storage block control signals corresponding to the storage blocks coupled to the column gating control signal, the storage block identification signal can be used for identification, and the storage block control signals corresponding to the storage blocks coupled to the column gating control signal can be accurately determined from the total control signal.

[0074] Or Figure 2 For example, the two storage blocks 201 coupled to each column selection control circuit 202 are respectively a first storage block and a second storage block. Figure 4As shown, the merging circuit 10 merges the selection signal CAC0 of the first storage block and the selection signal CAC1 of the second storage block into a total selection signal CAC01. At the same time, the identification generation circuit 30 generates a storage block identification signal BankFlag based on the selection signal CAC0 of the first storage block and the selection signal CAC1 of the second storage block. The delay control circuit 20 generates a total control signal YsaEn01 based on the total selection signal CAC01, and the separation circuit 40 separates the total control signal YsaEn01 into a storage block control signal YsaEn0 corresponding to the first storage block and a storage block control signal YsaEn1 corresponding to the second storage block according to the storage block identification signal BankFlag.

[0075] Figure 5 FIG. 1 is a schematic diagram of a structure of a merging circuit according to an embodiment of the present invention. Figure 5 As shown, optionally, the merging circuit 10 includes an OR gate 11. The first input end of the OR gate 11 is used to receive the selection signal CAC0 of the first storage block, the second input end of the OR gate 11 is used to receive the selection signal CAC1 of the second storage block, and the output end of the OR gate 11 is used to output the total selection signal CAC01 to the delay control circuit 20, so that the delay control circuit 20 generates the total control signal YsaEn01 based on the total selection signal CAC01.

[0076] In the above embodiment, the merging circuit includes an OR gate, each input end of which can receive selection signals of different storage blocks respectively, and merge the selection signals of at least two storage blocks to generate a total selection signal output.

[0077] In one implementation, the identification generation circuit 30 includes an RS latch. The first input terminal of the RS latch is used to receive the selection signal CAC0 of the first storage block, the second input terminal of the RS latch is used to receive the selection signal CAC1 of the second storage block, and the positive phase output terminal and / or the negative phase output terminal of the RS latch is used to output the storage block identification signal BankFlag.

[0078] For example, Figure 6 As shown, the RS latch includes a first NOR gate 31 and a second NOR gate 32. The first input end of the first NOR gate 31 is used to receive the selection signal CAC0 of the first storage block, the second input end of the first NOR gate 31 is connected to the output end of the second NOR gate 32, and the output end of the first NOR gate 31 is the positive output end of the RS latch. The first input end of the second NOR gate 32 is connected to the output end of the first NOR gate 31, the second input end of the second NOR gate 32 is used to receive the selection signal CAC1 of the second storage block, and the output end of the second NOR gate 32 is the negative output end of the RS latch.

[0079] like Figure 7As shown, the RS latch includes a first NAND gate 33 and a second NAND gate 34. The first input end of the first NAND gate 33 is used to receive the selection signal CAC0 of the first storage block, the second input end of the first NAND gate 33 is connected to the output end of the second NAND gate 34, and the output end of the first NAND gate 33 is the positive phase output end of the RS latch. The first input end of the second NAND gate 34 is connected to the output end of the first NAND gate 33, the second input end of the second NAND gate 34 is used to receive the selection signal CAC1 of the second storage block, and the output end of the second NAND gate 34 is the negative phase output end of the RS latch.

[0080] In another implementation, the identification generation circuit 30 includes an encoder. Multiple input terminals of the encoder are used to receive selection signals of different storage blocks respectively, such as the first input terminal of the encoder is used to receive the selection signal CAC0 of the first storage block, and the second input terminal of the encoder is used to receive the selection signal CAC1 of the second storage block. The output terminal of the encoder is used to output the storage block identification signal BankFlag <n:0>, n+1 is the number of storage blocks. For example, when each column selection control circuit 202 is coupled to two storage blocks 201, the output end of the encoder outputs the storage block identification signal BankFlag<1:0>.

[0081] Optionally, the total control signal includes multiple total control sub-signals, and the storage block control signal corresponding to each storage block 202 also includes multiple storage block control sub-signals. The separation circuit 40 includes multiple separation sub-circuits, and the multiple separation sub-circuits correspond to the multiple total control sub-signals and the multiple storage block control sub-signals one by one. Each separation sub-circuit is connected to the delay control circuit 20 and the identification generation circuit 30 respectively, and is used to generate a corresponding storage block control sub-signal based on the received storage block identification signal and a corresponding total control sub-signal.

[0082] In one implementation, Figure 8 As shown, each separation sub-circuit includes a NOT gate 41, a first AND gate 42, and a second AND gate 43. The input end of the NOT gate 41 receives the storage block identification signal BankFlag. The first input end of the first AND gate 42 is connected to the output end of the NOT gate 41, the second input end of the first AND gate 42 is used to receive a corresponding total control sub-signal, and the output end of the first AND gate 42 is used to output a storage block control sub-signal corresponding to the first storage block. The first input end of the second AND gate 43 is connected to the input end of the NOT gate 41, the second input end of the second AND gate 43 is used to receive a corresponding total control sub-signal, and the output end of the second AND gate 43 is used to output a storage block control sub-signal corresponding to the second storage block.

[0083] by Figure 4 For example, the identification generation circuit 30 generates a storage block identification signal BankFlag based on the selection signal CAC0 of the first storage block and the selection signal CAC1 of the second storage block. The input end of the NOT gate 41 receives the storage block identification signal BankFlag and outputs it to the first input end of the first AND gate 42, the second input end of the first AND gate 42 receives the total selection signal CAC01, and the output end of the first AND gate 42 outputs the storage block control signal YsaEn0 corresponding to the first storage block. The first input end of the second AND gate 43 receives the storage block identification signal BankFlag, the second input end of the second AND gate 43 receives the total selection signal CAC01, and the output end of the second AND gate 43 outputs the storage block control signal YsaEn1 corresponding to the second storage block.

[0084] In another implementation, Fig. 9 As shown, the separation circuit 40 includes a third AND gate 44 and a fourth AND gate 45. The first input end of the third AND gate 44 is connected to the inverting output end of the RS latch, the second input end of the third AND gate 44 is connected to the delay control circuit 20, and the output end of the third AND gate 44 is used to output the control signal of the first storage block. The first input end of the fourth AND gate 45 is connected to the positive phase output end of the RS latch, the second input end of the fourth AND gate 44 is connected to the delay control circuit 20, and the output end of the fourth AND gate 44 is used to output the control signal of the second storage block.

[0085] In one embodiment, Fig.10 As shown, the column strobe control circuit 202 includes a merging circuit 10 , a delay control circuit 20 , a flag generating circuit 30 and a separating circuit 40 .

[0086] The merging circuit 10 includes an OR gate 11. The first input end of the OR gate 11 is used to receive the selection signal CAC0 of the first storage block, the second input end of the OR gate 11 is used to receive the selection signal CAC1 of the second storage block, and the output end of the OR gate 11 is used to output the total selection signal CAC01 to the delay control circuit 20, so that the delay control circuit 20 generates the total control signal YsaEn01 based on the total selection signal CAC01.

[0087] The identification generation circuit 30 includes an RS latch. The first input terminal of the RS latch is used to receive the selection signal CAC0 of the first storage block, the second input terminal of the RS latch is used to receive the selection signal CAC1 of the second storage block, and the positive output terminal and / or the negative output terminal of the RS latch is used to output the storage block identification signal BankFlag.

[0088] The separation circuit 40 includes a NOT gate 41, a first AND gate 42, and a second AND gate 43. The input end of the NOT gate 41 receives the storage block identification signal BankFlag. The first input end of the first AND gate 42 is connected to the output end of the NOT gate 41, the second input end of the first AND gate 42 is used to receive the total control signal YsaEn01, and the output end of the first AND gate 42 is used to output the storage block control signal YsaEn0 corresponding to the first storage block. The first input end of the second AND gate 43 is connected to the input end of the NOT gate 41, the second input end of the second AND gate 43 is used to receive the total control signal YsaEn01, and the output end of the second AND gate 43 is used to output the storage block control signal YsaEn1 corresponding to the second storage block.

[0089] In practical applications, the delay control circuit 20 is usually implemented using an analog circuit, which occupies a very large area. In the present application, two storage blocks (i.e., the first storage block and the second storage block) share a delay control circuit 20, and corresponding storage block control signals can also be generated based on their corresponding selection signals, which can also effectively reduce the area occupied by the analog circuit.

[0090] In one embodiment, a storage block includes a storage cell array and an error checking and correcting (ECC) circuit. A plurality of general control sub-signals include a plurality of array general control sub-signals and a plurality of ECC general control sub-signals, the array general control sub-signals are used to control the storage cell array, and the ECC general control sub-signals are used to control the ECC circuit. A plurality of storage block control sub-signals include a plurality of array control sub-signals and a plurality of ECC control sub-signals. The storage cell array performs a read / write data operation based on the array control sub-signals, and the error checking and correcting circuit performs an error checking and correcting operation on the read / write data based on the ECC control sub-signals.

[0091] Optionally, the storage block control sub-signal includes an enable signal of a data read circuit (such as a read amplifier) ​​in the storage cell array, an enable signal of a data write circuit (such as a write driver) in the storage cell array, and an enable signal of an error correction and detection circuit.

[0092] Exemplarily, the read / write operation includes controlling an amplifier in a data read circuit to process read data, or controlling a driver in a data write circuit to drive data to be written.

[0093] Based on the same inventive concept, the present application also provides an electronic device, which includes the semiconductor memory provided by any of the above embodiments.

[0094] The electronic device includes a semiconductor memory, wherein a column gating control circuit in the semiconductor memory is coupled to at least two memory blocks among a plurality of memory blocks, each memory block is coupled to a column gating control circuit, and each memory coupled to the same column gating control circuit shares a column gating control circuit. Compared with each memory using a different column gating control circuit, the number of column gating control circuits can be reduced, and the occupied area can be saved. Moreover, the column gating control circuit receives the selection signal of each memory block coupled thereto, and generates a corresponding memory block control signal based on the selection signal of each memory block. The memory block receives the corresponding memory block control signal, and performs a read / write operation in response to the memory block control signal, which has the same effect as each memory using a different column gating control circuit. It can be seen that the electronic device reduces the number of column gating control circuits and saves the occupied area on the basis of realizing the separate control of each memory block.

[0095] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0096] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor memory, characterized in that: The semiconductor memory comprises: Multiple storage blocks; At least one column gating control circuit, each of the column gating control circuits is coupled to at least two of the plurality of storage blocks, each of the storage blocks is coupled to one column gating control circuit, and each of the storage blocks coupled to the same column gating control circuit shares one column gating control circuit; The column gating control circuit is used to receive the selection signal of each of the storage blocks coupled thereto, and generate a corresponding storage block control signal based on the selection signal of each of the storage blocks; The storage block is used to receive the corresponding storage block control signal and perform a read / write operation in response to the storage block control signal.

2. The semiconductor memory according to claim 1, wherein: The column gating control circuit comprises: A merging circuit, used for receiving the selection signals of the respective storage blocks coupled to the column gating control circuit, and merging the received selection signals of the respective storage blocks to generate a total selection signal; a delay control circuit connected to the merging circuit and configured to generate a total control signal based on the received total selection signal; an identification generating circuit, configured to receive selection signals of the respective storage blocks coupled to the column gating control circuit, and generate a storage block identification signal based on the received selection signals of the respective storage blocks; A separation circuit is connected to the delay control circuit and the identification generation circuit respectively, and is used to generate storage block control signals corresponding to each storage block coupled to the column selection control circuit based on the received total control signal and the storage block identification signal.

3. The semiconductor memory according to claim 2, wherein: Each of the column enable control circuits is arranged adjacent to each of the coupled storage blocks; the storage blocks coupled to the same column enable control circuit are arranged adjacent to each other in the first direction and / or the second direction, so that the control signal transmission distance between the column enable control circuit and each of the coupled storage blocks is the same, and the first direction and the second direction intersect.

4. The semiconductor memory according to claim 3, wherein: The storage blocks coupled to each of the column strobe control circuits include a first storage block and a second storage block, and the column strobe control circuit is located between the coupled first storage block and the second storage block.

5. The semiconductor memory according to claim 4, characterized in that The first storage block, the column strobe control circuit coupled to the first storage block, and the second storage block coupled to the column strobe control circuit are sequentially arranged in an interval along the first direction.

6. The semiconductor memory according to claim 5, wherein: The semiconductor memory includes a plurality of column enable control circuits, and the first storage blocks and the second storage blocks respectively coupled to the plurality of column enable control circuits. The plurality of column enable control circuits are arranged in sequence and spaced apart along the second direction. The plurality of first storage blocks respectively coupled to the plurality of column enable control circuits are arranged in sequence and spaced apart along the second direction. The plurality of second storage blocks respectively coupled to the plurality of column enable control circuits are arranged in sequence and spaced apart along the second direction.

7. The semiconductor memory according to claim 6, wherein: The first direction is a row direction, and the second direction is a column direction.

8. The semiconductor memory according to any one of claims 4 to 7, characterized in that: The merging circuit comprises: An OR gate, wherein the first input end of the OR gate is used to receive the selection signal of the first storage block, the second input end of the OR gate is used to receive the selection signal of the second storage block, and the output end of the OR gate is used to output the total selection signal.

9. The semiconductor memory according to any one of claims 4 to 7, characterized in that: The identification generating circuit comprises: RS latch, the first input end of the RS latch is used to receive the selection signal of the first storage block, the second input end of the RS latch is used to receive the selection signal of the second storage block, and the positive output end and / or the negative output end of the RS latch is used to output the storage block identification signal.

10. The semiconductor memory according to claim 9, wherein: The overall control signal includes a plurality of overall control sub-signals, and the storage block control signal corresponding to each storage block also includes a plurality of storage block control sub-signals; the separation circuit includes a plurality of separation sub-circuits, and the plurality of separation sub-circuits correspond one-to-one to the plurality of overall control sub-signals and the plurality of storage block control sub-signals respectively; Each of the separation sub-circuits is connected to the delay control circuit and the identification generation circuit respectively, and is used to generate a corresponding storage block control sub-signal based on the received storage block identification signal and a corresponding general control sub-signal.

11. The semiconductor memory according to claim 10, wherein: Each of the separation sub-circuits comprises: A NOT gate, wherein an input end of the NOT gate receives the storage block identification signal; a first AND gate, wherein a first input terminal of the first AND gate is connected to an output terminal of the NOT gate, a second input terminal of the first AND gate is used to receive a corresponding one of the general control sub-signals, and an output terminal of the first AND gate is used to output a storage block control sub-signal corresponding to the first storage block; A second AND gate, wherein the first input terminal of the second AND gate is connected to the input terminal of the NOT gate, the second input terminal of the second AND gate is used to receive a corresponding one of the total control sub-signals, and the output terminal of the second AND gate is used to output a storage block control sub-signal corresponding to the second storage block.

12. The semiconductor memory according to claim 10, wherein: The separation circuit comprises: A third AND gate, wherein a first input terminal of the third AND gate is connected to the inverting output terminal of the RS latch, a second input terminal of the third AND gate is connected to the delay control circuit, and an output terminal of the third AND gate is used to output a control signal of the first storage block; A fourth AND gate, wherein a first input terminal of the fourth AND gate is connected to the positive phase output terminal of the RS latch, a second input terminal of the fourth AND gate is connected to the delay control circuit, and an output terminal of the fourth AND gate is used to output a control signal of the second storage block.

13. The semiconductor memory according to claim 10, wherein: The storage block includes a storage cell array and an error correction and detection circuit; the plurality of the general control sub-signals include a plurality of array general control sub-signals and a plurality of ECC general control sub-signals, and the plurality of the storage block control sub-signals include a plurality of array control sub-signals and a plurality of ECC control sub-signals; The memory cell array performs a read / write data operation based on the array control sub-signal, and the error correction and detection circuit performs an error correction and detection operation on the read / write data based on the ECC control sub-signal.

14. The semiconductor memory according to claim 13, wherein: The storage block control sub-signals include an enable signal of a data reading circuit in the storage cell array, an enable signal of a data writing circuit in the storage cell array, and an enable signal of the error correction and detection circuit.

15. An electronic device, characterized in that: The electronic device comprises the semiconductor memory as claimed in any one of claims 1 to 14.

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