Training program for receiver associated with memory device

Abstract

The invention relates to a training program for a receiver associated with a memory device. The training program may be configured to compensate for variations that may occur in different symbols of the signal. For example, an individual training operation may be performed on each reference voltage within a first unit interval. These individual training operations may allow a reference voltage for the first unit interval to be positioned independently of other reference voltages within the same unit interval or a different unit interval. In another example, an individual training operation may be performed on a sampling time associated with a reference voltage. These individual training operations may allow a sampling time associated with a reference voltage within the first unit interval to be positioned independently of other sampling times within the same unit interval or a different unit interval.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application of the invention patent application with the application date of August 13, 2019, application number 201980053467.3, and invention name "Training procedure for a receiver associated with a memory device".

[0003] Cross-references

[0004] This patent application claims priority to PCT Application No. PCT / US2019 / 046398, filed on August 13, 2019, entitled “TRAINING PROCEDURE FOR RECEIVERS ASSOCIATEDWITH A MEMORY DEVICE” by Mayer et al., which claims priority to U.S. Patent Application No. 16 / 538,329, filed on August 12, 2019, entitled “TRAINING PROCEDURE FOR RECEIVERS ASSOCIATEDWITH A MEMORY DEVICE” by Mayer et al., and U.S. Provisional Patent Application No. 62 / 720,817, filed on August 21, 2018, entitled “TRAINING PROCEDURE FOR RECEIVERS ASSOCIATEDWITH A MEMORY DEVICE” by Mayer et al., each of which is assigned to the assignee of this application, and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to a system including at least one memory device, and more particularly to a training procedure for a receiver associated with the memory device. Background Art

[0006] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device can store one of two states, which are usually represented by a logical 1 or a logical 0. In other devices, more than two states can be stored. To access the stored information, the components of the device can read or sense at least one stored state in the memory device. To store information, the components of the device can write or program the state in the memory device.

[0007] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods of time even in the absence of external power. Volatile memory devices (e.g., DRAM) may lose their stored state over time unless they are periodically refreshed by an external power source.

[0008] The memory device may contain various channels for communicating information with other devices within the system (eg, a controller). A training procedure may be used to configure the receiver to ensure that data is communicated effectively and efficiently between the memory device and other components. Summary of the invention

[0009] A device is described. The device may include: a pin configured to be coupled to a data bus; and a receiver coupled to the pin and configured to receive a plurality of symbols within a series of unit intervals, the receiver including a comparator stage and a sampler stage. In some instances of the device, the comparator stage may include: a first comparator coupled to the pin and a first reference voltage, the first comparator configured to use the first reference voltage to distinguish between a first symbol candidate and a second symbol candidate during a first unit interval in the series; and a second comparator coupled to the pin and a second reference voltage different from the first reference voltage, the second comparator configured to use the second reference voltage to distinguish between the first symbol candidate and the second symbol candidate during a second unit interval in the series. In some instances of the device, the sampler stage may include: a first latch coupled to the first comparator and configured to sample an output of the first comparator during the first unit interval; and a second latch coupled to the second comparator and configured to sample an output of the second comparator during the second unit interval.

[0010] A method is described. The method may include: receiving a set of symbols during a series of unit intervals, each unit interval in the series containing a symbol in the set of symbols; identifying a baseline level offset associated with a first reference voltage to distinguish a first symbol candidate from a second symbol candidate in the set of symbols; after identifying the baseline level offset, identifying a first level offset for the first reference voltage within a first unit interval in the series and a second level offset for the first reference voltage within a second unit interval in the series, the first level offset being different from the second level offset; and configuring the first reference voltage within the first unit interval with the first level offset and configuring the first reference voltage within the second unit interval with the second level offset.

[0011] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to perform the following operations: receive a set of symbols during a series of unit intervals, each unit interval in the series including one symbol in the set of symbols; identify a baseline level shift associated with a first reference voltage to distinguish between a first symbol candidate and a second symbol candidate in the set of symbols; after identifying the baseline level shift, identify a first level shift for the first reference voltage within a first unit interval in the series and identify a second level shift for the first reference voltage within a second unit interval in the series, the first level shift being different from the second level shift; and configure the first reference voltage within the first unit interval with the first level shift and configure the first reference voltage within the second unit interval with the second level shift.

[0012] Another apparatus is described. The apparatus may include: means for receiving a set of symbols during a series of unit intervals, each unit interval in the series containing a symbol in the set of symbols; means for identifying a baseline level shift associated with a first reference voltage to distinguish between a first symbol candidate and a second symbol candidate in the set of symbols; means for identifying a first level shift for the first reference voltage within a first unit interval in the series and a second level shift for the first reference voltage within a second unit interval in the series after identifying the baseline level shift, the first level shift being different from the second level shift; and means for configuring the first reference voltage within the first unit interval with the first level shift and configuring the first reference voltage within the second unit interval with the second level shift.

[0013] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: receive a set of symbols during a series of unit intervals, each unit interval in the series including a symbol in the set of symbols; identify a baseline level offset associated with a first reference voltage to distinguish between a first symbol candidate and a second symbol candidate in the set of symbols; after identifying the baseline level offset, identify a first level offset for the first reference voltage within a first unit interval in the series and identify a second level offset for the first reference voltage within a second unit interval in the series, the first level offset being different from the second level offset; and configure the first reference voltage within the first unit interval with the first level offset and configure the first reference voltage within the second unit interval with the second level offset.

[0014] A method is described. The method may include: receiving a set of symbols within a series of unit intervals, each unit interval in the series containing one symbol from the set of symbols; identifying a baseline timing offset associated with a sampling time for latching during the series of unit intervals; after identifying the baseline timing offset, identifying a first timing offset for a first sampling time within a first unit interval in the series and identifying a second timing offset for a second sampling time within a second unit interval in the series, the first timing offset being different from the second timing offset; and configuring the first sampling time with the first timing offset and configuring the second sampling time with the second timing offset.

[0015] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to perform the following operations: receive a set of symbols within a series of unit intervals, each unit interval in the series including one symbol from the set of symbols; identify a baseline timing offset associated with a sampling time for latching during the series of unit intervals; after identifying the baseline timing offset, identify a first timing offset for a first sampling time within a first unit interval in the series and identify a second timing offset for a second sampling time within a second unit interval in the series, the first timing offset being different from the second timing offset; and configure the first sampling time with the first timing offset and configure the second sampling time with the second timing offset.

[0016] Another apparatus is described. The apparatus may include: means for receiving a set of symbols within a series of unit intervals, each unit interval in the series containing one symbol from the set of symbols; means for identifying a baseline timing offset associated with a sampling time for latching during the series of unit intervals; means for identifying a first timing offset for a first sampling time within a first unit interval in the series and a second timing offset for a second sampling time within a second unit interval in the series after identifying the baseline timing offset, the first timing offset being different from the second timing offset; and means for configuring the first sampling time with the first timing offset and configuring the second sampling time with the second timing offset.

[0017] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to: receive a set of symbols within a series of unit intervals, each unit interval in the series containing one symbol from the set of symbols; identify a baseline timing offset associated with a sampling time for latching during the series of unit intervals; after identifying the baseline timing offset, identify a first timing offset for a first sampling time within a first unit interval in the series and identify a second timing offset for a second sampling time within a second unit interval in the series, the first timing offset being different from the second timing offset; and configure the first sampling time with the first timing offset and configure the second sampling time with the second timing offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 An example of a system supporting a training procedure for a receiver associated with a memory device in accordance with aspects of the present disclosure is presented.

[0019] Figure 2 An example of a memory die supporting a training procedure for a receiver associated with a memory device in accordance with aspects of the present disclosure is shown.

[0020] Figure 3 Examples of eye diagrams supporting a training procedure for a receiver associated with a memory device are shown in accordance with aspects of the present disclosure.

[0021] Figure 4 An example of a flow chart supporting a training procedure for a receiver associated with a memory device in accordance with aspects of the present disclosure is presented.

[0022] Figure 5A and 5B Examples of eye diagrams supporting a training procedure for a receiver associated with a memory device are shown in accordance with aspects of the present disclosure.

[0023] Fig. 6A and 6B Examples of eye diagrams supporting a training procedure for a receiver associated with a memory device are shown in accordance with aspects of the present disclosure.

[0024] Figure 7 An example of a circuit diagram supporting a training procedure for a receiver associated with a memory device in accordance with aspects of the present disclosure is shown.

[0025] Figure 8 A block diagram of a device supporting a training procedure for a receiver associated with a memory device is shown in accordance with aspects of the present disclosure.

[0026] Figures 9 to 12 A flow chart is shown demonstrating one or more methods of supporting a training procedure for a receiver associated with a memory device in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0027] For some memory systems, a training procedure can be used to tune a receiver that transmits data between a host device and a memory device. Tuning a receiver can reduce errors that may occur during transmission. Examples of receiver parameters that can be tuned can include reference voltages and sampling times. Due to different conversion rates, crosstalk, duty cycles, and / or pulse train position mismatches, signals received across different unit intervals and / or different symbols or levels may be different. Individual training operations to tune the receiver can be used to account for these differences.

[0028] Techniques for performing a training procedure (e.g., performed on reference voltages and / or sampling times associated with individual symbols transmitted across conductive lines) are described herein. The training procedure may include a baseline training operation, one or more individual training operations, or both. The training procedure may be configured to compensate for variations in the signal that may occur at different symbols, different unit intervals, or both. For example, an individual training operation may be performed for each reference voltage within a first unit interval. These individual training operations may allow a low level reference voltage of a first unit interval to be positionable independently of a low level reference voltage of a second unit interval, independently of a high level reference voltage of the first unit interval, or both.

[0029] In another example, individual training operations can be performed on sampling times associated with reference voltages. These individual training operations can allow sampling times associated with a low-level reference voltage within a first unit interval to be positionable independently of sampling times associated with a high-level reference voltage within the first unit interval, the high-level reference voltage within the first unit interval, or both. Additionally, these individual training operations can allow sampling times within the first unit interval to be positionable independently of one or more sampling times within other unit intervals.

[0030] In this article Figure 1 and 2 Features of the present disclosure are described in the context of a memory system in. Figures 3 to 7 Features of the present disclosure are described in the context of eye diagrams, flow charts, and circuit diagrams. Figures 8 to 12 These and other features of the present disclosure are further shown and described including apparatus diagrams and flow diagrams relating to a training procedure for a receiver associated with a memory device.

[0031] Figure 1 An example of a system 100 utilizing one or more memory devices according to various aspects disclosed herein is shown. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 to the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0032] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet connection device, etc. Memory device 110 may be a component of the system that is configured to store data for one or more other components of system 100. In some instances, system 100 may be configured to perform two-way wireless communications with other systems or devices using a base station or access point. In some instances, system 100 may be capable of machine type communication (MTC), machine to machine (M2M) communication, or device to device (D2D) communication.

[0033] At least a portion of the system 100 may be an instance of a host device. Such a host device may be an instance of a device that uses memory to perform processing, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet connection device, some other fixed or portable electronic device, etc. In some cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as a host or a host device. In some instances, the system 100 is a graphics card. The host device may include multiple drivers, and the multiple drivers couple the channels that connect the host device to the memory device. A training program may be used to tune one or more receivers to ensure that information is effectively and efficiently transmitted between components.

[0034] In some cases, the memory device 110 may be a stand-alone device or component that is configured to communicate with other components of the system 100 and provide physical memory addresses / spaces for potential use or reference by the system 100. In some instances, the memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between components of the system 100 and the memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packaging of the system 100 and the memory device 110, clock signaling and synchronization between the system 100 and the memory device 110, timing conventions, and / or other factors.

[0035] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., in response to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0036] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be coupled or in electronic communication with each other using a bus 140.

[0037] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In such cases, the processor 120 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other instances.

[0038] BIOS component 125 may be a software component including BIOS operating as firmware that may initialize and run various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0039] The one or more peripheral components 130 may be any input device or output device or interface for such a device that may be integrated into or with the system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot. The one or more peripheral components 130 may be other components as would be understood by one of ordinary skill in the art to be peripheral devices.

[0040] I / O controller 135 may manage data transfers between processor 120 and one or more peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0041] Input 145 may represent a device or signal external to system 100 that may provide information, signals, or data to system 100 or its components. This may include a user interface or an interface with other devices or interfaces between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 through one or more peripheral components 130 or may be managed by I / O controller 135.

[0042] Output 150 may represent a device or signal external to system 100 that is configured to receive an output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 through one or more peripheral components 130 or that may be managed by I / O controller 135.

[0043] The components of system 100 may be composed of general or special purpose circuitry designed to perform its functions. This may include various circuit elements, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to perform the functions described herein.

[0044] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0045] The memory device 110 may be an example of a two-dimensional (2D) array of memory cells, or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as stacks, levels, layers, or dies. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). Compared to a single 2D memory device, this may increase the number of memory cells that may be positioned on a substrate, which in turn may reduce production costs or improve the performance of the memory array, or both. In some 3D memory devices, different stacks may share at least one common access line, such that some stacks may share at least one of a word line, a digit line, and / or a plate line.

[0046] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. As such, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may be configured to communicate with the external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 will store certain data on behalf of a component of the system 100 (e.g., the processor 120), or a read command indicating that the memory device 110 will provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, etc. The device memory controller 155 and / or one or more local memory controllers 165 may be used to execute a training procedure to tune a receiver coupled to the channel 115. The controllers 155, 165 may implement a training procedure including a baseline training operation and an individual training operation as described herein.

[0047] The local memory controller 165 (e.g., local to the memory die 160) can be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 can be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 can support the device memory controller 155 to control the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 can perform the various functions described herein. Thus, the local memory controller 165 can be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0048] The external memory controller 105 may be configured to enable the transfer of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the details of the operation of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) that the external memory controller 105 satisfies to the external memory controller 105. The external memory controller 105 may convert or translate the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal. In some instances, the external memory controller 105 may be used to perform a training program to tune a receiver coupled to the channel 115. The external memory controller 105 may implement a training program that includes a baseline training operation and an individual training operation as described herein.

[0049] In some cases, the external memory controller 105 or other components of the system 100 or its functions described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functions described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110 such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120).

[0050] Components of system 100 can exchange information with memory device 110 using multiple channels 115. In some examples, channels 115 can enable communication between external memory controller 105 and memory device 110. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 can include a first terminal, which includes one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. Pins can be examples of conductive input or output points of devices of system 100, and pins can be configured to act as part of a channel. In some cases, the pins or pads of a terminal can be part of a signal path to channel 115. Additional signal paths can be coupled to the terminals of the channel for routing signals within the components of system 100. For example, the memory device 110 may include a signal path (e.g., a signal path internal to the memory device 110 or a component thereof, such as a signal path internal to the memory die 160) that routes signals from terminals of the channel 115 to various components of the memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170). Drivers, receivers, or both may be used to transmit signals across the channel 115. In some cases, a reference voltage and / or sampling time of the receiver may be tuned to improve communication across the conductive lines. A training procedure including a baseline training operation and an individual training operation may be implemented to tune the receiver.

[0051] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying a particular type of information. In some cases, channel 115 may be an aggregate channel and may therefore include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc.

[0052] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channel 186 may be configured to transmit commands between external memory controller 105 and memory device 110, the commands including control information (e.g., address information) associated with the commands. For example, CA channel 186 may include a read command with an address of desired data. In some cases, CA channel 186 may be registered on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channel 186 may include eight or nine signal paths.

[0053] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channel 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to adjust (e.g., oscillate) between a high state and a low state and coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal path of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. In some cases, the clock signal may be a 1.5 GHz signal. CK channel 188 may include any number of signal paths. In some cases, clock signal CK (e.g., CK_t signal and CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. Therefore, clock signal CK may be referred to variously as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0054] In some cases, channels 115 may include one or more data (e.g., DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer information to be written to memory device 110 (e.g., bidirectional) or information to be read from memory device 110. Data channels 190 may transfer signals that may be modulated using a variety of different modulation schemes (e.g., NRZ, PAM4).

[0055] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0056] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference (e.g., a timing reference for read and write operations) for general access operations of the memory device 110. Therefore, the write clock signal WCK may also be referred to as a data clock signal WCK. The WCK channel may be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., an oscillator, a crystal, a logic gate, a transistor, etc.).

[0057] In some cases, other channels 192 may include one or more error detection code (EDC) channels. An EDC channel may be configured to transmit error detection signals (eg, checksums) to improve system reliability. An EDC channel may include any number of signal paths.

[0058] The channel 115 can use a variety of different architectures to couple the external memory controller 105 to the memory device 110. Examples of various architectures can include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path can at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0059] The signals transmitted over the channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals transmitted between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0060] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals transmitted between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels for encoding more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0061] Figure 2 An example of a memory die 200 according to various examples of the present disclosure is shown. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 is programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

[0062] The memory cell 205 may store a charge representing a programmable state in a capacitor. In a DRAM architecture, the memory cell 205 may include a capacitor including a dielectric material for storing a charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, a nonlinear dielectric material may be used.

[0063] Operations such as reading or writing can be performed on memory cell 205 by activating or selecting access lines such as word lines 210 and / or digit lines 215. In some cases, digit lines 215 may also be referred to as bit lines. References to access lines, word lines, and digit lines, or the like, are interchangeable without loss of understanding or operation. Activating or selecting word lines 210 or digit lines 215 may include applying a voltage to the corresponding line.

[0064] The memory die 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210 and the digit lines 215. By biasing the word lines 210 and the digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at the intersection of the word lines and the digit lines.

[0065] Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word lines 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and may activate the digit lines 215 based on the received column address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, for example, WL_1 and DL_3, the memory cells 205 at their intersections may be accessed. In a two-dimensional or three-dimensional configuration, the intersection of a word line 210 and a digit line 215 may be referred to as the address of the memory cell 205.

[0066] Memory cell 205 may include a logic storage component, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage supply 240. In some cases, voltage supply 240 is ground, such as Vss. In some cases, voltage supply 240 may be an example of a plate line coupled to a plate line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes (e.g., stops) electronic communication between two components.

[0067] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the switching component 235. The capacitor 230 can be in electronic communication with the digit line 215 using the switching component 235. For example, when the switching component 235 is deactivated, the capacitor 230 can be isolated from the digit line 215, and when the switching component 235 is activated, the capacitor 230 can be coupled to the digit line 215. In some cases, the switching component 235 can be or include a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, the switching component 235 can be or include a p-type transistor or an n-type transistor. The word line 210 can be in electronic communication with the gate of the switching component 235 and can activate / deactivate the switching component 235 based on applying a voltage to the word line 210.

[0068] The word line 210 may be a conductive line in electronic communication with the memory cell 205 that may be used to perform access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching component 235 of the memory cell 205 and may be configured to control the switching component 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching component.

[0069] The digit line 215 can be a conductive line that connects the memory cell 205 to the sensing component 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 and the digit line 215 of the memory cell 205. In some architectures, the memory cell 205 can be in (e.g., constant) electronic communication with the digit line 215.

[0070] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205, and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be small. As such, the sensing component 245 may include one or more sense amplifiers for amplifying the signal output by the memory cell 205. The sense amplifier may detect a small change in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., release charge) to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change. The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the stored state of the memory cell 205 based on the comparison. For example, in binary signaling, if the voltage of digit line 215 is higher than the voltage of reference signal 250, then readout component 245 can determine that the stored state of memory cell 205 is a logic 1, and if the voltage of digit line 215 is lower than the voltage of reference signal 250, then readout component 245 can determine that the stored state of memory cell 205 is a logic 0. Readout component 245 can include various transistors or amplifiers for detecting and amplifying differences in signals. The detected logic state of memory cell 205 can be output by column decoder 225 in the form of output 255. In some cases, readout component 245 can be part of another component (e.g., column decoder 225, row decoder 220). In some cases, readout component 245 can be in electronic communication with row decoder 220 or column decoder 225.

[0071] The local memory controller 260 may control the operation of the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, and the readout component 245). The local memory controller 260 may be a reference Figure 1 1. In some cases, one or more of the row decoder 220, column decoder 225, and readout component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to receive data from the external memory controller 105 (or reference 106). Figure 1The device memory controller 155 described herein receives commands and / or data, translates the commands and / or data into information that can be used by the memory die 200, performs one or more operations on the memory die 200, and transmits data from the memory die 200 to the external memory controller 105 (or device memory controller 155) in response to performing the one or more operations. The local memory controller 260 can generate row address signals and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein can be adjusted or changed and can be different for the various operations discussed in operating the memory die 200. The local memory controller 260 can be used to perform a training procedure to tune a receiver coupled to a channel that operates between multiple devices (such as a host device and a memory device). Local memory controller 260 may implement a training program including baseline training operations and individual training operations as described herein.

[0072] In some cases, the local memory controller 260 can be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. In some cases, multiple memory cells 205 can be programmed during a single write operation. The local memory controller 260 can identify a target memory cell 205 to which the write operation is to be performed. The local memory controller 260 can identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 may apply a first signal (e.g., a voltage) to the digit line 215 during a write operation to store a first state (e.g., a charge) in the capacitor 230 of the memory cell 205, and the first state (e.g., a charge) may indicate a desired logic state. To receive write commands, the receiver of the memory device may be tuned using a baseline training procedure and / or an individual training procedure as described herein.

[0073] In some cases, the local memory controller 260 can be configured to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cell 205 of the memory die 200 can be determined. In some cases, multiple memory cells 205 can be sensed during a single read operation. The local memory controller 260 can identify the target memory cell 205 on which the read operation is performed. The local memory controller 260 can identify the target word line 210 and the target digit line 215 in electronic communication with the target memory cell 205 (the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sense component 245 in response to the biased access line. The sense component 245 can amplify the signal. The local memory controller 260 may activate the sensing component 245 (e.g., latching sensing component) and thereby compare the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. The local memory controller 260 may transmit the logic state stored on the memory cell 205 to the external memory controller 105 (or device memory controller 155) as part of the read operation. To receive the output of the memory die 200, the receiver of the host device may be tuned using a baseline training procedure and / or an individual training procedure as described herein.

[0074] In some memory architectures, accessing the memory cell 205 can degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture can partially or completely discharge the capacitor of the target memory cell. The local memory controller 260 can perform a rewrite operation or a refresh operation to return the memory cell to its original logic state. The local memory controller 260 can rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation can be considered as part of the read operation. Additionally, activating a single access line such as word line 210 can disturb the state stored in some memory cells that are in electronic communication with the access line. Therefore, a rewrite operation or a refresh operation can be performed on one or more memory cells that may not have been accessed.

[0075] Figure 3 An example of an eye diagram 300 supporting a training procedure for a receiver associated with a memory device according to aspects of the present disclosure is shown. In some examples, the eye diagram 300 may show reference Figure 1 and 2 Implementations of aspects of system 100 or memory die 200 are described.

[0076] Eye diagram 300 illustrates the characteristics of eye diagrams and how individualized training procedures can improve readout techniques in memory devices. Eye diagram 300 shows two unit intervals 305-a and 305-b of four-state pulse amplitude modulation (PAM4) signaling as an example. Eye diagram 300 shows four different levels or symbols that can be transmitted (e.g., across a conductor). Sometimes, the acronym "UI" may be used herein to refer to a unit interval. To generate eye diagram 300, an oscilloscope or other computing device may sample a digital signal according to a unit interval 305. Unit interval 305 may be defined by a clock associated with the transmission of the measured signal. In some instances, an oscilloscope or other computing device may measure the voltage level of the signal during the unit interval to form a trace 310. Noise and other factors may cause the trace 310 measured from the signal to deviate from a set of ideal functions. Variations in the trace may represent various possible signals that may be detected by a receiver on the data line.

[0077] In some examples, various characteristics about the measured signal may be determined by overlaying multiple traces 310. For example, eye diagram 300 may be used to identify different characteristics of a communication signal, such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. A closed eye may indicate a noisy and / or unpredictable signal.

[0078] The 'eye' of the eye diagram 300 may refer to the space between the traces 310. As the signal converges toward one of the four levels, the area between the levels may not contain the trace 310, which may be referred to as the eye of the eye diagram 300. In order to distinguish between different levels when decoding the signal, reference voltages 315, 320, 325 may be positioned between the different levels represented by the traces. For example, the low level reference voltage 315 may be positioned between the first level and the second level; the mid level reference voltage 320 may be positioned between the second level and the third level; and the high level reference voltage 325 may be positioned between the third level and the fourth level.

[0079] When decoding, the signal represented by the trace may be compared to the reference voltages 315, 320, 325 at sampling times 330, which may be specific to each unit interval 305. The smaller the eye associated with the reference voltages 315, 320, 325 and each sampling time 330, the greater the likelihood that an error may be introduced into the detection. For example, if a signal at a first level inadvertently crosses a low level reference voltage 315, an error (e.g., an incorrect value) may be detected. In such instances, the receiver may determine that the second level is present when, in fact, the first level is present.

[0080] In some cases, a training procedure may be initiated to modify the reference voltages and / or sampling times for an entire block of unit intervals 305. In such a training procedure, all reference voltages 315, 320, 325 in a single block of unit intervals 305, or all sampling times 330 in a single block of unit intervals 305, or both may be adjusted together. Although such a training procedure may improve the overall performance of the receiver measured within an entire block of unit intervals, some symbols may experience an increase in bit error rate. The characteristics of the data eye may be different for each different symbol or level because of different slew rates, crosstalk, duty cycle, and / or burst position mismatches.

[0081] Techniques for performing training procedures on individual symbols can be used to compensate for unique variations that may otherwise exist in different symbols. For example, individual training operations can be performed on each reference voltage 315 within a single unit interval 305. These individual training operations can allow the low level reference voltage 315 of the first unit interval 305-a to be positioned independently of the low level reference voltage 315 of the second unit interval 305-b and / or to be positioned independently of the mid-level reference voltage 320 or the high level reference voltage 325. In other examples, individual training operations can be performed on the sampling time 330 associated with each reference voltage 315, 320, 325. These individual training operations can allow the sampling time 330 associated with the low level reference voltage 315 within the first unit interval 305-a to be positioned independently of the sampling time 330 associated with the mid-level reference voltage 320 within the first unit interval 305-a or the high level reference voltage 325 within the first unit interval 305-a. Additionally, these individual training operations may allow the sampling times 330 in the first unit interval 305 - a to be located independently of the sampling times in other unit intervals (eg, the second unit interval 305 - b ).

[0082] Figure 4 An example of a flowchart 400 for supporting a training procedure for a receiver associated with a memory device according to aspects of the present disclosure is shown. In some examples, the flowchart 400 may show reference Figure 1 and 2Implementations of various aspects of the described system 100 or memory die 200. Flowchart 400 illustrates one or more training procedures that can be performed by a receiver to independently configure reference voltages, sampling times, other parameters, or combinations thereof. The functions of flowchart 400 can be performed by a host device or a memory device, among other examples.

[0083] At block 405, memory devices associated with the system may be powered on. In some cases, the training procedures described herein may occur in conjunction with powering on the memory devices.

[0084] At block 410, the host device or the memory device may initiate a training procedure. In some cases, the training procedure may be initiated based at least in part on determining that the memory device has been activated (e.g., after being deactivated). In some cases, the training procedure may be initiated after a period of inactivity, a dormant, sleep state, or in other circumstances. In some cases, these training procedures may be initiated for each conductive path or conductive line extending between the host device and the memory device. For example, if a data channel has four data lines (e.g., x4), a training procedure may be initiated for each of the four data lines of the data channel.

[0085] At block 415, a receiver of a host device or memory device may receive one or more training sequences (sometimes referred to as training pulse trains). A training pulse train may include a plurality of symbols transmitted using a series of unit intervals. In some cases, a training pulse train may include a set of determined symbols. For example, a training pulse train may include the transmission of eight symbols using eight consecutive unit intervals. The symbols transmitted during a training pulse train may be configured according to a training mode. For example, the symbols of a training pulse train may be all symbols of the same type (e.g., all high level symbols, medium high level symbols, medium low level symbols, or low level symbols). In other instances, the symbols may be organized according to a determined signal mode (e.g., a mode may include the following symbols: high, high, medium, low, low, medium, high, medium).

[0086] In some examples, a training procedure to refine each reference voltage and / or each sampling time may have at least two parts. During the first part of the training procedure, the host device or memory device may train at least some reference voltages (if not all reference voltages together) and / or at least some sampling times (if not all sampling times together). During the first part, the host device or memory device may identify a baseline reference voltage or a baseline adjustment to the reference voltage for each reference voltage. Additionally or alternatively, the host device or memory device may identify a baseline sampling time or a baseline adjustment to the sampling time for each sampling time in the training pulse train. During the second part of the training procedure, the host device or memory device may train individual reference voltages, individual sampling times, or both. The procedure may use one or more baselines that have been identified during the first part during the second part. In this way, the amount of time to perform individual training operations may be reduced. In fact, the baseline training operation may be used as a coarse refinement of the reference voltage and / or sampling time, and the individual training operation may be used to provide a fine refinement of the individual reference voltage and / or individual sampling time.

[0087] At block 420, the host device or the memory device may perform one or more baseline training operations. Examples of baseline training operations may include baseline reference voltage training operations and baseline timing training operations.

[0088] At 425, the host device or memory device may perform a baseline reference voltage training operation to identify a baseline level offset for a plurality of reference voltages used during a series of unit intervals. In some cases, the baseline offset may be applied to each reference voltage within the series of unit intervals, while in other cases, the baseline offset may be applied to a subset of the reference voltages within the series of unit intervals. As discussed above, the reference voltage may be used to distinguish between different symbol candidates. By comparing the received signal with the reference voltage, the host device and the memory device may be configured to determine whether the signal is a first symbol candidate (or below the first symbol candidate) or a second symbol candidate (or below the second symbol candidate). The symbol candidate may refer to a hypothesis of a symbol associated with a reference voltage. By comparing the signal with the reference voltage, the receiver may identify one of the two symbol candidates as a possible symbol represented by the signal. In a multi-symbol signal (e.g., PAM4), multiple reference voltages may be used to determine the actual symbol of a unit interval.

[0089] In some cases, to identify the baseline level shift, the host device or memory device may adjust one or more of the reference voltages until an error occurs. For example, the host device or memory device may know in advance which symbols are in the training burst. The host device or memory device may adjust (e.g., increase) one or more of the reference voltages until one or more errors occur with at least one of the reference voltages. The error may be such that the receiver identifies the symbol as the first symbol when the receiver actually expects the symbol to be a second symbol different from the first symbol. When the bit error rate meets the threshold, the host device or memory device may identify the voltage level of the reference voltage being used when the bit error rate meets the threshold as the upper bound of the reference voltage. An example of a threshold may be a bit error rate threshold. The host device or memory device may also reduce the reference voltage until one or more errors occur with at least one of the reference voltages. When the bit error rate meets the threshold, the host device or memory device may identify the voltage level of the reference voltage being used when the bit error rate meets the threshold as the lower bound of the reference voltage.

[0090] The host device or memory device may identify a pass point (e.g., a midpoint) between an upper bound of the reference voltage and a lower bound of the reference voltage. In some examples, the baseline level shift may represent a difference between an original level of the reference voltage and a pass point of the reference voltage, the pass point being identified by a baseline voltage training operation. In order to move the reference voltage to a baseline value, the baseline level shift may be applied to the original reference voltage value.

[0091] In some cases, the difference between the upper bound of the reference voltage and the lower bound of the reference voltage is referred to as a pass window.The baseline level shift may be configured to position the reference voltage at a pass point identified within the pass window.

[0092] At 430, the host device or the memory device may perform a baseline timing training operation to identify a baseline timing offset for a plurality of sampling times used during a series of unit intervals. In some cases, the baseline timing offset may be applied to each sampling time within the series of unit intervals. The sampling time may refer to the time during a unit interval at which a signal is compared to one or more reference voltages. In some instances, the sampling time of a unit interval may affect the number of errors detected when reading a signal received by a receiver through a conductive path.

[0093] In some cases, to identify the baseline timing offset, the host device or memory device may adjust the sampling time for at least some unit intervals (if not every unit interval) within a series of unit intervals at once. The host device or memory device may identify a passing point for the sampling time. If no passing point is identified, the host device or memory device may repeat the procedure at a lower speed. The host device or memory device may adjust the sampling time until an error occurs. For example, the host device or memory device may know in advance which symbols are in the training burst. The host device or memory device may adjust (e.g., increase) the sampling time until one or more errors occur with at least one sampling time within a unit interval. When the bit error rate meets the threshold, the host device or memory device may identify the sampling time being used when the bit error rate meets the threshold as an upper bound of the sampling time. The host device or memory device may adjust (e.g., decrease) the sampling time until one or more errors occur with at least one sampling time within a unit interval. When the bit error rate meets the threshold, the host device or memory device may identify the sampling time being used when the bit error rate meets the threshold as a lower bound of the sampling time.

[0094] The host device or memory device may identify a passing point (e.g., a midpoint) between an upper bound of the sampling time and a lower bound of the sampling time. The baseline timing offset may represent a difference between the original timing of the sampling time and the passing point of the sampling time, the passing point being identified by the baseline timing training operation. In order to move the sampling time to a baseline value, the baseline timing offset may be applied to the original sampling time.

[0095] At 435, the host device or the memory device may perform one or more individual training operations to refine the reference voltage and / or latch time. In some cases, the individual training operation may use one or more of the baseline offsets (e.g., baseline level offset, baseline timing offset, both offsets, other offsets) as a starting point for the training operation. An example of an individual training operation may include one or more individual reference voltage training operations and one or more individual timing training operations.

[0096] At 440, the host device or the memory device may perform one or more individual level training operations. The individual level training operations may be used to identify individual level offsets for particular reference voltages within particular unit intervals. As an example, a first individual level training operation may be used to determine a first individualized level offset for a first reference voltage 315 found within a first unit interval 305-a, and a second individual level training operation may be used to determine a second individualized level offset for a first reference voltage 315 found within a second unit interval 305-b. Similarly, a first individual level training operation may be used to determine a first individualized level offset for a first reference voltage 315 found within a first unit interval 305-a, and a second individual level training operation may be used to determine a second individualized level offset for a second reference voltage 320 found within the first unit interval 305-a.

[0097] In some cases, individual level training operations can be used to determine level offsets for multiple reference voltages. For example, individual level training operations can be used to identify a common level offset for at least some or each reference voltage within a single unit interval (e.g., reference voltages 315, 320, and 325). The multiple reference voltages served by a single individual level offset can be any combination of reference voltages within any unit interval.

[0098] The individual level training operation may be performed in a manner similar to the baseline level training operation. In such cases, the individual level training operation may identify upper and lower bounds for the reference voltage in question and may identify a passing point between the upper and lower bounds. The individual level training operation may include other features of the baseline level training operation.

[0099] At 445, the host device or the memory device may perform one or more individual timing training operations. The individual timing training operations may be used to identify individual timing offsets for specific sampling times within a specific unit interval. As an example, a first individual timing training operation may be used to determine a first individualized timing offset associated with sampling a first reference voltage 315 found within a first unit interval 305-a, and a second individual timing training operation may be used to determine a second individualized timing offset associated with sampling a second reference voltage 320 found within the first unit interval 305-a. Similarly, a first individual timing training operation may be used to determine a first individualized timing offset associated with sampling a first reference voltage 315 found within a first unit interval 305-a, and a second individual timing training operation may be used to determine a second individualized timing offset associated with sampling a first reference voltage 315 found within a second unit interval 305-b.

[0100] In some cases, an individual timing training operation can be used to determine a timing offset for multiple sampling times. For example, an individual timing training operation can be used to identify a common timing offset associated with sampling at least some or each reference voltage within a single unit interval (e.g., reference voltages 315, 320, and 325). The multiple sampling times served by a single individual timing offset can be any combination of sampling times associated with any reference voltage within any unit interval.

[0101] The individual timing training operation may be performed in a manner similar to the baseline timing training operation. In such cases, the individual timing training operation may identify upper and lower bounds for the sampling time in question and may identify a passing point between the upper and lower bounds. The individual timing training operation may include other features of the baseline timing training operation.

[0102] At 450, the host device and the memory device can transmit feedback to the transmitting device (e.g., the host device or the memory device) during the training procedure. In some instances, the training procedure can be initiated (e.g., run) by an external memory controller of the host device. When the receiver being trained is part of a memory device, the memory device can transmit one or more checksums or error correction data to indicate when an error occurs. The external memory controller of the host device can use the checksums or error correction data to identify upper and lower bounds of a reference voltage and / or sampling time, and to identify passing points and / or offsets (e.g., baseline level offsets, baseline timing offsets, individual level offsets, and / or individual timing offsets). In some instances, determination of passing points, offsets, and other information of the training procedure can be performed by a memory device (e.g., a device memory controller or one or more local memory controllers).

[0103] At 455, the host device or memory device may configure the receiver or initiate the configuration of the receiver based on the results of the training procedure. For example, the host device or memory device may take the original reference voltage level and apply a baseline level offset or an individual level offset, or both. In some cases, the individual level offset or the individual timing offset may have been combined with a baseline offset. In such cases, the host device or memory device may apply an individual offset (e.g., an individual level offset or an individual timing offset) to the original value (e.g., the original reference voltage level or the individual sampling time). In some cases, the individual offset may represent the difference between the individual level or time and the baseline level or time. In such cases, the host device or memory device may apply an individual offset (e.g., an individual level offset or an individual timing offset) and a baseline offset (e.g., a baseline level offset or a baseline timing offset) to the original value (e.g., the original reference voltage level or the individual sampling time).

[0104] In some cases, level training may be performed concurrently or simultaneously on one or more conductive paths (eg, data lines). In some cases, timing training may be performed concurrently or simultaneously on one or more conductive paths (eg, data lines).

[0105] Figure 5A and 5B 500 - a and 500 - b respectively illustrate examples of eye diagrams 500 - a and 500 - b that support a training procedure for a receiver associated with a memory device according to aspects of the present disclosure. In some examples, the eye diagrams 500 - a and 500 - b may illustrate reference Figure 1 and 2 Embodiments of various aspects of the described system 100 or memory die 200. Eye diagrams 500-a and 500-b each illustrate different aspects of a training procedure. The first eye diagram 500-a illustrates an example of a baseline level training operation, and the second eye diagram 500-b illustrates two examples of individual level training operations. The eye diagrams 500-a and 500-b illustrate binary symbol signals across two unit intervals 505 (e.g., a first unit interval 505-a and a second unit interval 505-b) to simplify the description. However, the principles described herein can be extended to apply to binary symbol signals transmitted across multiple unit intervals and / or multi-symbol signals transmitted across multiple unit intervals.

[0106] The first eye diagram 500-a illustrates how a baseline level training operation may affect a common reference voltage 510 used to distinguish symbol candidates within a first unit interval 505-a and a second unit interval 505-b. During a baseline level training operation, the common reference voltage 510 may be adjusted for both unit intervals. For example, a baseline level shift may be applied to the common reference voltage 510 so that the reference voltage for the first unit interval 505-a may be the same as the reference voltage for the second unit interval 505-b. Thus, conditions within the second unit interval 505-b may prevent the common reference voltage 510 from being positioned at an ideal location for the first unit interval 505-a, and vice versa.

[0107] The second eye diagram 500-b shows how two individual level training operations can affect two reference voltages 515 and 520 used to distinguish symbol candidates within the first unit interval 505-a and the second unit interval 505-b. During the first individual level training operation, the reference voltage 515 of the first unit interval 505-a can be adjusted. During the second individual level training operation, the reference voltage 520 of the second unit interval 505-b can be adjusted independently of the adjustment of the reference voltage 515. In such an example, a first individual level shift can be applied to the reference voltage 515 (e.g., applied to the first reference voltage), and a second individual level shift different from the first level shift can be applied to the reference voltage 520 (e.g., applied to the second reference voltage). In such a manner, the reference voltages 515, 520 of each unit interval 505-a, 505-b can be set to an ideal position independently of the other reference voltage.

[0108] Fig. 6A and 6B 600 - a and 600 - b respectively illustrate examples of eye diagrams 600 - a and 600 - b that support a training procedure for a receiver according to aspects of the present disclosure. In some examples, eye diagrams 600 - a and 600 - b may illustrate reference Figure 1 and 2 Embodiments of various aspects of the described system 100 or memory die 200. Eye diagrams 600-a and 600-b each illustrate different aspects of a training procedure. The first eye diagram 600-a illustrates an example of a baseline timing training operation, and the second eye diagram 600-b illustrates two examples of individual timing training operations. The eye diagrams 600-a and 600-b illustrate binary symbol signals across unit intervals 605 to simplify the description. However, the principles described herein can be extended to apply to binary symbol signals transmitted across multiple unit intervals and / or multi-symbol signals transmitted across multiple unit intervals.

[0109] The first eye diagram 600-a illustrates how a baseline timing training operation may affect a common sampling time 610 used to sample and compare a signal to both a first reference voltage 615 and a second reference voltage 620 within a unit interval. During a baseline timing training operation, the common sampling time 610 may be adjusted for the reference voltages 615, 620. For example, a baseline timing offset may be applied to the common sampling time 610 so that the time used to compare the signal to the first reference voltage 615 and the time used to compare the signal to the second reference voltage 620 are the same. In this manner, a condition of the eye associated with the first reference voltage 615 may prevent the common sampling time 610 from being positioned at an ideal location for the eye associated with the second reference voltage 620, and vice versa.

[0110] The second eye diagram 600-b shows how two individual timing training operations can affect sampling and comparing a signal to two reference voltages 615 and 620 at two different sampling times (e.g., a first sampling time 625 and a second sampling time 630). During the first individual timing training operation, the sampling time 625 associated with the first reference voltage 615 can be adjusted. During the second individual timing training operation, the second sampling time 630 associated with the second reference voltage 620 can be adjusted independently of the adjustment of the sampling time 625. In such an example, a first individual timing offset can be applied to the sampling time 625, and a second individual timing offset different from the first timing offset can be applied to the second sampling time 630. In such a manner, the sampling times 625, 630 associated with each reference voltage 615, 620 within a unit interval can be set to an ideal position independently of another sampling time.

[0111] Figure 7 An example of a circuit diagram 700 that supports a training procedure for a receiver according to aspects of the present disclosure is shown. In some examples, the circuit diagram 700 may implement a reference Figure 1 and 2 Aspects of the described system 100 or memory die 200. Circuit diagram 700 shows a receiver coupled to a single conductive line 705 (e.g., a DQ line and sometimes referred to as a pin) at a host device or a memory device. The receiver can be configured to determine a symbol transmitted on the conductive line 705. The receiver can include components configured to perform one or more training procedures, the one or more training procedures including baseline training operations (e.g., levels, timing), individual training operations (e.g., levels, timing), or both.

[0112] Circuit diagram 700 shows the structure of a receiver for a single conductive line 705. Similar structures can be used for other conductive lines in the system.

[0113] The receiver may include two stages, which may include a comparator stage 710 and a sampler stage 715. The comparator stage 710 may include one or more comparators 720 configured to compare a received signal (e.g., using conductive wire 705) with a reference voltage 725. In some cases, the reference voltage 725 may be tunable. In some cases, the comparator 720 may have a differential output. In some cases, the comparator may have a single-ended output.

[0114] The sampler stage 715 may include one or more latches 730 configured to latch and / or store the output of the comparator 720. The input of the latch 730 may be coupled to the output of the comparator 720 (differential or single-ended) and the sampling time 735. When the sampling time signal registers an activation command, the latch 730 may be activated and may output a signal to the controller. The sampling time 735 may be associated with a specific reference voltage. In some cases, the sampling time may be tunable. The controller may receive information from each latch 730 in the sampler stage 715. The controller may use the information from the latch 730 to determine the symbol being transmitted across the conductive line 705 during a unit interval, or a plurality of symbols being transmitted across the conductive line 705 during a series of unit intervals.

[0115] The circuit diagram 700 of the receiver shows the components required for concurrently detecting multiple reference signals across multiple unit intervals. Some receivers can be configured to decode multiple unit intervals simultaneously. For example, if the common word length of the signal is eight symbols, the receiver can be configured to decode eight unit intervals concurrently. To achieve this, other components can be added to the receiver. In addition, when the number of symbols that may be transmitted increases, the number of comparators and reference voltages may also increase.

[0116] The first row of components of circuit diagram 700 illustrates the circuit diagram of the circuit diagram 700 and the circuit diagram 700 that is used to compare the received signal with the first unit interval (e.g., reference Figure 3 The first unit interval 305-a) is described as a high level reference voltage (eg, reference Figure 3 The comparator stage 710 and the sampler stage 715 are associated with comparing the received signal to the second unit interval (e.g., the reference voltage 325) described above. The second row of components of the circuit diagram 700 shows components associated with comparing the received signal to the second unit interval (e.g., the reference voltage 325). Figure 3 The second unit interval 305-b) is described as a high level reference voltage (eg, reference Figure 3 The reference voltage 325 ) is described to be compared with the associated comparator stage 710 and the sampler base 715 .

[0117] Although not shown, the receiver may include an additional row for each unit interval that the receiver can decode (e.g., concurrently). For example, if the receiver can decode eight unit intervals (e.g., concurrently), there may be eight rows with a high level reference voltage (e.g., reference Figure 3 The receiver may be constructed or configured to decode any number of unit intervals at a time. Thus, there may be any number of rows of components associated with a high level reference voltage (e.g., one row, two rows, three rows, four rows, five rows, six rows, seven rows, eight rows, etc.).

[0118] In circuit diagram 700, each reference voltage 725 can be tunable (e.g., independently tunable) and each sampling time 735 can be tunable (e.g., independently tunable). Such a configuration can allow a training program to provide one or more offsets (e.g., level offsets and / or timing offsets) for a particular reference voltage within a particular unit interval.

[0119] The structure associated with recording the high level reference voltage can be replicated for other reference voltages. For example, the third row shown in circuit diagram 700 contains the structure associated with the mid level reference voltage (e.g., reference Figure 3 Components and rows of components associated with the mid-level reference voltage may be configured in a similar manner to the high-level components, except that the reference voltage input to comparator 720 may be different from the high-level reference voltage.

[0120] The receiver can be configured to use any number of reference signals to decode the signal. In some examples, the one or more signals transmitted across the conductive line 705 can be one or more PAM4 signals. As such, there may be three different reference voltages (e.g., high, medium, and low). The structures and components described herein can be extended to use any number of reference voltages and / or any number of unit intervals.

[0121] Making each reference voltage 725 and each sampling time 735 independently configurable allows the training program to perform individual level training operations and individual timing training operations as described herein. For example, when performing a baseline level training operation, at least some of the reference voltages 725 (if not all of the reference voltages) of the receiver can be adjusted together. When performing an individual level training operation, one or more of the reference voltages 725 can be adjusted (e.g., simultaneously, concurrently, in parallel). Similarly, when performing a baseline timing training operation, at least some of the sampling times 735 (if not all of the sampling times) of the receiver can be adjusted together. When performing an individual timing training operation, one or more of the sampling times 735 can be adjusted (e.g., simultaneously, concurrently, in parallel).

[0122] In some cases, each reference voltage 725 and / or each sampling time 735 may not be independently tunable or configurable. In some cases, the reference voltages 725 and / or sampling times 735 may be grouped into configurable sets (e.g., independently configurable sets). For example, a high level reference voltage (e.g., a reference Figure 3The reference voltages 325 described may not be independently tunable for each unit interval, but may be tunable across some or all unit intervals. When this is the case, the components shown in the circuit diagram 700 may be combined and / or rearranged. Another example of a set of configurable variables may be that the sampling time 735 of a single unit interval may be configurable, but the sampling time 735 associated with the individual reference voltages 725 may not be independently configurable. For tuning purposes, any combination of reference voltages 725 and / or sampling times 735 may be grouped together. When this is the case, the components shown in the circuit diagram 700 may be combined and / or rearranged.

[0123] Figure 8 A block diagram 800 of a training manager 805 supporting a training procedure for a receiver according to aspects of the present disclosure is shown. The functionality of the training manager 805 may be described by referring to Figure 1 and 2 The controller described (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) performs. The training manager 805 can include a receiver manager 810, a baseline voltage training manager 815, an individual voltage training manager 820, an individual training manager 825, a sampling manager 830, an error manager 835, a startup manager 840, a baseline timing training manager 845, and an individual timing training manager 850. Each of these modules can communicate with each other (e.g., through one or more buses) directly or indirectly.

[0124] The receiver manager 810 may receive a set of symbols during a series of unit intervals, each unit interval in the series including one symbol in the set of symbols. In some instances, the receiver manager 810 may configure a first reference voltage within a first unit interval with a first level offset, and configure the first reference voltage within a second unit interval with a second level offset. In some instances, the receiver manager 810 may receive a set of symbols within a series of unit intervals, each unit interval in the series including one symbol in the set of symbols.

[0125] In some instances, the receiver manager 810 may configure the first sampling time with a first timing offset and the second sampling time with a second timing offset. In some instances, the receiver manager 810 may configure the second reference voltage within the first unit interval with a third level offset. In some instances, the receiver manager 810 may receive a set of training pulse trains to identify level offsets for individual reference voltages associated with individual unit intervals in the series, wherein individual training pulse trains in the set include a set of symbols. In some instances, a set of training pulse trains are received during a training procedure, each training pulse train including a predetermined set of symbols, wherein an individual training pulse train includes the set of symbols.

[0126] The baseline voltage training manager 815 may identify a baseline level offset associated with the first reference voltage to distinguish between a first symbol candidate and a second symbol candidate in the symbol set. In some instances, the baseline voltage training manager 815 may apply a baseline level offset to the first reference voltage of a unit interval in the series. In some cases, the baseline level offset includes an initial value, and the first level offset and the second level offset are identified based on the initial value.

[0127] After identifying the baseline level shift, the individual voltage training manager 820 may identify a first level shift for a first reference voltage within a first unit interval in the series and a second level shift for a first reference voltage within a second unit interval in the series, the first level shift being different from the second level shift.

[0128] After identifying the baseline level shift, the individual training manager 825 may identify a third level shift for a second reference voltage within a first unit interval in the series, the third level shift being different from the first level shift and the second level shift.

[0129] During the first unit interval, the sampling manager 830 may sample a first output of the first comparator associated with the first reference voltage based on the first level shift and the first reference voltage.

[0130] The error manager 835 may adjust a first reference voltage for a first unit interval. In some instances, the error manager 835 may determine that an error occurred when demodulating one of the set of symbols based on adjusting the first reference voltage, wherein the first level offset is identified based on determining that the error occurred. In some instances, the error manager 835 may transmit an indication of the error occurring, wherein the first level offset is identified based on transmitting the indication.

[0131] In some examples, the error manager 835 may adjust a first sampling time of the first unit interval. In some examples, the error manager 835 may determine that an error occurred when demodulating one of the set of symbols based on adjusting the first sampling time, wherein the first timing offset is identified based on determining that the error occurred. In some examples, the error manager 835 may transmit a checksum indicating the error occurred, wherein the first timing offset is identified based on transmitting the checksum.

[0132] The startup manager 840 may start a training program including a baseline level training program and a set of individual level training programs, wherein receiving a set of symbols is performed based on starting the training program. In some instances, the startup manager 840 may start a training program for determining a baseline timing offset and an individual timing offset, wherein receiving a set of symbols is performed based on starting the training program. In some cases, the training program may be started for each pin of a channel. In some cases, the training program may be started for each data pin of a channel.

[0133] The baseline timing training manager 845 may identify a baseline timing offset associated with the sampling time for latching during the series of unit intervals. In some instances, the baseline timing training manager 845 may apply the baseline timing offset to the sampling time of the unit intervals in the series. In some cases, the baseline timing offset includes an initial value, and the first timing offset and the second timing offset are identified based on the initial value.

[0134] After identifying the baseline timing offset, the individual timing training manager 850 may identify a first timing offset for a first sampling time within a first unit interval in the series and a second timing offset for a second sampling time within a second unit interval in the series, the first timing offset being different from the second timing offset. In some instances, the individual timing training manager 850 may sample a first output of a first comparator associated with a first reference voltage at a first time during the first unit interval, the first time being based on the first sampling time and the first timing offset. In some instances, the individual timing training manager 850 may sample a second output of a second comparator associated with a second reference voltage at a second time different from the first time during the first unit interval, the second time being based on the first sampling time and a third timing offset.

[0135] Fig. 9A flow chart illustrating a method 900 for supporting a training procedure for a receiver in accordance with aspects of the present disclosure is shown. The operations of the method 900 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) or a component thereof as described herein. For example, the operations of the method 900 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) as described herein. Figure 8 The training manager described herein is executed. In some examples, the controller may execute an instruction set for controlling the functional elements of the controller to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform various aspects of the functions described herein.

[0136] At 905, the controller may receive a set of symbols during a series of unit intervals, each unit interval in the series containing one symbol from the set of symbols. In some examples, aspects of the operation of 905 may be implemented as described in reference to Figure 8 The receiver described performs the following.

[0137] At 910, the controller may identify a baseline level offset associated with a first reference voltage to distinguish a first symbol candidate from a second symbol candidate in a symbol set. In some examples, aspects of the operation of 910 may be accomplished by, for example, referring to Figure 8 The described baseline voltage training manager is implemented.

[0138] At 915, after identifying the baseline level shift, the controller may identify a first level shift for the first reference voltage within a first unit interval in the series and a second level shift for the first reference voltage within a second unit interval in the series, the first level shift being different from the second level shift. In some examples, aspects of the operation of 915 may be accomplished by, for example, referring to Figure 8 The described individual voltage training manager is executed.

[0139] At 920, the controller may configure the first reference voltage within the first unit interval with a first level shift and configure the first reference voltage within the second unit interval with a second level shift. In some examples, aspects of the operation of 920 may be implemented by, for example, reference Figure 8 The receiver described performs the following.

[0140] An apparatus as described herein may perform one or more methods, such as method 900. An apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a set of symbols during a series of unit intervals, each unit interval in the series including a symbol in the set of symbols; identifying a baseline level shift associated with a first reference voltage to distinguish between a first symbol candidate and a second symbol candidate in the set of symbols; after identifying the baseline level shift, identifying a first level shift for a first reference voltage within a first unit interval in the series and a second level shift for a first reference voltage within a second unit interval in the series, the first level shift being different from the second level shift; and configuring the first reference voltage within the first unit interval with the first level shift and configuring the first reference voltage within the second unit interval with the second level shift.

[0141] Some instances of the method or apparatus may further include operations, features, components, or instructions for: after identifying a baseline level offset, identifying a third level offset for a second reference voltage within a first unit interval in the series, the third level offset being different from the first level offset and the second level offset; and configuring the second reference voltage within the first unit interval with the third level offset.

[0142] Some examples of method or apparatus may further include operations, features, components, or instructions for sampling a first output of a first comparator associated with a first reference voltage based on a first level shift and the first reference voltage during a first unit interval.

[0143] Some instances of the method or apparatus may further include operations, features, components, or instructions for: adjusting a first reference voltage for a first unit interval; and determining, based on adjusting the first reference voltage, that an error occurs when demodulating a symbol in a set of symbols, wherein a first level offset may be identified based on determining that an error occurs.

[0144] Some examples of methods or apparatus may further include operations, features, components, or instructions for transmitting an indication of an error occurrence, wherein the first level offset may be identified based on the transmitted indication.

[0145] Some instances of method or apparatus may further include operations, features, components, or instructions for initiating a training procedure including a baseline level training procedure and a set of individual level training procedures, wherein receiving the set of symbols may be based on initiating the training procedure.

[0146] In some examples of methods or apparatus described herein, a training procedure can be initiated for each pin of a channel.

[0147] Some instances of the method or apparatus may further include operations, features, components, or instructions for receiving a set of training pulse trains to identify level shifts for individual reference voltages associated with individual unit intervals in the series, wherein an individual training pulse train in the set comprises a set of symbols.

[0148] In some examples of methods or apparatus described herein, the baseline level offset includes an initial value, and the first level offset and the second level offset can be identified based on the initial value.

[0149] Some examples of method or apparatus may further include operations, features, components, or instructions for applying a baseline level shift to a first reference voltage of a unit interval in the series.

[0150] Fig.10 A flow chart illustrating a method 1000 for supporting a training procedure for a receiver in accordance with aspects of the present disclosure is shown. The operations of the method 1000 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) or a component thereof as described herein. For example, the operations of the method 1000 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) as described herein. Figure 8 The training manager described herein is executed. In some examples, the controller may execute an instruction set for controlling the functional elements of the controller to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform various aspects of the functions described herein.

[0151] At 1005, the controller may initiate a training program including a baseline level training program and a set of individual level training programs. In some examples, aspects of the operation of 1005 may be described by referring to Figure 8 The described boot manager is executed.

[0152] At 1010, the controller may receive a set of symbols during a series of unit intervals based on initiating a training procedure, each unit interval in the series containing one symbol from the set of symbols. In some examples, aspects of the operation of 1010 may be implemented as described in reference to Figure 8 The receiver described performs the following.

[0153] At 1015, the controller may identify a baseline level offset associated with the first reference voltage to distinguish between a first symbol candidate and a second symbol candidate in the symbol set. In some examples, aspects of the operation of 1015 may be accomplished by, for example, referring to Figure 8 The described baseline voltage training manager is implemented.

[0154] At 1020, after identifying the baseline level shift, the controller may identify a first level shift for the first reference voltage within a first unit interval in the series and a second level shift for the first reference voltage within a second unit interval in the series, the first level shift being different from the second level shift. In some examples, aspects of the operation of 1020 may be accomplished by, for example, referring to Figure 8 The described individual voltage training manager is executed.

[0155] At 1025, the controller may configure the first reference voltage within the first unit interval with a first level shift and configure the first reference voltage within the second unit interval with a second level shift. In some examples, aspects of the operation of 1025 may be configured as described in the reference example. Figure 8 The receiver described performs the following.

[0156] Fig.11 A flow chart illustrating a method 1100 for supporting a training procedure for a receiver according to aspects of the present disclosure is shown. The operations of the method 1100 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) or a component thereof as described herein. For example, the operations of the method 1100 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) as described herein. Figure 8 The training manager described herein is executed. In some examples, the controller may execute an instruction set for controlling the functional elements of the controller to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform various aspects of the functions described herein.

[0157] At 1105, the controller may receive a set of symbols within a series of unit intervals, each unit interval in the series containing one symbol from the set of symbols. In some examples, aspects of the operation of 1105 may be implemented as described in reference to Figure 8 The receiver described performs the following.

[0158] At 1110, the controller may identify a baseline timing offset associated with a sampling time to latch during the series of unit intervals. In some examples, aspects of the operation of 1110 may be implemented as described with reference to Figure 8 The described baseline timed training manager is executed.

[0159] At 1115, after identifying the baseline timing offset, the controller may identify a first timing offset for a first sampling time within a first unit interval in the series and a second timing offset for a second sampling time within a second unit interval in the series, the first timing offset being different from the second timing offset. In some examples, aspects of the operation of 1115 may be implemented as described with reference to Figure 8 The described individual timed training manager is executed.

[0160] At 1120, the controller may configure the first sampling time with a first timing offset and configure the second sampling time with a second timing offset. In some examples, aspects of the operation of 1120 may be described by referring to Figure 8 The receiver described performs the following.

[0161] An apparatus as described herein may perform one or more methods, such as method 1100. An apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a set of symbols within a series of unit intervals, each unit interval in the series including one symbol from the set of symbols; identifying a baseline timing offset associated with a sampling time for latching during the series of unit intervals; after identifying the baseline timing offset, identifying a first timing offset for a first sampling time within a first unit interval in the series and identifying a second timing offset for a second sampling time within a second unit interval in the series, the first timing offset being different from the second timing offset; and configuring the first sampling time with the first timing offset and configuring the second sampling time with the second timing offset.

[0162] Some instances of the method or apparatus may further include operations, features, components, or instructions for identifying a third timing offset within a first unit interval that is different from the first timing offset, wherein the first sampling time may be associated with a first reference voltage of the first unit interval, and the third sampling time may be associated with a second reference voltage of the first unit interval.

[0163] Some instances of the method or apparatus may further include operations, features, components, or instructions for: sampling a first output of a first comparator associated with a first reference voltage at a first time during a first unit interval, the first time being based on a first sampling time and a first timing offset; and sampling a second output of a second comparator associated with a second reference voltage at a second time different from the first time during the first unit interval, the second time being based on the first sampling time and a third timing offset.

[0164] Some instances of the method or apparatus may further include operations, features, components, or instructions for: adjusting a first sampling time of a first unit interval; and determining, based on adjusting the first sampling time, that an error occurs when demodulating one symbol in a set of symbols, wherein a first timing offset may be identified based on determining that an error occurs.

[0165] Some examples of method or apparatus may further include operations, features, components, or instructions for transmitting a checksum indicating the occurrence of an error, wherein the first timing offset may be identified based on the transmitted checksum.

[0166] Some examples of methods or apparatus may further include operations, features, components, or instructions for initiating a training procedure for determining a baseline timing offset and an individual timing offset, wherein receiving a set of symbols may be based on initiating the training procedure.

[0167] In some examples of the methods or apparatus described herein, a training procedure can be initiated for each data pin of a channel.

[0168] Some instances of the method or apparatus may further include operations, features, components, or instructions for receiving a set of training pulse trains during a training procedure, each training pulse train including a predetermined set of symbols, wherein a single training pulse train includes the set of symbols.

[0169] In some examples of methods or apparatus described herein, the baseline timing offset includes an initial value, and the first timing offset and the second timing offset may be identified based on the initial value.

[0170] Some examples of method or apparatus may further include operations, features, components, or instructions for applying a baseline timing offset to the sampling times of the unit intervals in the series.

[0171] Fig.12 A flow chart illustrating a method 1200 for supporting a training procedure for a receiver in accordance with aspects of the present disclosure is shown. The operations of the method 1200 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) or a component thereof as described herein. For example, the operations of the method 1200 may be performed by a controller (e.g., external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or a combination thereof) as described herein. Figure 8 The training manager described herein is executed. In some examples, the controller may execute an instruction set for controlling the functional elements of the controller to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform various aspects of the functions described herein.

[0172] At 1205, the controller may initiate a training procedure for determining baseline timing offsets and individual timing offsets. In some examples, aspects of the operation of 1205 may be performed as described with reference to Figure 8 The described boot manager is executed.

[0173] At 1210, the controller may receive a set of symbols within a series of unit intervals based on initiating a training procedure, each unit interval in the series containing one symbol from the set of symbols. In some examples, aspects of the operation of 1210 may be implemented as described in reference to Figure 8 The receiver described performs the following.

[0174] At 1215, the controller may identify a baseline timing offset associated with a sampling time to latch during the series of unit intervals. In some examples, aspects of the operation of 1215 may be described by reference to Figure 8 The described baseline timed training manager is executed.

[0175] At 1220, after identifying the baseline timing offset, the controller may identify a first timing offset for a first sampling time within a first unit interval in the series and a second timing offset for a second sampling time within a second unit interval in the series, the first timing offset being different from the second timing offset. In some examples, aspects of the operation of 1220 may be performed as described with reference to Figure 8 The described individual timed training manager is executed.

[0176] At 1225, the controller may configure the first sampling time with a first timing offset and configure the second sampling time with a second timing offset. In some examples, aspects of the operation of 1225 may be described by referring to Figure 8 The receiver described performs the following.

[0177] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. In addition, aspects of two or more of the methods described may be combined.

[0178] In some instances, an apparatus or device may perform various aspects of the functions described herein using general or dedicated hardware. The apparatus or device may include a pin configured to be coupled to a data bus, a receiver coupled to the pin and configured to receive a set of symbols within a series of unit intervals, and a receiver including a comparator stage and a sampler stage. The comparator stage may include a first comparator coupled to the pin and a first reference voltage and a second comparator coupled to the pin and a second reference voltage different from the first reference voltage, the first comparator being configured to use the first reference voltage to distinguish between a first symbol candidate and a second symbol candidate during a first unit interval, and the second comparator being configured to use the second reference voltage to distinguish between a first symbol candidate and a second symbol candidate during a second unit interval. The sampler stage may include a first latch coupled to the first comparator and configured to sample the output of the first comparator during the first unit interval, and a second latch coupled to the second comparator and configured to sample the output of the second comparator during the second unit interval.

[0179] In some examples, the comparator stage may include a third comparator coupled to the pin and a third reference voltage, the third comparator may be configured to distinguish a third symbol candidate from a second symbol candidate during a first unit interval using the third reference voltage. In some examples, the sampler stage may include a third latch coupled to the third comparator and configured to sample an output of the third comparator during a first unit interval, wherein the first latch is configured to sample the output of the first comparator at a first sampling time during the first unit interval, and the third latch is configured to sample the output of the third comparator at a second sampling time during the first unit interval that is different from the first sampling time.

[0180] In some examples, a receiver can include a comparator and latch tuned to each reference voltage within each unit interval of a pin, the comparator and latch configured to demodulate multiple symbols received using the pin.

[0181] In some examples, the reference voltage coupled to each tuned comparator can be adjusted independently of other reference voltages coupled to other tuned comparators of the receiver. In some examples, the sampling time of each tuned latch can be adjusted independently of other sampling times of other tuned latches of the receiver.

[0182] The information and signals described herein may be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some figures may show multiple signals as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have various bit widths.

[0183] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly coupled to the ground. Thus, in a steady state, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V. The virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. "Virtual ground" or "virtual grounded" means connected to approximately 0V.

[0184] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled to each other) if there is any conductive path between the components that can support signal flow between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some cases, for example, one or more intermediate components (such as switches or transistors) may be used to interrupt the signal flow between the connected components for a period of time.

[0185] The term "coupling" refers to a condition of moving from an open circuit relationship between components where signals cannot currently be transmitted between components via a conductive path to a closed circuit relationship between components where signals can be transmitted between components via a conductive path. When a component such as a controller couples other components together, the component causes a change that allows signals to flow between the other components via a conductive path that previously did not allow signals to flow.

[0186] The term "isolated" refers to a relationship between components in which a signal is not currently able to flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, two components separated by a switch positioned between the two components are isolated from one another when the switch is open. When a controller isolates two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0187] As used herein, the term "substantially" means that the modified property (eg, a verb or adjective modified by the term substantially) need not be absolute, but is close enough to achieve the advantage of the property.

[0188] As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, lead, conductive line, conductive layer, etc., that provides a conductive path between elements or components of a memory array.

[0189] As used herein, the term "short" refers to a relationship between components in which a conductive path is established between the components by activating a single intermediate component between the two components in question. For example, a first component shorted to a second component can exchange signals with the second component when a switch between the two components is closed. Thus, a short can be a dynamic operation that enables charge to flow between components (or lines) in electronic communication.

[0190] The devices including memory arrays discussed herein may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of a substrate or a sub-region of a substrate may be controlled by doping with various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

[0191] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials such as metals. The source and drain may be conductive and may include heavily doped, for example, degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "disconnected" or "deactivated".

[0192] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented within the scope of the claims or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "superior to other examples." The detailed description contains specific details for providing an understanding of the described techniques. However, these techniques may be implemented without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0193] In the drawings, similar parts or features may have the same reference number. Further, components of the same type may be distinguished by following the reference number with a dash and a second reference that distinguishes between similar parts. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number without regard to the second reference number.

[0194] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0195] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or executed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0196] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function can be stored or transmitted as one or more instructions or codes on a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of the software, the functions described herein can be implemented using software, hardware, firmware, hard wiring, or any combination thereof executed by a server. The features of the implementation functions can also be physically located at various locations, including being distributed so that the various parts of the functions are implemented at different physical locations. And, as used herein (including in the claims), as used in a list of items (e.g., a list of items ending with phrases such as "at least one of..." or "one or more of..."), "or" indicates an inclusive list, so that, for example, at least one of the lists A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). And, as used herein, the phrase "based on" should not be interpreted as a reference to a conditional closed set. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0197] Computer-readable media includes non-transitory computer storage media and communication media including any media that promotes computer programs to be transferred from one place to another.Non-transitory storage media can be any available media that can be accessed by a general or special computer.By way of example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device or can be used for carrying or storing expected program code means in the form of instructions or data structures and any other non-transitory media that can be accessed by a general or special computer or a general or special processor.And, any connection is appropriately referred to as a computer-readable medium.For example, if a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are used to transmit software from a website, server or other remote source, the coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave are included in the definition of media. Disk or disc, as used herein, includes CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0198] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is intended to conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: Initiating a training procedure for a signal including one or more data eyes; identifying a reference voltage level for a first data eye of the one or more data eyes based at least in part on initiating the training procedure; identifying a reference timing for the first data eye based at least in part on initiating the training procedure; as well as A receiver is configured using the reference voltage level and the reference timing of the first data eye.

2. The method according to claim 1, wherein: Initiating the training procedure by the host device; as well as The training procedure is initiated based at least in part on activation of a memory device, a duration of inactivity of the memory device, exiting a sleep state of the memory device, or any combination thereof.

3. The method according to claim 1, wherein: The signal is associated with a data line associated with a channel of the memory device; and The training procedure is initiated for each data line of the channel.

4. The method according to claim 1, further comprising: identifying a second reference voltage level for a second data eye of the one or more data eyes based at least in part on initiating the training procedure; identifying a second reference timing for the second data eye based at least in part on initiating the training procedure; as well as The receiver is configured using the second reference voltage level and the second reference timing of the second data eye.

5. The method according to claim 1, further comprising: A plurality of training pulse trains are received to identify the reference voltage level of the first data eye and the reference timing of the first data eye, wherein a single training pulse train of the plurality of training pulse trains includes a plurality of data eyes including the first data eye.

6. The method according to claim 1, wherein: identifying the reference voltage level based on starting at a baseline voltage level offset that includes a first initial value; and The reference timing is identified based on starting at a baseline timing offset that includes a second initial value.

7. The method according to claim 1, further comprising: identifying one or more errors that occurred during the training procedure; as well as Information associated with the one or more errors is transmitted to a host device, wherein the information facilitates identification of a first boundary of the reference voltage level, a second boundary of the reference timing, or both.

8. The method according to claim 1, wherein: identifying the reference voltage level comprises identifying a plurality of reference voltage levels, the plurality of reference voltage levels including the reference voltage level of the first data eye and one or more other data eyes; as well as Identifying the reference timing includes identifying a plurality of reference timings including the reference timing of the first data eye and one or more other data eyes.

9. A device comprising: a pin configured to be coupled to a data bus; as well as a receiver coupled to the pin and configured to receive a plurality of symbols within a series of unit intervals, the receiver comprising a comparator stage and a sampler stage; The comparator stage comprises: a first comparator coupled to the pin and a first reference voltage, the first comparator configured to use the first reference voltage to distinguish between a first symbol candidate and a second symbol candidate during a first unit interval in the series; and a second comparator coupled to the pin and a second reference voltage different from the first reference voltage, the second comparator being configured to distinguish between the first symbol candidate and the second symbol candidate during a second unit interval in the series using the second reference voltage; and The sampler stage comprises: a first latch coupled to the first comparator and configured to sample an output of the first comparator during the first unit interval; and A second latch is coupled to the second comparator and configured to sample an output of the second comparator during the second unit interval.

10. The device of claim 9, wherein the comparator stage further comprises: a third comparator coupled to the pin and a third reference voltage, the third comparator configured to distinguish between the second symbol candidate and a third symbol candidate during the first unit interval using the third reference voltage; and The sampler stage further comprises: a third latch coupled to the third comparator and configured to sample an output of the third comparator during the first unit interval, wherein the first latch is configured to sample the output of the first comparator at a first sampling time during the first unit interval, and the third latch is configured to sample the output of the third comparator at a second sampling time during the first unit interval that is different from the first sampling time.

11. The device of claim 9, wherein the receiver further comprises: A comparator and a latch tuned to each reference voltage within each unit interval of the pin, the comparator and the latch configured to demodulate the plurality of symbols received using the pin.

12. The device of claim 11, wherein the reference voltage coupled to each tuned comparator is adjustable independently of other reference voltages coupled to other tuned comparators of the receiver.

13. The device of claim 11, wherein a sampling time of each tuned latch is adjustable independently of other sampling times of other tuned latches of the receiver.

14. An apparatus comprising: one or more memory devices; as well as processing circuitry coupled to the one or more memory devices and configured to cause the apparatus to: Initiating a training procedure for a signal including one or more data eyes; identifying a reference voltage level for a first data eye of the one or more data eyes based at least in part on initiating the training procedure; identifying a reference timing for the first data eye based at least in part on initiating the training procedure; as well as A receiver is configured using the reference voltage level and the reference timing of the first data eye.

15. The device according to claim 14, wherein: Initiating the training procedure by the host device; as well as The training procedure is initiated based at least in part on activation of a memory device, a duration of inactivity of the memory device, exiting a sleep state of the memory device, or any combination thereof.

16. The device according to claim 14, wherein: The signal is associated with a data line associated with a channel of the memory device; and The training procedure is initiated for each data line of the channel.

17. The apparatus of claim 14, wherein the processing circuitry is further configured to cause the apparatus to: identifying a second reference voltage level for a second data eye of the one or more data eyes based at least in part on initiating the training procedure; identifying a second reference timing for the second data eye based at least in part on initiating the training procedure; as well as The receiver is configured using the second reference voltage level and the second reference timing of the second data eye.

18. The apparatus of claim 14, wherein the processing circuitry is further configured to cause the apparatus to: A plurality of training pulse trains are received to identify the reference voltage level of the first data eye and the reference timing of the first data eye, wherein a single training pulse train of the plurality of training pulse trains includes a plurality of data eyes including the first data eye.

19. The apparatus of claim 14, wherein: identifying the reference voltage level based on starting at a baseline voltage level offset that includes a first initial value; and The reference timing is identified based on starting at a baseline timing offset that includes a second initial value.

20. The apparatus of claim 14, wherein the processing circuitry is further configured to cause the apparatus to: identifying one or more errors that occurred during the training procedure; and Information associated with the one or more errors is transmitted to a host device, wherein the information facilitates identification of a first boundary of the reference voltage level, a second boundary of the reference timing, or both.

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