Ferroelectric memory and data read and write methods therefor

Abstract

The present disclosure provides a ferroelectric memory and a data reading method and a data writing method thereof, and relates to the technical field of semiconductor technology, and is used to solve the technical problem of low storage density. The ferroelectric memory comprises a storage cell array, the storage cell array comprises a plurality of storage cells arranged in an array, each storage cell stores n-bit data, wherein each storage cell comprises a transistor and 2 n -1 ferroelectric capacitor coupled to the transistor, n is a positive integer greater than 1; a plurality of word lines, each word line is coupled to the storage cells arranged in a row in the storage cell array; a plurality of bit lines, each bit line is coupled to the storage cells arranged in a column in the storage cell array. The polarization direction of the 2 n -1 ferroelectric capacitor can determine 2 n a storage state, each storage state corresponds to one data, so that the 2 n -1 ferroelectric capacitor stores n-bit data, realizes the multi-state storage of the ferroelectric memory, and improves the storage density of the ferroelectric memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a ferroelectric memory and a data reading method and a data writing method thereof. Background Art

[0002] With the rapid development of electronic technology, non-volatile transistor memories have seen significant growth, with the ability to be prepared using solution methods and compatible with integrated circuits. These include NAND flash memory, NOR flash memory, resistance random access memory, phase change memory, magnetoresistive random access memory, ferroelectric memory, and spin transfer torque random access memory. Among these, ferroelectric memory holds the greatest commercial value due to its high integration density, good repeatability, and fast response speed. However, ferroelectric memory suffers from relatively low storage density. Summary of the Invention

[0003] In view of the above problems, embodiments of the present disclosure provide a ferroelectric memory and a data reading method and a data writing method thereof, so as to improve the storage density of the ferroelectric memory.

[0004] According to some embodiments, a first aspect of the present disclosure provides a ferroelectric memory comprising:

[0005] A memory cell array, wherein the memory cell array includes a plurality of memory cells arranged in an array, each of the memory cells storing n-bit data, wherein each of the memory cells includes: a transistor and a 2-bit transistor coupled to the transistor. n -1 ferroelectric capacitor, wherein n is a positive integer greater than 1;

[0006] a plurality of word lines, each word line coupled to the memory cells arranged in a row in the memory cell array;

[0007] A plurality of bit lines are provided, each of the bit lines being coupled to the memory cells arranged in a column in the memory cell array.

[0008] In some possible embodiments, each of the ferroelectric capacitors includes a first electrode plate and a second electrode plate that are oppositely arranged, and a dielectric layer filled between the first electrode plate and the second electrode plate;

[0009] 2 n - 1 said ferroelectric capacitors are arranged in sequence along the first direction, 2 n -1 the first electrode plates are connected into an integrated structure, 2 n -1 the second electrode plate is connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integral structure, and the dielectric layers have different thicknesses.

[0010] In some possible embodiments, along the first direction, 2n -The thickness of the dielectric layer of each of the ferroelectric capacitors increases sequentially.

[0011] In some possible embodiments, along the first direction, 2 n -1 The coercive voltages of the ferroelectric capacitors are arranged in an arithmetical order.

[0012] In some possible embodiments, 2 n -1 The second plate has the same potential as 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

[0013] In some possible embodiments, each of the ferroelectric capacitors includes a first electrode plate and a second electrode plate that are oppositely arranged, and a dielectric layer filled between the first electrode plate and the second electrode plate;

[0014] 2 n - 1 said ferroelectric capacitors are arranged in sequence along the first direction, 2 n -1 the first electrode plates are connected into an integrated structure, 2 n -1 said dielectric layers are connected into an integrated structure, 2 n - One of the second electrode plates is arranged at intervals.

[0015] In some possible embodiments, 2 n -1 The thickness of the dielectric layer is equal to that of 2 n -1 The coercive voltages of the ferroelectric capacitors are the same.

[0016] In some possible embodiments, 2 n -1 The second electrode plates have the same length.

[0017] In some possible embodiments, 2 n -1 The second plate potentials are different, 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line

[0018] The ferroelectric memory provided by the embodiments of the present disclosure has at least the following advantages:

[0019] The ferroelectric memory provided by the embodiment of the present disclosure includes a memory cell array, a plurality of word lines and a plurality of bit lines. The memory cell array includes a plurality of memory cells arranged in an array. Each word line is coupled to a memory cell arranged in a row in the memory cell array, and each bit line is coupled to a memory cell arranged in a column in the memory cell array. Each memory cell includes a transistor and a 2-bit transistor coupled to the transistor. n -1 ferroelectric capacitor, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of a ferroelectric capacitor can determine 2 n storage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor stores n bits of data, thereby realizing polymorphic storage of the ferroelectric memory and improving the storage density of the ferroelectric memory.

[0020] According to some embodiments, a second aspect of the present disclosure provides a data reading method for a ferroelectric memory, which is applied to the ferroelectric memory as described above. The data reading method includes:

[0021] Using bit lines and transistors, the corresponding 2 n - the first plates of the ferroelectric capacitors are all charged to a first voltage, wherein the first voltage causes the polarization direction of each of the ferroelectric capacitors to point toward the first plate, and when the polarization direction of the ferroelectric capacitors is reversed, the ferroelectric capacitors discharge positive charge to the bit line;

[0022] Data in the storage unit is acquired according to a change in the charge amount of the bit line, wherein the storage unit stores n bits of the data.

[0023] The data reading method of the ferroelectric memory provided by the embodiment of the present disclosure has at least the following advantages:

[0024] The data reading method of the ferroelectric memory provided by the embodiment of the present disclosure is applied to the ferroelectric memory of polymorphic storage. Each storage unit of the ferroelectric memory includes a transistor and a 2 coupled transistor. n -1 ferroelectric capacitor, n is a positive integer greater than 1. By n -1 The first plates of the ferroelectric capacitors are all charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor to point to the first plate. The polarization direction of the ferroelectric capacitor is reversed to flow out positive charge to the bit line. According to the change in the charge amount of the bit line, the data in the storage unit can be obtained, and the reading of n-bit data can be realized, thereby improving the storage density of the ferroelectric memory.

[0025] According to some embodiments, a third aspect of the present disclosure provides a data writing method for a ferroelectric memory, which is applied to the ferroelectric memory as described above, wherein the data reading method includes:

[0026] Using bit lines and transistors, the corresponding 2 n - charging the first plate of a ferroelectric capacitor to a first voltage, wherein the first voltage causes the polarization direction of each storage capacitor to point to the first plate, so as to initialize each ferroelectric capacitor;

[0027] Applying a write voltage to the bit line, the memory cell stores data; wherein the write voltage has a value of 2 n A voltage value, the storage unit stores n bits of data, each voltage value corresponds to one type of data, some of the voltage values ​​cause the polarization direction of at least some of the ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of the ferroelectric capacitors whose polarization directions are flipped.

[0028] The data writing method of the ferroelectric memory provided by the embodiment of the present disclosure has at least the following advantages:

[0029] The data writing method of the ferroelectric memory in the embodiment of the present disclosure is applied to the ferroelectric memory of polymorphic storage. Each storage unit of the ferroelectric memory includes a transistor and a 2 coupled transistor. n -1 ferroelectric capacitor, n is a positive integer greater than 1. By n The first plates of the ferroelectric capacitors are all charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor to point toward the first plate, thereby initializing each ferroelectric capacitor. Different write voltage values ​​are then used, each voltage value corresponding to a type of data. Some voltage values ​​cause the polarization direction of at least some ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors to flip their polarization directions, thereby enabling the writing of n-bit data and improving the storage density of the ferroelectric memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a ferroelectric capacitor storage device 1 in the related art;

[0031] Figure 2 Schematic diagram of the storage 0 principle of a ferroelectric capacitor in the related art;

[0032] Figure 3 Schematic diagram of the structure of a ferroelectric memory in one embodiment of the present disclosure;

[0033] Figure 4 is a schematic diagram of a polarization state in an embodiment of the present disclosure;

[0034] Figure 5 Schematic diagram of a structure of a ferroelectric capacitor in one embodiment of the present disclosure;

[0035] Figure 6 for Figure 5The first storage state of the ferroelectric capacitor in

[0036] Figure 7 for Figure 5 The second storage state of the ferroelectric capacitor in

[0037] Figure 8 for Figure 5 The third storage state of the ferroelectric capacitor in

[0038] Figure 9 for Figure 5 The fourth storage state of the ferroelectric capacitor in

[0039] Figure 10 is another structural schematic diagram of a ferroelectric capacitor in one embodiment of the present disclosure;

[0040] Figure 11 Schematic diagram of the connection between a transistor and a ferroelectric capacitor in one embodiment of the present disclosure;

[0041] Figure 12 for Figure 10 The first storage state of the ferroelectric capacitor in

[0042] Figure 13 for Figure 10 The second storage state of the ferroelectric capacitor in

[0043] Figure 14 for Figure 10 The third storage state of the ferroelectric capacitor in

[0044] Figure 15 for Figure 10 The fourth storage state of the ferroelectric capacitor in

[0045] Figure 16 Flowchart of a method for reading data from a ferroelectric capacitor in one embodiment of the present disclosure;

[0046] Figure 17 for Figure 5 Schematic diagram of bit line precharging when reading ferroelectric capacitor data;

[0047] Figure 18 for Figure 5 A polarization direction change diagram of the first storage state of the ferroelectric capacitor;

[0048] Figure 19 for Figure 5 A diagram showing a change in polarization direction of a second storage state of a ferroelectric capacitor;

[0049] Figure 20 for Figure 5 A diagram showing the change in polarization direction of the third storage state of the ferroelectric capacitor;

[0050] Figure 21 for Figure 5 A diagram showing a change in polarization direction of the fourth storage state of the ferroelectric capacitor;

[0051] Figure 22 for Figure 10 Schematic diagram of bit line precharging when reading ferroelectric capacitor data;

[0052] Figure 23 for Figure 10 A polarization direction change diagram of the first storage state of the ferroelectric capacitor;

[0053] Figure 24 for Figure 10 A diagram showing a change in polarization direction of a second storage state of a ferroelectric capacitor;

[0054] Figure 25 for Figure 10 A diagram showing the change in polarization direction of the third storage state of the ferroelectric capacitor;

[0055] Figure 26 for Figure 10 A diagram showing the change in polarization direction of the third storage state of the ferroelectric capacitor;

[0056] Figure 27 Flowchart of a method for writing data into a ferroelectric capacitor in one embodiment of the present disclosure;

[0057] Figure 28 for Figure 5 Schematic diagram of bit line precharging when writing ferroelectric capacitor data;

[0058] Figure 29 for Figure 5 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a first preset value;

[0059] Figure 30 for Figure 5 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a second preset value;

[0060] Figure 31 for Figure 5 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a third preset value;

[0061] Figure 32 for Figure 5 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a fourth preset value;

[0062] Figure 33 for Figure 10 Schematic diagram of bit line precharging when writing ferroelectric capacitor data;

[0063] Figure 34 for Figure 10 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a first preset value;

[0064] Figure 35 for Figure 10 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a second preset value;

[0065] Figure 36 for Figure 10 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a third preset value;

[0066] Figure 37 for Figure 10 A diagram showing a change in polarization direction of the ferroelectric capacitor when the write voltage is a fourth preset value.

[0067] Description of reference numerals:

[0068] 11-transistor; 12-ferroelectric capacitor;

[0069] 20-bit line; 30-word line;

[0070] 40-substrate; 50-gate dielectric layer;

[0071] 60-plug; 70-wire. DETAILED DESCRIPTION

[0072] The ferroelectric memory in the related art has a storage density problem. The inventors have found that the reason is that the ferroelectric memory includes multiple memory cells, each of which is usually a 1T1C (Ferroelectric Cell) structure, which includes a transistor and a ferroelectric capacitor. Figure 1 and Figure 2 The polarization direction of the ferroelectric capacitor is two, that is, it has two stable states. These two stable states are stored in the form of "0" or "1". Each storage unit can only store one bit of data, and the storage density is low.

[0073] To this end, the present disclosure provides a ferroelectric memory comprising a plurality of memory cells, each memory cell comprising a transistor and a 2-pole coupled to the transistor. n -1 ferroelectric capacitor, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of a ferroelectric capacitor can determine 2 n storage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor stores n bits of data, realizing polymorphic storage of ferroelectric memory and improving the storage density of ferroelectric memory.

[0074] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0075] See Figure 3 The present disclosure provides a semiconductor structure including a memory cell array, and a plurality of word lines 30 and a plurality of bit lines 20 electrically connected to the memory cell array. The memory cell array is used to store data, and includes a plurality of memory cells arranged in an array and spaced apart, that is, the plurality of memory cells are arranged in multiple rows and columns, and the row direction ( Figure 3 X direction shown) and column direction ( Figure 3 The Y direction is perpendicular to the memory cell array to increase the storage density of the memory cell array.

[0076] Multiple word lines 30 are arranged at intervals, and multiple bit lines 20 are arranged at intervals. The word lines 30 extend in a direction that intersects, for example, is perpendicular to, the direction of extension of the bit lines 20. Each word line 30 is coupled to memory cells arranged in rows in the memory cell array, i.e., each word line 30 is coupled to a row of memory cells. Each bit line 20 is coupled to memory cells arranged in columns in the memory cell array, i.e., each bit line 20 is coupled to a column of memory cells.

[0077] Continue reading Figure 3 Each memory cell stores n bits of data. Each memory cell includes a transistor 11 and two transistors coupled to the transistor 11. n -1 ferroelectric capacitor 12, where n is a positive integer greater than 1. When the transistor 11 is turned on, the memory cell performs data writing or data reading.

[0078] Each ferroelectric capacitor 12 includes a first plate and a second plate that are arranged opposite to each other, and a dielectric layer filled between the first plate and the second plate. The first plate and the second plate are respectively arranged on both sides of the dielectric layer, and the material of the dielectric layer is ferroelectric material, that is, the second plate, the dielectric layer and the first plate are stacked in sequence. Figure 3 As shown, the second plate is the lower plate of the ferroelectric capacitor 12 , and the first plate is the upper plate of the ferroelectric capacitor 12 .

[0079] Due to 2 n Each of the ferroelectric capacitors 12 can be polarized according to 2 n -1 The polarization direction of the ferroelectric capacitor 12 can be determined by 2 nstorage states, each storage state corresponds to a data, so that 2 n -1 ferroelectric capacitor 12 stores n bits of data. Among them, the storage state is 2 n -The number of ferroelectric capacitors 12 with a polarization direction in a preset direction in one ferroelectric capacitor 12 .

[0080] For example, see Figure 4 , when n is 2, the transistor 11 in each memory cell is connected to three ferroelectric capacitors 12. The three ferroelectric capacitors 12 can determine four storage states to store 2-bit data. Among them, the ferroelectric capacitor 12 with the polarization direction pointing to the third direction can have 3, 2, 1 or 0. Correspondingly, the three ferroelectric capacitors 12 correspond to data 00, 10, 01, and 11 respectively. Figure 4 As shown, the polarization direction pointing to the third direction means the polarization direction is upward, that is, the polarization direction is toward the upper plate (first plate) of the ferroelectric capacitor 12. Of course, when n is 3, the transistor 11 in each memory cell is connected to 7 ferroelectric capacitors 12, and the three ferroelectric capacitors 12 can determine 8 storage states to store 3 bits of data.

[0081] It can be understood that when there are 3 ferroelectric capacitors 12 with polarization directions pointing to the third direction, that is, all three ferroelectric capacitors 12 are polarized in the third direction (upward), and the three ferroelectric capacitors 12 correspond to 00, that is, the memory cell stores 00. When there are 2 polarization directions pointing to the third direction, that is, any two ferroelectric capacitors 12 of the three ferroelectric capacitors 12 are polarized in the third direction (upward), and the other ferroelectric capacitor 12 is polarized in the opposite direction (downward) of the third direction, and the three ferroelectric capacitors 12 correspond to 10, that is, the memory cell stores 10. When there is 1 polarization direction pointing to the third direction, that is, any one ferroelectric capacitor 12 of the three ferroelectric capacitors 12 is polarized in the third direction (upward), and the other two ferroelectric capacitors 12 are polarized in the opposite direction (downward) of the third direction, and the three ferroelectric capacitors 12 correspond to 01, that is, the memory cell stores 01. When the number of ferroelectric capacitors 12 with polarization pointing in the third direction is zero, that is, all three ferroelectric capacitors 12 are polarized in the opposite direction (downward) of the third direction, the three ferroelectric capacitors 12 correspond to 11, that is, the memory cell stores 11. The three ferroelectric capacitors 12 have four different polarization modes and thus have four storage states to store 2 bits of data.

[0082] See Figure 3 and Figure 5 In some possible embodiments, 2 n -1 ferroelectric capacitors 12 are arranged in sequence along the first direction, wherein 2 n -1 first plate forms an integrated structure, 2 n -1 second plate forms an integrated structure, 2 n-1 dielectric layer forms an integrated structure, and 2 n -1 The thickness of the dielectric layer is different so that 2 n The coercive voltages of the −1 ferroelectric capacitors 12 are different, and thus the ferroelectric capacitors 12 have n memory states.

[0083] It is understood that due to the varying thicknesses of the dielectric layers, the second plates are spaced apart along the thickness of the dielectric layers, with adjacent second plates connected by a connecting plate to form a single unit. For dielectric layers made of the same material, a thicker dielectric layer increases the coercive voltage of ferroelectric capacitor 12 and, consequently, the applied voltage required to reverse its polarization direction.

[0084] In some examples, along the first direction, 2 n -1 The thickness of the dielectric layer of the ferroelectric capacitor 12 increases successively, that is, 2 n -1 second electrode plate is connected in a step shape, the second electrode plate forms a step surface, and the two ends of the connecting electrode plate are respectively connected to the two adjacent second electrode plates. n The coercive voltages of the ferroelectric capacitors 12 are sequentially increased, thereby reducing the leakage current between adjacent ferroelectric capacitors 12 .

[0085] Among them, along the first direction, 2 n -1 The coercive voltages of the ferroelectric capacitors 12 are arranged in an arithmetic order, that is, along the first direction 2 n The coercive voltage gradient of each ferroelectric capacitor 12 is increased. This configuration reduces leakage current while also providing a certain degree of differentiation between the coercive voltages of the ferroelectric capacitors 12, thereby preventing erroneous polarization reversal of the ferroelectric capacitors 12. In an example where the memory cell includes three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 may be 0.5V, 1.5V, and 2.5V, respectively.

[0086] Continue reading Figure 3 and Figure 5 , 2 n -1 second plates have the same potential, for example, connected to zero potential, that is, the external voltage applied to each ferroelectric capacitor 12 is the same. When the external voltage is greater than the coercive voltage, the polarization direction of the ferroelectric capacitor 12 is reversed. n A first electrode plate is connected to one of the source and drain of the corresponding transistor 11, and the other of the source and drain of the transistor 11 is connected to the corresponding bit line 20, so that data can be written to the ferroelectric capacitor 12 via the bit line 20, or data in the ferroelectric capacitor 12 can be read out to the bit line 20. The gate of the transistor 11 is connected to the corresponding word line 30, which controls whether the transistor 11 is turned on or off.

[0087] like Figure 3 and Figure 5 As shown, 2 n-1 first electrode plate is formed into one piece and connected to the bit line 20, 2 through the transistor 11 n -1 second electrode plate is formed into one piece and connected to the same power line PL so that 2 n -1 second plates have the same potential. The voltage difference between the first plate and the second plate arranged opposite to each other is the external voltage of the ferroelectric capacitor 12. n -1 ferroelectric capacitor 12 has the same applied voltage, while 2 n -1 ferroelectric capacitor 12 has different coercive voltages. According to the relationship between the applied voltage and the coercive voltage, n The polarization direction of a ferroelectric capacitor 12 is reversed or remains unchanged, thereby writing or reading data.

[0088] See Figures 6 to 9 , 2 n -1 ferroelectric capacitor 12 with 2 n There are 2 storage states n There are four different polarization states, each storage state can correspond to one data, so as to store n bits of data. For example, when n is 2, the three ferroelectric capacitors 12 have four storage states, corresponding to 00, 10, 01, and 11 respectively.

[0089] like Figure 6 As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 are directed toward the first plate, and this polarization state corresponds to 00. Figure 7 As shown, the polarization directions of two of the three ferroelectric capacitors 12 point to the first plate, and this polarization state corresponds to 10. Figure 8 As shown, the polarization direction of one of the three ferroelectric capacitors 12 points to the first plate, and this polarization state corresponds to 01. Figure 9 As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 point to the second electrode plate, and this polarization state corresponds to 11.

[0090] See Figure 10 and Figure 11 In some other possible embodiments, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n -1 first plate connected into an integrated structure, 2 n -1 dielectric layer connected into an integrated structure, 2 n The second plates are arranged at intervals of -1, so that the applied voltages of the ferroelectric capacitors 12 are different (for example, arranged equidistantly) and the applied voltages of the ferroelectric capacitors 12 remain unchanged, thereby having n storage states. In an example where the memory cell includes three ferroelectric capacitors 12, the applied voltages of the three ferroelectric capacitors 12 can be -1V, 0V, and 1V, respectively.

[0091] Among them, 2 n -1 dielectric layer has the same thickness so that 2 n The coercive voltages of the ferroelectric capacitors 12 are the same to facilitate manufacturing. Due to the coercive voltages of the ferroelectric capacitors 12, there is no need to distinguish the ferroelectric capacitors 12. By adjusting the applied voltage of each ferroelectric capacitor 12, data can be written to or read from the storage unit. n The lengths of the second plates are the same so that the ferroelectric capacitors 12 are the same.

[0092] It can be understood that in order to achieve the connection between the ferroelectric capacitors 12, a connecting plate is connected between two adjacent first plates along the first direction, and a connecting layer is connected between two adjacent dielectric layers, so that the first plates are formed into one, the dielectric layers are formed into one, and the second plates are arranged at intervals.

[0093] In order to write or read data, Figure 11 As shown, 2 n -1 The second plate potentials are different, 2 n −1 first electrode plate is connected to one of the source and drain of the corresponding transistor 11 , the other of the source and drain of the transistor 11 is connected to the corresponding bit line 20 , and the gate of the transistor 11 is connected to the corresponding word line 30 .

[0094] like Figure 10 As shown, 2 n -1 first electrode plate is formed into one piece and connected to the bit line 20, 2 through the transistor 11 n -1 second plate is connected to different power lines, so that 2 n The potential of the first and second plates is different. The voltage difference between the first and second plates arranged opposite to each other is the external voltage of the ferroelectric capacitor 12. n -1 ferroelectric capacitor 12 has different applied voltages. According to the relationship between the applied voltage and the coercive voltage, 2 n The polarization direction of a ferroelectric capacitor 12 is reversed or remains unchanged, thereby writing or reading data.

[0095] See Figures 10 to 15 , 2 n -1 ferroelectric capacitor 12 with 2 n There are 2 storage states n There are four different polarization states, each storage state can correspond to a data, so as to store n bits of data. For example, when n is 2, the three ferroelectric capacitors 12 have four storage states, corresponding to 00, 10, 01, and 11 respectively.

[0096] like Figure 12As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 are directed toward the first plate, and this polarization state corresponds to 00. Figure 13 As shown, the polarization directions of two of the three ferroelectric capacitors 12 point to the first plate, and this polarization state corresponds to 10. Figure 14 As shown, the polarization direction of one of the three ferroelectric capacitors 12 points to the first plate, and this polarization state corresponds to 01. Figure 15 As shown, the polarization directions of all the ferroelectric capacitors 12 in the three ferroelectric capacitors 12 point to the second electrode plate, and this polarization state corresponds to 11.

[0097] The type and structure of transistor 11 in the disclosed embodiment are not limited. Transistor 11 may be a thin film transistor (TFT) to facilitate 3D stacking. Transistor 11 may also be a planar transistor, etc., to be compatible with dynamic random access memory (DRAM) processes.

[0098] For example, Figure 11 As shown, transistor 11 includes an active region disposed within substrate 40, a gate dielectric layer 50 located above the active region, and a gate located on gate dielectric layer 50. Word line 30 serves as the gate. The first plates of ferroelectric capacitor 12 are connected to form an integral whole and are connected to the active region via plug 60. The second plates of ferroelectric capacitor 12 are connected to wires 70, which are connected to peripheral circuits via wires 70 to provide different voltage values ​​to the second plates of ferroelectric capacitor 12, thereby placing the second plates of ferroelectric capacitor 12 at different potentials.

[0099] In summary, the ferroelectric memory provided by the embodiment of the present disclosure includes a memory cell array, a plurality of word lines 30 and a plurality of bit lines 20. The memory cell array includes a plurality of memory cells arranged in an array. Each word line 30 is coupled to a memory cell arranged in a row in the memory cell array, and each bit line 20 is coupled to a memory cell arranged in a column in the memory cell array. Each memory cell includes a transistor 11 and a 2 coupled transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1, to store n bits of data. n -1 The polarization direction of the ferroelectric capacitor 12 can be determined by 2 n storage states, each storage state corresponds to a data, so that 2 n - One ferroelectric capacitor 12 stores n-bit data, realizing polymorphic storage of the ferroelectric memory and improving the storage density of the ferroelectric memory.

[0100] The present disclosure also provides a data reading method for a ferroelectric memory, which is applied to the above-mentioned ferroelectric memory. Figure 3 、 Figure 5 、 Figure 10 and Figure 11 The specific structure of the ferroelectric memory can be found in the above embodiment and will not be described in detail here. Figure 16 , the data reading method comprises the following steps:

[0101] Step S100: Using bit lines and transistors, the corresponding 2 n The first plates of the -1 ferroelectric capacitors are all charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor to point to the first plate. When the polarization direction of the ferroelectric capacitor is reversed, the ferroelectric capacitor flows positive charge to the bit line.

[0102] The voltage on the bit line 20 is precharged to the first voltage, and the word line 30 and the transistor 11 are turned on, so that the corresponding 2 n The first plates of each of the ferroelectric capacitors 12 are charged to a first voltage, i.e., the first plates of all of the ferroelectric capacitors 12 are at the first voltage. The first voltage is a low voltage, and the absolute value of the potential difference between the first plate and the second plate is greater than the coercive voltage of each ferroelectric capacitor 12, so that the polarization direction of each ferroelectric capacitor 12 is toward the first plate.

[0103] In 2 n -1 Before the first plate of the ferroelectric capacitor 12 is charged, 2 n -1 The polarization direction of the ferroelectric capacitor 12 can have multiple situations, so that 2 n -1 ferroelectric capacitor 12 is in different storage states to store data. n After the first plates of the -1 ferroelectric capacitors 12 are charged, the polarization directions of these ferroelectric capacitors 12 all point to the first plates. If the polarization directions of each ferroelectric capacitor 12 do not change, no charge flows from the ferroelectric capacitors 12 to the bit lines 20. If the polarization direction of any ferroelectric capacitor 12 is reversed, then during the reversal process, charge flows from the ferroelectric capacitor 12 to the bit lines 20, and the amount of positive charge is positively correlated with the number of ferroelectric capacitors 12 that are reversed.

[0104] Step S200: acquiring data in a storage unit according to a change in the charge amount of a bit line, wherein the storage unit stores n-bit data.

[0105] According to the change of the charge amount of the bit line 20, the data in the memory cell can be obtained. n -1 The polarization direction of the ferroelectric capacitor 12 can be determined by 2 n There are storage states, each storage state corresponds to one type of data, and the storage unit can store n bits of data.

[0106] In some examples, such as Figure 5 As shown, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n -1 first plate forms an integrated structure, 2 n -1 second plate forms an integrated structure, 2 n -1 dielectric layer forms an integrated structure, and 2 n To facilitate the description of the data reading process of the ferroelectric memory, n is set to 2, that is, each memory cell has three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 are 0.5V, 1V, and 1.5V, respectively, and the external voltage of the second plates of the three ferroelectric capacitors 12 is 0V.

[0107] See Figure 17 The voltage of bit line 20 is precharged to a first voltage. The absolute value of the difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3V. Word line 30 and transistor 11 are turned on. The potential of the first plates of the three ferroelectric capacitors 12 is all at the first voltage, that is, -3V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward the first plate.

[0108] See Figure 18 Before the word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the first plate, the three ferroelectric capacitors 12 store 00. After the word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 do not change, and no charge flows.

[0109] See Figure 19 Before the word line 30 and transistor 11 are turned on, if the polarization directions of the two ferroelectric capacitors 12 are both directed toward the first plate, and the polarization direction of one ferroelectric capacitor 12 is directed toward the second plate, for example, the polarization direction of the first ferroelectric capacitor 12 is directed toward the second plate, then the three ferroelectric capacitors 12 store 10. After the word line 30 and transistor 11 are turned on, the polarization direction of one ferroelectric capacitor 12 is reversed, and the first plate of the ferroelectric capacitor 12 changes from positive charge to negative charge, equivalent to two positive charges flowing to the bit line 20. The polarization directions of the other two ferroelectric capacitors 12 do not change and do not contribute to the flow of charge, resulting in a total of two positive charges flowing to the bit line 20.

[0110] See Figure 20Before word line 30 and transistor 11 are turned on, if the polarization direction of one ferroelectric capacitor 12 points to the first plate, and the polarization directions of two ferroelectric capacitors 12 both point to the second plate, for example, the polarization direction of the third ferroelectric capacitor 12 points to the first plate, then the three ferroelectric capacitors 12 store 01. After word line 30 and transistor 11 are turned on, the polarization directions of the two ferroelectric capacitors 12 are reversed, and the first plates of these two ferroelectric capacitors 12 change from positive charge to negative charge, equivalent to four positive charges flowing to bit line 20. The polarization direction of the other ferroelectric capacitor 12 does not change and does not contribute to the charge flow, resulting in a total of four positive charges flowing to bit line 20.

[0111] See Figure 21 Before word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the second plate, the three ferroelectric capacitors 12 store 11. After word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 are reversed, and a total of six equivalent positive charges flow to bit line 20.

[0112] The positive charge flowing into the bit line 20 changes the voltage or current on the bit line 20. The corresponding data can be read according to the change in the charge on the bit line 20. A total of four different storage states can be read, that is, 2 bits of data can be read. After the data is read, it needs to be written back to the ferroelectric capacitor 12.

[0113] In other examples, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n -1 first plate connected into an integrated structure, 2 n -1 dielectric layer connected into an integrated structure, 2 n To facilitate the description of the data reading process of the ferroelectric memory, n is set to 2, that is, each memory cell has three ferroelectric capacitors 12, the coercive voltage of the three ferroelectric capacitors 12 is 1.5V, and the external voltages of the second plates of the three ferroelectric capacitors 12 are -1V, 0V, and 1V respectively.

[0114] See Figure 22 The voltage of bit line 20 is precharged to a first voltage. The absolute value of the potential difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3V. Word line 30 and transistor 11 are turned on. The potential of the first plates of the three ferroelectric capacitors 12 is all at the first voltage, that is, -3V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward the first plate.

[0115] See Figure 23Before the word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the first plate, the three ferroelectric capacitors 12 store 00. After the word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 do not change, and no charge flows.

[0116] See Figure 24 Before the word line 30 and transistor 11 are turned on, if the polarization directions of the two ferroelectric capacitors 12 are both directed toward the first plate, and the polarization direction of one ferroelectric capacitor 12 is directed toward the second plate, for example, the polarization direction of the first ferroelectric capacitor 12 is directed toward the second plate, then the three ferroelectric capacitors 12 store 10. After the word line 30 and transistor 11 are turned on, the polarization direction of one ferroelectric capacitor 12 is reversed, and the first plate of the ferroelectric capacitor 12 changes from positive charge to negative charge, equivalent to two positive charges flowing to the bit line 20. The polarization directions of the other two ferroelectric capacitors 12 do not change and do not contribute to the flow of charge, resulting in a total of two positive charges flowing to the bit line 20.

[0117] See Figure 25 Before word line 30 and transistor 11 are turned on, if the polarization direction of one ferroelectric capacitor 12 points to the first plate, and the polarization directions of two ferroelectric capacitors 12 both point to the second plate, for example, the polarization direction of the third ferroelectric capacitor 12 points to the first plate, then the three ferroelectric capacitors 12 store 01. After word line 30 and transistor 11 are turned on, the polarization directions of the two ferroelectric capacitors 12 are reversed, and the first plates of these two ferroelectric capacitors 12 change from positive charge to negative charge, equivalent to four positive charges flowing to bit line 20. The polarization direction of the other ferroelectric capacitor 12 does not change and does not contribute to the charge flow, resulting in a total of four positive charges flowing to bit line 20.

[0118] See Figure 26 Before word line 30 and transistor 11 are turned on, if the polarization directions of the three ferroelectric capacitors 12 all point to the second plate, the three ferroelectric capacitors 12 store 11. After word line 30 and transistor 11 are turned on, the polarization directions of the three ferroelectric capacitors 12 are reversed, and a total of six equivalent positive charges flow to bit line 20.

[0119] The positive charge flowing into the bit line 20 changes the voltage or current on the bit line 20. The corresponding data can be read according to the change in the charge on the bit line 20. A total of four different storage states can be read, that is, 2 bits of data can be read. After the data is read, it needs to be written back to the ferroelectric capacitor 12.

[0120] In summary, the data reading method of the ferroelectric memory in the embodiment of the present disclosure is applied to a ferroelectric memory with multi-state storage, wherein each storage unit of the ferroelectric memory includes a transistor 11 and a 2 coupled to the transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1. Byn -1 The first plates of the ferroelectric capacitors 12 are all charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor 12 to point to the first plate. The polarization direction of the ferroelectric capacitor 12 is reversed to flow out positive charge to the bit line 20. According to the change in the charge amount of the bit line 20, the data in the storage unit can be obtained, and the reading of n-bit data can be realized, thereby improving the storage density of the ferroelectric memory.

[0121] The present disclosure also provides a data writing method for a ferroelectric memory, which is applicable to the above ferroelectric memory. Figure 3 、 Figure 5 、 Figure 30 and Figure 31 The specific structure of the ferroelectric memory can be found in the above embodiment and will not be described in detail here. Figure 27 , the data writing method may include the following steps:

[0122] Step a: Use bit lines and transistors to connect the corresponding 2 n - The first plates of one ferroelectric capacitor are charged to a first voltage, where the first voltage causes the polarization directions of the storage capacitors to point toward the first plate, so as to initialize the ferroelectric capacitors.

[0123] The voltage on the bit line 20 is precharged to the first voltage, and the word line 30 and the transistor 11 are turned on, so that the corresponding 2 n The first plates of the ferroelectric capacitors 12 are all charged to the first voltage, that is, the potentials of the first plates of these ferroelectric capacitors 12 are all the first voltage. The first voltage is a low voltage, and the absolute value of the potential difference between the first plate and the second plate is greater than the coercive voltage of each ferroelectric capacitor 12, so that the polarization direction of each ferroelectric capacitor 12 is directed to the first plate, completing 2 n - Initialization of 1 ferroelectric capacitor 12.

[0124] Step b: Apply a write voltage to the bit line, and the memory cell stores data; wherein the write voltage has a value of 2 n The storage unit stores n bits of data, each voltage value corresponds to one type of data, and some voltage values ​​cause the polarization directions of at least some ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors whose polarization directions flip.

[0125] A write voltage is applied to the bit line 20, and the corresponding 2 is connected through the transistor 11. n -1 ferroelectric capacitor 12 writes data so that the memory cell stores data. Wherein, the write voltage has 2 n voltage values, each voltage value corresponds to 2 n -1 ferroelectric capacitor 12 has a storage state corresponding to a data. The storage state refers to 2 n-1 polarization state of the ferroelectric capacitor 12, specifically 2 n -The number of ferroelectric capacitors 12 with polarization directions pointing to the second plate (or the first plate) in one ferroelectric capacitor 12.

[0126] It is understandable that the write voltage is 2 n One of the voltage values ​​makes 2 n -1 ferroelectric capacitors 12 have no polarization direction change, that is, the number of ferroelectric capacitors 12 whose polarization direction is reversed is 0, and the other voltage value makes 2 n -1 The polarization direction of each ferroelectric capacitor 12 is reversed, that is, the number of ferroelectric capacitors 12 whose polarization direction is reversed is 2 n -1. The rest of the voltage values ​​are 2 n -1 ferroelectric capacitor 12 has its polarization direction reversed, and each of the remaining voltage values ​​corresponds to a different number of reversed ferroelectric capacitors 12, ranging from 0 to 2. n Different voltage values ​​cause different numbers of ferroelectric capacitors 12 whose polarization directions are reversed, so that each voltage value corresponds to different data.

[0127] For example, when n is 2, the write voltage has four voltage values, which are the first preset value, the second preset value, the third preset value and the fourth preset value. When the voltage value of the write voltage is the first preset value, the polarization direction of 0 ferroelectric capacitors 12 is reversed. When the voltage value of the write voltage is the second preset value, the polarization direction of 1 ferroelectric capacitor 12 is reversed. When the voltage value of the write voltage is the third preset value, the polarization direction of 2 ferroelectric capacitors 12 is reversed. When the voltage value of the write voltage is the fourth preset value, the polarization direction of 3 ferroelectric capacitors 12 is reversed.

[0128] In some examples, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n -1 first plate forms an integrated structure, 2 n -1 second plate forms an integrated structure, 2 n -1 dielectric layer forms an integrated structure, and 2 n To facilitate the description of the data writing process of the ferroelectric memory, n is set to 2, that is, each memory cell has three ferroelectric capacitors 12, the coercive voltages of the three ferroelectric capacitors 12 are 0.5V, 1V, and 1.5V, respectively, and the external voltage value of the second plate of the three ferroelectric capacitors 12 is 0V.

[0129] See Figure 28The voltage of bit line 20 is precharged to a first voltage. The absolute value of the difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3V. Word line 30 and transistor 11 are turned on. The potential of the first plates of the three ferroelectric capacitors 12 is all at the first voltage, that is, -3V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward the first plate.

[0130] See Figure 29 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is a first preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the first preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. The absolute value of the difference between the first preset value of each ferroelectric voltage and the voltage value of the external voltage is less than the coercive voltage of the ferroelectric capacitor 12. The polarization directions of the three ferroelectric capacitors 12 all point to the first plate, the polarization direction does not change, and the data 00 is stored. For example, if the first preset value is 0V, the difference between it and the voltage value of the external voltage 0V is less than the coercive voltage of each ferroelectric capacitor 12.

[0131] See Figure 30 , a write voltage is applied to the bit line 20. When the write voltage reaches a second preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all at the second preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all at the voltage value of the external voltage. Among the three ferroelectric capacitors 12, only one ferroelectric capacitor 12 has an absolute value of the difference between the second preset value and the voltage value of the external voltage that is greater than the coercive voltage of the ferroelectric capacitor 12. The polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization directions of the other two ferroelectric capacitors 12 remain unchanged, and data 10 is stored. For example, when the second preset value is 1V and the coercive voltage is 0.5V, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization directions of the other two ferroelectric capacitors 12 remain unchanged.

[0132] See Figure 31 , a write voltage is applied to the bit line 20. When the write voltage reaches a third preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all equal to the third preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all equal to the voltage of the external voltage. If the absolute value of the difference between the third preset value and the voltage value of the external voltage for two of the three ferroelectric capacitors 12 is greater than the coercive voltage of the ferroelectric capacitor 12, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization direction of the remaining ferroelectric capacitor 12 remains unchanged, and data 01 is stored. For example, if the third preset value is 2V and the coercive voltages are 0.5V and 1V, the polarization direction of the ferroelectric capacitors 12 is reversed, while the polarization direction of the other ferroelectric capacitor 12 remains unchanged.

[0133] See Figure 32, a write voltage is applied to the bit line 20. When the write voltage reaches a fourth preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all at the fourth preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all at the voltage value of the external voltage. The absolute value of the difference between the fourth preset value of the three ferroelectric capacitors 12 and the voltage value of the external voltage is greater than the coercive voltage, causing the polarization directions of the three ferroelectric capacitors 12 to flip, and data 11 is stored. For example, when the third preset value is 3V, the polarization directions of the ferroelectric capacitors 12 with coercive voltages of 0.5V, 1V, and 1.5V flip.

[0134] In other examples, 2 n -1 ferroelectric capacitor 12 is arranged in sequence along the first direction, 2 n -1 first plate connected into an integrated structure, 2 n -1 dielectric layer connected into an integrated structure, 2 n To facilitate the description of the data writing process of the ferroelectric memory, n is set to 2, that is, each memory cell has three ferroelectric capacitors 12, the coercive voltage of the three ferroelectric capacitors 12 is 1.5V, and the external voltages of the second plates of the three ferroelectric capacitors 12 are -1V, 0V, and 1V respectively.

[0135] See Figure 33 The voltage of bit line 20 is precharged to a first voltage. The absolute value of the potential difference between the first voltage and each external voltage is greater than the coercive voltage. For example, the first voltage can be -3V. Word line 30 and transistor 11 are turned on. The potential of the first plates of the three ferroelectric capacitors 12 is all at the first voltage, that is, -3V. The potential difference between the first plate and the second plate is greater than the coercive voltage, and the potential of the first plate is lower, so that the polarization direction of the three ferroelectric capacitors 12 is all toward the first plate.

[0136] See Figure 34 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is the first preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the first preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage, and the voltage values ​​of the external voltage are different. The absolute value of the difference between the first preset value of each ferroelectric voltage and the voltage value of the external voltage is less than 1.5V, that is, it is less than the coercive voltage of the ferroelectric capacitor 12. The polarization directions of these three ferroelectric capacitors 12 all point to the first plate, the polarization direction does not change, and the data 00 is stored. For example, the first preset value is 0V, and the absolute value of the difference between the first preset value and -1V, 0V, and 1V is less than 1.5V.

[0137] See Figure 35, a write voltage is applied to the bit line 20. When the voltage value of the write voltage is a second preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the second preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. Among the three ferroelectric capacitors 12, only one ferroelectric capacitor 12 has an absolute value of the difference between the second preset value and the voltage value of the external voltage that is greater than the coercive voltage of the ferroelectric capacitor 12. The polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization directions of the other two ferroelectric capacitors 12 remain unchanged, and data 10 is stored. For example, when the second preset value is 1V and the voltage value of the external voltage is -1V, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization directions of the other two ferroelectric capacitors 12 remain unchanged.

[0138] See Figure 36 , a write voltage is applied to the bit line 20. When the voltage value of the write voltage is a third preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all the third preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all the voltage value of the external voltage. When the absolute value of the difference between the third preset value and the voltage value of the external voltage of two of the three ferroelectric capacitors 12 is greater than the coercive voltage of the ferroelectric capacitor 12, the polarization direction of the ferroelectric capacitor 12 is reversed, while the polarization direction of the remaining ferroelectric capacitor 12 remains unchanged, and the data 01 is stored. For example, when the third preset value is 2V, the polarization directions of the ferroelectric capacitors 12 with the voltage values ​​of -1V and 0V of the external voltage are both reversed, while the polarization direction of the ferroelectric capacitor 12 with the voltage value of 1V remains unchanged.

[0139] See Figure 37 , a write voltage is applied to the bit line 20. When the write voltage reaches a fourth preset value, the potentials of the first plates of the three ferroelectric capacitors 12 are all at the fourth preset value, and the potentials of the second plates of the three ferroelectric capacitors 12 are all at the voltage value of the external voltage. The absolute value of the difference between the fourth preset value of the three ferroelectric capacitors 12 and the voltage value of the external voltage is greater than the coercive voltage, causing the polarization directions of the three ferroelectric capacitors 12 to flip, and data 11 is stored. For example, when the third preset value is 3V, the polarization directions of the ferroelectric capacitors 12 with external voltage values ​​of -1V, 0V, and 1V flip.

[0140] In summary, the data writing method of the ferroelectric memory in the embodiment of the present disclosure is applied to a ferroelectric memory of polymorphic storage, wherein each storage unit of the ferroelectric memory includes a transistor 11 and a 2 coupled to the transistor 11. n -1 ferroelectric capacitor 12, n is a positive integer greater than 1. By nThe first plates of all ferroelectric capacitors 12 are charged to a first voltage. The first voltage causes the polarization direction of each ferroelectric capacitor 12 to point toward the first plate, thereby initializing each ferroelectric capacitor 12. Different write voltage values ​​are then used, with each voltage value corresponding to a type of data. Some voltage values ​​cause the polarization direction of at least some ferroelectric capacitors 12 to flip, and different voltage values ​​cause different numbers of ferroelectric capacitors 12 to flip their polarization directions. This allows writing of n-bit data, thereby improving the storage density of the ferroelectric memory.

[0141] In this specification, each embodiment or implementation method is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The descriptions with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A ferroelectric memory, characterized in that: include: A memory cell array, wherein the memory cell array comprises a plurality of memory cells arranged in an array, each of the memory cells storing n-bit data, wherein each of the memory cells comprises: a transistor and a 2-bit transistor coupled to the transistor; n -1 ferroelectric capacitor, wherein n is a positive integer greater than 1; each of the ferroelectric capacitors comprises a first plate, a second plate, and a dielectric layer filled between the first plate and the second plate. n -1 ferroelectric capacitors are arranged in sequence along the first direction, 2 n -1 the first electrode plates are connected into an integrated structure, 2 n - one of the dielectric layers is connected into an integrated structure; a plurality of word lines, each word line coupled to the memory cells arranged in a row in the memory cell array; A plurality of bit lines are provided, each of the bit lines being coupled to the memory cells arranged in a column in the memory cell array.

2. The ferroelectric memory according to claim 1, wherein 2 n - one of the second electrode plates is connected into an integrated structure, and the thickness of each dielectric layer is different.

3. The ferroelectric memory according to claim 2, wherein: Along the first direction, 2 n -The thickness of the dielectric layer of each of the ferroelectric capacitors increases sequentially.

4. The ferroelectric memory according to claim 3, wherein Along the first direction, 2 n -1 The coercive voltages of the ferroelectric capacitors are arranged in an arithmetical order.

5. The ferroelectric memory according to any one of claims 2 to 4, characterized in that: 2 n -1 The second plate has the same potential as 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

6. The ferroelectric memory according to claim 1, wherein 2 n - One of the second electrode plates is arranged at intervals.

7. The ferroelectric memory according to claim 6, wherein: 2 n -1 The thickness of the dielectric layer is equal to that of 2 n -1 The coercive voltages of the ferroelectric capacitors are the same.

8. The ferroelectric memory according to claim 7, wherein: 2 n -1 The second electrode plates have the same length.

9. The ferroelectric memory according to any one of claims 6 to 8, wherein: 2 n -1 The second plate potentials are different, 2 n -1 first electrode plate is connected to one of the source and drain of the corresponding transistor, the other of the source and drain of the transistor is connected to the corresponding bit line, and the gate of the transistor is connected to the corresponding word line.

10. A method for reading data from a ferroelectric memory, characterized in that: Applied to the ferroelectric memory according to any one of claims 1 to 9, the data reading method comprises: Using bit lines and transistors, the corresponding 2 n - the first plates of the ferroelectric capacitors are all charged to a first voltage, wherein the first voltage causes the polarization direction of each of the ferroelectric capacitors to point toward the first plate, and when the polarization direction of the ferroelectric capacitors is reversed, the ferroelectric capacitors discharge positive charge to the bit line; Data in the storage unit is acquired according to a change in the charge amount of the bit line, wherein the storage unit stores n bits of the data.

11. A method for writing data into a ferroelectric memory, characterized in that: Applied to the ferroelectric memory according to any one of claims 1 to 9, the data writing method comprises: Using bit lines and transistors, the corresponding 2 n - charging the first plate of a ferroelectric capacitor to a first voltage, wherein the first voltage causes the polarization direction of each storage capacitor to point to the first plate, so as to initialize each ferroelectric capacitor; Applying a write voltage to the bit line, the memory cell stores data; wherein the write voltage has a value of 2 n A voltage value, the storage unit stores n bits of data, each voltage value corresponds to one type of data, some of the voltage values ​​cause the polarization direction of at least some of the ferroelectric capacitors to flip, and different voltage values ​​cause different numbers of the ferroelectric capacitors whose polarization directions are flipped.

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