Controller and operating method, memory system and operating method, and readable medium

Abstract

The embodiment of the invention provides a controller and an operation method thereof, a memory system and an operation method thereof, and a readable medium. The controller comprises a storage structure which is configured to store M rows * N columns of address sets, the address sets comprise fault addresses and corresponding redundant addresses, and both M and N are positive integers; the controller is configured to: determine whether there is a selected row in M rows according to an operation address of an operation command and a feature fault address of each row; the feature fault addresses of each row are selected from N address sets of the same row; and determining whether a selected address set exists in the selected row or not according to the operation address and the N address sets of the selected row under the condition of determining that the selected row exists in the M rows.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a controller and operating method, a memory system and operating method, and a readable medium. Background Art

[0002] With the continuous development of semiconductor technology, the storage capacity of semiconductor devices is getting larger and larger. However, in the mass production process of semiconductor devices, errors may occur in the production process, resulting in faulty units (also called "faulty units") in semiconductor devices. In order to improve the quality and manufacturing yield of semiconductor devices, redundant units (also called "spare units" or "mapping units") can be used to replace faulty units for redundancy repair. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a controller and an operating method, a memory system and an operating method, and a readable medium.

[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a controller, comprising: a storage structure, configured to: store M rows * N columns of address sets, the address sets including fault addresses and corresponding redundant addresses, M and N being positive integers; the controller, configured to: determine whether there is a selected row in the M rows according to an operation address of an operation command and a characteristic fault address of each row; the characteristic fault address of each row is selected from N address sets of the same row; and in a case where it is determined that there is a selected row in the M rows, determine whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row.

[0006] In some embodiments, the controller is further configured to: when it is determined that the selected row contains a selected address set, execute the operation command according to the redundant addresses in the selected address set; when it is determined that the selected row does not contain a selected address set, execute the operation command according to the operation address.

[0007] In some embodiments, the controller includes: a first composite module, connected to the storage structure and the control unit, and configured to: compare the operation address of the operation command sent by the control unit with the characteristic fault address of each row to obtain a first comparison result; the control unit is configured to: determine whether there is a selected row in the M rows based on the first comparison result.

[0008] In some embodiments, the first composite module includes: a first register unit, configured to store a characteristic fault address of each row; a first comparison unit, connected to the first register unit, configured to compare the operation address with the characteristic fault address of each row to obtain a first comparison result; the control unit is configured to determine that there is a selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address meet a preset condition; and determine that there is no selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address do not meet the preset condition; wherein the preset condition includes that the operation address is within a limited range of the characteristic fault addresses of each row.

[0009] In some embodiments, the control unit is further configured to: when it is determined that there is no selected row in the M rows, execute the operation command according to the operation address.

[0010] In some embodiments, the controller includes: a second composite module, connected to the storage structure and the control unit, and configured to: when it is determined that there is a selected row in the M rows, compare the operation address with the N address sets in the selected row to obtain a second comparison result; the control unit is configured to: determine whether there is a selected address set in the selected row based on the second comparison result.

[0011] In some embodiments, the second composite module includes: a second register unit, configured to store N address sets of the selected row; a second comparison unit, connected to the second register unit, configured to compare the operation address with a fault address in the N address sets of the selected row to obtain a second comparison result; the control unit is configured to determine that there is a selected address set in the selected row when the second comparison result indicates that the operation address and a fault address in 1 address set of the selected row are the same; and determine that there is no selected address set in the selected row when the second comparison result indicates that the operation address and the fault addresses in the N address sets of the selected row are different.

[0012] In some embodiments, the M rows*N columns address sets are obtained by sorting the fault addresses in the address set.

[0013] In a second aspect, an embodiment of the present disclosure provides a memory system, the memory system comprising: a controller as described in the first aspect of the present disclosure and a memory coupled to the controller.

[0014] In a third aspect, an embodiment of the present disclosure provides an operating method of a controller, the operating method comprising: providing M rows*N columns of address sets, the address sets comprising a fault address and a corresponding redundant address, M and N being positive integers; determining whether there is a selected row in the M rows according to an operation address of an operation command and a characteristic fault address of each row; the characteristic fault address of each row is selected from N address sets of the same row; when it is determined that there is a selected row in the M rows, determining whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row.

[0015] In some embodiments, when it is determined that there is a selected row in the M rows, after determining whether the selected row has a selected address set based on the operation address and N address sets of the selected row, the operation method further includes: when it is determined that there is a selected address set in the selected row, executing the operation command based on redundant addresses in the selected address set; when it is determined that there is no selected address set in the selected row, executing the operation command based on the operation address.

[0016] In some embodiments, determining whether there is a selected row in M ​​rows based on the operation address of the operation command and the characteristic fault address of each row includes: comparing the operation address and the characteristic fault address of each row to obtain a first comparison result; and determining whether there is a selected row in M ​​rows based on the first comparison result.

[0017] In some embodiments, determining whether there is a selected row in M ​​rows based on the first comparison result includes: determining that there is a selected row in M ​​rows when the first comparison result indicates that the operation address and the characteristic fault address meet a preset condition; determining that there is no selected row in M ​​rows when the first comparison result indicates that the operation address and the characteristic fault address do not meet the preset condition; wherein the preset condition includes that the operation address is within a limited range of the characteristic fault addresses of each row.

[0018] In some embodiments, after determining that there is no selected row in the M rows, the operation method further includes: executing the operation command according to the operation address.

[0019] In some embodiments, when it is determined that there is a selected row in M ​​rows, determining whether there is a selected address set in the selected row based on the operation address and the N address sets of the selected row includes: when it is determined that there is a selected row in M ​​rows, comparing the operation address and the N address sets of the selected row to obtain a second comparison result; and determining whether there is a selected address set in the selected row based on the second comparison result.

[0020] In some embodiments, determining whether the selected row has a selected address set based on the second comparison result includes: determining that the selected row has a selected address set when the second comparison result indicates that the operation address and a fault address in one address set of the selected row are the same; and determining that the selected row does not have a selected address set when the second comparison result indicates that the operation address and the fault addresses in N address sets of the selected row are different.

[0021] In some embodiments, the M rows*N columns address set is obtained after sorting the faulty addresses in the address set.

[0022] In a fourth aspect, an embodiment of the present disclosure provides an operating method of a memory system, the memory system comprising: a controller and a memory coupled to the controller; the operating method comprises: the operating method of the controller as described in the third aspect of the present disclosure.

[0023] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method of the memory system as described in the fourth aspect of the present disclosure can be implemented.

[0024] The embodiments of the present disclosure provide a controller and an operation method, a memory system and an operation method, and a readable medium. In the embodiments of the present disclosure, a storage structure stores M rows and N columns of address sets, and the address sets include fault addresses and corresponding redundant addresses; first, based on the operation address and the characteristic fault address of each row, it is determined whether there is a selected row in the M rows; if there is a selected row in the M rows, it is determined whether there is a selected address set in the selected row based on the operation address and the N address sets of the selected row; in this way, when it is determined that there is a selected address set in the selected row, the operation command can be executed based on the redundant addresses in the selected address set; so that the controller can efficiently perform redundancy repair and save the circuit area occupied by the storage redundant repair resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a controller provided in an embodiment of the present disclosure;

[0026] Figure 2 A schematic diagram of a set of M rows and N columns of addresses provided in an embodiment of the present disclosure;

[0027] Figure 3A An example is provided in which the minimum fault address of each row is determined as a characteristic fault address;

[0028] Figure 3B An example is provided in which the maximum fault address of each row is determined as a characteristic fault address;

[0029] Figure 4 An operation flow chart of a memory system provided by an embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of a memory system provided by an embodiment of the present disclosure;

[0031] Figure 6 A schematic diagram of an operating method of a memory system provided by an embodiment of the present disclosure;

[0032] Figure 7 A schematic diagram of a computer-readable storage medium provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0037] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0040] As mentioned above, the production process of semiconductor devices may go wrong, resulting in faulty units in semiconductor devices. The following will be explained by taking semiconductor devices including dynamic random access memory (DRAM) as an example. In order to improve the quality and manufacturing yield of DRAM, additional redundant units can be added in addition to the storage unit, and the redundant unit can be used to replace the faulty unit for repair during use. Correspondingly, it is also necessary to add DRAM redundancy repair logic in the DRAM controller (DRAM Memory Controller, DMC), respectively record the address of the faulty unit (also called "fault address") and the address of the corresponding redundant unit (also called "redundant address" or "mapping address"), and compare the operation address and the fault address of the operation command; if the operation address and the fault address are the same, then according to the redundant address corresponding to the fault address, that is, the redundant address is used to replace the operation address, and the operation command is executed; if the operation address and the fault address are different, then according to the operation address, the operation command is executed.

[0041] In some embodiments, the DRAM controller may include: a register for storing a fault address and a corresponding redundant address; a comparator connected to the register and the control unit, for comparing the operation address of the operation command sent by the control unit with the fault address stored in the register, and generating a comparison result; if the operation address and the fault address stored in the register are the same, it means that the operation address is stored in the register, and the redundant address can be used to replace the operation address to execute the operation command; if the operation address and the fault address stored in the register are different, it means that the operation address is not stored in the register, and the operation address can be used directly to execute the operation command.

[0042] Here, it is necessary to add additional redundant units outside the storage units of the DRAM, and correspondingly, add DRAM redundant repair logic in the DRAM controller.

[0043] It should be noted that in the above technical solution, redundant repair is performed in units of storage cells. In addition, redundant repair can also be performed in units of rows or columns. Exemplarily, additional redundant rows / redundant columns can be added outside the storage array, and redundant rows / redundant columns can be used to replace faulty rows / faulty columns for repair during use; wherein the faulty row / faulty column includes at least one faulty unit. In this way, additional redundant rows / redundant columns need to be added outside the DRAM storage array, and correspondingly, DRAM redundant repair logic is added to the DRAM controller.

[0044] In the above technical solution, registers can be used to store fault addresses and redundant addresses. As the storage capacity of DRAM increases, redundant resources also increase accordingly, and the occupied area of ​​registers used to store fault addresses and redundant addresses also increases accordingly, resulting in serious back-end expansion. Especially for the current three-dimensional DRAM (3D DRAM), after the storage capacity increases, the redundant resources will also increase significantly, and the mapping resources between the fault address and the redundant address will increase linearly, accounting for too high a proportion of the resources of the logic chip, resulting in the inability to implement redundant repair logic.

[0045] In view of this, embodiments of the present disclosure provide a controller and an operating method, a memory system and an operating method, and a readable medium.

[0046] refer to Figure 1 , Figure 1 Schematic diagram of a controller provided in an embodiment of the present disclosure. Figure 1 As shown, an embodiment of the present disclosure provides a controller, which includes: a storage structure 102, configured to: store M rows*N columns of address sets, the address sets including fault addresses and corresponding redundant addresses, and M and N are both positive integers; the controller 100 is configured to: determine whether there is a selected row in the M rows according to the operation address of the operation command and the characteristic fault address of each row; the characteristic fault address of each row is selected from N address sets of the same row; and when it is determined that there is a selected row in the M rows, determine whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row.

[0047] Here, the storage structure 102 may include a static random access memory (SRAM). The SRAM is used to store multiple address sets, each of which includes a fault address and a corresponding redundant address.

[0048] refer to Figure 2 , Figure 2 Schematic diagram of a set of M rows and N columns of addresses provided in an embodiment of the present disclosure. Figure 2As shown, multiple address sets are arranged in an array to form an address set array, the number of rows is M and the number of columns is N, and M and N are both positive integers. The address set can be denoted by G xy , where x is the row number of the address set in the address set array, and y is the column number of the address set in the address set array.

[0049] For example, G 11 Indicates that the address set is located in the first column of the first row in the address set array (ie, the row number is 1 and the column number is 1); G 1N Indicates that the address set is located in the Nth column of the 1st row in the address set array (i.e., the row number is 1 and the column number is N); G M1 Indicates that the address set is located in the first column of the Mth row in the address set array (i.e., the row number is M and the column number is 1); G MN It indicates that the address set is located in the Nth column of the Mth row in the address set array (ie, the row number is M and the column number is N).

[0050] Still refer to Figure 2 As shown, each address set includes a faulty address and a corresponding redundant address. The faulty address can be denoted as A xy , where x is the row number of the address set including the faulty address in the address set array, and y is the column number of the address set including the faulty address in the address set array; the redundant address can be recorded as R xy , wherein x is the row number of the address set including the redundant address in the address set array, and y is the column number of the address set including the redundant address in the address set array.

[0051] For example, A 11 Indicates the fault address in the address set located in the first column of the first row in the address set array; R 11 Represents the redundant address in the address set located at the 1st column of the 1st row in the address set array.

[0052] It should be noted that, for each address set, there is a mapping relationship between the faulty address and the redundant address, or the faulty address and the redundant address are in one-to-one correspondence. Here, the address set array includes the faulty address array and the corresponding redundant address array.

[0053] In some embodiments, the fault address may include the address of the faulty unit, and the redundant address may include the address of the redundant unit. In other embodiments, the fault address may include the address of the faulty row / faulty column, and the redundant address may include the address of the redundant row / redundant column; wherein the faulty row / faulty column includes at least one faulty unit. In other words, redundant repair may be performed in units of storage units, or in units of rows / columns. In other words, for each address set, the storage unit (or, redundant row / redundant column) indicated by the redundant address may be used to replace the storage unit (or, faulty row / faulty column) indicated by the faulty address.

[0054] In some embodiments, the M rows*N columns of address sets are obtained by sorting the faulty addresses in the address sets.

[0055] Here, the faulty addresses in each address set may be sorted to form multiple address sets arranged in M ​​rows*N columns. The present disclosure has no special limitation on the sorting rules of the faulty addresses in the M rows*N columns address sets.

[0056] Exemplarily, the fault addresses in the address set may be arranged in order from small to large to form an address set array of M rows and N columns. In this case, the address set including the smallest fault address is arranged in the first column of the first row in the address set array, and the address set including the largest fault address is arranged in the Nth column of the Mth row in the address set array. For example, 9 address sets are provided, and the fault addresses in the 9 address sets are arranged in order from small to large, namely the first address set, the second address set, the third address set, the fourth address set, the fifth address set, the sixth address set, the seventh address set, the eighth address set and the ninth address set; after the first row is fully arranged from left to right, the second row is arranged, and after the second row is fully arranged from left to right, the third row is arranged; the first, second and third address sets are arranged in order in the 1st, 2nd and 3rd columns of the 1st row of the address set array, the fourth, fifth and sixth address sets are arranged in order in the 1st, 2nd and 3rd columns of the 2nd row of the address set array, and the seventh, eighth and ninth address sets are arranged in order in the 1st, 2nd and 3rd columns of the 3rd row of the address set array.

[0057] Exemplarily, the fault addresses in the address set may be arranged in descending order to form an address set array of M rows and N columns. In this case, the address set including the largest fault address is arranged in the first column of the first row in the address set array, and the address set including the smallest fault address is arranged in the Nth column of the Mth row in the address set array. For example, 9 address sets are provided, and the fault addresses in the 9 address sets are arranged in descending order, namely the ninth address set, the eighth address set, the seventh address set, the sixth address set, the fifth address set, the fourth address set, the third address set, the second address set and the first address set; after the first row is fully arranged from left to right, the second row is arranged, and after the second row is fully arranged from left to right, the third row is arranged; the ninth, eighth and seventh address sets are arranged in sequence in the 1st, 2nd and 3rd columns of the 1st row of the address set array, the sixth, fifth and fourth address sets are arranged in sequence in the 1st, 2nd and 3rd columns of the 2nd row of the address set array, and the third, second and first address sets are arranged in sequence in the 1st, 2nd and 3rd columns of the 3rd row of the address set array.

[0058] In some embodiments, the characteristic failure address of each row is the maximum failure address or the minimum failure address in a set of N addresses of the same row.

[0059] Here, the characteristic fault address of each row can be used as a representative fault address among the N fault addresses in the N address set of each row, or one fault address in the N address set of each row can be used as the characteristic fault address corresponding to the row. By comparing the operation address with the fault address of each row, it can be determined whether the operation address belongs to the range of the N fault addresses of each row, and then it can be determined whether there is a selected row in the M rows.

[0060] Here, the number of characteristic fault addresses is the same as the number of rows, both of which are M. Figure 2 Characteristic fault address 1, characteristic fault address 2, ..., characteristic fault address M are indicated.

[0061] In some embodiments, the fault addresses in the address set are arranged in order from small to large to form M rows*N columns of address sets, and the characteristic fault address of each row is the minimum fault address in the N address sets of the same row. Figure 3A It shows that the fault addresses in the address set are arranged in order from small to large to form 3 rows*3 columns, a total of 9 address sets, and the characteristic fault address of each row is the smallest fault address in the 3 address sets in the same row. The characteristic fault address of the first row is the first address set G 11 The first fault address A in 11 (2), the characteristic fault address of the second row is the fourth address set G 21 The fourth fault address A in 21(9), the characteristic fault address of row 3 is the seventh address set G 31 The seventh fault address A in 31 (19). Thus, the characteristic fault address of the first row and the characteristic fault address of the second row jointly define the range of all fault addresses in the set of all addresses in the first row, that is, 2≤all fault addresses in the set of all addresses in the first row<9; the characteristic fault address of the second row and the characteristic fault address of the third row jointly define the range of all fault addresses in the set of all addresses in the second row, that is, 9≤all fault addresses in the set of all addresses in the second row<19; the characteristic fault address of the third row defines the range of all fault addresses in the set of all addresses in the third row≥19.

[0062] In some embodiments, the fault addresses in the address set are arranged in order from small to large to form M rows*N columns of address sets, and the characteristic fault address of each row is the largest fault address in the N address sets of the same row. Figure 3B It shows that the fault addresses in the address set are arranged in order from small to large to form 3 rows*3 columns, a total of 9 address sets, and the characteristic fault address of each row is the largest fault address in the 3 address sets in the same row. The characteristic fault address of the first row is the third address set G 13 The third fault address A in 13 (7), the characteristic fault address of the second row is the sixth address set G 23 The sixth fault address A in 23 (15), the characteristic fault address of row 3 is the ninth address set G 33 The ninth fault address A 33 (25). Thus, the characteristic fault address of the first row defines the range of all fault addresses in the set of all addresses in the first row, that is, all fault addresses in the set of all addresses in the first row ≤ 7; the characteristic fault address of the first row and the characteristic fault address of the second row together define the range of all fault addresses in the set of all addresses in the second row, that is, 7 < all fault addresses in the set of all addresses in the second row ≤ 15; the characteristic fault address of the second row and the characteristic fault address of the third row together define the range of all fault addresses in the set of all addresses in the third row, that is, 15 < all fault addresses in the set of all addresses in the third row ≤ 25.

[0063] Still refer to Figure 1 As shown, in some embodiments, the controller 100 includes: a first composite module 104 (such as Figure 1The control unit 108 is connected to the storage structure 102 and the control unit 108, and is configured to compare the operation address of the operation command sent by the control unit 108 with the characteristic fault address of each row to obtain a first comparison result; the control unit 108 is configured to determine whether there is a selected row in the M rows according to the first comparison result.

[0064] In some embodiments, the first composite module 104 includes: a first register unit 110, configured to store the characteristic fault address of each row; a first comparison unit 112, connected to the first register unit 110, configured to compare the operation address and the characteristic fault address of each row to obtain a first comparison result; a control unit 108, configured to determine that there is a selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address meet a preset condition; and determine that there is no selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address do not meet the preset condition; wherein the preset condition includes that the operation address is within a limited range of the characteristic fault addresses of each row.

[0065] Here, the operation address and the characteristic fault address of each row can be compared; if the operation address is within the limited range of the characteristic fault addresses of each row, it is determined that there is a selected row in the M rows; if the operation address is not within the limited range of the characteristic fault addresses of each row, it is determined that there is no selected row in the M rows. Further, in the case where it is determined that there is a selected row in the M rows, it is further determined whether there is a selected address set in the N address sets of the selected row; in the case where it is determined that there is no selected row in the M rows, the operation command is executed according to the operation address.

[0066] Here, the first register unit 110 may include a plurality of registers, each of which may be used to store one characteristic fault address. Therefore, if the number of rows of the address set array is M, then the number of registers used to store the characteristic fault addresses may be M.

[0067] Here, the first comparison unit 112 may include a plurality of comparators, one comparator may correspond to one register, each comparator compares the operation address with the characteristic fault address stored in the corresponding register, each comparator may generate a comparison result, and the comparison result may include the size relationship between the operation address and the characteristic fault address. Further, according to the comparison result, it may be determined whether there is a selected row in the M rows, and which row is the selected row.

[0068] In some embodiments, the fault addresses in the address set are arranged in order from small to large to form M rows * N columns of address sets, and the characteristic fault address of each row is the minimum fault address in the N address sets of the same row; the control unit 108 is configured as follows: if the operation address is less than the minimum characteristic fault address, it is determined that there is no selected row in the M rows; if the operation address is greater than or equal to the minimum characteristic fault address, it is determined that there is a selected row in the M rows.

[0069] In some embodiments, the control unit 108 is specifically configured as follows: if the operation address is ≥ the maximum characteristic fault address, the Mth row is determined as the selected row; if the minimum characteristic fault address is ≤ the operation address and < the maximum characteristic fault address, the row corresponding to the characteristic fault address that is smaller than the operation address and has the smallest difference with the operation address is determined as the selected row.

[0070] Here, the minimum characteristic failure address refers to the minimum value among all characteristic failure addresses, and the maximum characteristic failure address refers to the maximum value among all characteristic failure addresses.

[0071] Still refer to Figure 3A As shown, the operation address is 12, and the operation address is respectively 11 (2) Fourth fault address A 21 (9) Seventh fault address A 31 (19) Compare to determine whether there is a selected row. Considering that the minimum fault address of each row is determined as the characteristic fault address of the row, the first fault address A 11 (2) Fourth fault address A 21 (9) are all less than the operation address (12), the seventh fault address A 31 (19) is greater than the operation address (12), so it can be determined that there is a selected row, and the second row can be determined as the selected row.

[0072] In some embodiments, the fault addresses in the address set are arranged in order from small to large to form M rows * N columns of address sets, and the characteristic fault address of each row is the maximum fault address in the N address sets of the same row; the control unit 108 is configured as follows: if the operation address is greater than the maximum characteristic fault address, it is determined that there is no selected row in the M rows; if the operation address is less than or equal to the maximum characteristic fault address, it is determined that there is a selected row in the M rows.

[0073] In some embodiments, the control unit 108 is specifically configured as follows: if the operation address ≤ the minimum characteristic fault address, then the first row is determined as the selected row; if the minimum characteristic fault address < the operation address ≤ the maximum characteristic fault address, then the row corresponding to the characteristic fault address that is greater than the operation address and has the smallest difference with the operation address is determined as the selected row.

[0074] Still refer to Figure 3BAs shown, the operation address is 12, and the operation address is respectively 13 (7) Sixth fault address A 23 (15) Ninth fault address A 33 (25) is compared to determine whether there is a selected row. Considering that the maximum fault address of each row is determined as the characteristic fault address of each row, the third fault address A 13 (7) is less than the operation address (12), the sixth fault address A 23 (15) Ninth fault address A 33 (25) are all greater than the operation address (12), so it can be determined that there is a selected row, and it can be determined that the second row is determined as the selected row.

[0075] In some embodiments, the fault addresses in the address set are arranged in order from large to small to form M rows * N columns of address sets, and the characteristic fault address of each row is the minimum fault address in the N address sets of the same row; the control unit 108 is configured as follows: if the operation address is less than the minimum characteristic fault address, it is determined that there is no selected row in the M rows; if the operation address is greater than or equal to the minimum characteristic fault address, it is determined that there is a selected row in the M rows.

[0076] In some embodiments, the control unit 108 is specifically configured as follows: if the operation address is ≥ the maximum characteristic fault address, the first row is determined to be the selected row; if the minimum characteristic fault address is ≤ the operation address and < the maximum characteristic fault address, the row corresponding to the characteristic fault address that is smaller than the operation address and has the smallest difference with the operation address is determined to be the selected row.

[0077] In some embodiments, the fault addresses in the address set are arranged in order from large to small to form M rows * N columns of address sets, and the characteristic fault address of each row is the maximum fault address in the N address sets of the same row; the control unit 108 is configured as follows: if the operation address is greater than the maximum characteristic fault address, it is determined that there is no selected row in the M rows; if the operation address is less than or equal to the maximum characteristic fault address, it is determined that there is a selected row in the M rows.

[0078] In some embodiments, the control unit 108 is specifically configured as follows: if the operation address ≤ the minimum characteristic fault address, then the Mth row is determined as the selected row; if the minimum characteristic fault address < the operation address ≤ the maximum characteristic fault address, then the row corresponding to the characteristic fault address that is greater than the operation address and has the smallest difference with the operation address is determined as the selected row.

[0079] In some embodiments, the control unit 108 is further configured to: execute the operation command according to the operation address when it is determined that there is no selected row in the M rows.

[0080] Here, the absence of a selected row in the M rows indicates that the operation address does not belong to any faulty address in the entire address set arranged in an array. At this time, the operation command can be executed on the memory according to the original address of the operation command (ie, the operation address).

[0081] Still refer to Figure 1 As shown, in some embodiments, the controller 100 includes: a second composite module 106 (such as Figure 1 The storage structure 102 and the control unit 108 are connected and configured to: when it is determined that there is a selected row in the M rows, compare the operation address with the N address sets in the selected row to obtain a second comparison result; the control unit 108 is configured to: determine whether there is a selected address set in the selected row according to the second comparison result.

[0082] In some embodiments, the second composite module 106 includes: a second register unit 114, configured to store N address sets of the selected row; a second comparison unit 116, connected to the second register unit 114, configured to compare the operation address with the fault address in the N address sets of the selected row to obtain a second comparison result; a control unit 108, configured to determine that the selected row has the selected address set when the second comparison result indicates that the operation address and the fault address in 1 address set of the selected row are the same; and determine that the selected row does not have the selected address set when the second comparison result indicates that the operation address and the fault address in the N address sets of the selected row are different.

[0083] Here, the operation address and the fault address in the N address sets of the selected row can be compared; if there is a fault address in one address set among the N address sets of the selected row that is the same as the operation address, then it is determined that the N address sets of the selected row include the selected address set; if the fault addresses in the N address sets of the selected row are all different from the operation address, then it is determined that the N address sets of the selected row do not include the selected address set. Figure 2 It is illustrated that after the selected row is determined, an address set 1 of the selected row, an address set 2 of the selected row, ..., an address set N of the selected row are obtained.

[0084] Here, the second register unit 114 may include a plurality of registers, each of which may be used to store one address set. Therefore, if the number of columns of the address set array is N, then the number of registers used to store the address set of the selected row may be N.

[0085] Here, the second comparison unit 116 may include multiple comparators, one comparator may correspond to one register, each comparator compares the operation address with the fault address stored in the corresponding register, and each comparator may generate a comparison result, which may include whether the operation address is the same as the fault address of the selected row. Further, according to the comparison result, it may be determined whether the N address set rows of the selected row have a selected address set.

[0086] Still refer to Figure 3A As shown, the operation address is 10, and the operation address is respectively 11 (2) Fourth fault address A 21 (9) Seventh fault address A 31 (19) compares and determines that the second row is the selected row. The fourth address set, the fifth address set and the sixth address set of the second row are temporarily stored in the second register unit, and the operation address (10) and the fourth fault address A are respectively 21 (9) Fifth fault address A 22 (12) Sixth fault address A 23 (15) After comparison, the operation address (10) and the fault addresses in the three address sets of the selected row are all different. Therefore, it is determined that the selected row does not have a selected address set.

[0087] Still refer to Figure 3A As shown, the operation address is 12, and the operation address is respectively 11 (2) Fourth fault address A 21 (9) Seventh fault address A 31 (19) compares and determines that the second row is the selected row. The fourth address set, the fifth address set and the sixth address set of the second row are temporarily stored in the second register unit, and the operation address (12) and the fourth fault address A are respectively stored in the second register unit. 21 (9) Fifth fault address A 22 (12) Sixth fault address A 23 (15) Compare the operation address (12) and the fifth fault address A 22 (12) is the same, therefore, it is determined that the selected row has a selected address set, and further the fifth address set is determined to be the selected address set.

[0088] In some embodiments, the controller 100 (more specifically, the control unit 108) is also configured to: when it is determined that the selected row contains a selected address set, execute an operation command based on the redundant addresses in the selected address set; when it is determined that the selected row does not contain a selected address set, execute an operation command based on the operation address.

[0089] Here, the absence of the selected address set in the N address sets of the selected row indicates that the operation address does not belong to any faulty address in the N address sets of the selected row, that is, the operation command can be executed on the memory according to the original address of the operation command (ie, the operation address).

[0090] Here, the presence of a selected address set in the N address sets of the selected row indicates that the operation address is a faulty address, that is, the operation address needs to be repaired redundantly, and the operation command is executed on the memory according to the redundant address corresponding to the faulty address.

[0091] refer to Figure 4 , Figure 4 The operation flow chart of the memory system provided by the embodiment of the present disclosure is as follows. Figure 4 As shown, in step S401, M rows*N columns of address sets are provided, each address set includes a faulty address and a corresponding redundant address.

[0092] In step S402, the operation address and the characteristic fault address of each row are compared to obtain a first comparison result; if "yes", that is, the operation address and the characteristic fault address of each row meet the preset conditions, step S403 is executed to determine whether there is a selected row in the M rows; if "no", that is, the operation address and the characteristic fault address of each row do not meet the preset conditions, step S404 is executed to determine whether there is no selected row in the M rows.

[0093] When it is determined in step S404 that there is no selected row in the M rows, step S405 is executed to execute the operation command according to the operation address.

[0094] In the case where it is determined in step S403 that there is a selected row in the M rows, step S406 is executed to compare the operation address with the fault addresses in the N address sets of the selected row; if "yes", that is, the operation address and the fault address in one of the N address sets of the selected row are the same, step S407 is executed to determine that there is a selected address set in the selected row; if "no", that is, the operation address and the fault addresses in the N address sets of the selected row are different, step S408 is executed to determine that there is no selected address set in the selected row.

[0095] When it is determined in step S407 that the selected row contains a selected address set, step S409 is executed to execute the operation command according to the redundant addresses in the selected address set.

[0096] When it is determined in step S408 that the selected row does not contain the selected address set, step S410 is performed to execute the operation command according to the operation address.

[0097] In the related technical solution, the operation address and each fault address are compared to determine whether to perform redundant repair. If the number of fault addresses is M*N, then the number of registers used to store the operation address and the corresponding redundant address is M*N, and the number of comparisons required is M*N times. In the embodiment of the present disclosure, the operation address and the characteristic fault address of each row are first compared to determine whether there is a selected row in the M rows, and the number of comparisons is M times; in the case where there is a selected row in the M rows, the operation address and the N address sets of the selected row are compared to determine whether there is a selected address set in the N address sets of the selected row, and the number of comparisons is N times; that is, the number of registers used to store the characteristic fault address and the address set of the selected row is (M+N), and the number of comparisons is (M+N) times in total. In this way, redundant repair can be performed efficiently, saving the circuit area occupied by storing redundant repair resources.

[0098] In some embodiments, the operation command may include, but is not limited to, a read command or a write command.

[0099] refer to Figure 5 , Figure 5 Schematic diagram of a memory system provided by an embodiment of the present disclosure. Figure 5 As shown, the embodiment of the present disclosure provides a memory system 500, which includes: the controller 100 (such as Figure 5 The controller 100 includes a memory 502 and a dotted line box.

[0100] Here, the memory system 500 may include a controller 100 and one or more memories 502. The memory 502 may include, but is not limited to, NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, DRAM, Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM) and Nano Random Access Memory (NRAM), etc. In this article, only the memory 502 is DRAM as an example for illustration, which does not constitute a limitation on the protection scope of the present disclosure.

[0101] Exemplarily, the memory 502 may include a DRAM. In a DRAM, a memory array includes a plurality of memory cells arranged in an array, so that a selected memory cell can be addressed by its row address and column address. The DRAM may be a 1-transistor-1-capacitor (1T1C) architecture, where each memory cell includes a transistor and a capacitor, the gate of the transistor is connected to a word line, the drain of the transistor is connected to a bit line, and the source of the transistor is connected to the capacitor. The voltage signal on the word line can control the conduction or disconnection of the transistor, thereby reading the data stored in the capacitor through the bit line, or writing the data into the capacitor through the bit line for storage.

[0102] Here, when it is determined that there is no selected row in the M rows, and when it is determined that there is no selected address set in the selected row, the controller 100 executes an operation command on the memory 502 according to the operation address; when it is determined that there is a selected address set in the selected row, the controller 100 executes an operation command on the memory 502 according to the redundant address in the selected address set. Figure 5 It illustrates that when it is determined that the selected address set is included in the N address sets of the selected row, a fault flag and a redundant address corresponding to the fault address are returned.

[0103] refer to Figure 6 , Figure 6 A schematic diagram of an operating method of a memory system provided by an embodiment of the present disclosure.

[0104] like Figure 6 As shown, an embodiment of the present disclosure provides an operating method of a controller, and the operating method includes:

[0105] Step S601: providing an address set of M rows and N columns, the address set including a fault address and a corresponding redundant address, where M and N are both positive integers;

[0106] Step S602: determining whether there is a selected row in the M rows according to the operation address of the operation command and the characteristic fault address of each row; the characteristic fault address of each row is selected from the N address set of the same row;

[0107] Step S603: when it is determined that there is a selected row in the M rows, determine whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row.

[0108] In some embodiments, after step S603, the above operation method also includes: when it is determined that the selected row has a selected address set, executing the operation command according to the redundant addresses in the selected address set; when it is determined that the selected row does not have a selected address set, executing the operation command according to the operation address.

[0109] In some embodiments, step S602 includes: comparing the operation address with the characteristic fault address of each row to obtain a first comparison result; and determining whether there is a selected row in the M rows according to the first comparison result.

[0110] In some embodiments, determining whether there is a selected row in the M rows based on the first comparison result includes: determining that there is a selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address meet a preset condition; determining that there is no selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address do not meet the preset condition; wherein the preset condition includes that the operation address is within a limited range of the characteristic fault addresses of each row.

[0111] In some embodiments, after determining that there is no selected row in the M rows, the operation method further includes: executing an operation command according to the operation address.

[0112] In some embodiments, step S603 includes: when it is determined that there is a selected row in the M rows, comparing the operation address with the N address sets of the selected row to obtain a second comparison result; and determining whether there is a selected address set in the selected row based on the second comparison result.

[0113] In some embodiments, determining whether the selected row contains a selected address set is performed based on the second comparison result, including: determining that the selected row contains a selected address set when the second comparison result indicates that the operation address and a fault address in one address set of the selected row are the same; and determining that the selected row does not contain a selected address set when the second comparison result indicates that the operation address and the fault addresses in N address sets of the selected row are different.

[0114] In some embodiments, after sorting the faulty addresses in the address set, an address set of M rows and N columns is obtained.

[0115] An embodiment of the present disclosure provides an operating method of a memory system, the memory system comprising: a controller and a memory coupled to the controller; the operating method comprises: the operating method of the controller in the above technical solution.

[0116] refer to Figure 7 , Figure 7 Schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure. Figure 7 As shown, an embodiment of the present disclosure provides a computer-readable storage medium 700, which stores a computer program 702. When the computer program 702 is executed, the operating method of the memory system in the above technical solution can be implemented.

[0117] In the embodiment of the present disclosure, the computer-readable storage medium 700 may include: random access memory (Random Access Memory, RAM), internal memory, read-only memory (Read-Only Memory, ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, read-only compact disks (CD-ROMs), or any other form of program code medium known in the technical field.

[0118] In an embodiment of the present disclosure, an SRAM is established to store address sets, each address set includes a fault address and a redundant address, and is divided into M rows, each row includes N groups of address sets; wherein the fault addresses are processed according to a specific sorting order, for example, the fault addresses are arranged in order from small to large and stored in the SRAM.

[0119] A first register unit (e.g., a row address range register) and a first comparison unit (e.g., a comparator) are established. The row address range register is used to store the top address of each row (e.g., the maximum fault address or the minimum fault address), and the operation address of the operation command and the top address are compared to determine whether there is a selected row.

[0120] A second register unit (e.g., a fault address and redundant address register) and a second comparison unit (e.g., a comparator) are established. The fault address and redundant address register are used to store the N address sets of the selected row read from the SRAM, and the operation address of the operation command is compared with the fault address in the N address sets of the selected row to determine whether there is a selected address set. If there is a selected address, the operation command can be executed according to the redundant address corresponding to the fault address; if there is no selected row and no selected address, the operation command can be executed according to the operation address.

[0121] In the disclosed embodiment, a specific sorting process is used to store the address set in SRAM; a small number of registers are reserved externally, and the redundant address corresponding to the fault address that is the same as the operation address is read based on the sorting search address space, which can save 50-80% of the circuit area. In 3D DRAM, SRAM can be read in advance, that is, SRAM can be read immediately after obtaining the operation address of the operation command, in parallel with the existing instructions, hiding the latency.

[0122] The embodiments of the present disclosure provide a controller and an operation method, a memory system and an operation method, and a readable medium. In the embodiments of the present disclosure, a storage structure stores M rows and N columns of address sets, and the address sets include fault addresses and corresponding redundant addresses; first, based on the operation address and the characteristic fault address of each row, it is determined whether there is a selected row in the M rows; if there is a selected row in the M rows, it is determined whether there is a selected address set in the selected row based on the operation address and the N address sets of the selected row; in this way, when it is determined that there is a selected address in the selected row, the operation command can be executed based on the redundant addresses in the selected address set; so that the controller can efficiently perform redundancy repair and save the circuit area occupied by the storage redundant repair resources.

[0123] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0124] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A controller, characterized in that: The controller comprises: A storage structure is configured to: store M rows*N columns of address sets, wherein the address sets include a fault address and a corresponding redundant address, and M and N are both positive integers; The controller is configured to: determine whether there is a selected row in the M rows according to the operation address of the operation command and the characteristic fault address of each row; the characteristic fault address of each row is selected from the N address sets of the same row; and When it is determined that there is a selected row in the M rows, it is determined whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row.

2. The controller according to claim 1, characterized in that: The controller is further configured to: when it is determined that the selected row has a selected address set, execute the operation command according to redundant addresses in the selected address set; When it is determined that the selected row does not have a selected address set, the operation command is executed according to the operation address.

3. The controller according to claim 1, characterized in that: The controller comprises: A first composite module is connected to the storage structure and the control unit and is configured to: compare the operation address of the operation command sent by the control unit with the characteristic fault address of each row to obtain a first comparison result; The control unit is configured to determine whether there is a selected row in the M rows according to the first comparison result.

4. The controller according to claim 3, characterized in that: The first composite module comprises: The first register unit is configured to: store a characteristic fault address of each row; A first comparison unit, connected to the first register unit, is configured to: compare the operation address with the characteristic fault address of each row to obtain a first comparison result; The control unit is configured to: determine that there is a selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address meet a preset condition; determine that there is no selected row in the M rows when the first comparison result indicates that the operation address and the characteristic fault address do not meet the preset condition; wherein the preset condition includes that the operation address is within a limited range of the characteristic fault addresses of each row.

5. The controller according to claim 4, characterized in that: The control unit is further configured to: when it is determined that there is no selected row in the M rows, execute the operation command according to the operation address.

6. The controller according to claim 1, characterized in that: The controller comprises: A second composite module is connected to the storage structure and the control unit, and is configured to: when it is determined that there is a selected row in the M rows, compare the operation address with the N address sets in the selected row to obtain a second comparison result; The control unit is configured to determine whether the selected row contains a selected address set according to the second comparison result.

7. The controller according to claim 6, characterized in that: The second composite module comprises: A second register unit is configured to: store the N address sets of the selected row; A second comparison unit connected to the second register unit and configured to: compare the operation address with the fault address in the N address set of the selected row to obtain a second comparison result; The control unit is configured to: determine that there is a selected address set in the selected row when the second comparison result indicates that the operation address and a fault address in one address set of the selected row are the same; and determine that there is no selected address set in the selected row when the second comparison result indicates that the operation address and the fault addresses in N address sets of the selected row are different.

8. The controller according to claim 1, characterized in that: The M rows*N columns address sets are obtained by sorting the fault addresses in the address set.

9. A memory system, characterized in that: The memory system comprises: a controller according to any one of claims 1 to 8 and a memory coupled to the controller.

10. A method for operating a controller, characterized in that: The operation method comprises: Provide M rows*N columns of address sets, the address sets include fault addresses and corresponding redundant addresses, and M and N are both positive integers; Determine whether there is a selected row in the M rows according to the operation address of the operation command and the characteristic fault address of each row; the characteristic fault address of each row is selected from the N address set of the same row; When it is determined that there is a selected row in the M rows, it is determined whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row.

11. The operating method according to claim 10, characterized in that: In the case where it is determined that there is a selected row in the M rows, after determining whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row, the operation method further includes: In the case of determining that the selected row has a selected address set, executing the operation command according to redundant addresses in the selected address set; When it is determined that the selected row does not have a selected address set, the operation command is executed according to the operation address.

12. The operating method according to claim 10, characterized in that: The step of determining whether there is a selected row in the M rows according to the operation address of the operation command and the characteristic fault address of each row includes: Comparing the operation address with the characteristic fault address of each row to obtain a first comparison result; According to the first comparison result, it is determined whether there is a selected row in the M rows.

13. The operating method according to claim 12, characterized in that: The determining, according to the first comparison result, whether there is a selected row in the M rows includes: When the first comparison result indicates that the operation address and the characteristic fault address meet a preset condition, determining that there is a selected row in the M rows; When the first comparison result indicates that the operation address and the characteristic fault address do not satisfy the preset condition, it is determined that there is no selected row in the M rows; wherein the preset condition includes that the operation address is within a limited range of characteristic fault addresses of each row.

14. The operating method according to claim 13, characterized in that: After determining that there is no selected row in the M rows, the operation method further includes: The operation command is executed according to the operation address.

15. The operating method according to claim 10, characterized in that: In the case where it is determined that there is a selected row in the M rows, determining whether there is a selected address set in the selected row according to the operation address and the N address sets of the selected row includes: When it is determined that there is a selected row in the M rows, comparing the operation address with the N address sets of the selected row to obtain a second comparison result; According to the second comparison result, it is determined whether the selected row contains a selected address set.

16. The operating method according to claim 15, characterized in that: The determining, according to the second comparison result, whether the selected row has a selected address set includes: If the second comparison result indicates that the operation address is the same as a fault address in one address set of the selected row, determining that the selected row has a selected address set; When the second comparison result indicates that the operation address and the failure addresses in the N address sets of the selected row are all different, it is determined that the selected row does not have a selected address set.

17. The operating method according to claim 10, characterized in that: The M rows*N columns address set is obtained after sorting the fault addresses in the address set.

18. A method for operating a memory system, characterized in that: The memory system comprises: a controller and a memory coupled to the controller; the operating method comprises: an operating method of the controller according to any one of claims 10 to 17.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method of the memory system according to claim 18 can be implemented.

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