Vertical conductive semiconductor device and preparation method thereof

Abstract

The invention provides a vertical conductive type semiconductor device and a preparation method thereof. An annular closed groove is formed in an edge region of a terminal region in a front process; in the scribing process, the acting force between the scribing grinding wheel and the inorganic passivation layer at the scribing channel can be transmitted to the annular closed groove firstly and then can be transmitted to the interior of the terminal area in the process of transmitting the acting force to the terminal area, and due to the fact that the annular closed groove is in the closed groove shape, the direction and the path of the transmitted acting force can be changed and lengthened. Therefore, the transmitted acting force is effectively weakened or even blocked, that is, the transmitted acting force is effectively blocked by the annular closed groove, the adhesion between the inorganic passivation layer on the terminal region and the internal region thereof and the front metal layer and the dielectric layer on the front structure is effectively ensured, the reliability of the vertical conductive semiconductor device is improved, and the reliability of the vertical conductive semiconductor device is improved. And the preparation method is high in practicability, easy to prepare and low in cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a vertical conductive semiconductor device and a preparation method thereof. Background Art

[0002] Semiconductor power devices are basic electronic components for energy control and conversion in power electronics systems. For example, they are widely used in fields such as motor drive in power systems and frequency conversion in consumer electronics. The continuous development of power electronics technology has opened up a wide range of application fields for semiconductor power devices. Vertical conductive semiconductor power devices represented by IGBT and VDMOS are the mainstream devices in the field of power electronics today. IGBT and VDMOS are currently formed by planar gate or trench gate processes, especially the trench gate primitive cell structure is widely used.

[0003] The preparation process of IGBT devices and VDMOS devices includes front-side process and back-side process. Generally, the front-side process is completed before the back-side process. In order to improve the reliability of the device, a laminated passivation layer structure of an inorganic passivation layer and a polyimide passivation layer needs to be formed on the surface of the front structure of the device. Usually, the polyimide passivation layer is retained at the scribe line to improve the flatness of the front of the device and the quality of the blue film attached to the front of the device during the subsequent back-side process to prevent the chemical reagent from penetrating from the edge of the wafer along the scribe line to the internal area of ​​the wafer during cleaning or corrosion with the blue film, affecting the adhesion of the passivation layer. In order to save device tape-out costs, the inorganic passivation layer and the polyimide passivation layer are often etched through a mask plate. The polyimide passivation layer is first etched with the help of a photoresist, and then the polyimide passivation layer is used as an etching mask layer for the inorganic passivation layer. Therefore, the inorganic passivation layer at the scribe line on the wafer will also be retained. During subsequent scribes, the force between the scribe wheel and the inorganic passivation layer at the scribe line will be transmitted through the passivation layer to the inorganic passivation layer in the terminal area of ​​the device chip, which can easily affect the adhesion of the inorganic passivation layer to the front metal and dielectric layers, and ultimately lead to reduced device reliability. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a vertical conductive semiconductor device and a method for preparing the same, so as to solve the problem that when a stacked passivation layer structure of an inorganic passivation layer and a polyimide passivation layer is provided on the front side and the scribing path of the vertical conductive semiconductor device in the prior art, during scribing, the force between the scribing grinding wheel and the inorganic passivation layer at the scribing path will be transmitted through the passivation layer to the inorganic passivation layer at the terminal area of ​​the device chip, which is likely to affect the adhesion of the inorganic passivation layer to the front metal and dielectric layers, ultimately leading to reduced device reliability.

[0005] To achieve the above object and other related objects, the present invention provides a method for preparing a vertical conductive semiconductor device, the method comprising the following steps:

[0006] Providing a substrate having opposite front and back surfaces, the substrate comprising an active region, a transition region and a terminal region nested in sequence;

[0007] A front process of a vertical conductive semiconductor device is performed on the front of the active area, the transition area and the terminal area to form a front structure of the vertical conductive semiconductor device; wherein the front process includes: forming an annular closed groove in the edge area of ​​the terminal area; sequentially forming an inorganic passivation layer and a polyimide passivation layer on the front of the substrate, and the inorganic passivation layer and the polyimide passivation layer fill the annular closed groove; patterning the inorganic passivation layer and the polyimide passivation layer to form a pad window of the front structure;

[0008] thinning the back side of the substrate;

[0009] A backside process of the vertical conductive semiconductor device is performed on the backside of the substrate to form a backside structure of the vertical conductive semiconductor device.

[0010] Optionally, the annular closed groove has a width of 3 μm to 10 μm and a depth of 0.6 μm to 2 μm.

[0011] Optionally, the cross-sectional shape of the annular closed groove is the same as the cross-sectional shape of the terminal region.

[0012] Furthermore, the width of the annular closed groove is 3 μm to 10 μm, the depth is 0.6 μm to 2 μm, and the distance between the annular closed groove and the edge of the terminal region is 0 μm to 20 μm.

[0013] Optionally, the substrate is a silicon substrate, and the inorganic passivation layer is a single-layer structure of a Si3N4 passivation layer or a single-layer structure of a SRN passivation layer or a stacked structure of a Si3N4 passivation layer and a SRN passivation layer.

[0014] Optionally, the vertical conductive semiconductor device is an IGBT or a VDMOS.

[0015] Furthermore, the gate structure of the front structure of the vertical conductive semiconductor device is a trench gate or a planar gate.

[0016] Furthermore, the vertical conductive semiconductor device is an IGBT, the gate structure of the front structure of the vertical conductive semiconductor device is a trench gate, and the front process includes the following steps:

[0017] Forming a lateral variable doping region in the front side of the transition region and the terminal region by ion implantation and annealing activation;

[0018] forming a field oxide layer on the front side of the terminal region;

[0019] Forming a plurality of trench gates arranged at intervals in the front surface of the active area and a portion of the transition area, wherein the top of the trench gate has a gate groove;

[0020] Forming a carrier storage region in the front surface of the active region and part of the transition region, a body region in the front surface of the active region and the transition region, and an emitter region in the front surface of the active region in sequence through ion implantation and annealing activation;

[0021] forming a thermal oxide layer on the bottom and sidewall surfaces of all the gate grooves;

[0022] forming a dielectric layer on the front surface of the substrate, wherein the dielectric layer completely fills the gate groove;

[0023] Forming a first patterned photoresist layer on the surface of the dielectric layer, wherein the first patterned photoresist layer exposes the area where the active area is located and the area where the annular closed groove is located;

[0024] Based on the first patterned photoresist layer, etching is performed to remove the material layer on the area where the active area is exposed and the area where the annular closed groove is exposed until the corresponding front surface of the substrate is exposed;

[0025] Etching the exposed front surface of the substrate based on the first patterned photoresist layer to form an active area contact hole and the annular closed groove, and then removing the first patterned photoresist layer, wherein the active area contact hole is formed by etching the exposed front surface of the substrate based on the patterned photoresist layer using a self-aligned etching process;

[0026] forming a front metal layer on the front side of the substrate;

[0027] forming the inorganic passivation layer and the polyimide passivation layer in sequence on the front surface of the substrate;

[0028] The polyimide passivation layer is photolithographically etched to expose the area where the pad window is located, and the inorganic passivation layer is etched using the polyimide passivation layer as a mask to expose the pad window.

[0029] Furthermore, the method for forming the trench gate includes:

[0030] forming a plurality of grooves arranged at intervals in the front surface of the active area and a portion of the transition area;

[0031] Forming a gate insulating layer and a gate conductive layer in sequence on the front side of the substrate, wherein the gate conductive layer fills the groove; etching the gate conductive layer and the gate insulating layer of a preset thickness on the front side of the substrate except for a partial area of ​​the terminal area close to the transition area, and etching a portion of the gate insulating layer and the gate conductive layer in the groove, thereby retaining a partial thickness of the gate insulating layer on the front side of the substrate and forming the gate groove;

[0032] After forming the dielectric layer, the method further includes: forming a second patterned photoresist layer on the surface of the dielectric layer; etching the second patterned photoresist layer to form a required circuit lead-out hole; and removing the second patterned photoresist layer.

[0033] The present invention also provides a vertical conductive semiconductor device, which is prepared by using any of the above methods for preparing a vertical conductive semiconductor device.

[0034] As described above, the vertical conductive semiconductor device and preparation method of the present invention form an annular closed groove in the edge area of ​​the terminal area during the front process. During the scribing process, the force between the scribing wheel and the inorganic passivation layer at the scribing path is first transmitted to the annular closed groove before continuing to be transmitted toward the inside of the terminal area. Since the annular closed groove is in the shape of a closed groove, the direction and path of the transmitted force will be changed and lengthened, thereby effectively weakening or even blocking the transmitted force, that is, the transmitted force is effectively blocked by the annular closed groove, effectively ensuring the adhesion between the inorganic passivation layer on the terminal area and its internal area and the front metal layer and dielectric layer on the front structure, thereby improving the reliability of the vertical conductive semiconductor device. In addition, the preparation method is highly practical, easy to prepare and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a schematic cross-sectional structure diagram of a vertical conductive semiconductor device according to an example of the present invention.

[0036] Figures 2 to 4 The schematic diagrams of the top views of three examples of the positional relationship among the active region, transition region, terminal region and annular closed trench in the vertical conductive semiconductor device of the present invention are shown.

[0037] Figures 5 to 23 It is a schematic diagram of the cross-sectional structure of each step in the method for preparing a vertical conductive semiconductor device of the present invention, wherein the vertical conductive semiconductor device is an IGBT and the gate structure is a trench gate.

[0038] Component number description

[0039] 10 Substrate

[0040] 100 Active Area

[0041] 101 Transition Zone

[0042] 102 Terminal Area

[0043] 103 Annular closed groove

[0044] 104 Front

[0045] 105 Back

[0046] 11 Front structure

[0047] 110 Lateral variable doping region

[0048] 111 Cut-off ring

[0049] 112 Field Oxide Layer

[0050] 113 Trench Gate

[0051] 114 gate insulating layer

[0052] 115 gate conductive layer

[0053] 116 Groove

[0054] 117 Gate groove

[0055] 118 Carrier storage area

[0056] 119 Body Area

[0057] 120 emitter region

[0058] 121 Thermal Oxide Layer

[0059] 122 Dielectric layer

[0060] 123 Second patterned photoresist layer

[0061] 124 Circuit lead hole

[0062] 125 First patterned photoresist layer

[0063] 126 Active area contact hole

[0064] 127 front metal layer

[0065] 128 Inorganic passivation layer

[0066] 129 Polyimide passivation layer

[0067] 130 Pad Window

[0068] 12 Back structure

[0069] 131 Buffer layer

[0070] 132 Collector region

[0071] 133 Collector metal layer DETAILED DESCRIPTION

[0072] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure may not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0074] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0075] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0076] See also Figures 1 to 23 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0077] Embodiment 1

[0078] like Figures 1 to 4 As shown, this embodiment provides a method for preparing a vertical conductive semiconductor device, and the preparation method comprises the following steps:

[0079] Providing a substrate having opposite front and back surfaces, wherein the substrate comprises an active region 100, a transition region 101 and a terminal region 102 which are nested in sequence;

[0080] A front process of a vertical conductive semiconductor device is performed on the front of the active area 100, the transition area 101 and the terminal area 102 to form a front structure 11 of the vertical conductive semiconductor device; wherein the front process includes: forming an annular closed groove 103 in the edge area of ​​the terminal area 102; sequentially forming an inorganic passivation layer 128 and a polyimide passivation layer 129 on the front of the substrate, and the inorganic passivation layer 128 and the polyimide passivation layer 129 fill the annular closed groove 103; patterning the inorganic passivation layer 128 and the polyimide passivation layer 129 to form a pad window 130 of the front structure;

[0081] thinning the back side of the substrate;

[0082] A backside process of the vertical conductive semiconductor device is performed on the backside of the substrate to form a backside structure 12 of the vertical conductive semiconductor device.

[0083] The preparation method of the vertical conductive semiconductor device of the present embodiment is mainly aimed at the vertical conductive semiconductor device which needs to perform front process and back process. After the front process is completed and before the back process is performed, the front structure formed by the front process needs to be protected by a protective layer such as a blue film, and in order to ensure the flatness of the protective layer on the entire wafer surface, the inorganic passivation layer and the polyimide passivation layer formed on the front structure need to be retained on the scribing path. Based on the background technology, due to the inorganic passivation layer and the polyimide passivation layer retained on the scribing path, when the subsequent scribing process is performed, the force between the scribing wheel and the inorganic passivation layer at the scribing path will be transmitted through the passivation layer to the inorganic passivation layer at the terminal area of ​​the device chip, thereby affecting the adhesion of the inorganic passivation layer to the front metal layer and the dielectric layer on the front structure, resulting in reduced device reliability. The preparation method of the present embodiment forms an annular closed groove in the edge area of ​​the terminal area during the front process. During the scribing process, the force between the scribing wheel and the inorganic passivation layer at the scribing path is first transmitted to the annular closed groove before continuing to be transmitted toward the inside of the terminal area. Since the annular closed groove is in the shape of a closed groove, the direction and path of the transmitted force will be changed and lengthened, thereby effectively weakening or even blocking the transmitted force, that is, the transmitted force is effectively blocked by the annular closed groove, effectively ensuring the adhesion between the inorganic passivation layer on the terminal area and its internal area and the front metal layer and the dielectric layer on the front structure, thereby improving the reliability of the vertical conductive semiconductor device. In addition, the preparation method is highly practical, easy to prepare and low in cost.

[0084] Since the main function of the annular closed groove 103 is to isolate the force between the scribing grinding wheel and the inorganic passivation layer 128 at the scribing path from being transmitted to the terminal area 102, the most basic requirement of the annular closed groove 103 is to be in a closed ring shape to seal and protect its internal area. Considering that the annular closed groove 103 is still formed on the terminal area 102, in order to ensure that the function of the terminal area 102 is not affected, the size of the annular closed groove 103 also needs to be set within a reasonable range. In this embodiment, the width of the annular closed groove 103 is preferably 3μm to 10μm and the depth is 0.6μm to 2μm. In addition, it should be noted that the width and depth of the annular closed groove 103 on its extension path can be the same or different, as long as the width is 3μm to 10μm and the depth is 0.6μm to 2μm, it will not have a significant impact on the function of the terminal area 102. In this embodiment, the width and depth of the annular closed groove 103 are preferably the same on its extension path, which is convenient for process preparation.

[0085] In addition, by setting the cross-sectional shape of the annular closed groove 103 to be the same as the cross-sectional shape of the terminal area 102, the area of ​​the terminal area 102 inside the annular closed groove 103 can be effectively increased. Figures 2 to 4 The cross-sectional shape of the annular closed groove 103 and the cross-sectional shape of the terminal area 102 are both rectangular. Furthermore, in order to ensure the area of ​​the terminal area 102 inside the annular closed groove 103, the spacing L between the annular closed groove 103 and the edge of the terminal area 102 can be selected in the range of 0 μm to 20 μm, including the end value. Figure 2 and Figure 3 As shown, Figure 2 The distance L between the annular closed groove 103 and the edge of the terminal area 102 is Figure 3 The distance L between the annular closed groove 103 and the edge of the terminal area 102 is relatively large. Figure 4 The annular closed groove 103 is arranged at the edge of the terminal area 102 .

[0086] In this embodiment, the cross-sectional shape of the annular closed groove 103 is preferably the same as that of the terminal area 102, and the width of the annular closed groove 103 is 3μm to 10μm, the depth is 0.6μm to 2μm, and the spacing L between the annular closed groove 103 and the edge of the terminal area 102 is 0μm to 20μm.

[0087] As an example, the material of the substrate can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon, germanium, red phosphorus, silicon germanium, silicon carbide, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or other III / V compound semiconductors, and can also include a multilayer structure formed by these semiconductors, or silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator and germanium on insulator, or it can also be a double-sided polished silicon wafer, or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and the specific selection is based on actual needs.

[0088] As an example, the inorganic passivation layer 128 is a single-layer structure of a Si3N4 passivation layer or a single-layer structure of a SRN passivation layer (silicon-rich silicon nitride passivation layer) or a stacked structure of a Si3N4 passivation layer and a SRN passivation layer.

[0089] The preparation method of the vertical conductive semiconductor device of the present embodiment is mainly aimed at the vertical conductive semiconductor device that needs to be processed on the front side and the back side, and is therefore suitable for high-voltage power semiconductor devices, such as IGBT, VDMOS, etc. When the vertical conductive semiconductor device is an IGBT or a VDMOS, the gate structure of its front structure can be a trench gate or a planar gate. The trench gate can be a conventional trench gate, which includes a gate insulating layer formed on the inner side wall and the bottom of the gate trench and a gate conductive layer formed on the gate insulating layer; the trench gate can also be a trench shielding gate (abbreviated as SGT), which includes a gate insulating layer formed on the inner side wall and the bottom of the gate trench and a control gate conductive layer and a shielding gate conductive layer formed on the gate insulating layer, and the control gate conductive layer and the shielding gate conductive layer are isolated by a dielectric isolation layer.

[0090] Embodiment 2

[0091] This embodiment describes in detail the method for preparing a vertical conductive semiconductor device by taking the vertical conductive semiconductor device as an IGBT and the gate structure of the front structure of the vertical conductive semiconductor device as a trench gate as an example.

[0092] like Figure 2 and Figure 5 As shown, step S1 is first performed to provide a substrate 10 having a front side 104 and a back side 105 opposite to each other, wherein the substrate 10 comprises an active region 100, a transition region 101 and a terminal region 102 nested in sequence. Subsequent front processes are performed based on the front side 104, and back processes are performed based on the back side 105.

[0093] In this embodiment, the substrate 10 is selected to be an N-type single crystal silicon substrate. In some embodiments, the substrate 10 may also be made of other materials, such as but not limited to silicon germanium or germanium. In other embodiments, the substrate 10 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide. The doping concentration and thickness of the substrate 10 may be set according to the withstand voltage performance of the IGBT device.

[0094] like Figure 6 As shown, step S2 is then performed to form a lateral variable doping region 110 in the front surface of the transition region 101 and the terminal region 102 through ion implantation and annealing activation.

[0095] As an example, the process parameters of the ion implantation and annealing activation process for forming the lateral variable doping region 110 are: P-type boron ion implantation, the implantation dose is 1e12cm -2 ~5e13cm -2 , the injection energy is 60keV~200keV, the annealing activation push temperature is 1050℃~1250℃, and the push time is 30min~300min. The formed lateral variable doping region 110 is a JTE terminal or a VLD terminal. Furthermore, while forming the lateral variable doping region 110, a cut-off ring 111 can be formed at the edge of the terminal region 102 by ion implantation and annealing activation. The process parameters of the ion implantation and annealing activation process for forming the cut-off ring 111 are: N-type phosphorus ion implantation, the implantation dose is 1e15cm -2 ~1e16cm -2 The implantation energy is 60keV to 200keV, the annealing activation push temperature is 1050°C to 1250°C, and the push time is 30min to 300min. It should be noted that the annealing activation process of the cutoff ring 111 and the annealing activation process of the lateral variable doping region 110 can be performed independently or simultaneously.

[0096] like Figure 7 As shown, step S3 is then performed to form a field oxide layer 112 on the front surface of the terminal region 102 .

[0097] As an example, the method for forming the field oxide layer 112 includes: using a thermal oxidation process, such as a wet oxidation process or a dry oxidation process, to form the field oxide layer 112 on the front side of the substrate 10; and then using a photolithography process to photoetch the field oxide layer 112, and only retaining the field oxide layer 112 on the front side of the terminal region 102. It should be noted here that when the terminal region 102 is formed with the above-mentioned stop ring 111, the subsequent annular closed groove 103 is formed in the stop ring 111, and at this time, the field oxide layer 112 on the stop ring 111 in the area where the annular closed groove 103 is located needs to be etched and removed.

[0098] like Fig.10 As shown, step S4 is then performed to form a plurality of trench gates 113 arranged at intervals in the front surface of the active region 100 and a portion of the transition region 101 , wherein the top of the trench gate 113 has a gate groove 117 .

[0099] like Figures 8 to 10 As shown, as a specific example, the method for forming the trench gate 113 includes the following steps:

[0100] like Figure 8 As shown, step S41 is first performed to form a plurality of spaced trenches 116 in the front surface of the active area 100 and a portion of the transition area 101. For example, the spaced trenches 116 may be formed by photolithography and etching processes.

[0101] like Fig. 9 and Fig.10 As shown, step S41 is then performed to sequentially form a gate insulating layer 114 and a gate conductive layer 115 on the front surface of the substrate 10, wherein the gate conductive layer 115 fills the trench 116 (eg, Fig. 9 As shown), the gate insulating layer 114 may be made of silicon oxide material, and the gate conductive layer 116 may be made of polysilicon material; the gate conductive layer 115 and the gate insulating layer 114 of a preset thickness are etched on the front side of the substrate 10 except for a portion of the terminal region 102 near the transition region 101, and a portion of the gate insulating layer 114 and the gate conductive layer 115 in the groove are etched at the same time, thereby retaining the gate insulating layer 114 of a portion of the thickness on the front side of the substrate (the thickness of the retained gate insulating layer 114 is selected according to actual needs), and forming the gate groove 117. In a specific example, the depth of the gate groove 117 is 0.3μm to 0.7μm. After step S41, the trench gate 113 is formed in the active area 100 and part of the transition area 101, which is formed by the gate insulating layer 114 and the gate conductive layer 115 thereon. At the same time, a gate bus region is formed in a part of the terminal area 102 close to the transition area 101. Subsequently, the circuit lead-out of the trench gate 113 can be realized by forming an electrical lead-out structure in the gate bus region.

[0102] like Fig.11 As shown, step S5 is then performed to form a carrier storage region 118 in the front surface of the active region 100 and part of the transition region 101, a body region 119 in the front surface of the active region 100 and the transition region 101, and an emitter region 120 in the front surface of the active region 100 through ion implantation and annealing activation.

[0103] As a specific example, the process parameters of the ion implantation and annealing activation process for forming the carrier storage area 118 are: N-type phosphorus ion implantation is performed through a mask, and the implantation dose is 1e12 cm -2 ~5e13cm -2 The injection energy is 1MeV~2MeV, the annealing activation push temperature is 1050℃~1250℃, and the push time is 30min~300min.

[0104] As a specific example, the process parameters of the ion implantation and annealing activation process for forming the body region 119 are: P-type boron ion implantation is performed by general implantation (without mask), and the implantation dose is 2e13 cm -2 ~1.5e14cm -2 The injection energy is 60keV~200keV, the annealing activation push temperature is 1050℃~1250℃, and the push time is 30min~120min.

[0105] As a specific example, the process parameters of the ion implantation and annealing activation process for forming the emitter region 120 are: N-type arsenic ion implantation is performed through a mask, and the implantation dose is 8e15cm -2 ~2e16cm -2 The implantation energy is 60keV~200keV, the annealing activation temperature is 900℃~1000℃, and the implantation time is 30min~120min.

[0106] It should be noted here that when designing semiconductor devices, in order to improve the robustness of the semiconductor device structure when it is turned off, the trench of the trench gate 113 located in the transition zone 101 is usually designed not to be used, so the emitter region 120 is only formed around the trench gate 113 in the active area 100, and the emitter region 120 is not formed around the trench gate 113 in the transition zone 101.

[0107] like Fig.12 As shown, step S6 is then performed to form a thermal oxide layer 121 on the bottom and sidewall surfaces of all the gate grooves 117 .

[0108] As an example, the thermal oxide layer 121 may be grown by a furnace tube, and the thickness of the thermal oxide layer 121 is

[0109]

[0110] like Fig.13 As shown, step S7 is then performed to form a dielectric layer 122 on the front surface of the substrate 10 , and the dielectric layer 122 completely fills the gate groove 117 .

[0111] As an example, the dielectric layer 122 may include a borophosphosilicate glass (BPSG) layer. When the dielectric layer 122 includes the BPSG layer, the thickness of the BPSG layer is selected to be Furthermore, after the BPSG layer is formed, a BPSG reflow process may be used to further process the BPSG layer, wherein the reflow temperature is selected to be 900° C. to 1000° C., and the reflow time is selected to be 30 min to 240 min.

[0112] like Fig.14 and Fig.15 As shown, as an example, after forming the dielectric layer 122, the step of forming the required circuit lead-out hole 124 is also included, specifically including: Fig.14 As shown, a photoresist layer is first formed on the surface of the dielectric layer 122 and patterned to obtain a second patterned photoresist layer 123, wherein the second patterned photoresist layer 123 exposes the surface area of ​​the dielectric layer 122 where the circuit lead-out hole 124 is to be formed; Fig.15 As shown, the required circuit lead-out hole 124 is then formed by etching based on the second patterned photoresist layer 123. For example, the gate insulating layer 114 and the dielectric layer 122 on the surface of the cut-off ring 111 at the edge of the transition region 101 and the terminal region are etched based on the second patterned photoresist layer 123 to expose the substrate surface, and the dielectric layer 122 in the gate bus region on the terminal region 102 is etched to expose the gate conductive layer 115 underneath; finally, the second patterned photoresist layer 123 is removed.

[0113] like Fig.16 As shown, step S8 is then performed to form a first patterned photoresist layer 125 on the surface of the dielectric layer 122 , wherein the first patterned photoresist layer 125 exposes the area where the active region 100 and the area where the annular closed trench 103 are located.

[0114] like Fig.17 As shown, step S9 is then performed, in which the material layer in the area where the exposed active area 100 and the area where the annular closed groove 103 are located is removed by etching based on the first patterned photoresist layer 125 until the corresponding front surface of the substrate is exposed. For example, the dielectric layer 122 and the gate insulating layer 114 of the active area are removed by etching based on the first patterned photoresist layer 125 until the front surface of the substrate is exposed, and the dielectric layer 122 and the gate insulating layer 114 of the terminal area 102 are removed by etching at the same time until the front surface of the substrate is exposed.

[0115] like Fig.18As shown, step S10 is then performed, in which the active area contact hole 126 and the annular closed groove 103 are formed by etching the exposed front surface of the substrate based on the first patterned photoresist layer 125, and then the first patterned photoresist layer 125 is removed, wherein the active area contact 126 is formed by etching the exposed front surface of the substrate based on the patterned photoresist layer 125 using a self-aligned etching process.

[0116] It can be seen from the above steps that the first patterned photoresist layer 125 exposes the entire surface of the active area 100. In addition, the surface of the active area 100 is formed by the thermal oxide layer 121, the dielectric layer 122 and the emitter area 120 outside the groove 116 formed in the groove 116. The material in the groove 116 is different from the substrate material outside the groove 116. The different etching rates of the thermal oxide layer 121, the dielectric layer 122 and the emitter area 120 during the etching process can be utilized, and a self-aligned etching process can be used for etching to achieve accurate etching of the active area contact hole 126 required for the process without the need for a mask, thereby reducing the process complexity and improving the alignment accuracy. Taking the case where the thermal oxide layer 121 is made of silicon oxide, the dielectric layer 122 is made of BPSG, and the emitter region 120 is made of silicon as an example, during the self-aligned etching process, an etching material that can etch away silicon very quickly but can etch away silicon oxide very slowly or almost not at all can be selected to directly etch the active region 100 based on the exposed opening of the first patterned photoresist layer 125, thereby obtaining the active region contact hole 126. The self-aligned etching process can select any suitable etching process, such as dry etching or wet etching, and dry etching is more and preferably selected.

[0117] As a preferred example, when etching to form the active area contact hole 126 and the annular closed groove 103, an etching angle of 75° to 85° (the angle with the horizontal plane is defined as the etching angle) is adopted to form a trapezoidal hole and a trapezoidal groove which are larger at the top and smaller at the bottom; wherein, the aperture of the active area contact hole 126 is selected to be 0.2μm to 0.6μm and the depth is 0.6μm to 1.0μm, the width of the annular closed groove 103 is selected to be 3μm to 10μm and the depth is selected to be 0.6μm to 2μm, and the depth of the active area contact hole 126 and the annular closed groove 103 can be achieved by adjusting the etching menu and adjusting the etching load effect.

[0118] like Fig.19 As shown, step S11 is then performed to form a front metal layer 127 on the front surface of the substrate.

[0119] As an example, the front metal layer 127 generally includes a filling metal layer filling the active area contact hole 126 and the circuit lead-out hole 124 and a lead-out metal layer connected to the filling metal layer. The specific preparation process includes: first, a material layer of the filling metal layer is deposited on the front side of the obtained structure, such as a stacked material layer of titanium / titanium nitride / tungsten; then, the material layer of the filling metal layer is generally etched to obtain a material layer of the filling metal layer that is only filled in the active area contact hole 126 and the circuit lead-out hole 124, thereby forming the filling metal layer, and during the general etching process, the material layer of the filling metal layer in the annular closed groove 103 is also etched cleanly; then, a material layer of the lead-out metal layer is deposited on the front side of the obtained structure, such as an aluminum-copper material layer; finally, the material layer of the lead-out metal layer is photoetched to obtain the desired lead-out metal layer.

[0120] like Fig. 20 and Fig.21 As shown, step S12 is then performed to sequentially form the inorganic passivation layer 128 and the polyimide passivation layer 129 on the front surface of the substrate.

[0121] As an example, the inorganic passivation layer 128 is a single-layer structure of a Si3N4 passivation layer or a single-layer structure of a SRN passivation layer (silicon-rich silicon nitride passivation layer) or a stacked structure of a Si3N4 passivation layer and a SRN passivation layer. When the inorganic passivation layer 128 is a single-layer structure of a Si3N4 passivation layer, the thickness is selected to be When the inorganic passivation layer 128 is a single-layer structure of a SRN passivation layer, the thickness is selected to be

[0122] As an example, the thickness of the polyimide passivation layer 129 is selected to be 6 μm to 20 μm.

[0123] like Fig. 22 As shown, step S13 is then performed to photolithographically etch the polyimide passivation layer 129 to expose the area where the pad window 130 is located, and to etch the inorganic passivation layer 128 using the polyimide passivation layer 129 as a mask to expose the pad window 130 .

[0124] After step S13, the front process of the IGBT device is basically completed, and the back process is subsequently performed. Generally, a blue film is attached to the front structure obtained after the front process is completed before the back process is performed.

[0125] Next, the back side process of the IGBT device is performed, the front side structure with the blue film is turned over to perform step S14, the back side of the substrate is thinned, and the thinning thickness depends on the withstand voltage requirement of the IGBT device.

[0126] like Fig.23As shown, step S15 is finally performed to form a buffer layer 131 , a P-type collector region 132 and a collector metal layer 133 on the lower surface of the substrate 10 .

[0127] As an example, the process of forming the buffer layer 131 and the collector region 132 includes: firstly, implanting P-type ions, such as boron ions, into the lower surface of the substrate 10, with an ion implantation energy of 20KeV to 60KeV and an ion implantation dose of 1e12cm -2 ~1e14cm -2 , and use laser annealing equipment to propel the injected P-type ions to form the collector region 132 ; then hydrogen ions are implanted into the lower surface of the substrate 10 and annealed to form the buffer layer 131 .

[0128] As an example, the collector metal layer 133 may be a single conductive material layer or a stacked structure of multiple conductive material layers. For example, the collector metal layer 133 may be a stacked structure of aluminum layer-titanium layer-nickel layer-silver layer from top to bottom.

[0129] Embodiment 3

[0130] This embodiment provides a vertical conductive semiconductor device, which can be prepared by the method for preparing the vertical conductive semiconductor device described in Embodiment 1 and Embodiment 2. The beneficial effects that can be achieved can be found in Embodiment 1 and Embodiment 2, and will not be described in detail below.

[0131] In summary, the present invention provides a vertical conductive semiconductor device and a preparation method thereof. In the front process, an annular closed groove is formed in the edge area of ​​the terminal area. During the scribing process, the force between the scribing wheel and the inorganic passivation layer at the scribing path will be first transmitted to the annular closed groove before continuing to be transmitted toward the inside of the terminal area. Since the annular closed groove is in the shape of a closed groove, the direction and path of the transmitted force will be changed and lengthened, thereby effectively weakening or even blocking the transmitted force, that is, the transmitted force is effectively blocked by the annular closed groove, effectively ensuring the adhesion of the inorganic passivation layer on the terminal area and its internal area with the front metal layer and dielectric layer on the front structure, thereby improving the reliability of the vertical conductive semiconductor device. The preparation method is highly practical, easy to prepare and low in cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0132] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a vertical conductive semiconductor device, characterized in that: The preparation method comprises the following steps: Providing a substrate having opposite front and back surfaces, the substrate comprising an active region, a transition region and a terminal region nested in sequence; A front process of a vertical conductive semiconductor device is performed on the front of the active area, the transition area and the terminal area to form a front structure of the vertical conductive semiconductor device; wherein the front process includes: forming an annular closed groove in the edge area of ​​the terminal area; sequentially forming an inorganic passivation layer and a polyimide passivation layer on the front of the substrate, and the inorganic passivation layer and the polyimide passivation layer fill the annular closed groove; patterning the inorganic passivation layer and the polyimide passivation layer to form a pad window of the front structure; thinning the back side of the substrate; A backside process of the vertical conductive semiconductor device is performed on the backside of the substrate to form a backside structure of the vertical conductive semiconductor device.

2. The method for preparing a vertical conductive semiconductor device according to claim 1, characterized in that: The annular closed groove has a width of 3 μm to 10 μm and a depth of 0.6 μm to 2 μm.

3. The method for preparing a vertical conductive semiconductor device according to claim 1, characterized in that: The cross-sectional shape of the annular closed groove is the same as the cross-sectional shape of the terminal area.

4. The method for preparing a vertical conductive semiconductor device according to claim 3, characterized in that: The width of the annular closed groove is 3 μm to 10 μm, the depth is 0.6 μm to 2 μm, and the distance between the annular closed groove and the edge of the terminal area is 0 μm to 20 μm.

5. The method for preparing a vertical conductive semiconductor device according to claim 1, characterized in that: The substrate is a silicon substrate, and the inorganic passivation layer is a single-layer structure of a Si3N4 passivation layer or a single-layer structure of a SRN passivation layer or a stacked structure of a Si3N4 passivation layer and a SRN passivation layer.

6. The method for preparing a vertical conductive semiconductor device according to claim 1, characterized in that: The vertical conductive semiconductor device is an IGBT or a VDMOS.

7. The method for preparing a vertical conductive semiconductor device according to claim 6, characterized in that: The gate structure of the front structure of the vertical conductive semiconductor device is a trench gate or a planar gate.

8. The method for preparing a vertical conductive semiconductor device according to claim 7, characterized in that: The vertical conductive semiconductor device is an IGBT, the gate structure of the front structure of the vertical conductive semiconductor device is a trench gate, and the front process includes the following steps: Forming a lateral variable doping region in the front side of the transition region and the terminal region by ion implantation and annealing activation; forming a field oxide layer on the front side of the terminal region; Forming a plurality of trench gates arranged at intervals in the front surface of the active area and a portion of the transition area, wherein the top of the trench gate has a gate groove; Forming a carrier storage region in the front surface of the active region and part of the transition region, a body region in the front surface of the active region and the transition region, and an emitter region in the front surface of the active region in sequence through ion implantation and annealing activation; forming a thermal oxide layer on the bottom and sidewall surfaces of all the gate grooves; forming a dielectric layer on the front surface of the substrate, wherein the dielectric layer completely fills the gate groove; Forming a first patterned photoresist layer on the surface of the dielectric layer, wherein the first patterned photoresist layer exposes the area where the active region is located and the area where the annular closed groove is located; Based on the first patterned photoresist layer, etching is performed to remove the material layer on the area where the active area is exposed and the area where the annular closed groove is exposed until the corresponding front surface of the substrate is exposed; Etching the exposed front surface of the substrate based on the first patterned photoresist layer to form an active area contact hole and the annular closed groove, and then removing the first patterned photoresist layer, wherein the active area contact hole is formed by etching the exposed front surface of the substrate based on the patterned photoresist layer using a self-aligned etching process; forming a front metal layer on the front side of the substrate; forming the inorganic passivation layer and the polyimide passivation layer in sequence on the front surface of the substrate; The polyimide passivation layer is photolithographically etched to expose the area where the pad window is located, and the inorganic passivation layer is etched using the polyimide passivation layer as a mask to expose the pad window.

9. The method for preparing a vertical conductive semiconductor device according to claim 8, characterized in that: The method of forming the trench gate includes: forming a plurality of grooves arranged at intervals in the front surface of the active area and a portion of the transition area; Forming a gate insulating layer and a gate conductive layer in sequence on the front side of the substrate, wherein the gate conductive layer fills the groove; etching the gate conductive layer and the gate insulating layer of a preset thickness on the front side of the substrate except for a partial area of ​​the terminal area close to the transition area, and etching a portion of the gate insulating layer and the gate conductive layer in the groove, thereby retaining a partial thickness of the gate insulating layer on the front side of the substrate and forming the gate groove; After forming the dielectric layer, the method further includes: forming a second patterned photoresist layer on the surface of the dielectric layer; etching the second patterned photoresist layer to form a required circuit lead-out hole; and removing the second patterned photoresist layer.

10. A vertical conductive semiconductor device, characterized in that: The vertical conductive semiconductor device is prepared by the method for preparing the vertical conductive semiconductor device as claimed in any one of claims 1 to 9.

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