Substrate process flow for implementing substrate-to-die hybrid bonding

Abstract

The invention relates to a substrate process flow for implementing substrate-to-die hybrid bonding. Various disclosed embodiments relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrates, semiconductor dies, and / or interconnects. The present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of which bonds two or more components to each other.

Description

Technical Field

[0001] Embodiments described herein generally relate to electrical interconnects and interconnect methods. Specific examples include electrical interconnects between a substrate and a semiconductor die. Background Art

[0002] For various semiconductor package designs, pitch bump scaling may be used to help reduce the overall package size. Electrical connections and methods that address these concerns and other technical challenges are desirable. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The accompanying drawings are not necessarily drawn to scale. In the accompanying drawings, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. Figure 1 The various embodiments discussed in this document are presented generally by way of example and not by way of limitation.

[0004] Figure 1 A cross-sectional view of a semiconductor package assembly having a hybrid bonded substrate in an example is shown.

[0005] Figures 2A to 2G A method of hybrid joining in an example is shown.

[0006] Figures 3A to 3H A method of hybrid joining in an example is shown.

[0007] Figures 4A to 4F A method of bonding a semiconductor package substrate to a semiconductor die in an example is shown.

[0008] Figure 5 A system-level diagram depicting an example of an electronic device in an example is shown. DETAILED DESCRIPTION

[0009] The following description and accompanying drawings sufficiently illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process and other changes. Portions and features of some embodiments may be included in or may replace those of other embodiments. The embodiments set forth in the claims encompass all available equivalents of those claims.

[0010] A method of forming a substrate-to-silicon die electrical connection using a hybrid bonding technique is discussed herein. Hybrid bonding combines an embedded metal, such as copper (Cu), with a dielectric bond, such as silicon oxide (SiOx), to form a permanent bond. Hybrid bonding enables increased power, greater bandwidth, and signal integrity.

[0011] Such hybrid bonding techniques and methods may be used to electrically connect semiconductor dies such as silicon integrated circuits (ICs) while maintaining scaled down interconnect dimensions, such as solder bump interconnects with a pitch less than 40 microns.

[0012] Advanced and complex packaging requires interconnection to electrically couple components such as semiconductor die, substrate and other components. As package size decreases and the complexity of various IC packages increases, it has become necessary to develop different types of interconnections. Such interconnections should maintain signal integrity while processing larger amounts of data. However, as devices shrink and more components are added to semiconductor packages to store, move and process data, additional inputs and outputs (I / O) are desired. For this reason, connections such as solder balls and microbumps should be appropriately scaled down to provide a desired number of interconnections while maintaining signal integrity.

[0013] In particular, microbumps can provide vertical interconnections such as between chips or between a tube core and a package component (such as a substrate). For example, microbumps can include small copper bumps on a tube core. The size range of such bumps can be reduced from 40 micron spacing to 20 microns or 10 micron spacing. In particular, for multi-chip monolithic packaging architectures, bridge interconnects benefit from the bump spacing being scaled down, such as a bump spacing less than 40 microns. However, when the shortened assembly process window is timed, such smaller bump spacing may pose a challenge to the reliability of solder joints. One way to address this challenge is a top tube core priority process, but this is not a monolithic method; on the contrary, it is a process flow based on a carrier, in which a small chip is reorganized on a carrier in a face-up configuration, and a bridge is attached to an exposed pad. However, in applications where the top tube core small chip is more expensive, this top tube core priority process is not desirable.

[0014] A method for connecting a substrate to a silicon die using hybrid bonding is discussed herein. These methods for forming interconnections with smaller bump spacings may include forming interconnections between a substrate and a silicon die using a hybrid bonding process. Two methods are discussed, including a monolithic method and a carrier-based or coreless method. These methods allow for efficient and effective use of smaller bump spacings (e.g., less than 40 microns) while maintaining solder joint integrity. In addition, these methods may allow for good electrical connections.

[0015] Figure 1 A cross-sectional view of a semiconductor package component interconnect 100 using hybrid bonding in an example is shown. Hybrid bonding includes both dielectric material and embedded metal to form an interconnect. The embedded metal contains recesses to allow the hybrid bond to form because heat forces the metal together during bonding (because it expands more than oxide), causing it to bond. Figure 1, the interconnect 100 may have a die pad side 110 and a substrate side 120 with a via 130 extending therebetween. On the substrate side 120 there may be a substrate 122 and a substrate side copper pad 124. On the die side 110 there may be a die side copper pad 112. The via 130 extends between the die pad side 110 and the substrate side 120. The hybrid joint may include a solder mask 134, the via 130, and a thin film dielectric layer 116. The interconnect 100 may be, for example, a first level interconnect (FLI).

[0016] The via 130 can be made of a metal (e.g., copper or nickel) and a dielectric material to fasten the semiconductor die on the die side 110 to the substrate 122 on the substrate side 120. The use of a metal or metal-containing material in combination with a surrounding dielectric material allows for a beneficial hybrid bond. Here, the via 130 relies on a direct copper-to-copper bond surrounded by a dielectric material. For example, the copper pads 112, 124 and the via 130 can form such a copper-to-copper bond. When the semiconductor die is attached to the interconnect 100, the die is bonded to the dielectric material (e.g., the thin film dielectric layer 116). During the generation process, when the temperature rises and the copper pads 112, 124 and the via 130 begin to expand toward each other, a hybrid bond is formed. When the copper pads 112, 124 contact the via 130, a bond is formed therebetween, thereby forming a metal-metal bond. The embedded metal-containing pads allow for such a hybrid bond.

[0017] In this example, the die-side copper pads 112, substrate-side copper pads 124, and vias 130 may be made of copper metal. In other examples, the pads and bonds may be made of another metal suitable for metal-to-metal bonding in a hybrid bonding scheme.

[0018] Solder resist layer 134 may be located on substrate 122 and at least partially encapsulate substrate side copper pad 124. Solder resist layer 134 may be an organic dielectric material. In some cases, layer 134 may be epoxy-based. Substrate 122 may be a standard semiconductor package substrate, such as a printed circuit board or other suitable substrate material.

[0019] Thin film dielectric layer 116 may be a material that allows hybrid bonding, such as a silicon-based film. Examples may include a silicon-based dielectric, or a combination of silicon-based films that may include carbon, silicon carbon nitride, or oxynitride. In some cases, this may be an organic material. Such hybrid bonding in interconnect 100 includes a metal-on-metal (e.g., Cu-Cu) direct bond surrounded by a dielectric-to-dielectric bond formed by a thin film (such as a SiOx, SiNx, or SiCxNy film).

[0020] Figures 2A to 2G and Figures 3A to 3H Two different process flow diagrams for producing hybrid bonding in such substrate-to-die interconnects are depicted. Figures 2A to 2G The method depicted in is a monolithic approach, while Figures 3A to 3H The method described in is a coreless method. Both methods can be utilized to generate a hybrid bond of substrate to die type, such as the one described above in Figure 1 The example joint shown in .

[0021] Figures 2A to 2G A method 200 of generating an interconnect 205 for hybrid bonding in an example is shown. For example, the method 200 can be used with a monolithic substrate that may include complex bridges or interconnects embedded in various semiconductor substrate layers. Here, using a copper pad that is slightly recessed relative to the surrounding thin film material can be used to create a hybrid bond.

[0022] The substrate 210 may be a monolithic substrate, i.e., the substrate 210 may be built on or embedded with other layers, such as metal and organic dielectric layers. For example, a bridge interconnect or other multilayer structure may be incorporated into the substrate 210. A substrate core may be included in such a monolithic substrate. Here, a hybrid bond may be built on the first layer interconnect (FLI) side of the substrate 210.

[0023] First, in Figure 2A In the embodiment, a first copper pad 212 is deposited on a substrate 210. In an example, the substrate 210 itself may be an epoxy resin or an organic-based dielectric material. Figure 2B In the embodiment, a solder resist layer 214 is applied over a first copper pad 212 on a substrate 210. The solder resist layer 214 may be, for example, an organic dielectric layer. Figure 2C , a thin film layer 216 is deposited on top of dielectric layer 214. Here, thin film layer 216 (which is a thin film dielectric) is deposited on an organic dielectric. In an example, the thin film can be silicon nitride or silicon oxide, which can act as a bonding layer. The thin film layer is deposited on the final surface insulator layer (e.g., solder resist material). In some cases, multiple layers can be deposited. Such layers can be deposited, for example, by selective deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, or other suitable deposition techniques.

[0024] exist Figure 2D In the embodiment, a cavity 218 is laser drilled through the film layer 216 and the solder mask layer 214. The cavity 218 can be, for example, a laser via, which is drilled to create an opening for electrical connection. In an example, a single damascene process, via filling and planarization can be used to create a recess for filling with copper. During this step, the recess depth can be controlled to provide a hybrid bonding field.

[0025] exist Figure 2E In the embodiment, a sputtering seed layer 222 may be deposited on the cavity 218. In an example, electrolytic copper plating may be used to fill the cavity 218. This may be done by a sputtering technique. Figure 2F In the embodiment, copper bonding 224 may be deposited into cavity 218, such as by non-patterned plating. The surface of cavity 218 may also be covered with a copper layer. Figure 2G In the process, the copper bond 224 can be planarized. Copper chemical mechanical polishing (Cu CMP) can be used to ensure that there is an amount of recess in the copper so that the copper bond 224 is not flush with the top of the interconnect 205.

[0026] The recess in copper bond 224 can allow copper bond 224 and thin film layer 216 to hybrid bond with the semiconductor die. When interconnect 205 is used to form a hybrid bond (such as with a semiconductor die), thin film layer 216 is first bonded to the semiconductor die at the copper pad. When heated, copper bond 224 and the corresponding copper pad on the semiconductor die form a copper-copper bond. This can occur because the copper material expands vertically when heated and enters the gap between the two, allowing a copper-copper joint to be formed. The depth of the gap allows this to occur and form such a hybrid bond, where both copper and thin film layers form a bond with the corresponding semiconductor die.

[0027] Figures 3A to 3H A method of hybrid bonding in an example is shown. Here, a carrier or coreless process is shown, using the initial carrier flatness to control the copper recess depth used in creating the hybrid bond. In this example method, (one or more) seed layers, adhesion layers, or barrier layers can be used to control the final copper recess depth. Such layers can be made of etch selective materials to allow removal at the end of the process.

[0028] First, in Figure 3A In the embodiment of the present invention, a carrier 310 is used together with an etching material 312. A first copper pad 314 is deposited on the etching material 312. The etching material 312 can be, for example, a seed layer, an adhesion layer, or a barrier layer that is selectively removable relative to copper. For example, the material can be a titanium sputtered layer. This layer will be removed at the end of the process and can therefore be composed of an element that has a high etching selectivity to copper and dielectrics. The use of such a layer can help control the recess depth of the copper.

[0029] then, Figure 3B As shown in FIG. 1 , the first copper pad 314 and the etching material 312 are etched to a desired size and shape. Subsequently, Figure 3C 3, a thin film layer 316 is deposited on the first copper pad 314. The thin film layer 316 may be a dielectric deposition, such as a nitride or oxide layer.

[0030] exist Figure 3D , a solder resist material 318 is deposited over the thin film layer 316. A recess 320 for a copper via 322 may be made in the solder resist material 318 (see Figure 3E). This recess 320 may be filled with copper to create a copper via 322. A second copper pad 324 (shown in FIG. 1 ) may then be deposited on the surface of the copper via 322. Figure 3F ). In the example, Figures 3A to 3F The method can be repeated multiple times to build multiple layers. Once the desired number of layers has been built, it can be separated from the carrier 310.

[0031] Here, another solder mask or dielectric layer 326 may be deposited over the second copper pad 324. The assembly may then be flipped over as needed (see Figure 3G ), and the etching material 312 layer can be removed ( Figure 3H ). Once the etching material 312 is removed, the recess 330 above the first copper pad 314 can be utilized to allow for hybrid bonding. The creation of the recess 330 can be controlled using the initial carrier 310 flatness. The amount and type of etching material 312 can be tailored to create a desired depth of the recess 330 above the first copper pad 314. The fabricated assembly having the copper pad 314, the recess 330, and the surrounding thin film layer 316 can be used to form a hybrid bond (such as with a semiconductor die).

[0032] Figures 4A to 4F The method of hybrid bonding a semiconductor package substrate and a semiconductor die is shown in an example. Figures 4A to 4F In the method, you can use the reference Figures 1 to 3H Example hybrid bonding structures are shown and discussed to attach one or more semiconductor dies to a substrate or other interconnect. Figures 4A to 4F The use of a coreless approach (such as reference Figures 3A to 3H The method discussed herein is an example process of attaching a bridge interconnect 450 and two semiconductor dies 452, 454 to an assembly.

[0033] Figure 4A As shown in FIG. 4 , a carrier 410 having an etched material 412 may be used. Here, a copper via 420 has been formed on the carrier 410 between the solder resist material 418 and the thin film layer 416. The copper via 420 and the surrounding materials and layers may be as described above with reference to FIG. Figures 3A to 3H Established as discussed.

[0034] exist Figure 4B 4, a bridge interconnect die 450 is attached to a copper via 420 on a first side 422. The bridge interconnect 450 may be attached using a copper pad 424 on the first side 422. For example, the bridge interconnect 450 may be an interconnect, an intervening layer, or other bridge component, such as a silicon-based bridge with wiring therein to allow electrical connection between different components. The bridge interconnect 450 may include multiple wirings and vias as desired. In an example, a solder attachment may be made between the copper pad on the bridge interconnect 450 and the copper pad 424.

[0035] exist Figure 4C In the embodiment, the bridge interconnect 450 may be encapsulated, for example, using a molding material. Figure 4D In the embodiment of the present invention, additional layers may be built on the bridge interconnect 450. For example, an additional dielectric material layer 456 may be deposited, and additional openings 458 for vias (such as copper vias) may be made. Additional vias, pads, and layers may be built as needed.

[0036] exist Figure 4E , preparation for hybrid bonding may be performed prior to attaching dies 452, 454. Here, carrier 410 may be removed to expose thin film layer 416 and etch material 412. Once exposed, etch material 412 may be removed to provide recess 430 in copper via 420 to allow hybrid bonding.

[0037] exist Figure 4F 4, two dies 452, 454 may be attached to the copper via 420 by hybrid bonding. The dies 452, 454 may first be bonded to the thin film layer 416 and then bonded to the copper from the copper via 420. The copper may expand vertically when heated to fill the recess 430 and create a bond between the metal-containing pads on the dies 452, 454 and the copper via 420.

[0038] Figure 5 A system-level diagram is shown that depicts an example of an electronic device (e.g., system) that may include the above-described hybrid interface components and / or methods. In one embodiment, system 500 includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular phone, a mobile computing device, a smart phone, an Internet appliance, or any other type of computing device. In some embodiments, system 500 includes a system-on-chip (SOC) system.

[0039] In one embodiment, processor 510 has one or more processor cores 512 and 512N, where 512N represents the Nth processor core within processor 510, where N is a positive integer. In one embodiment, system 500 includes multiple processors including 510 and 505, where processor 505 has logic similar to or the same as that of processor 510. In some embodiments, processing core 512 includes, but is not limited to, pre-fetch logic for fetching instructions, decoding logic for decoding instructions, execution logic for executing instructions, and the like. In some embodiments, processor 510 has a cache memory 516 for caching instructions and / or data for system 500. Cache memory 516 can be organized into a hierarchical structure including one or more levels of cache memory.

[0040] In some embodiments, the processor 510 includes a memory controller 514 that is operable to perform functions that enable the processor 510 to access and communicate with a memory 530 including a volatile memory 532 and / or a non-volatile memory 534. In some embodiments, the processor 510 is coupled to the memory 530 and the chipset 520. The processor 510 may also be coupled to a wireless antenna 578 to communicate with any device configured to transmit and / or receive wireless signals. In one embodiment, the interface for the wireless antenna 578 operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related series, Home Plug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0041] In some embodiments, the volatile memory 532 includes, but is not limited to, synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), RAMBUS dynamic random access memory (RDRAM), and / or any other type of random access memory device. The non-volatile memory 534 includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

[0042] Memory 530 stores information and instructions to be executed by processor 510. In one embodiment, memory 530 may also store temporary variables or other intermediate information while processor 510 executes instructions. In the illustrated embodiment, chipset 520 is connected to processor 510 via point-to-point (PtP or PP) interfaces 517 and 522. Chipset 520 enables processor 510 to connect to other elements in system 500. In some embodiments of the example system, interfaces 517 and 522 are configured in accordance with, for example, The embodiment of the present invention may be operated with a PtP communication protocol such as QuickPath Interconnect (QPI), etc. In other embodiments, a different interconnect may be used.

[0043] In some embodiments, the chipset 520 is operable to communicate with the processors 510, 505, the display device 540, and other devices, including a bus bridge 572, a smart TV 576, an I / O device 574, a non-volatile memory 560, a storage medium (such as one or more mass storage devices) 562, a keyboard / mouse 564, a network interface 566, and various forms of consumer electronics 577 (such as PDAs, smart phones, tablets, etc.), etc. In one embodiment, the chipset 520 is coupled to these devices through an interface 524. The chipset 520 can also be coupled to a wireless antenna 578 to communicate with any device configured to transmit and / or receive wireless signals. In one example, as described in the present disclosure, any combination of components in the chipset can be separated by a continuous flexible shield.

[0044] Chipset 520 is connected to display device 540 via interface 526. Display 540 may be, for example, a liquid crystal display (LCD), a light emitting diode (LED) array, an organic light emitting diode (OLED) array, or any other form of visual display device. In some embodiments of the example system, processor 510 and chipset 520 are incorporated into a single SOC. In addition, chipset 520 is connected to one or more buses 550 and 555, which interconnect various system elements, such as I / O devices 574, non-volatile memory 560, storage media 562, keyboard / mouse 564, and network interface 566. Buses 550 and 555 may be interconnected together via bus bridge 572.

[0045] In one embodiment, the mass storage device 562 includes, but is not limited to, a solid state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, the network interface 566 is implemented by any type of well-known network interface standard, including but not limited to an Ethernet interface, a universal serial bus (USB) interface, a peripheral component interconnect (PCI) express interface, a wireless interface, and / or any other suitable type of interface. In one embodiment, the wireless interface operates according to, but is not limited to, the IEEE 802.11 standard and its related series, Home Plug AV (HPAV), Ultra Wideband (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

[0046] Although it will Figure 5 The modules shown in FIG. 5 are depicted as separate blocks within system 500, but the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory 516 is depicted as a separate block within processor 510, cache memory 516 (or selected aspects of 516) may be incorporated into processor core 512. Various notes and examples

[0047] To better illustrate the methods and apparatus disclosed herein, a non-limiting list of examples is provided here:

[0048] Example 1 is a semiconductor component, comprising: a component; a semiconductor die having a semiconductor die pad; and a hybrid bond connecting the semiconductor die to a substrate, wherein the hybrid bond comprises: a via; a first metal-containing pad at a first end of the via, the first metal-containing pad bonded to the semiconductor die pad; a dielectric layer surrounding the first metal-containing pad, the dielectric layer bonded to the semiconductor die around the semiconductor die pad; and a second metal-containing pad at a second end of the via, the second metal-containing pad bonded to the component.

[0049] In Example 2, the subject matter of Example 1 can optionally include: a dielectric material surrounding the via.

[0050] In Example 3, the subject matter of any one or more of Examples 1-2 may optionally include wherein the via, the first metal-containing pad, and the second metal-containing pad comprise copper.

[0051] In Example 4, the subject matter of any one or more of Examples 1-3 can optionally include wherein the dielectric layer comprises silicon nitride or silicon oxide.

[0052] In Example 5, the subject matter of any one or more of Examples 1-4 may optionally include wherein the component includes a substrate.

[0053] In Example 6, the subject matter of any one or more of Examples 1-5 may optionally include wherein the component comprises an interconnect.

[0054] Example 7 is a method of making a semiconductor component, the method comprising: making a hybrid bonded component; and connecting two components through the hybrid bonded component. Making the hybrid bonded component comprises: depositing a first metal-containing pad on a surface; encapsulating the first metal-containing pad with a dielectric material; depositing a dielectric layer on the dielectric material opposite to the surface; then removing a portion of the dielectric material and a portion of the dielectric layer to create a cavity above the first metal-containing pad; filling the cavity with a metal-containing material to generate a via.

[0055] In Example 8, the subject matter of Example 7 optionally includes: wherein the surface includes a substrate.

[0056] In Example 9, the subject matter of Example 8 can optionally include depositing a sputtering seed layer in the cavity prior to filling the cavity with the metal-containing material.

[0057] In Example 10, the subject matter of any one or more of Examples 8-9 can optionally include wherein filling the cavity with the metal-containing material comprises plating.

[0058] In Example 11, the subject matter of any one or more of Examples 8-10 can optionally include leveling the metal-containing material after filling the cavity.

[0059] In Example 12, the subject matter of any one or more of Examples 8-11 can optionally include: wherein depositing the dielectric layer is performed after encapsulating the first metal-containing pad.

[0060] In Example 13, the subject matter of any one or more of Examples 7-12 can optionally include: wherein the surface comprises an etched material on a carrier.

[0061] In Example 14, the subject matter of Example 13 can optionally include: wherein depositing the dielectric layer is performed before encapsulating the first metal-containing pad.

[0062] In Example 15, the subject matter of any one or more of Examples 13-14 can optionally include removing the carrier and the etching material after filling the cavity.

[0063] In Example 16, the subject matter of any one or more of Examples 13-15 may optionally include depositing a second metal-containing pad on the via opposite the first metal-containing pad.

[0064] In Example 17, the subject matter of Example 16 can optionally include establishing additional layers of dielectric material and vias.

[0065] In Example 18, the subject matter of any one or more of Examples 7-17 optionally includes: wherein connecting the two components by the hybrid bonding assembly includes: bonding a first component of the two components to a dielectric layer by metal-metal bonding, and bonding the first component of the two components to a via.

[0066] In Example 19, the subject matter of any one or more of Examples 7-18 optionally includes: wherein connecting the two components by the hybrid bonding component includes: heating the hybrid bonding component to create a metal-metal bond between the via and the metal-containing portion of one of the two components.

[0067] Example 20 is a device comprising: a component; a semiconductor die having a semiconductor die pad; a hybrid bond connecting the semiconductor die to a substrate; and a screen, wherein the hybrid bond comprises: a via; a first metal-containing pad at a first end of the via, the first metal-containing pad bonded to the semiconductor die pad; a dielectric layer surrounding the first metal-containing pad, the dielectric layer bonded to the semiconductor die around the semiconductor die pad; and a second metal-containing pad at a second end of the via, the second metal-containing pad bonded to the component.

[0068] Throughout this specification, multiple instances may implement components, operations or structures described as single instances. Although the individual operations of one or more methods are illustrated and described as separate operations, one or more operations in the individual operations may be performed simultaneously, and it is not required to perform these operations in the illustrated order. The structures and functionality presented as separate components in the example configuration may be implemented as combined structures or components. Similarly, the structures and functionality presented as single components may be implemented as separate components. These and other changes, modifications, additions and improvements all fall within the scope of the subject matter herein.

[0069] Although the overview of the inventive subject matter has been described with reference to specific example embodiments, various modifications and changes may be made to these embodiments without departing from the broader scope of the embodiments of the present disclosure. Such embodiments of the inventive subject matter may be referred to herein individually or collectively by the term "invention", which is merely for convenience and is not intended to limit the scope of the present application to any single disclosure or inventive concept if, in fact, more than one disclosure or inventive concept is disclosed.

[0070] The embodiments shown herein are described in sufficient detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. Therefore, this detailed description is not to be considered limiting, and the scope of the various embodiments is limited only by the appended claims and the full range of equivalents to which such claims are entitled.

[0071] As used herein, the term "or" may be interpreted as inclusive or exclusive. In addition, multiple instances may be provided for resources, operations, or structures described herein as a single instance. In addition, the boundaries between various resources, operations, modules, engines, and data storage devices are somewhat arbitrary, and specific operations are described in the context of a specific illustrative configuration. Other allocations of functionality are contemplated and may fall within the scope of various embodiments of the present disclosure. In general, structures and functionality presented as separate resources in the example configuration may be implemented as combined structures or resources. Similarly, structures and functionality presented as a single resource may be implemented as separate resources. These and other changes, modifications, additions, and improvements fall within the scope of the embodiments of the present disclosure as represented by the appended claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive.

[0072] For purposes of explanation, the foregoing description has been described with reference to specific example embodiments. However, the above illustrative discussion is not intended to be exhaustive of possible example embodiments or to limit them to the precise forms disclosed. In light of the above teachings, many modifications and variations are possible. The example embodiments have been chosen and described in order to best explain the principles involved and their practical applications, thereby enabling those skilled in the art to best utilize the various example embodiments with various modifications suitable for the particular use contemplated.

[0073] It will also be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first contact may be referred to as a second contact and similarly a second contact may be referred to as a first contact without departing from the scope of this example embodiment. The first contact and the second contact are both contacts, but they are not the same contact.

[0074] The terms used in the description of the exemplary embodiments herein are only for the purpose of describing the specific exemplary embodiments, and are not intended to be limiting. As used in the description of the exemplary embodiments and the accompanying examples, unless the context clearly indicates otherwise, the singular forms "one", "a" and "the" are intended to also include plural forms. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more items in the associated listed items. It will be further understood that the terms "including" and / or "comprising" when used in this specification specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0075] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if [the condition or event] is detected" may be interpreted to mean "upon determination" or "in response to determining" or "upon detection of [the condition or event]" or "in response to detecting [the condition or event]," depending on the context.

Claims

1. A semiconductor component, comprising: part; a semiconductor die having a semiconductor die pad; as well as A hybrid bond connecting the semiconductor die to a substrate, wherein the hybrid bond comprises: Vias containing metal; a first pad comprising metal at a first end of the via, the first pad being bonded to the semiconductor die pad; a dielectric layer surrounding the first pad, the dielectric layer bonded to the semiconductor die around the semiconductor die pad; and A second pad including metal at a second end of the via is bonded to the component.

2. The semiconductor component according to claim 1, further comprising: A dielectric material surrounds the via.

3. The semiconductor component according to claim 1, wherein: The via, the first pad, and the second pad include copper.

4. The semiconductor component according to claim 1, wherein: The dielectric layer includes silicon nitride or silicon oxide.

5. The semiconductor component according to claim 1, wherein: The component includes a substrate.

6. The semiconductor component according to claim 1, wherein: The components include interconnects.

7. A method for manufacturing a semiconductor component, comprising: Make hybrid joint assemblies, including: depositing a first pad comprising a metal on the surface; encapsulating the first pad with a dielectric material; depositing a dielectric layer on the dielectric material opposite the surface; subsequently removing a portion of the dielectric material and a portion of the dielectric layer to create a cavity over the first pad; filling the cavity with metal to create a via; and The two components are connected via the hybrid joint assembly.

8. The method of claim 7, further comprising: Prior to filling the cavity with the metal, a sputtered seed layer is deposited in the cavity.

9. The method of claim 7, wherein: Filling the cavity with metal includes plating.

10. The method of claim 7, further comprising: The metal is leveled after filling the cavity.

11. The method of claim 7, wherein: The dielectric layer is deposited after encapsulating the first pad.

12. The method of claim 7, wherein: The dielectric layer is deposited before encapsulating the first pad.

13. The method of claim 12, further comprising: The carrier and the etching material are removed after filling the cavity, and a second pad including a metal is deposited on the via opposite to the first pad.

14. The method of claim 7, wherein: Connecting two components through the hybrid bonding assembly includes bonding a first one of the two components to the dielectric layer and bonding the first one of the two components to the via through a metal-metal bond.

15. The method of claim 7, wherein: Connecting two components via the hybrid bonding assembly includes heating the hybrid bonding assembly to create a metal-to-metal bond between the via and a metal-containing portion of one of the two components.

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