Semiconductor device and method of manufacturing the same

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate including an active pattern; a channel pattern on the active pattern; a source / drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, in which an upper surface of the via is closer to the substrate than the upper surface of the interlayer dielectric layer in a first direction, in which the first direction is perpendicular to the upper surface of the substrate, and in which a portion of the adhesion layer is on a portion of an inner sidewall of the recess.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0078202 filed in the Korean Intellectual Property Office on June 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor. Background Art

[0004] A semiconductor device may include an integrated circuit that includes a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rules of semiconductor devices are gradually reduced, the size of the MOSFET is also gradually scaled down. The scaled down of the MOSFET may degrade the operating characteristics of the semiconductor device. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices with superior performance while overcoming the limitations caused by the high integration of the semiconductor device. Summary of the invention

[0005] Some embodiments of the inventive concept provide semiconductor devices having improved electrical characteristics and increased reliability.

[0006] Some embodiments of the inventive concept provide methods of fabricating semiconductor devices having improved electrical characteristics and increased reliability.

[0007] The objects of the present inventive concept are not limited to the above, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0008] According to some embodiments of the present invention, a semiconductor device may include: a substrate including an active pattern; a channel pattern located on the active pattern; a source / drain pattern electrically connected to the channel pattern; a gate electrode located on the channel pattern; an interlayer dielectric layer located on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via located in the recess of the interlayer dielectric layer; a wiring line located on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer located between the wiring line and an upper surface of the interlayer dielectric layer, wherein the upper surface of the via is closer to the substrate than the upper surface of the interlayer dielectric layer in a first direction, wherein the first direction is perpendicular to the upper surface of the substrate, and wherein a portion of the adhesion layer is located on a portion of an inner sidewall of the recess.

[0009] According to some embodiments of the present inventive concept, a semiconductor device may include: a substrate including an active pattern; a device isolation layer adjacent to the active pattern; a channel pattern located on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns stacked and spaced apart from each other in a first direction, and wherein the first direction is perpendicular to an upper surface of the substrate; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode extending around the plurality of semiconductor patterns; an active contact electrically connected to the source / drain pattern; and a gate contact electrically connected to the active pattern. The gate electrode; an interlayer dielectric layer located on the active contact and the gate contact, wherein the interlayer dielectric layer includes a recess; a via located in the recess of the interlayer dielectric layer and electrically connected to the active contact or the gate contact; a plurality of wiring lines located on the interlayer dielectric layer; and an adhesion layer located between the interlayer dielectric layer and the plurality of wiring lines, wherein one of the plurality of wiring lines is electrically connected to the via, and wherein the adhesion layer extends from the upper surface of the interlayer dielectric layer to a portion of the inner side wall of the recess.

[0010] According to some embodiments of the present invention, a method for manufacturing a semiconductor device may include: forming an interlayer dielectric layer on a substrate; patterning the interlayer dielectric layer to form a recess; forming a via in the recess; forming an adhesion layer, the adhesion layer being located on a portion of an inner side wall of the recess and on an upper surface of the interlayer dielectric layer, wherein the adhesion layer exposes the upper surface of the via; forming a wiring layer on the adhesion layer and the upper surface of the via; and patterning the wiring layer to form a plurality of wiring lines, wherein, in a first direction, the upper surface of the via is lower than the upper surface of the interlayer dielectric layer relative to the upper surface of the substrate, and wherein the first direction is perpendicular to the upper surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 3 A conceptual diagram showing a logic unit of a semiconductor device according to some embodiments of the inventive concept is shown.

[0012] Figure 4 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown.

[0013] Figure 5A , Figure 5B , Figure 5C and Figure 5D The Figure 4 sectional views taken along lines AA′, BB′, CC′, and DD′ show semiconductor devices according to some embodiments of the inventive concept.

[0014] FIG. 6A to FIG. 6E Shows Figure 5C FIG. 1 is an enlarged view of a portion E depicted in FIG. 1 , showing a semiconductor device according to some embodiments of the inventive concept.

[0015] 7A to 15D A cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept is illustrated.

[0016] Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A Shown along Figure 4 A cross-sectional view taken along line AA'.

[0017] Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B Shown along Figure 4 A cross-sectional view taken along line BB'.

[0018] Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C and Fig. 15C Shown along Figure 4 A cross-sectional view taken along line CC'.

[0019] Figure 7B , Fig.9D , Fig. 10D , Fig.11D , Fig.12D , Fig.13D , Fig.14D and Fig.15D Shown along Figure 4 A cross-sectional view taken along line D-D'.

[0020] FIG. 16A to FIG. 18D A cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept is illustrated.

[0021] Fig.16A , Fig.17A and Fig.18A Shown along Figure 4 A cross-sectional view taken along line AA'.

[0022] Fig. 16B , Fig. 17B and Fig.18B Shown along Figure 4 A cross-sectional view taken along line BB'.

[0023] Fig. 16C , Fig. 17C and Fig. 18C Shown along Figure 4 A cross-sectional view taken along line CC'.

[0024] Fig.16D , Fig.17D and Fig.18D Shown along Figure 4 A cross-sectional view taken along line D-D'. DETAILED DESCRIPTION

[0025] Now, some embodiments of the inventive concept will be described below with reference to the accompanying drawings. Throughout the specification, the same reference numerals may refer to the same components unless otherwise specifically stated.

[0026] Figures 1 to 3 A conceptual diagram illustrating a logic unit of a semiconductor device according to some embodiments of the inventive concept is shown.

[0027] Reference Figure 1 , a single height cell SHC may be provided. For example, a first power line M1_R1 and a second power line M1_R2 may be provided on the substrate 100. For example, the first power line M1_R1 may be a path for providing a source voltage VSS, and the second power line M1_R2 may be a path for providing a drain voltage VDD.

[0028] The single height cell SHC may be defined between the first power line M1_R1 and the second power line M1_R2. The single height cell SHC may include a first active area AR1 and a second active area AR2. One of the first active area AR1 and the second active area AR2 may be a PMOSFET area, and the other of the first active area AR1 and the second active area AR2 may be an NMOSFET area. The single height cell SHC may have a complementary metal oxide semiconductor (CMOS) structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0029] Each of the first active region AR1 and the second active region AR2 may have a first width W1 in the first direction D1. The first height HE1 may be defined to indicate the length of the single height cell SHC in the first direction D1. The first height HE1 may be substantially the same as the distance (e.g., spacing) between the first power line M1_R1 and the second power line M1_R2. The first direction D1 may extend parallel to the upper surface of the substrate 100.

[0030] The single height cell SHC may constitute a logic unit. In this specification, a logic unit may represent a logic device that performs a specific function, such as AND, OR, XOR, XNOR, and an inverter. For example, a logic unit may include transistors for constituting a logic device, and may also include wiring lines that connect the transistors to each other (e.g., electrically connected). It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it may be directly on another element or layer, directly connected to or directly coupled to another element or layer, or there may be one or more intermediate elements or layers. In contrast, when an element is referred to as being "directly coupled to", "directly connected to" or "directly responsive to" another element or "directly on another element", there is no intermediate element. In addition, "electrically connected" conceptually includes physical connection and physical disconnection.

[0031] Reference Figure 2 , a double height cell DHC can be provided. For example, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 may be provided on the substrate 100. The first power line M1_R1 may be provided between the second power line M1_R2 and the third power line M1_R3. For example, the second power line M1_R2 and the third power line M1_R3 may be a path for providing a source voltage VSS, and the first power line M1_R1 may be a path for providing a drain voltage VDD.

[0032] The double height cell DHC may be defined between the second power line M1_R2 and the third power line M1_R3 The double height cell DHC may include two first active regions AR1 and two second active regions AR2.

[0033] One of the two second active regions AR2 may be adjacent to the second power line M1_R2. The other of the two second active regions AR2 may be adjacent to the third power line M1_R3. The two first active regions AR1 may be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 may be disposed between the two first active regions AR1.

[0034] The second height HE2 may be defined to indicate the length of the double height unit DHC in the first direction D1. The second height HE2 may be Figure 1 The two first active regions AR1 of the double-height cell DHC may be commonly connected (eg, electrically connected) to serve as one active region.

[0035] In the present invention, Figure 2 The double height unit DHC shown in FIG. 1 may be defined as a multi-height unit. Although not shown, the multi-height unit may include a triple height unit, whose unit height is Figure 1The single-height cell in the SHC is approximately three times the cell height.

[0036] Reference Figure 3 , a first single height cell SHC1, a second single height cell SHC2, and a double height cell DHC arranged two-dimensionally may be arranged on the substrate 100. The first single height cell SHC1 may be arranged between the first power line M1_R1 and the second power line M1_R2. The second single height cell SHC2 may be arranged between the first power line M1_R1 and the third power line M1_R3. The second single height cell SHC2 may be adjacent to the first single height cell SHC1 in the first direction D1.

[0037] The double height cell DHC may be disposed between the second power line M1_R2 and the third power line M1_R3. The double height cell DHC may be adjacent to the first single height cell SHC1 and the second single height cell SHC2 in the second direction D2. The second direction D2 may extend parallel to the upper surface of the substrate 100. The first direction D1 and the second direction D2 may intersect each other (e.g., may be perpendicular).

[0038] The separation structure DB may be disposed between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. The separation structure DB may electrically separate the active region (e.g., the first active region AR1 and / or the second active region AR2) of the double height cell DHC from the active region (e.g., the first active region AR1 and / or the second active region AR2) of each of the first single height cell SHC1 and the second single height cell SHC2.

[0039] Figure 4 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown. Figure 5A , Figure 5B , Figure 5C and Figure 5D The Figure 4 sectional views taken along lines AA′, BB′, CC′, and DD′ show semiconductor devices according to some embodiments of the inventive concept.

[0040] Reference Figure 4 and FIG. 5A to FIG. 5D , a single height cell SHC may be provided on a substrate 100. The single height cell SHC may include a logic transistor included in a logic circuit. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including, for example, silicon, germanium and / or silicon germanium. For example, the substrate 100 may be a silicon substrate.

[0041] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in the second direction D2. For example, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0042] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR (or a device isolation layer ST in the trench TR, which will be discussed below) formed on the upper portion of the substrate 100. For example, the trench TR (device isolation layer ST) may be adjacent to the first active pattern AP1 and / or the second active pattern AP2. The first active pattern AP1 may be disposed on the first active area AR1, and the second active pattern AP2 may be disposed on the second active area AR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertical protrusions of the substrate 100. For example, the first active pattern AP1 and the second active pattern AP2 may protrude in the third direction D3. The third direction D3 may extend perpendicular to the upper surface of the substrate 100. The third direction D3 may intersect with the first direction D1 and the second direction D2 (e.g., perpendicular to the first direction D1 and the second direction D2). The third direction D3 may be referred to as a vertical direction.

[0043] A device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may at least partially fill the trench TR. The device isolation layer ST may include, for example, a silicon oxide layer. The device isolation layer ST may not cover any of the first channel pattern CH1 and the second channel pattern CH2 to be discussed below.

[0044] The first channel pattern CH1 may be disposed on the first active pattern AP1. The second channel pattern CH2 may be disposed on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction (e.g., a third direction D3).

[0045] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include, for example, silicon (Si), germanium (Ge), and / or silicon germanium (SiGe). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon, for example, single crystal silicon. According to some embodiments, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be stacked nanosheets.

[0046] A plurality of first source / drain patterns SD1 may be disposed on the first active pattern AP1. A plurality of first recesses RS1 may be formed on an upper portion of the first active pattern AP1. The first source / drain patterns SD1 may be correspondingly disposed in the first recesses RS1. The first source / drain patterns SD1 may be impurity regions of a first conductive type (e.g., n-type). The first channel pattern CH1 may be inserted between the first source / drain patterns SD1 adjacent to each other along the second direction D2. For example, the stacked first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the first channel pattern CH1 may connect (e.g., electrically connect) the first source / drain patterns SD1 adjacent to each other along the second direction D2.

[0047] A plurality of second source / drain patterns SD2 may be disposed on the second active pattern AP2. A plurality of second recesses RS2 may be formed on an upper portion of the second active pattern AP2. The second source / drain patterns SD2 may be correspondingly disposed in the second recesses RS2. The second source / drain patterns SD2 may be impurity regions of a second conductive type (e.g., p-type). The second channel pattern CH2 may be inserted between the second source / drain patterns SD2 adjacent to each other along the second direction D2. For example, the stacked first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the second channel pattern CH2 may be connected (e.g., electrically connected) to the second source / drain patterns SD2 adjacent to each other along the second direction D2.

[0048] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have an upper surface higher than an upper surface of the third semiconductor pattern SP3. In some embodiments, at least one selected from the first source / drain pattern SD1 and the second source / drain pattern SD2 may have an upper surface located at substantially the same level as an upper surface of the third semiconductor pattern SP3. Hereinafter, the terms high (higher), low (lower), etc. may refer to a relative distance from the substrate 100. For example, element A being higher than element B may mean that element A is disposed farther from the upper surface of the substrate 100 in the vertical direction than element B.

[0049] In some embodiments, the first source / drain pattern SD1 may include a semiconductor element (e.g., Si) that is the same as that of the substrate 100. The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element (e.g., Si) of the substrate 100. Therefore, the second source / drain patterns SD2 adjacent to each other in the second direction D2 may provide compressive stress to the second channel pattern CH2.

[0050] The second source / drain pattern SD2 may have a convex shape at its sidewall. For example, the sidewall of the second source / drain pattern SD2 may have a wavy (uneven) profile. The sidewall of the second source / drain pattern SD2 may protrude toward the first internal electrode PO1, the second internal electrode PO2, and the third internal electrode PO3 of the gate electrode GE to be discussed below.

[0051] The gate electrode GE may be disposed on the first channel pattern CH1 and the second channel pattern CH2. The etching of the gate electrode GE may extend in the first direction D1 while extending across the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. The gate electrodes GE may be spaced apart from each other in the second direction D2. As used herein, "element A overlaps element B in direction X (or similar language)" means that there is at least one line extending in direction X and intersecting both element A and element B.

[0052] Each of the gate electrodes GE may include a first internal electrode PO1 inserted between an active pattern (e.g., a first active pattern AP1 or a second active pattern AP2) and a first semiconductor pattern SP1, a second internal electrode PO2 inserted between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third internal electrode PO3 inserted between the second semiconductor pattern SP2 and a third semiconductor pattern SP3, and an external electrode PO4 on the third semiconductor pattern SP3 (the topmost semiconductor pattern).

[0053] Each of the gate electrodes GE may extend around (e.g., surround) an upper surface TS, a lower surface BS, and an opposite side wall SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., a multi-bridge channel (MBC) FET or a gate-all-around (GAA) FET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

[0054] On the first active area AR1, an inner spacer ISP may be inserted between the first source / drain pattern SD1 and the first, second, and third internal electrodes PO1, PO2, and PO3 of the gate electrode GE, respectively. Each of the first, second, and third internal electrodes PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the first source / drain pattern SD1 by the inner spacer ISP. The inner spacer ISP may prevent leakage current from the gate electrode GE.

[0055] A pair of gate spacers GS may be disposed on opposite side walls of the outer electrode PO4 of each gate electrode GE. The gate spacer GS may extend along the gate electrode GE in the first direction D1. For example, the gate spacer GS may include one or more of SiCN, SiCON, and SiN. In some embodiments, the gate spacer GS may include a multilayer formed of two or more of SiCN, SiCON, and SiN. The gate spacer GS may include, for example, a dielectric material containing silicon. The gate spacer GS may be used as an etch stop layer when forming the first active contact AC1 and the second active contact AC2 as described below. The gate spacer GS may be made to form the first active contact AC1 and the second active contact AC2 in a self-aligned manner.

[0056] A gate capping pattern GP may be disposed on each of the gate electrodes GE. The gate capping pattern GP may extend along the gate electrodes GE in the first direction D1. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be discussed below. For example, the gate capping pattern GP may include SiON, SiCN, SiCON, and / or SiN.

[0057] The gate dielectric layer GI may be inserted between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate dielectric layer GI may be on the upper surface TS, the lower surface BS, and the relative sidewall SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 (e.g., covering them). The gate dielectric layer GI may be on the upper surface of the device isolation layer ST below the gate electrode GE (e.g., covering the upper surface). For example, the gate dielectric layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. In some embodiments, the gate dielectric layer GI may have a structure in which a silicon oxide layer and a high-k dielectric layer are stacked. The high-k dielectric layer may include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric material may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0058] In some embodiments, the semiconductor device according to the inventive concept may include a negative capacitance field effect transistor using a negative capacitor. For example, the gate dielectric layer GI may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0059] The ferroelectric material layer may have a negative capacitance and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series (e.g., electrically connected), and when each capacitor has a positive capacitance, the total capacitance may be reduced to be less than the capacitance of each capacitor. Conversely, when at least one of the two or more capacitors connected in series has a negative capacitance, the total capacitance may have a positive value that is increased to be greater than the absolute value of the capacitance of each capacitor.

[0060] In the case where a ferroelectric material layer having negative capacitance is connected in series (e.g., electrically connected) with a paraelectric material layer having positive capacitance, the capacitance of the series-connected ferroelectric material layer and the paraelectric material layer as a whole increases. The increase in total capacitance can be used to enable a transistor including the ferroelectric material layer to have a subthreshold swing of less than about 60 mV / decade at room temperature.

[0061] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, and / or lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material in which hafnium oxide is doped with zirconium (Zr). For another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0062] The ferroelectric material layer may further include impurities doped therein. For example, the impurities may include aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and / or tin (Sn). The type of impurities included in the ferroelectric material layer may vary depending on the ferroelectric material included in the ferroelectric material layer.

[0063] When the ferroelectric material layer includes hafnium oxide, the ferroelectric material layer may include impurities such as gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0064] When the impurity is aluminum (Al), the ferroelectric material layer may include about 3 to about 8 (eg, 3 to 8) atomic percent of aluminum. In this specification, the ratio of the impurity may be a ratio of aluminum to the sum of hafnium and aluminum.

[0065] When the impurity is silicon (Si), the ferroelectric material layer may include about 2 to about 10 (e.g., 2 to 10) atomic percent silicon. When the impurity is yttrium (Y), the ferroelectric material layer may include about 2 to about 10 (e.g., 2 to 10) atomic percent yttrium. When the impurity is gadolinium (Gd), the ferroelectric material layer may include about 1 to about 7 (e.g., 1 to 7) atomic percent gadolinium. When the impurity is zirconium (Zr), the ferroelectric material layer may include about 50 to about 80 (e.g., 50 to 80) atomic percent zirconium.

[0066] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, silicon oxide and / or high-k metal oxide. The high-k metal oxide included in the paraelectric material layer may include, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited thereto.

[0067] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer may be different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0068] The ferroelectric material layer may have a thickness having ferroelectric properties. The thickness of the ferroelectric material layer may be in a range of, for example, about 0.5 nm to about 10 nm (e.g., 0.5 nm to 10 nm), but the inventive concept is not limited thereto. Because the ferroelectric material has its own critical thickness that exhibits ferroelectric properties, the thickness of the ferroelectric material layer may depend on the ferroelectric material.

[0069] For example, the gate dielectric layer GI may include a ferroelectric material layer. For another example, the gate dielectric layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate dielectric layer GI may have a stacking structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0070] The first interlayer dielectric layer 110 may be disposed on the substrate 100. The first interlayer dielectric layer 110 may extend around the gate spacer GS and the first and second source / drain patterns SD1 and SD2 (e.g., cover the gate spacer GS and the first and second source / drain patterns SD1 and SD2). The first interlayer dielectric layer 110 may have an upper surface substantially coplanar with an upper surface of the gate capping pattern GP and an upper surface of the gate spacer GS.

[0071] The second interlayer dielectric layer 120 may be disposed on the first interlayer dielectric layer 110. The third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120. The fourth interlayer dielectric layer 140 may be disposed on the third interlayer dielectric layer 130. For example, the first interlayer dielectric layer 110, the second interlayer dielectric layer 120, the third interlayer dielectric layer 130, and the fourth interlayer dielectric layer 140 may include a silicon oxide layer.

[0072] The single height cell SHC may have a first boundary BD1 and a second boundary BD2 opposite to each other in the second direction D2. Each of the first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The single height cell SHC may have a third boundary BD3 and a fourth boundary BD4 opposite to each other in the first direction D1. Each of the third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0073] The single height cell SHC may be provided with a pair of separation structures DB on opposite sides thereof, the pair of separation structures DB being opposite to each other in the second direction D2. For example, the separation structure pair DB may be correspondingly provided on the first boundary BD1 and the second boundary BD2 of the single height cell SHC. The separation structure DB may extend parallel to the gate electrode GE in the first direction D1.

[0074] The separation structure DB may penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to extend (at least partially) into the first active pattern AP1 and the second active pattern AP2. The separation structure DB may penetrate an upper portion of each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB may electrically separate an active region (e.g., the first active pattern AP1 and / or the second active pattern AP2) of the single height cell SHC from an active region of another adjacent cell.

[0075] The first active contact AC1 and the second active contact AC2 may be disposed to at least partially penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. The gate electrode GE may be located between the first active contacts AC1 adjacent to each other in the second direction D2 and between the second active contacts AC2 adjacent to each other in the second direction D2. When viewed in a plan view, each of the first active contact AC1 and the second active contact AC2 may have a bar shape extending in the first direction D1.

[0076] The first active contact AC1 may include a first conductive pattern FM1 and a first barrier pattern BM1 extending around (e.g., at least partially surrounding) the first conductive pattern FM1. The first barrier pattern BM1 may cover the sidewall and the lower surface of the first conductive pattern FM1. For example, the first conductive pattern FM1 may include aluminum, copper, tungsten, molybdenum and / or cobalt. The first barrier pattern BM1 may be a metal layer including titanium, tantalum, tungsten, nickel, cobalt and / or platinum, or a metal nitride layer including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN) and / or platinum nitride (PtN). The second active contact AC2 may include a second conductive pattern FM2 and a second barrier pattern BM2 extending around (e.g., at least partially surrounding) the second conductive pattern FM2. The second active contact AC2 may be substantially the same as the first active contact AC1 (e.g., may include the same material as the first active contact AC1).

[0077] Each of the first active contact AC1 and the second active contact AC2 may be a self-aligned contact. For example, the gate capping pattern GP and the gate spacer GS may be used to form the first active contact AC1 and the second active contact AC2 in a self-aligned manner. The first active contact AC1 and the second active contact AC2 may be disposed adjacent to the sidewall of the gate spacer GS. In some embodiments, the first active contact AC1 and the second active contact AC2 may be on a portion of the upper surface of the gate capping pattern GP (e.g., covering a portion of the upper surface of the gate capping pattern GP).

[0078] The metal-semiconductor compound layer SC may be disposed between the first active contact AC1 and the first source / drain pattern SD1 and between the second active contact AC2 and the second source / drain pattern SD2. The first active contact AC1 and the second active contact AC2 may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively, through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and / or cobalt silicide.

[0079] The gate contact GC may be provided to penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP, ​​thereby being electrically connected to the gate electrode GE. The gate contact GC may include a conductive pattern FM and a barrier pattern BM extending around (e.g., at least partially surrounding) the conductive pattern FM. The barrier pattern BM may cover the sidewall and lower surface of the conductive pattern FM. The conductive pattern FM may be substantially the same as (e.g., may include the same material as) the first conductive pattern FM1 and the second conductive pattern FM2 of the first active contact AC1 and the second active contact AC2. The barrier pattern BM may be substantially the same as (e.g., may include the same material as) the first barrier pattern BM1 and the second barrier pattern BM2 of the first active contact AC1 and the second active contact AC2. When viewed in a plan view, the gate contact GC may be provided to overlap with a corresponding one of the first active area AR1 and the second active area AR2. For example, the gate contact GC may be provided on the second active pattern AP2.

[0080] The first metal layer M1 may be disposed in the third interlayer dielectric layer 130. For example, the first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, and a first wiring line M1_I. The lines M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend in parallel in the second direction D2.

[0081] For example, the first power line M1_R1 and the second power line M1_R2 may be disposed on the third boundary BD3 and the fourth boundary BD4 of the single height cell SHC, respectively. The first power line M1_R1 may extend in the second direction D2 along the third boundary BD3. The second power line M1_R2 may extend in the second direction D2 along the fourth boundary BD4.

[0082] The first wiring lines M1_I of the first metal layer M1 may be disposed between the first power line M1_R1 and the second power line M1_R2. The first wiring lines M1_I of the first metal layer M1 may be spaced apart from each other in the first direction D1. Each of the first wiring lines M1_I may have a line width (e.g., a line width in the first direction D1) that is smaller than a line width of each of the first power line M1_R1 and the second power line M1_R2.

[0083] The first metal layer M1 may further include a first via VI 1. The first via VI 1 may be disposed under the lines M1_R1, M1_R2, and / or M1_I of the first metal layer M1. The first active contact AC1, the second active contact AC2, and the gate contact GC may be electrically connected to the lines M1_R1, M1_R2, and / or M1_I of the first metal layer M1 through the first via VI 1.

[0084] The lines M1_R1, M1_R2 and M1_I of the first metal layer M1 and the first vias VI1 thereunder may be formed by processes independent of each other. Fig. 6A and Figure 6B The lines M1_R1 , M1_R2 , and M1_I of the first metal layer M1 and the first via VI1 are discussed in further detail.

[0085] The second metal layer M2 may be disposed in the fourth interlayer dielectric layer 140. The second metal layer M2 may include a plurality of second wiring lines M2_I. The second wiring lines M2_I of the second metal layer M2 may each have a linear or bar shape extending along the first direction D1. The second wiring lines M2_I may extend in parallel along the first direction D1 and may be spaced apart from each other in the second direction D2.

[0086] The second metal layer M2 may further include a second via VI2, which is correspondingly disposed below the second wiring line M2_I. The line of the first metal layer M1 (e.g., the line M1_R1, M1_R2, and / or M1_I) may electrically reach the corresponding line of the second metal layer M2 (e.g., the second wiring line M2_I) through the second via VI2. A specific line of the second metal layer M2 and the second via VI2 thereunder may be formed simultaneously by a dual damascene process.

[0087] FIG. 6A to FIG. 6E Shows Figure 5C FIG. 1 is an enlarged view of a portion E depicted in FIG. 1 , showing a semiconductor device according to some embodiments of the inventive concept.

[0088] Reference Fig. 6A , the third interlayer dielectric layer 130 may include a lower interlayer dielectric layer 131 and an upper interlayer dielectric layer 135. The lower interlayer dielectric layer 131 may be located on the second interlayer dielectric layer 120 and the second active contact AC2. The upper interlayer dielectric layer 135 may be located on the lower interlayer dielectric layer 131. The fourth interlayer dielectric layer 140 may be located on the upper interlayer dielectric layer 135.

[0089] The lower interlayer dielectric layer 131 may have a recess RS. The recess RS may penetrate the lower interlayer dielectric layer 131 to expose the sidewall of the lower interlayer dielectric layer 131. For example, the width of the recess RS (e.g., the width in the first direction D1 or the width in the second direction D2) may change along the third direction D3. The width of the recess RS may increase in a direction from the lower surface 131b of the lower interlayer dielectric layer 131 toward the upper surface 131t of the lower interlayer dielectric layer 131. In some embodiments, the width of the recess RS may be constant along the third direction D3.

[0090] The first via VI 1 may be located in the recess RS of the lower interlayer dielectric layer 131. The upper surface VIt of the first via VI 1 may be located at a level lower than the level of the upper surface 131t of the lower interlayer dielectric layer 131. For example, the upper surface VIt of the first via VI 1 may not be located on the same plane as the upper surface 131t of the lower interlayer dielectric layer 131. The first via VI 1 may partially fill the recess RS. The first via VI 1 may fill the lower portion of the recess RS in the lower interlayer dielectric layer 131. Therefore, the inner wall (e.g., the inner side wall) of the recess RS may be partially exposed by the first via VI 1. For example, the upper portion of the inner wall of the recess RS may be exposed by the first via VI 1. The first via VI 1 may have a first length L1 along the first direction D1 at its upper surface VIt. The first length L1 may be the upper width of the first via VI 1. For example, the first length L1 may be in a range of about 5 nm to about 15 nm (e.g., 5 nm to 15 nm). The first via member VI1 may include, for example, a metal material such as aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), ruthenium (Ru) and / or cobalt (Co), and may include, for example, ruthenium (Ru) and / or molybdenum (Mo).

[0091] The second power line M1_R2 may be located on the lower interlayer dielectric layer 131 and the first via VI 1. The second power line M1_R2 may be connected (e.g., electrically connected) to the first via VI 1. The second power line M1_R2 may include a line portion LP and a protrusion PP. The protrusion PP may extend vertically from the line portion LP and be positioned below the line portion LP. The line portion LP may be located on the upper surface 131t of the lower interlayer dielectric layer 131, and the protrusion PP may be at least partially located in the recess RS of the lower interlayer dielectric layer 131. For example, the protrusion PP may contact the upper surface VIt of the first via VI 1 while at least partially filling the upper portion of the recess RS.

[0092] The first wiring line M1_I may be located on the lower interlayer dielectric layer 131. The first wiring line M1_I may be spaced apart from the second power line M1_R2 by a second length L2 in the first direction D1. The second length L2 may be Figure 4 , and the spacing between the lines M1_R1, M1_R2 and M1_I of the first metal layer M1 depicted in FIG. For example, the second length L2 may be in the range of about 10 nm to about 20 nm (e.g., 10 nm to 20 nm). Similar to the second power line M1_R2, the first wiring line M1_I may include a line portion and a protrusion extending vertically from the line portion. The first wiring line M1_I shown in the figure may correspond to the line portion of the first wiring line M1_I. The line portion of the first wiring line M1_I may be vertically and horizontally spaced apart from the upper surface VIt of the first via VI 1.

[0093] The second power line M1_R2 and the first wiring line M1_I of the first metal layer M1 may include, for example, aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), ruthenium (Ru) and / or cobalt (Co), and may include, for example, ruthenium (Ru).

[0094] The adhesion layer 133 may be located between the second power line M1_R2 and the lower interlayer dielectric layer 131 and between the first wiring line M1_I and the lower interlayer dielectric layer 131. For example, the adhesion layer 133 may not be located on the upper surface 131t of the lower interlayer dielectric layer 131 on which the first wiring line M1_I is not disposed. The adhesion layer 133 (e.g., the sidewall of the adhesion layer 133) may be aligned with the sidewall of the first wiring line M1_I. The adhesion layer 133 may have a sidewall aligned with one sidewall of the first wiring line M1_I. The adhesion layer 133 may be located between the lower interlayer dielectric layer 131 and the line portion LP of the second power line M1_R2 and between the recess RS (e.g., the inner wall (upper part of the inner wall) of the recess RS) and the protruding portion PP of the second power line M1_R2. The adhesion layer 133 between the lower interlayer dielectric layer 131 and the second power line M1_R2 connected to the first via member VI1 may extend from the upper surface 131t of the lower interlayer dielectric layer 131 to a portion of the inner wall of the recess RS. For example, a portion of the adhesion layer 133 may cover a portion of the inner wall of the recess RS (e.g., an upper portion of the inner wall).

[0095] The adhesion layer 133 may have excellent adhesion to the lower interlayer dielectric layer 131. In addition, the adhesion layer 133 may have superior adhesion to the first wiring line M1_I and the second power line M1_R2 of the first metal layer M1. Therefore, the adhesion layer 133 may prevent the first wiring line M1_I and the second power line M1_R2 from peeling (separating) from the lower interlayer dielectric layer 131. The adhesion layer 133 may include a dielectric material, such as silicon (Si), oxygen (O), carbon (C), aluminum (Al), titanium (Ti) and / or tantalum (Ta).

[0096] However, the present invention is not limited to the above discussion. FIG. 5A to FIG. 5DAs shown, the first via VI 1 may be connected to the first power line M1_R1 and / or the first wiring line M1_I of the first metal layer M1. In this case, the first power line M1_R1 and the first wiring line M1_I connected to the first via VI 1 may include a line portion LP on the upper surface 131t of the lower interlayer dielectric layer 131 and a protruding portion PP in the recess RS. For example, the lines M1_R1, M1_R2, and M1_I of the first metal layer M1 connected to the first via VI 1 may include a line portion LP and a protruding portion PP. In addition, the adhesion layer 133 may be located between the lower interlayer dielectric layer 131 and the lines M1_R1, M1_R2, and M1_I of the first metal layer M1. For example, the adhesion layer 133 may be located between the lower interlayer dielectric layer 131 and the lines M1_R1, M1_R2, and M1_I of the first metal layer M1. FIG. 6A to FIG. 6E A similar manner as described in is between the lower interlayer dielectric layer 131 and the lines M1_R1 , M1_R2 , and / or M1_I of the first metal layer M1 .

[0097] The upper interlayer dielectric layer 135 may be located between the second power line M1_R2 and the first wiring line M1_I. A portion of the upper interlayer dielectric layer 135 may be located in the recess RS, but the inventive concept is not limited thereto. The upper surface of the upper interlayer dielectric layer 135 may be coplanar with the upper surface of the first wiring line M1_I and the upper surface of the second power line M1_R2.

[0098] Reference Figure 6B , the adhesion layer 133 may completely cover the upper surface 131t of the lower interlayer dielectric layer 131. On the upper surface 131t of the lower interlayer dielectric layer 131, the adhesion layer 133 may be located between the first wiring line M1_I and the second power line M1_R2. For example, on the upper surface 131t of the lower interlayer dielectric layer 131, the adhesion layer 133 may extend between the first wiring line M1_I and the second power line M1_R2. Regardless of the first wiring line M1_I and the second power line M1_R2, the adhesion layer 133 may extend from the upper surface 131t of the lower interlayer dielectric layer 131 to a portion of the inner wall of the recess RS. For example, the adhesion layer 133 may be disposed on the upper portion of the opposite inner wall (e.g., the opposite side wall) of the recess RS. For example, in the process of forming the second power line M1_R2 and the first wiring line M1_I, the adhesion layer 133 may not be patterned.

[0099] Reference Figure 6C , the upper surface VIt of the first via VI1 may have a convex shape toward the second power line M1_R2. When the first via VI1 is formed by selective area growth (SAG), the upper surface VIt of the first via VI1 may have a convex shape, but the inventive concept is not limited thereto.

[0100] In this configuration, the upper surface VIt of the first via VI 1 may be at a maximum (e.g., uppermost or highest) level at a central region of the first via VI 1 along the first direction D1. The upper surface VIt of the first via VI 1 may be at a minimum (e.g., lowermost or lowest) level at an edge of the first via VI 1 along the first direction D1. The upper surface VIt of the first via VI 1 may not be parallel to the upper surface 131t of the lower interlayer dielectric layer 131. The lower surface of the protruding portion PP of the second power line M1_R2 may have a shape that is concave toward the lower surface 131b of the lower interlayer dielectric layer 131.

[0101] Reference Fig.6D , the first via member VI 1 may have a via recess VRS. The via recess VRS may penetrate a portion of the first via member VI 1 from the upper surface VIt of the first via member VI 1. The via recess VRS may contact the inner wall of the recess RS on which the adhesion layer 133 is not disposed. For example, a portion of the inner wall of the recess RS may be a portion of the inner wall of the via recess VRS. Therefore, the via recess VRS may expose at least a portion of the inner wall of the recess RS to the outside. The upper interlayer dielectric layer 135 may fill a portion of the recess RS and the via recess VRS.

[0102] In this configuration, the via recess VRS may be formed on the upper surface VIt of the first via member VI 1 on which the second power line M1_R2 is not disposed. For example, the via recess VRS may extend from one lateral surface (e.g., sidewall) of the second power line M1_R2. When viewed in a plan view, the via recess VRS may not overlap the second power line M1_R2 (in the vertical direction).

[0103] Reference Fig. 6E , the first via VI 1 and the second power line M1_R2 may include the same metal material. For example, the first via VI 1 and the second power line M1_R2 may be formed by their own processes. In this case, a visible interface VIt may be provided between the first via VI 1 and the second power line M1_R2, and the interface VIt may be the same as the upper surface VIt of the first via VI 1.

[0104] In some embodiments, the first via VI 1 and the second power line M1_R2 may be formed simultaneously with each other and may be integrally connected as a single object. In this case, an invisible interface VIt (or no interface) may be provided between the first via VI 1 and the second power line M1_R2. The single object herein may refer to a structure having no visible interface or no interface between its two substructures.

[0105] Since the adhesion layer 133 is disposed between the second power line M1_R2 and the lower interlayer dielectric layer 131, and since the second power line M1_R2 is integrally connected with the first via VI1 as a single object, the adhesion layer 133 may be disposed between the first via VI1 and the lower interlayer dielectric layer 131. For example, the adhesion layer 133 may extend from the upper surface 131t of the lower interlayer dielectric layer 131 to the lower surface 131b while covering at least a portion of the inner wall of the recess RS. The adhesion layer 133 may not cover the lower surface 131b of the lower interlayer dielectric layer 131.

[0106] Likewise, Fig.6D As shown, the first via member VI1 may have a via recess VRS. When forming the via recess VRS, a portion of the adhesive layer 133 may be removed. For example, the via recess VRS may allow the adhesive layer 133 to cover a portion of the inner wall of the recess RS, and may allow a portion of the inner wall of the recess RS not covered by the adhesive layer 133 to be exposed to the outside.

[0107] Return to reference 5A to 6E , the adhesion layer 133 may be disposed between the lower interlayer dielectric layer 131 and the wires M1_R1, M1_R2, and M1_I of the first metal layer M1, and may not be disposed between the first via VI 1 and the wires M1_R1, M1_R2, and M1_I of the first metal layer M1. In some embodiments, the first via VI 1 and each of the wires M1_R1, M1_R2, and M1_I of the first metal layer M1 may be formed as a single object. For example, the adhesion layer 133 of the present invention may not be included between the first via VI 1 and the wires M1_R1, M1_R2, and M1_I of the first metal layer M1. Therefore, since the adhesion layer 133 is not included between the first via VI 1 and the wires M1_R1, M1_R2, and M1_I of the first metal layer M1, the resistance between the first via VI 1 and the wires M1_R1, M1_R2, and M1_I of the first metal layer M1 may be prevented from increasing. As a result, the semiconductor device can improve electrical performance.

[0108] In addition, since the upper surface VIt of the first via VI1 is located at a lower level than the upper surface 131t of the lower interlayer dielectric layer 131, sufficient spacing can be obtained between the first via VI1 and the wires M1_R1, M1_R2, and M1_I of the first metal layer M1, each of which is adjacent to the first via VI1 but not connected to the first via VI1. Each of the wires M1_R1, M1_R2, and M1_I of the first metal layer M1 may include a wire portion LP and a protruding portion PP, and the wire portion LP may be vertically spaced apart from the upper surface VIt of the first via VI1. Therefore, a small spacing may be formed between the wires M1_R1, M1_R2, and M1_I of the first metal layer M1, and unintended electrical connection between the wires M1_R1, M1_R2, and M1_I of the first metal layer M1 may also be prevented. Therefore, the semiconductor device may have an increased degree of integration and improved electrical characteristics.

[0109] 7A to 15D 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A Shown along Figure 4 A cross-sectional view taken along line AA'. Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B Shown along Figure 4 A cross-sectional view taken along line BB'. Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C , Fig. 14C and Fig. 15C Shown along Figure 4 A cross-sectional view taken along line CC'. Figure 7B , Fig.9D , Fig. 10D , Fig.11D , Fig.12D , Fig.13D , Fig.14D and Fig.15D Shown along Figure 4 A cross-sectional view taken along line D-D'.

[0110] Reference Fig. 7A and Figure 7B , a substrate 100 including a first active region AR1 and a second active region AR2 may be provided. Active layers ACL and sacrificial layers SAL may be alternately stacked on the substrate 100. For example, the active layer ACL may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layer SAL may include another of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0111] The sacrificial layer SAL may include a material having an etching selectivity relative to the active layer ACL. For example, the active layer ACL may include silicon (Si), and the sacrificial layer SAL may include silicon germanium (SiGe). Each of the sacrificial layers SAL may have a germanium concentration of about 10 at % to about 30 at % (e.g., 10 at % to 30 at %).

[0112] A mask pattern may be formed on each of the first and second active regions AR1 and AR2 of the substrate 100. The mask pattern may have a linear or bar shape extending in the second direction D2.

[0113] A patterning process may be performed in which a mask pattern is used to form trenches TR defining the first active pattern AP1 and the second active pattern AP2. The first active pattern AP1 may be formed on the first active region AR1. The second active pattern AP2 may be formed on the second active region AR2.

[0114] A stack pattern STP may be formed on each of the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may include active layers ACL and sacrificial layers SAL that are alternately stacked. The stack pattern STP may be formed simultaneously with the first active pattern AP1 and the second active pattern AP2 during a patterning process.

[0115] Thereafter, a device isolation layer ST may be formed to fill (eg, at least partially fill) the trench TR. The formation of the device isolation layer ST may include forming a dielectric layer covering the first and second active patterns AP1 and AP2 and the stacked pattern STP on the upper surface of the substrate 100, and recessing the dielectric layer until the stacked pattern STP is exposed.

[0116] The device isolation layer ST may include a dielectric material such as a silicon oxide layer. The stack pattern STP may be exposed upward from the device isolation layer ST. The stack pattern STP may protrude vertically upward from the device isolation layer ST.

[0117] Reference FIG. 8A to FIG. 8C, sacrificial patterns PP1 extending across the stacked patterns STP may be formed on the substrate 100. The sacrificial patterns PP1 may be formed to each have a linear or bar shape extending in the first direction D1. The sacrificial patterns PP1 may be spaced apart from each other in the second direction D2.

[0118] For example, the formation of the sacrificial pattern PP1 may include forming a sacrificial layer on the upper surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may include, for example, polysilicon.

[0119] A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP1. The formation of the gate spacers GS may include conformally forming a gate spacer layer on the upper surface of the substrate 100 and anisotropically etching the gate spacer layer. For example, the gate spacer GS may be a multilayer including at least two layers.

[0120] Thereafter, a first recess RS1 may be formed in the stack pattern STP on the first active pattern AP1. A second recess RS2 may be formed in the stack pattern STP on the second active pattern AP2. During the formation of the first recess RS1 and the second recess RS2, the device isolation layer ST may be further recessed on opposite sides of each of the first active pattern AP1 and the second active pattern AP2.

[0121] For example, the hard mask pattern MP and the gate spacer GS may be used as an etching mask so that the stacked pattern STP on the first active pattern AP1 may be etched to form the first recess RS1. The first recess RS1 may be formed between the sacrificial patterns PP1 adjacent to each other along the second direction D2. The width of the first recess RS1 in the second direction D2 may decrease as the distance from the substrate 100 (in a vertical direction perpendicular to the upper surface of the substrate 100 (e.g., a third direction D3)) decreases.

[0122] Sequentially stacked first, second, and third semiconductor patterns SP1, SP2, and SP3 may be correspondingly formed by the active layer ACL between first recesses RS1 adjacent to each other in the second direction D2. The first channel pattern CH1 may include first, second, and third semiconductor patterns SP1, SP2, and SP3 between first recesses RS1 adjacent to each other in the second direction D2.

[0123] The first recess RS1 may expose the sacrificial layer SAL. A selective etching process may be performed on the exposed sacrificial layer SAL. The etching process may include a wet etching process that selectively etches only silicon germanium. In the etching process, each of the sacrificial layers SAL may be recessed to form a recessed region IDR. The recessed region IDR may allow the sacrificial layer SAL to have a recessed sidewall. A dielectric layer may be formed in the first recess RS1 to fill the recessed region IDR. The sacrificial layer SAL exposed by the first recess RS1 and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may become a seed layer for a dielectric layer (also referred to as an epitaxial dielectric layer). The dielectric layer may be a crystalline dielectric layer grown on a crystalline semiconductor included in the sacrificial layer SAL and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0124] The inner spacer ISP may be formed to fill (e.g., at least partially fill) the recessed region IDR. For example, the formation of the inner spacer ISP may include: wet etching the epitaxial dielectric layer until the sidewalls of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are exposed. Therefore, the epitaxial dielectric layer may remain only in the recessed region IDR, thereby constituting the inner spacer ISP.

[0125] The second recess RS2 in the stacked pattern STP on the second active pattern AP2 may be formed by a method similar to the method for forming the first recess RS1. The sacrificial layer SAL exposed by the second recess RS2 may undergo a selective etching process to form a recessed area IDE on the second active pattern AP2. The recessed area IDE may allow the second recess RS2 to have a wavy inner sidewall (e.g., an uneven inner sidewall). The inner spacer ISP may not be formed in the recessed area IDE on the second active pattern AP2. The second channel pattern CH2 may be composed of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between the adjacent (e.g., neighboring) second recesses RS2.

[0126] Reference 9A to 9D , a first source / drain pattern SD1 may be correspondingly formed in the first recess RS1. For example, a selective epitaxial growth (SEG) process may be performed, wherein the inner sidewall of the first recess RS1 is used as a seed layer to form an epitaxial layer that (at least partially) fills the first recess RS1. The epitaxial layer may be grown from a seed, or from the substrate 100 and the first, second, and third semiconductor patterns SP1, SP2, and SP3 exposed by the first recess RS1. For example, the selective epitaxial growth process may include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0127] For example, the first source / drain pattern SD1 may be formed of the same semiconductor element (e.g., Si) as the substrate 100. When forming the first source / drain pattern SD1, impurities (e.g., phosphorus, arsenic, and / or antimony) may be in-situ implanted to allow the first source / drain pattern SD1 to have, for example, an n-type conductivity type. In some embodiments, after forming the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1.

[0128] The second source / drain pattern SD2 may be correspondingly formed in the second recess RS2. For example, the formation of the second source / drain pattern SD2 may include performing a selective epitaxial growth process in which the inner sidewall of the second recess RS2 serves as a seed layer.

[0129] For example, the second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of a semiconductor element (e.g., Si) of the substrate 100. When forming the second source / drain pattern SD2, impurities (e.g., boron, gallium, or indium) may be in-situ implanted to allow the second source / drain pattern SD2 to have, for example, a p-type conductivity type. In some embodiments, after forming the second source / drain pattern SD2, impurities may be implanted into the second source / drain pattern SD2.

[0130] A first interlayer dielectric layer 110 may be formed on the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS (e.g., to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS). For example, the first interlayer dielectric layer 110 may include a silicon oxide layer.

[0131] The first interlayer dielectric layer 110 may be planarized until the upper surface of the sacrificial pattern PP1 is exposed. An etch-back or chemical mechanical polishing (CMP) process may be used to planarize the first interlayer dielectric layer 110. During the planarization process, the hard mask pattern MP may be entirely removed. As a result, the first interlayer dielectric layer 110 may have an upper surface coplanar with the upper surface of the sacrificial pattern PP1 and the upper surface of the gate spacer GS.

[0132] The exposed sacrificial pattern PP1 may be selectively removed. The removal of the sacrificial pattern PP1 may form an outer region ORG exposing the first and second channel patterns CH1 and CH2. The removal of the sacrificial pattern PP1 may include performing a wet etching process using an etchant capable of selectively etching polysilicon.

[0133] The sacrificial layer SAL exposed by the outer region ORG may be selectively removed to form an inner region IRG. For example, the inner region IRG may include a first inner region IRG1, a second inner region IRG2, and a third inner region IRG3. The first inner region IRG1 may be formed between the first active pattern AP1 and the first semiconductor pattern SP1, or between the second active pattern AP2 and the first semiconductor pattern SP1, the second inner region IRG2 may be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the third inner region IRG3 may be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0134] For example, only the sacrificial layer SAL may be removed, leaving the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the etching process may have a high etching rate relative to silicon germanium having a relatively high germanium concentration. In this case, the etching process may have a high etching rate relative to silicon germanium having a germanium concentration equal to or greater than about 10 at % (e.g., 10 at %).

[0135] A gate dielectric layer GI may be formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate dielectric layer GI may be formed to extend around (e.g., at least partially surround) each of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate dielectric layer GI may be formed in each of the first inner region IRG1, second inner region IRG2, and third inner region IRG3. The gate dielectric layer GI may be formed in the outer region ORG.

[0136] Reference FIG. 10A to FIG. 10D , a gate electrode GE may be formed on the gate dielectric layer GI. The gate electrode GE may include a first inner electrode PO1, a second inner electrode PO2, and a third inner electrode PO3 formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, respectively, and may further include an outer electrode PO4 formed in the outer region ORG. The gate electrode GE may be recessed to have a reduced height. A gate capping pattern GP may be formed on the recessed gate electrode GE.

[0137] A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110 and the gate capping pattern GP. The second interlayer dielectric layer 120 may have a constant thickness in the third direction D3. After forming the second interlayer dielectric layer 120, a planarization process may be performed.

[0138] Reference FIG. 11A to FIG. 11D, the first active contact AC1 and the second active contact AC2 may be formed to penetrate (e.g., at least partially penetrate or extend into) the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120. The first active contact AC1 may be connected (e.g., electrically connected) to an upper portion of the first source / drain pattern SD1. The second active contact AC2 may be connected (e.g., electrically connected) to an upper portion of the second source / drain pattern SD2.

[0139] The formation of the first active contact AC1 may include: forming a first recessed region penetrating (e.g., at least partially penetrating or extending into) the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, forming a first barrier pattern BM1 in the first recessed region, forming a first conductive pattern FM1 on the first barrier pattern BM1, and performing a planarization process on the first conductive pattern FM1.

[0140] The formation of the second active contact AC2 may include: forming a second recessed region that penetrates (e.g., at least partially penetrates or extends into) the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, forming a second barrier pattern BM2 in the second recessed region, forming a second conductive pattern FM2 on the second barrier pattern BM2, and performing a planarization process on the second conductive pattern FM2.

[0141] The first active contact AC1 and the second active contact AC2 may be formed by the same process or the same series of processes (simultaneously). For example, the first recessed area and the second recessed area may be formed concurrently, the first barrier pattern BM1 and the second barrier pattern BM2 may be formed simultaneously, and the first conductive pattern FM1 and the second conductive pattern FM2 may be formed coincidently. Thereafter, a planarization process may be performed on the first conductive pattern FM1 and the second conductive pattern FM2. In some embodiments, the first active contact AC1 and the second active contact AC2 may be formed independently.

[0142] The gate contact GC may be formed to penetrate (e.g., at least partially penetrate) the gate capping pattern GP and the second interlayer dielectric layer 120. The gate contact GC may contact the upper surface of the gate electrode GE (e.g., the upper surface of the external electrode PO4). The formation of the gate contact GC may include: forming a third recessed region penetrating (e.g., at least partially penetrating or extending into) the gate capping pattern GP and the second interlayer dielectric layer 120, forming a barrier pattern BM in the third recessed region, forming a conductive pattern FM on the barrier pattern BM, and performing a planarization process on the conductive pattern FM.

[0143] A lower interlayer dielectric layer 131 may be formed on the second interlayer dielectric layer 120. The lower interlayer dielectric layer 131 may be disposed on (eg, cover or overlap) the second interlayer dielectric layer 120, the first active contact AC1, the second active contact AC2, and the gate contact GC.

[0144] Reference FIG. 12A to FIG. 12D , the lower interlayer dielectric layer 131 may be patterned to form a recess RS. The formation of the recess RS may include: forming a mask on the lower interlayer dielectric layer 131, performing an anisotropic etching process on the lower interlayer dielectric layer 131 using the mask, and removing the mask. The recess RS may penetrate (e.g., at least partially penetrate or extend into) the lower interlayer dielectric layer 131 to expose at least one of the first active contact AC1, the second active contact AC2, and the gate contact GC to the outside. On the upper surface 131t of the lower interlayer dielectric layer 131, the width of the recess RS may decrease as the distance from the second interlayer dielectric layer 120 decreases, but the inventive concept is not limited thereto. In a cross-sectional view, the recess RS may be in an inverted trapezoidal shape.

[0145] The first via VI 1 may be formed in the recess RS. An upper surface VIt of the first via VI 1 may be located at a level lower than that of an upper surface 131t of the lower interlayer dielectric layer 131. The first via VI 1 may partially fill the recess RS. The first via VI 1 may fill a lower portion of the recess RS.

[0146] According to an embodiment, the formation of the first via VI 1 may include: forming a conductive layer filling the recess RS and performing a planarization process on the conductive layer. For example, the conductive layer may be on the upper surface 131t of the lower interlayer dielectric layer 131 (e.g., covering the upper surface 131t or overlapping with it) while filling the recess RS. The planarization process may have a polishing selectivity relative to the lower interlayer dielectric layer 131 and the conductive layer. A portion of the conductive layer may be removed while retaining the lower interlayer dielectric layer 131. Therefore, the first via VI 1 may be formed by the conductive layer to be located at a level lower than the level of the upper surface 131t of the lower interlayer dielectric layer 131.

[0147] According to an embodiment, the formation of the first via VI 1 may include: using selective area growth (SAG) to form the first via VI 1 in the recess RS. For example, the conductive material may be deposited only on the exposed first active contact AC1, the exposed second active contact AC2, and / or the exposed gate contact GC, thereby selectively forming the first via VI 1 only in the recess RS. In this case, since the deposition process can control the height of the first via VI 1, the planarization process may be omitted.

[0148] Reference FIG. 13A to FIG. 13D , a deposition preventing layer 133a may be formed on the upper surface Vit of the first via member VI 1. The deposition preventing layer 133a may not be formed on the lower interlayer dielectric layer 131. For example, the deposition preventing layer 133a may be selectively formed only on the upper surface Vit of the first via member VI 1. According to an embodiment, the deposition preventing layer 133a may be a self-assembled monolayer (SAM). For example, the deposition preventing layer 133a may include octadecylphosphonic acid (ODPA) and / or 1-hexadecanethiol.

[0149] An adhesion layer 133 may be formed on the lower interlayer dielectric layer 131. The adhesion layer 133 may have a constant (e.g., uniform) thickness to cover the upper surface 131t of the lower interlayer dielectric layer 131. In addition, since the upper surface VIt of the first via member VI1 is located at a lower level than the upper surface 131t of the lower interlayer dielectric layer 131, the inner wall of the recess RS may be partially exposed to the outside, so that the adhesion layer 133 may be formed on a portion of the inner wall of the recess RS. For example, the adhesion layer 133 may extend from the upper surface 131t of the lower interlayer dielectric layer 131 to the portion of the inner wall of the recess RS.

[0150] The deposition preventing layer 133a may prevent the adhesion layer 133 from being formed on the upper surface VIt of the first via VI 1. The adhesion layer 133 may expose at least a portion of the upper surface VIt of the first via VI 1. The deposition preventing layer 133a may interfere with the formation of the adhesion layer 133 on the upper surface VIt of the first via VI 1.

[0151] According to an embodiment, the formation of the deposition preventing layer 133a may be omitted. In this case, the adhesion layer 133 may be formed by using selective area growth. For example, the adhesion layer 133 may be formed on the upper surface 131t of the lower interlayer dielectric layer 131 and the outwardly exposed portion of the inner wall of the recess RS.

[0152] Reference FIG. 14A to FIG. 14D , a first wiring layer M1a may be formed on the lower interlayer dielectric layer 131, the first via VI1, and the adhesion layer 133. The first wiring layer M1a may contact the adhesion layer 133 and the upper surface VIt of the first via VI1. The formation of the first wiring layer M1a may include removing the deposition prevention layer 133a. For example, the deposition prevention layer 133a may be removed, and then the first wiring layer M1a may be formed.

[0153] The first wiring layer M1a may be formed using a deposition process. The deposition process may include, for example, one or a combination of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0154] For example, the first wiring layer M1a may include aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), ruthenium (Ru), and / or cobalt (Co), and may include ruthenium (Ru), for example.

[0155] A mask pattern MA may be formed on the first wiring layer M1a. The formation of the mask pattern MA may include forming a photoresist on the first wiring layer M1a and performing an exposure process on the photoresist.

[0156] Reference FIG. 15A to FIG. 15D , the first wiring layer M1a may be patterned to form a first power line M1_R1 (of the first metal layer M1), a second power line M1_R2, and / or a first wiring line M1_I on the lower interlayer dielectric layer 131. For example, the first power line M1_R1, the second power line M1_R2, and the first wiring line M1_I may be formed by the first wiring layer M1a.

[0157] For example, the mask pattern MA may be used as a mask to perform an anisotropic etching process. The anisotropic etching process may remove a portion of the first wiring layer M1a and a portion of the adhesion layer 133. Thus, a portion of the upper surface 131t of the lower interlayer dielectric layer 131 may be exposed to the outside. A portion of the first wiring layer M1a may be removed to form a first power line M1_R1, a second power line M1_R2, and / or a first wiring line M1_I from the first wiring layer M1a. The first metal layer M1 may thus be formed on the second interlayer dielectric layer 120.

[0158] According to an embodiment, the anisotropic etching process may not remove the adhesion layer 133. For example, Figure 6B As shown, the adhesion layer 133 may cover the upper surface 131t of the lower interlayer dielectric layer 131. In this case, the adhesion layer 133 may be used as an etch stop layer for the anisotropic etching process.

[0159] Return to reference FIG. 5A to FIG. 5D An upper interlayer dielectric layer 135 may be formed between the first power line M1_R1 , the second power line M1_R2 , and the first wiring line M1_I and on the lower interlayer dielectric layer 131 .

[0160] A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130, and a second metal layer M2 may be formed on the fourth interlayer dielectric layer 140. The formation of the second metal layer M2 may be substantially the same as the formation of the first metal layer M1.

[0161] However, the inventive concept is not limited to the above discussion. For example, the second metal layer M2 may be formed by a dual damascene process. The lines of the second metal layer M2 and the second via VI2 thereunder may be formed by the same process or the same process sequence (eg, simultaneously).

[0162] FIG. 16A to FIG. 18D A cross-sectional view illustrating a method of fabricating a semiconductor device according to some embodiments of the inventive concept. Fig.16A , Fig.17A and Fig.18A Shown along Figure 4 A cross-sectional view taken along line AA'. Fig. 16B , Fig. 17B and Fig.18B Shown along Figure 4 A cross-sectional view taken along line BB'. Fig. 16C , Fig. 17C and Fig. 18C Shown along Figure 4 A cross-sectional view taken along line CC'. Fig.16D , Fig.17D and Fig.18D Shown along Figure 4 A cross-sectional view taken along line D-D'.

[0163] Reference FIG. 16A to FIG. 16D The recess RS may be formed by patterning the lower interlayer dielectric layer 131 covering the second interlayer dielectric layer 120, the first active contact AC1, the second active contact AC2 and / or the gate contact GC. The second interlayer dielectric layer 120, the first active contact AC1, the second active contact AC2, the gate contact GC may be formed in the same manner as 7A to 15D are essentially the same as those discussed in .

[0164] The formation of the recess RS may include: forming a mask on the lower interlayer dielectric layer 131, performing an anisotropic etching process on the lower interlayer dielectric layer 131 using the mask, and removing the mask. The recess RS may penetrate (e.g., at least partially penetrate or extend into) the lower interlayer dielectric layer 131 to expose one of the first active contact AC1, the second active contact AC2, and / or the gate contact GC to the outside. On the upper surface 131t of the lower interlayer dielectric layer 131, the width of the recess RS may decrease as the distance from the second interlayer dielectric layer 120 decreases, but the inventive concept is not limited thereto.

[0165] A deposition preventing layer 133a may be formed on the exposed first active contact AC1, the exposed second active contact AC2, and / or the exposed gate contact GC. The deposition preventing layer 133a may be formed on the upper surfaces of the first active contact AC1, the second active contact AC2, and the gate contact GC, and may not be formed on any of the inner wall (inner sidewall) of the recess RS and the upper surface 131t of the lower interlayer dielectric layer 131. For example, the deposition preventing layer 133a may be selectively formed only on the upper surfaces of the first active contact AC1, the second active contact AC2, and the gate contact GC. According to an embodiment, the deposition preventing layer 133a may be a self-assembled monolayer (SAM). For example, the deposition preventing layer 133a may include octadecylphosphonic acid (ODPA) and 1-hexadecanethiol.

[0166] An adhesion layer 133 may be formed on the lower interlayer dielectric layer 131. The adhesion layer 133 may have a constant (e.g., uniform) thickness to cover the lower interlayer dielectric layer 131. For example, the adhesion layer 133 may cover the upper surface 131t of the lower interlayer dielectric layer 131 and the inner wall (e.g., inner sidewall) of the recess RS.

[0167] The deposition preventing layer 133a may prevent the adhesion layer 133 from being formed on the upper surfaces of the first active contact AC1, the second active contact AC2, and the gate contact GC. In this configuration, the adhesion layer 133 may expose the upper surfaces of the first active contact AC1, the second active contact AC2, and the gate contact GC. The deposition preventing layer 133a may interfere with the formation of the adhesion layer 133 on the upper surfaces of the first active contact AC1, the second active contact AC2, and the gate contact GC.

[0168] According to an embodiment, the formation of the deposition prevention layer 133a may be omitted. In this case, the adhesion layer 133 may be formed by using selective area growth. The adhesion layer 133 may be formed only on the upper surface 131t of the lower interlayer dielectric layer 131 and the exposed inner wall (e.g., inner sidewall) of the recess RS, and may not be formed on the upper surfaces of the first active contact AC1, the second active contact AC2, and the gate contact GC.

[0169] Reference FIG. 17A to FIG. 17B After removing the deposition prevention layer 133a, the first via VI1 and the first wiring layer M1a may be formed on the adhesion layer 133 (e.g., covering the adhesion layer 133 or overlapping with it) and fill (e.g., at least partially fill) the recess RS. The first via VI1 and the first wiring layer M1a may be formed by one or a combination of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). The first via VI1 may include, for example, ruthenium (Ru) and molybdenum (Mo), and the first wiring layer M1a may include, for example, ruthenium (Ru).

[0170] According to an embodiment, a first via VI 1 may be formed in the recess RS using selective area growth (SAG), and then a first wiring layer M1a may be formed on the first via VI and the upper surface 131t of the lower interlayer dielectric layer 131. The first wiring layer M1a may be formed by using, for example, a physical vapor deposition (PVD) process. For example, the first via VI 1 and the first wiring layer M1a may be formed by deposition processes different from each other. In this case, a visible interface VIt may be provided between the first via VI 1 and the first wiring layer M1a. The interface VIt between the first via VI 1 and the first wiring layer M1a may be substantially the same as the upper surface VIt of the first via VI 1.

[0171] According to one embodiment, the first via VI 1 and the first wiring layer M1a may be formed by an in-situ process. For example, the first via VI 1 and the first wiring layer M1a may be formed to constitute a single object. In this case, the first via VI 1 and the first wiring layer M1a may include the same metal material. Therefore, an invisible interface VIt (or no interface) may be provided between the first via VI 1 and the first wiring layer M1a.

[0172] Reference 18A to 18D , the first wiring layer M1a may be patterned to form a first power line M1_R1, a second power line M1_R2, and a first wiring circuit M1_I on the lower interlayer dielectric layer 131. The first power line M1_R1, the second power line M1_R2, and the first wiring circuit M1_I may be formed in the same manner as FIG. 14A to FIG. 15D The formation discussed in is essentially the same.

[0173] The first wiring line M1_I may be aligned with the first via VI 1, so the upper surface VIt of the first via VI 1 is not exposed to the outside, and the first power line M1_R1 and the second power line M1_R2 may not be aligned with the first via VI 1, so a portion of the upper surface VIt of the first via VI 1 may be exposed to the outside. Therefore, the exposed portion of the upper surface VIt of the first via VI 1 may be removed by the anisotropic etching process used to form the first power line M1_R1, the second power line M1_R2 and the first wiring line M1_I. FIG. 6A to FIG. 6E As shown, the first via member VI 1 may have a via recess VRS.

[0174] The semiconductor device of the present invention may include a via in an interlayer dielectric layer, a wiring line connected to the via, and an adhesion layer. Since the adhesion layer is located between the wiring line and the interlayer dielectric layer, the wiring line can be prevented from peeling off from the adhesion layer. In addition, since the adhesion layer is not included between the via and the wiring line, the resistance between the via and the wiring line can be prevented from increasing.

[0175] Since the upper surface of the via is located at a level lower than the level of the upper surface of the interlayer dielectric layer, a greater distance can be present between the via and other wiring lines that are not connected to the via. Therefore, an unexpected connection (e.g., an unexpected electrical connection) between the via and the wiring line can be prevented. Therefore, a semiconductor memory with improved electrical characteristics and increased reliability can be obtained.

[0176] Although the present invention has been described in conjunction with the embodiments of the present invention shown in the accompanying drawings, it should be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and features of the present invention. Therefore, it should be understood that the above embodiments are illustrative and not restrictive in all aspects.

Claims

1. A semiconductor device, include: a substrate including an active pattern; a channel pattern located on the active pattern; a source / drain pattern electrically connected to the channel pattern; a gate electrode located on the channel pattern; an interlayer dielectric layer located on the gate electrode, wherein the interlayer dielectric layer includes a recess; A via member located in the recessed portion of the interlayer dielectric layer; a wiring line located on the interlayer dielectric layer and electrically connected to the via; as well as an adhesive layer located between the wiring line and the upper surface of the interlayer dielectric layer, The upper surface of the via is closer to the substrate than the upper surface of the interlayer dielectric layer in the first direction. wherein the first direction is perpendicular to the upper surface of the substrate, and Wherein, a portion of the adhesive layer is located on a portion of the inner side wall of the recess.

2. The semiconductor device according to claim 1, in, The wiring line includes a line portion and a protruding portion extending from the line portion in the first direction, wherein the line portion is located on the upper surface of the interlayer dielectric layer, and At least a portion of the protruding portion is located in the concave portion of the interlayer dielectric layer.

3. The semiconductor device according to claim 2, in, The protruding portion of the wiring line is in contact with an upper surface of the via.

4. The semiconductor device according to claim 1, in, An upper surface of the via has a shape that protrudes toward the wiring line.

5. The semiconductor device according to claim 1, in, At least a portion of an upper surface of the via is exposed to the wiring line through the adhesive layer.

6. The semiconductor device according to claim 1, in, The adhesive layer has a side wall aligned with one side wall of the wiring line.

7. The semiconductor device according to claim 1, in, The via is electrically connected to the source / drain pattern or the gate electrode.

8. The semiconductor device according to claim 1, in, The wiring line includes ruthenium (Ru).

9. The semiconductor device according to claim 1, further comprising a contact between the source / drain pattern and the via or between the gate electrode and the via, in, The contact element comprises: a conductive pattern; and A barrier pattern is located on the sidewall and the lower surface of the conductive pattern.

10. The semiconductor device according to claim 1, in, The channel pattern includes a plurality of semiconductor patterns spaced apart from each other and stacked in the first direction, Wherein, the gate electrode comprises: a plurality of inner electrodes located between adjacent semiconductor patterns among the plurality of semiconductor patterns; and An external electrode is located on an uppermost semiconductor pattern among the plurality of semiconductor patterns.

11. A semiconductor device, include: a substrate including an active pattern; a device isolation layer adjacent to the active pattern; a channel pattern located on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns stacked and spaced apart from each other in a first direction, and wherein the first direction is perpendicular to an upper surface of the substrate; a source / drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode extending around the plurality of semiconductor patterns; an active contact electrically connected to the source / drain pattern; a gate contact electrically connected to the gate electrode; an interlayer dielectric layer located on the active contact and the gate contact, wherein the interlayer dielectric layer includes a recess; a via located in the recess of the interlayer dielectric layer and electrically connected to the active contact or the gate contact; a plurality of wiring lines located on the interlayer dielectric layer; and an adhesive layer located between the interlayer dielectric layer and the plurality of wiring lines, wherein one of the plurality of wiring lines is electrically connected to the via, and The adhesion layer extends from the upper surface of the interlayer dielectric layer to a portion of the inner sidewall of the recess.

12. The semiconductor device according to claim 11, in, In the first direction, an upper surface of the via is lower than an upper surface of the interlayer dielectric layer relative to an upper surface of the substrate.

13. The semiconductor device according to claim 11, in, each of the plurality of wiring lines includes a line portion and a protruding portion extending from the line portion in the first direction, The line portion is spaced apart from an upper surface of the via member in the first direction.

14. The semiconductor device according to claim 13, in, The via and one of the plurality of wiring lines are integrally connected to each other.

15. A method for manufacturing a semiconductor device, the method include: forming an interlayer dielectric layer on the substrate; patterning the interlayer dielectric layer to form a recess; forming a via in the recess; forming an adhesive layer, the adhesive layer being located on a portion of the inner sidewall of the recess and on the upper surface of the interlayer dielectric layer, wherein the adhesive layer exposes the upper surface of the via; forming a wiring layer on the upper surface of the adhesion layer and the via member; as well as patterning the wiring layer to form a plurality of wiring lines, Wherein, in the first direction, the upper surface of the via is lower than the upper surface of the interlayer dielectric layer relative to the upper surface of the substrate, and The first direction is perpendicular to the upper surface of the substrate. 16 . The method according to claim 15 , before forming the adhesion layer, further comprising forming a deposition prevention layer on the via member.

17. The method according to claim 16, in, The deposition preventing layer includes octadecylphosphonic acid (ODPA) and / or 1-hexadecanethiol.

18. The method according to claim 15, in, Forming the via member includes: forming a conductive layer, the conductive layer being located in the recess; and A planarization process is performed on the conductive layer.

19. The method according to claim 15, in, Forming the via includes using selective area growth.

20. The method according to claim 15, in, Forming the plurality of wiring lines includes patterning the adhesion layer.

Images