Active area construction type test unit and polysilicon gate line width roughness test method

Abstract

The invention relates to the technical field of semiconductors, and provides an active area construction type test unit and a polysilicon gate line width roughness test method. The active area constructed test unit comprises an active area and a polysilicon gate, the active area comprises a plurality of mutually isolated active sub-areas, and the plurality of mutually isolated active sub-areas are arranged along the length direction of the polysilicon gate; each active sub-region comprises a source region and a drain region; the source regions and the drain regions of the plurality of active sub-regions are independently connected with metal leads, and the metal leads connected with the source regions and the drain regions of the plurality of active sub-regions are connected with corresponding test keys through a plurality of metal interconnection layers; the line width of each active sub-region can be adjusted, and the length of the polysilicon gate changes along with the adjustment of the line widths of the plurality of active sub-regions. According to the invention, the length of the polysilicon gate can be changed by adjusting the line width of the active region, so that the line width roughness of the polysilicon gate is changed, and the correlation between the line width roughness of the polysilicon gate and an electrical parameter is obtained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an active area configuration test unit and a polysilicon gate line width roughness test method. Background Art

[0002] Polysilicon gate is an important structure that controls the opening and closing of MOS devices. The line width of polysilicon gate will affect the electrical parameters of MOS devices. Due to the limitations of lithography technology and fluctuations in manufacturing process parameters in the chip manufacturing process, the line width of polysilicon gate will be uneven or the surface will be uneven, which will lead to many negative effects such as unstable device current characteristics, threshold voltage drift, and increased leakage current.

[0003] Testkey is a test unit that is added to a fixed position on the wafer during the chip manufacturing process to monitor whether the chip manufacturing process is healthy and whether the device performance is normal. Testkey needs to be designed during the tape-out (trial production) process to monitor the electrical properties of MOS devices in the polysilicon gate line width pull-off experiment.

[0004] In the prior art, the electrical data of devices with different polysilicon gate line widths are obtained by pulling the line width of the polysilicon gate, and the influence of the overall line width of the polysilicon gate on the electrical data can be analyzed. However, in reality, due to the differences in the line width roughness of the polysilicon gate, even devices with the same overall polysilicon gate line width exhibit different electrical properties.

[0005] At present, the Testkey designed during the tape-out process can monitor the electrical properties of the MOS device in the overall polysilicon gate line width deviation experiment, but it cannot effectively evaluate the line width roughness (LWR) of the polysilicon gate. As a result, the line width roughness of the polysilicon gate measured online cannot match the final electrical results, and the source of the electrical difference cannot be analyzed. Summary of the invention

[0006] In order to solve the above technical defects, the present invention provides an active area configuration test unit and a polysilicon gate line width roughness test method.

[0007] On one hand, the present invention provides an active region configuration test unit, comprising an active region and a polysilicon gate located above the active region, wherein the polysilicon gate is connected to a corresponding test key, wherein the active region comprises a plurality of mutually isolated active sub-regions, and the plurality of mutually isolated active sub-regions are arranged along the length direction of the polysilicon gate;

[0008] Each active sub-region includes a source region and a drain region;

[0009] The source regions and drain regions of the multiple active sub-regions are connected to metal leads separately, and the metal leads connected to the source regions and drain regions of the multiple active sub-regions are connected to corresponding test keys through a multi-layer metal interconnection layer;

[0010] The line width of each active sub-region is adjustable, and the length of the polysilicon gate changes with the adjustment of the line widths of the multiple active sub-regions.

[0011] In an embodiment of the present invention, the metal lead includes a source metal lead and a drain metal lead;

[0012] The source region of each active sub-region is connected to a corresponding source region metal lead, and the drain region of each active sub-region is connected to a corresponding drain region metal lead.

[0013] In the embodiment of the present invention, every two active sub-regions in the plurality of active sub-regions are isolated from each other by an isolation region.

[0014] In the embodiment of the present invention, the widths of the isolation regions between every two active sub-regions are the same.

[0015] In an embodiment of the present invention, the multi-layer metal interconnection layer includes a plurality of inner metal layers, and the plurality of inner metal layers are interconnected through through holes;

[0016] The metal leads connecting the source region and the drain region of each active sub-region are connected to the multi-layer metal interconnection layer through the contact hole.

[0017] In the embodiment of the present invention, the line width roughness of the polysilicon gate varies according to the length of the polysilicon gate.

[0018] In the embodiment of the present invention, when the line widths of the plurality of active sub-regions increase, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases.

[0019] Another aspect of the present invention provides a method for testing the roughness of a polysilicon gate line width. The method is based on the above-mentioned active area configuration test unit, and the method comprises:

[0020] Adjusting the line width of the active area of ​​the active area configuration test unit so that the length of the polysilicon gate changes following the adjustment of the line width of the active area, so that the line width roughness of the polysilicon gate changes;

[0021] In the process of the polysilicon gate length changing, the corresponding electrical parameters are tested, and the variable of the polysilicon gate length and the corresponding variable of the line width roughness are calculated;

[0022] The electrical performance of the MOS device is evaluated based on the variation of the line width roughness of the polysilicon gate and the corresponding electrical parameters.

[0023] In an embodiment of the present invention, adjusting the line width of the active area of ​​the active area configuration test unit includes:

[0024] Under the condition that the width of the isolation region between every two active sub-regions is ensured to be within a preset value range, the line width of each active sub-region is increased.

[0025] The present invention also provides a chip testing method, the method comprising:

[0026] During the chip manufacturing process, the active area configuration test unit is added to the wafer, and the MOS device in the chip is electrically tested by the active area configuration test unit.

[0027] The active area configuration test unit of the present invention can change the length of the polysilicon gate by adjusting the line width of the active area, thereby changing the line width roughness of the polysilicon gate, and can realize electrical testing of different areas of the same polysilicon gate. By analyzing the electrical data of different polysilicon gate line width roughnesses, the correlation between the polysilicon gate line width roughness and the electrical parameters is obtained, thereby analyzing the source of the electrical difference, providing a basis for the manufacturing process of the polysilicon gate.

[0028] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0030] Figure 1 Schematic diagram of the planar structure of an active area configuration test unit provided in an embodiment of the present invention;

[0031] Figure 2 is a schematic cross-sectional view of a metal interconnect layer in an active area configuration test unit provided in an embodiment of the present invention;

[0032] Figure 3 It is a flow chart of a polysilicon gate line width roughness testing method provided by an embodiment of the present invention.

[0033] Description of Reference Numerals

[0034] 10-polysilicon gate, 11-active sub-region, 12-source region, 13-drain region, 14-isolation region,

[0035] 15-source metal lead, 16-drain metal lead, 20-metal interconnect layer, 30-test key,

[0036] 21a-first inner metal layer, 21b-second inner metal layer, 21c-third inner metal layer,

[0037] 22a / 22b-through hole, 23-contact hole. DETAILED DESCRIPTION

[0038] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "surface", "bottom", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, "multiple" means at least two, such as two, three, etc.

[0040] In the present invention, unless otherwise clearly specified and limited, the terms such as "interconnection / interconnection", "connection", "connection" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] In the process of realizing the present invention, the inventors found that the Testkey designed during the tape-out process can monitor the electrical properties of the MOS device in the overall polysilicon gate line width pull-off experiment, but cannot effectively evaluate the line width roughness of the polysilicon gate, making it impossible for the line width roughness of the polysilicon gate measured online to match the final electrical properties results.

[0042] In view of the above problems, an embodiment of the present invention provides an active area configuration test unit, including an active area and a polysilicon gate located above the active area, the polysilicon gate is connected to a corresponding test key (PAD), the active area includes a plurality of mutually isolated active sub-areas, and the plurality of mutually isolated active sub-areas are arranged along the length direction of the polysilicon gate. Each active sub-area includes a source area and a drain area. The source areas and drain areas of the plurality of active sub-areas are separately connected to metal leads, and the metal leads connected to the source areas and drain areas of the plurality of active sub-areas are connected to the corresponding test keys through a multi-layer metal interconnection layer. The line width of each active sub-area can be adjusted, and the length of the polysilicon gate changes with the adjustment of the line width of the plurality of active sub-areas, so that the line width roughness of the polysilicon gate changes. The active area configuration test unit of the present invention can change the length of the polysilicon gate by adjusting the line width of the active area, thereby changing the line width roughness of the polysilicon gate, and can realize electrical testing of different areas of the same polysilicon gate. By analyzing the electrical data of different polysilicon gate line width roughnesses, the correlation between the polysilicon gate line width roughness and the electrical parameters is obtained, thereby analyzing the source of the electrical difference, providing a basis for the manufacturing process of the polysilicon gate.

[0043] like Figure 1 As shown, the active region configuration test unit provided in the embodiment of the present invention includes an active region and a polysilicon gate 10 located above the active region, the polysilicon gate 10 is connected to the corresponding test key 30, and the active region includes four mutually isolated active sub-regions 11, and the four mutually isolated active sub-regions 11 are arranged along the length direction of the polysilicon gate 10. Every two active sub-regions are isolated from each other by an isolation region 14. Each active sub-region includes a source region 12 and a drain region 13. It should be noted that the number of active sub-regions can be divided or set according to the actual test scenario, and is not limited to the number of active sub-regions in this embodiment.

[0044] Reference Figure 1 The source regions 12 and drain regions 13 of the four active sub-regions are connected to metal leads separately, and the metal leads connected to each active sub-region are connected to corresponding test keys (the test keys corresponding to the source region and the drain region are not shown in the drawings) through a multi-layer metal interconnection layer. The metal leads include source region metal leads 15 and drain region metal leads 16. The source region 12 of each active sub-region is connected to the corresponding source region metal lead 15 separately, and the drain region 13 of each active sub-region is connected to the corresponding drain region metal lead 16 separately.

[0045] The multi-layer metal interconnection layer includes multiple inner metal layers, and the multiple inner metal layers are interconnected through through holes. Figure 2In this embodiment, the multi-layer metal interconnection layer 20 includes a first inner metal layer 21a, a second inner metal layer 21b, and a third inner metal layer 21c. The first inner metal layer 21a and the second inner metal layer 21b are connected via a through hole 22a, and the second inner metal layer 21b and the third inner metal layer 21c are connected via a through hole 22b. The metal leads ( Figure 2 The metal interconnection layer 20 is connected to the metal interconnection layer 20 through the contact hole 23.

[0046] In this embodiment, the source region and drain region of each active sub-region are connected to the corresponding test key (PAD) through different metal interconnection layers. In order to collect the line width roughness of different polysilicon gates as much as possible, the line width of each active sub-region is pulled to be biased, which will cause the spacing between adjacent active sub-regions to be relatively small, which means that the spacing between the metal leads above each active sub-region is also relatively small. If the metal leads of the same layer are used to lead out the source and drain regions of different active sub-regions, it may cause short circuits between the metal leads, thereby causing the device to be scrapped. Therefore, the present invention uses different metal connection layers to lead out the source and drain regions of different active sub-regions to detect the non-uniformity of the polysilicon gate line width.

[0047] In the prior art, to verify the correlation between the polysilicon gate line width roughness and electrical parameters, it is necessary to collect data from at least two MOS devices with the same polysilicon gate line width design. However, in the actual manufacturing process, the average line width and line width roughness of the polysilicon gate in these two MOS devices may be different, so it is impossible to determine which variable causes the change in the electrical parameters.

[0048] In the embodiment of the present invention, the line width of each active sub-region can be adjusted, and the length of the polysilicon gate changes with the adjustment of the line width of multiple active sub-regions, so that the line width roughness of the polysilicon gate changes. The variable of the length of the polysilicon gate can be determined according to the variable of the line width of multiple active sub-regions. The line width roughness of the polysilicon gate changes according to the change of the length of the polysilicon gate. When the line width of multiple active sub-regions increases, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases. The active region configuration test unit of the present invention is used to ensure that the electrical parameters of multiple MOS devices are measured in the same device. Since it is the same device, the average line width is the same, so only the influence of the line width roughness on the electrical properties can be considered. In order to adjust the difference in line width roughness, the present invention introduces a variable of the line width of the active area. The line width of the active area determines the length of the polysilicon gate mounted on the active area. The length of the polysilicon gate is different, and its line width roughness is also different. Therefore, a roughness pull-off variable can be introduced to make the change degree of related electrical properties more drastic, and the corresponding relationship between the line width roughness and the electrical parameters can be found.

[0049] In an optional embodiment, the width of the isolation region between every two active sub-regions in the plurality of active sub-regions is the same, so as to facilitate biasing the line width of each active sub-region and obtain data of a plurality of MOS devices with the same polysilicon gate line width design.

[0050] The embodiment of the present invention also provides a polysilicon gate line width roughness test method, which is based on the above-mentioned active area configuration test unit. Figure 3 As shown, the polysilicon gate line width roughness testing method comprises the following steps:

[0051] S301, adjusting the line width of the active area of ​​the active area configuration test unit, so that the length of the polysilicon gate changes following the adjustment of the line width of the active area, so that the line width roughness of the polysilicon gate changes;

[0052] S302, in the process of the length of the polysilicon gate changing, testing the corresponding electrical parameters, and calculating the variable of the length of the polysilicon gate and the corresponding variable of the line width roughness;

[0053] S303 , evaluating the electrical performance of the MOS device according to the variable of the line width roughness of the polysilicon gate and the corresponding electrical parameters.

[0054] In the above step S301, adjusting the line width of the active area of ​​the active area configuration test unit specifically includes: increasing the line width of each active sub-area while ensuring that the width of the isolation area between every two active sub-areas meets the preset value range.

[0055] In the prior art, to verify the correlation between the polysilicon gate line width roughness and electrical parameters, it is necessary to collect data from at least two MOS devices with the same polysilicon gate line width design. However, in the actual manufacturing process, the average line width and line width roughness of the polysilicon gate in these two MOS devices may be different, so it is impossible to determine which variable causes the change in electrical parameters. The present invention uses an active area configuration test unit to perform a polysilicon gate line width roughness test method. The line width of each active sub-area in the active area configuration test unit is adjustable, and the variable of the length of the polysilicon gate can be determined according to the variable of the line width of multiple active sub-areas. The electrical parameters of multiple MOS devices can be measured in the same device, and the average line width of the polysilicon gate in the same device is the same, so only the influence of the line width roughness on the electrical properties can be considered. In order to adjust the difference in line width roughness, the present invention introduces a variable of the line width of the active area. The line width of the active area determines the length of the polysilicon gate mounted on the active area. The length of the polysilicon gate is different, and its line width roughness is also different. Therefore, a roughness pull-off variable can be introduced to make the change degree of related electrical properties more drastic, and the corresponding relationship between the line width roughness and the electrical parameters can be found.

[0056] After the integrated circuit design is completed, in order to test whether the designed circuit meets the performance and functional requirements, the designer will first produce several to dozens of chip samples for testing. This process involves manufacturing chips on the assembly line (tapeout) through a series of process steps. The chip can only enter the mass production stage after passing the tapeout test.

[0057] An embodiment of the present invention also provides a chip testing method, which includes: adding an active area configuration test unit to a wafer during a chip (tape-out) manufacturing process, and performing electrical testing on MOS devices in the chip through the active area configuration test unit.

[0058] The active area configuration test unit includes an active area and a polysilicon gate located above the active area, the polysilicon gate is connected to a corresponding test key (PAD), the active area includes a plurality of mutually isolated active sub-areas, and the plurality of mutually isolated active sub-areas are arranged along the length direction of the polysilicon gate. Every two active sub-areas are isolated from each other by an isolation area. Each active sub-area includes a source area and a drain area. The source areas and drain areas of the plurality of active sub-areas are individually connected to metal leads, and the metal leads connected to the source areas and drain areas of the plurality of active sub-areas are connected to the corresponding test keys through a multi-layer metal interconnection layer. The line width of each active sub-area can be adjusted, and the length of the polysilicon gate changes with the adjustment of the line width of the plurality of active sub-areas, so that the line width roughness of the polysilicon gate changes. The metal leads include source area metal leads and drain area metal leads, the source area of ​​each active sub-area is individually connected to the corresponding source area metal lead, and the drain area of ​​each active sub-area is individually connected to the corresponding drain area metal lead. The multi-layer metal interconnection layer includes multiple inner metal layers, and the multiple inner metal layers are interconnected through through holes. The metal leads connecting the source region and the drain region of each active sub-region are connected to the multi-layer metal interconnection layer through contact holes.

[0059] The source and drain regions of each active sub-region in the active region configuration test unit are connected to the corresponding PAD through different metal leads. The source and drain regions of different active sub-regions are led out using a multi-layer metal interconnect layer, so that the non-uniformity of the polysilicon gate line width can be detected.

[0060] The line width of each active sub-region in the active sub-region configuration test unit can be adjusted, and the length of the polysilicon gate changes with the adjustment of the line width of multiple active sub-regions, so that the line width roughness of the polysilicon gate changes. The variable of the length of the polysilicon gate can be determined according to the variable of the line width of multiple active sub-regions. The line width roughness of the polysilicon gate changes according to the change of the length of the polysilicon gate. When the line width of multiple active sub-regions increases, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases. The use of the active sub-region configuration test unit can ensure that the electrical parameters of multiple MOS devices are measured in the same device. Since it is the same device, the average line width is the same, so only the influence of the line width roughness on the electrical properties can be considered. In order to adjust the difference in line width roughness, the present invention introduces a variable of the line width of the active area. The line width of the active area determines the length of the polysilicon gate mounted on the active area. The length of the polysilicon gate is different, and its line width roughness is also different. Therefore, a roughness pull-off variable can be introduced to make the change degree of related electrical properties more drastic, and the corresponding relationship between the line width roughness and the electrical parameters can be found.

[0061] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An active area structured test unit, comprising an active area and a polysilicon gate located above the active area, wherein the polysilicon gate is connected to a corresponding test key, characterized in that: The active region includes a plurality of mutually isolated active sub-regions, and the plurality of mutually isolated active sub-regions are arranged along the length direction of the polysilicon gate; Each active sub-region includes a source region and a drain region; The source regions and drain regions of the multiple active sub-regions are connected to metal leads separately, and the metal leads connected to the source regions and drain regions of the multiple active sub-regions are connected to corresponding test keys through a multi-layer metal interconnection layer; The line width of each active sub-region is adjustable, and the length of the polysilicon gate changes with the adjustment of the line widths of the multiple active sub-regions.

2. The active area configuration test unit according to claim 1, characterized in that: The metal leads include source metal leads and drain metal leads; The source region of each active sub-region is connected to a corresponding source region metal lead, and the drain region of each active sub-region is connected to a corresponding drain region metal lead.

3. The active area configuration test unit according to claim 1, characterized in that: Every two active sub-regions in the plurality of active sub-regions are isolated from each other by an isolation region.

4. The active area configuration test unit according to claim 3, characterized in that: The width of the isolation region between every two active sub-regions is the same.

5. The active area configuration test unit according to claim 1, characterized in that: The multi-layer metal interconnection layer includes a plurality of inner metal layers, and the plurality of inner metal layers are interconnected through through holes; The metal leads connecting the source region and the drain region of each active sub-region are connected to the multi-layer metal interconnection layer through the contact hole.

6. The active area configuration test unit according to claim 1, characterized in that: The line width roughness of the polysilicon gate varies according to the length of the polysilicon gate.

7. The active area configuration test unit according to claim 6, characterized in that: When the line widths of the multiple active sub-regions increase, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases.

8. A method for testing the width roughness of a polysilicon gate line, characterized in that: The method is based on the active-division-type test unit according to any one of claims 1 to 7, and the method comprises: Adjusting the line width of the active area of ​​the active area configuration test unit so that the length of the polysilicon gate changes following the adjustment of the line width of the active area, so that the line width roughness of the polysilicon gate changes; In the process of the polysilicon gate length changing, the corresponding electrical parameters are tested, and the variable of the polysilicon gate length and the corresponding variable of the line width roughness are calculated; The electrical performance of the MOS device is evaluated based on the variation of the line width roughness of the polysilicon gate and the corresponding electrical parameters.

9. The polysilicon gate line width roughness testing method according to claim 8, characterized in that: Adjusting the line width of the active area of ​​the active area configuration test unit includes: Under the condition that the width of the isolation region between every two active sub-regions is ensured to be within a preset value range, the line width of each active sub-region is increased.

10. A chip testing method, characterized in that: include: During the chip manufacturing process, the active area configuration test unit according to any one of claims 1 to 7 is added to the wafer, and the MOS device in the chip is electrically tested by the active area configuration test unit.

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