Active region split test unit, polysilicon gate line width roughness test method

Abstract

The present invention relates to the field of semiconductor technology, and provides an active region split-structured test unit and a method for testing the line width roughness of a polysilicon gate. The active region split-structured test unit includes an active region and a polysilicon gate. The active region includes a plurality of mutually isolated active sub-regions, and the plurality of mutually isolated active sub-regions are arranged along the length direction of the polysilicon gate; each active sub-region includes a source region and a drain region; the source regions and drain regions of the plurality of active sub-regions are separately connected to metal leads, and the metal leads connected to the source regions and drain regions of the plurality of active sub-regions are connected to corresponding test keys through a multi-layer metal interconnection layer; the line width of each active sub-region can be adjusted, and the length of the polysilicon gate changes following the adjustment of the line widths of the plurality of active sub-regions. The present invention can change the length of the polysilicon gate by adjusting the line width of the active region, so as to change the line width roughness of the polysilicon gate, and obtain the correlation between the line width roughness of the polysilicon gate and the electrical parameters.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a heterogeneous test unit for an active region and a method for measuring the line width roughness of a polysilicon gate. Background Art

[0002] The polysilicon gate is an important structure for controlling the turn-on and turn-off of MOS devices, and the line width of the polysilicon gate affects the electrical parameters of MOS devices. Due to problems such as limitations in lithography technology and fluctuations in manufacturing process parameters during chip manufacturing, the line width of the polysilicon gate may be uneven or the surface may be uneven, which may lead to many negative effects such as unstable device current characteristics, threshold voltage drift, and increased leakage current.

[0003] Testkey is a test unit added at a fixed position on a wafer during the chip manufacturing process to monitor whether the chip manufacturing process is healthy and whether the device performance is normal. During the wafer run (trial production) process, Testkey needs to be designed to monitor the electrical properties of MOS devices in the polysilicon gate line width biasing experiment.

[0004] In the prior art, by biasing the line width of the polysilicon gate to obtain electrical property data of devices with different polysilicon gate line widths, the influence of the overall line width of the polysilicon gate on the electrical property data can be analyzed. However, in fact, due to the difference in the line width roughness of the polysilicon gate, even devices with the same overall polysilicon gate line width may exhibit different electrical performances.

[0005] Currently, the Testkey designed during the wafer run process can monitor the electrical properties of MOS devices in the overall polysilicon gate line width biasing experiment, but it cannot effectively evaluate the line width roughness (LWR) of the polysilicon gate, resulting in the inability to match the line width roughness of the polysilicon gate measured online with the final electrical property results and the inability to analyze the source of the electrical property differences. Summary of the Invention

[0006] To solve the above technical deficiencies, the present invention provides a heterogeneous test unit for an active region and a method for measuring the line width roughness of a polysilicon gate.

[0007] On the one hand, the present invention provides a heterogeneous test unit for an active region, including an active region and a polysilicon gate located above the active region. The polysilicon gate is connected to a corresponding test key. The active region includes a plurality of mutually isolated active sub-regions, and the plurality of mutually isolated active sub-regions are arranged along the length direction of the polysilicon gate;

[0008] Each active sub-region includes a source region and a drain region;

[0009] The source regions and drain regions of multiple active sub-regions are separately connected to metal leads, and the metal leads connected to the source regions and drain regions of the multiple active sub-regions are connected to corresponding test pads through multiple layers of metal interconnect layers;

[0010] The line width of each active sub-region is adjustable, and the length of the polysilicon gate changes following the adjustment of the line widths of the multiple active sub-regions.

[0011] In an embodiment of the present invention, the metal leads include source region metal leads and drain region metal leads;

[0012] The source region of each active sub-region is connected to the corresponding source region metal lead, and the drain region of each active sub-region is connected to the corresponding drain region metal lead.

[0013] In an embodiment of the present invention, every two active sub-regions among the multiple active sub-regions are isolated from each other by isolation regions.

[0014] In an embodiment of the present invention, the widths of the isolation regions between every two active sub-regions are the same.

[0015] In an embodiment of the present invention, the multiple layers of metal interconnect layers include multiple inner metal layers, and the multiple inner metal layers are interconnected through vias;

[0016] The metal leads connected to the source regions and drain regions of each active sub-region are connected to the multiple layers of metal interconnect layers through contact holes.

[0017] In an embodiment of the present invention, the line width roughness of the polysilicon gate changes according to the change in the length of the polysilicon gate.

[0018] In an embodiment of the present invention, when the line widths of the multiple active sub-regions increase, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases.

[0019] On the other hand, the present invention provides a method for testing the line width roughness of a polysilicon gate. This method is based on the above-mentioned active region split-structured test unit, and the method includes:

[0020] Adjust the line width of the active region of the active region split-structured test unit, so that the length of the polysilicon gate changes following the adjustment of the line width of the active region, so as to change the line width roughness of the polysilicon gate;

[0021] During the process of the change in the length of the polysilicon gate, test the corresponding electrical parameters, and calculate the variable of the length of the polysilicon gate and the corresponding variable of the line width roughness;

[0022] Evaluate the electrical performance of the MOS device according to the variable of the line width roughness of the polysilicon gate and the corresponding electrical parameters.

[0023] In an embodiment of the present invention, adjusting the line width of the active region of the active region split-structured test unit includes:

[0024] While ensuring that the width of the isolation region between every two active sub-regions meets the preset value range, increase the line width of each active sub-region.

[0025] The present invention also provides a chip testing method, which includes:

[0026] During the chip manufacturing process, add the above-mentioned active region split-type test unit into the wafer, and perform electrical testing on the MOS devices in the chip through the active region split-type test unit.

[0027] The active region split-type test unit of the present invention can change the length of the polysilicon gate by adjusting the line width of the active region, thereby changing the line width roughness of the polysilicon gate, and can realize the electrical testing of different regions of the same polysilicon gate. By analyzing the electrical data of the line width roughness of different polysilicon gates, the correlation between the line width roughness of the polysilicon gate and the electrical parameters can be obtained, so as to analyze the source of the electrical difference and provide a basis for the manufacturing process of the polysilicon gate.

[0028] Other features and advantages of the technical solution of the present invention will be described in detail in the following specific implementation section. Description of the Drawings

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0030] Figure 1 is a schematic plan view of the active region split-type test unit provided by an embodiment of the present invention;

[0031] Figure 2 is a schematic cross-sectional view of the metal interconnection layer in the active region split-type test unit provided by an embodiment of the present invention;

[0032] Figure 3 is a flowchart of the polysilicon gate line width roughness testing method provided by an embodiment of the present invention.

[0033] Description of the Reference Numerals

[0034] 10 - polysilicon gate, 11 - active sub-region, 12 - source region, 13 - drain region, 14 - isolation region,

[0035] 15 - source region metal lead, 16 - drain region metal lead, 20 - metal interconnection layer, 30 - test key,

[0036] 21a - first layer of inner layer metal, 21b - second layer of inner layer metal, 21c - third layer of inner layer metal,

[0037] 22a / 22b - via holes, 23 - contact holes. Detailed implementation manners

[0038] In order to make the technical solutions and advantages in the embodiments of the present invention clearer and more understandable, the following further details the exemplary embodiments of the present invention with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0039] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "surface", "bottom surface", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc.

[0040] In the present invention, unless otherwise clearly defined and limited, terms such as "interconnect / interconnection", "connected", "connection", etc. should be understood in a broad sense. For example, it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0041] In the process of implementing the present invention, the inventor found that the Testkey designed in the chip manufacturing process can monitor the electrical properties of MOS devices in the overall polysilicon gate line width pull - deviation experiment, but it cannot effectively evaluate the line width roughness of the polysilicon gate, resulting in the inability to match the line width roughness of the polysilicon gate measured online with the final electrical results.

[0042] In view of the above problems, an active region differentiated structure test unit provided by an embodiment of the present invention includes an active region and a polysilicon gate located above the active region. The polysilicon gate is connected to a corresponding test key (PAD). The active region includes a plurality of mutually isolated active sub-regions, and the plurality of mutually isolated active sub-regions are arranged along the length direction of the polysilicon gate. Each active sub-region includes a source region and a drain region. The source regions and drain regions of the plurality of active sub-regions are separately connected to metal leads, and the metal leads connected to the source regions and drain regions of the plurality of active sub-regions are connected to the corresponding test keys through a multi-layer metal interconnection layer. The line width of each active sub-region can be adjusted, and the length of the polysilicon gate changes following the adjustment of the line widths of the plurality of active sub-regions, so that the line width roughness of the polysilicon gate changes. The active region differentiated structure test unit of the present invention can change the length of the polysilicon gate by adjusting the line width of the active region, thereby changing the line width roughness of the polysilicon gate, and can realize the electrical test of different regions of the same polysilicon gate. By analyzing the electrical data of the line width roughness of different polysilicon gates, the correlation between the line width roughness of the polysilicon gate and the electrical parameters can be obtained, so as to analyze the source of the electrical difference and provide a basis for the manufacturing process of the polysilicon gate.

[0043] As Figure 1 shown, the active region differentiated structure test unit provided by an embodiment of the present invention includes an active region and a polysilicon gate 10 located above the active region. The polysilicon gate 10 is connected to a corresponding test key 30. The active region includes four mutually isolated active sub-regions 11, and the four mutually isolated active sub-regions 11 are arranged along the length direction of the polysilicon gate 10. Each two active sub-regions are isolated from each other by an isolation region 14. Each active sub-region includes a source region 12 and a drain region 13. It should be noted that the number of active sub-regions can be divided or set according to the actual test scenario, and is not limited to the number of active sub-regions in this embodiment.

[0044] Referring to Figure 1 , the source regions 12 and drain regions 13 of the four active sub-regions are separately connected to metal leads, and the metal leads connected to each active sub-region are connected to the corresponding test keys through a multi-layer metal interconnection layer (the test keys corresponding to the source regions and drain regions are not shown in the drawings). The metal leads include a source region metal lead 15 and a drain region metal lead 16. The source region 12 of each active sub-region is separately connected to the corresponding source region metal lead 15, and the drain region 13 of each active sub-region is separately connected to the corresponding drain region metal lead 16.

[0045] The multi-layer metal interconnection layer includes a plurality of inner metal layers, and the plurality of inner metal layers are interconnected through vias. Referring to Figure 2, in this embodiment, the multi-layer metal interconnect layer 20 includes a first inner-layer metal 21a, a second inner-layer metal 21b, and a third inner-layer metal 21c. The first inner-layer metal 21a is connected to the second inner-layer metal 21b through a via 22a, and the second inner-layer metal 21b is connected to the third inner-layer metal 21c through a via 22b. The metal leads ( Figure 2 not shown) connected to the source regions 12 and drain regions 13 of each active sub-region are connected to the metal interconnect layer 20 through contact holes 23.

[0046] In this embodiment, the source and drain regions of each active sub-region are connected to the corresponding test pads (PADs) through different metal interconnect layers. In order to collect the line width roughness of different polysilicon gates as much as possible, the line widths of each active sub-region are offset, which results in a relatively small distance between adjacent active sub-regions. This means that the distance between the metal leads above each active sub-region is also relatively small. If the same layer of metal leads is used to lead out the source and drain regions of different active sub-regions, it may cause a short circuit between the metal leads, resulting in device failure. Therefore, the present invention uses different metal connection layers to lead out the source and drain regions of different active sub-regions to detect the non-uniformity of the polysilicon gate line width.

[0047] In the prior art, to verify the correlation between the polysilicon gate line width roughness and electrical parameters, it is necessary to collect data of at least two MOS devices with the same polysilicon gate line width design. However, in the actual manufacturing process, the average line width and line width roughness of the polysilicon gates in these two MOS devices may be different, so it is impossible to determine which variable causes the change in electrical parameters.

[0048] In the embodiment of the present invention, the line width of each active sub-region can be adjusted, and the length of the polysilicon gate changes following the adjustment of the line widths of multiple active sub-regions, so that the line width roughness of the polysilicon gate changes. The variable of the length of the polysilicon gate can be determined according to the variables of the line widths of multiple active sub-regions. The line width roughness of the polysilicon gate changes according to the change in the length of the polysilicon gate. When the line widths of multiple active sub-regions increase, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases. By using the active region split-type test unit of the present invention, it is possible to ensure that the electrical parameters of multiple MOS devices are measured in the same device. Since it is the same device and the average line width is the same, only the influence of the line width roughness on the electricity can be considered. In order to adjust the difference in line width roughness, the present invention introduces a variable of the active region line width. The line width of the active region determines the length of the polysilicon gate carried on the active region, and different lengths of the polysilicon gate result in different line width roughnesses. Therefore, a variable of roughness offset can be introduced to make the change degree of the relevant electricity more intense and find the corresponding relationship between the line width roughness and the electrical parameters more easily.

[0049] In an alternative embodiment, the width of the isolation region between every two active sub-regions among the multiple active sub-regions is the same. This facilitates the biasing of the line widths of the respective active sub-regions, and data of MOS devices with multiple identical polysilicon gate line width designs can be obtained.

[0050] An embodiment of the present invention further provides a method for testing the roughness of a polysilicon gate line width, and this method is based on the above-mentioned active region split-structured test unit. As Figure 3 shown, the method for testing the roughness of a polysilicon gate line width includes the following steps:

[0051] S301, adjust the line width of the active region of the active region split-structured test unit, so that the length of the polysilicon gate changes following the adjustment of the line width of the active region, so as to change the roughness of the polysilicon gate line width;

[0052] S302, during the process of the change in the length of the polysilicon gate, test the corresponding electrical parameters, and calculate the variable of the length of the polysilicon gate and the variable of the corresponding line width roughness;

[0053] S303, evaluate the electrical performance of the MOS device according to the variable of the roughness of the polysilicon gate line width and the corresponding electrical parameters.

[0054] In the above step S301, adjusting the line width of the active region of the active region split-structured test unit specifically includes: increasing the line widths of the respective active sub-regions on the premise that the width of the isolation region between every two active sub-regions meets the preset value range.

[0055] In the prior art, to verify the correlation between the roughness of the polysilicon gate line width and the electrical parameters, data of at least two MOS devices with the same polysilicon gate line width design need to be obtained. However, in the actual manufacturing process, the average line width and the line width roughness of the polysilicon gates in these two MOS devices may be different, so it is impossible to determine which variable causes the change in the electrical parameters. The present invention adopts an active region split-structured test unit for the method of testing the roughness of the polysilicon gate line width. The line width of each active sub-region in the active region split-structured test unit can be adjusted, and the variable of the length of the polysilicon gate can be determined according to the variables of the line widths of the multiple active sub-regions. The electrical parameters of multiple MOS devices can be measured in the same device, and the average line width of the polysilicon gate in the same device is the same. Therefore, only the influence of the line width roughness on the electricity can be considered. In order to adjust the differences in the line width roughness, the present invention introduces the variable of the active region line width. The line width of the active region determines the length of the polysilicon gate carried on the active region, and different lengths of the polysilicon gate result in different line width roughnesses. Therefore, the variable of the roughness biasing can be introduced, so that the degree of change in the relevant electricity is more intense, and the corresponding relationship between the line width roughness and the electrical parameters can be found more easily.

[0056] After the integrated circuit design is completed, in order to test whether the designed circuit meets the performance and functional requirements, the designer will first produce several to dozens of chip samples for testing. This process involves manufacturing chips (tape-out) on the production line through a series of process steps. Only when the tape-out test passes can the mass production stage be entered.

[0057] An embodiment of the present invention also provides a chip testing method, which includes: during the chip (tape-out) manufacturing process, a structured test unit with active regions is added to the wafer, and the MOS devices in the chip are electrically tested through this structured test unit with active regions.

[0058] The structured test unit with active regions includes an active region and a polysilicon gate located above the active region. The polysilicon gate is connected to the corresponding test pad (PAD). The active region includes a plurality of mutually isolated active sub-regions, and the plurality of mutually isolated active sub-regions are arranged along the length direction of the polysilicon gate. Each two active sub-regions are isolated from each other by an isolation region. Each active sub-region includes a source region and a drain region. The source regions and drain regions of the plurality of active sub-regions are separately connected to metal leads, and the metal leads connected to the source regions and drain regions of the plurality of active sub-regions are connected to the corresponding test pads through multiple layers of metal interconnect layers. The line width of each active sub-region can be adjusted, and the length of the polysilicon gate changes following the adjustment of the line widths of the plurality of active sub-regions, so that the line width roughness of the polysilicon gate changes. The metal leads include source region metal leads and drain region metal leads. The source region of each active sub-region is separately connected to the corresponding source region metal lead, and the drain region of each active sub-region is separately connected to the corresponding drain region metal lead. The multiple layers of metal interconnect layers include a plurality of inner metal layers, and the plurality of inner metal layers are interconnected through vias. The metal leads connected to the source regions and drain regions of each active sub-region are connected to the multiple layers of metal interconnect layers through contact holes.

[0059] In the structured test unit with active regions, the source region and the drain region of each active sub-region are connected to the corresponding PAD through different metal leads. By using multiple layers of metal interconnect layers to lead out the source and drain regions of different active sub-regions, the non-uniformity of the polysilicon gate line width can be detected.

[0060] The line width of each active sub-region in the active region split-structured test unit can be adjusted. The length of the polysilicon gate changes following the adjustment of the line widths of multiple active sub-regions, causing the line width roughness of the polysilicon gate to change. The variable of the length of the polysilicon gate can be determined according to the variables of the line widths of multiple active sub-regions. The line width roughness of the polysilicon gate changes according to the change in the length of the polysilicon gate. When the line widths of multiple active sub-regions increase, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases. By using this active region split-structured test unit, it is possible to ensure that the electrical parameters of multiple MOS devices are measured in the same device. Since it is the same device and the average line width is the same, only the influence of the line width roughness on the electrical properties needs to be considered. To adjust the differences in line width roughness, the present invention introduces a variable for the line width of the active region. The line width of the active region determines the length of the polysilicon gate carried on the active region, and different lengths of the polysilicon gate result in different line width roughnesses. Therefore, a bias variable for the roughness can be introduced, making the change in the relevant electrical properties more drastic and enabling the establishment of the corresponding relationship between the line width roughness and the electrical parameters.

[0061] The optional embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Additionally, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner as long as the combination does not violate the idea of the embodiments of the present invention, and it should equally be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A method for testing the width roughness of a polysilicon gate line, characterized in that: The method is based on an active region configuration test unit, the active region configuration test unit comprises: an active region and a polysilicon gate located above the active region, the polysilicon gate is connected to a corresponding test key, the active region comprises a plurality of mutually isolated active sub-regions, the plurality of mutually isolated active sub-regions are arranged along the length direction of the polysilicon gate, each active sub-region comprises a source region and a drain region, the source regions and drain regions of the plurality of active sub-regions are separately connected to metal leads, and the metal leads connected to the source regions and drain regions of the plurality of active sub-regions are connected to the corresponding test keys through a multi-layer metal interconnection layer; The method comprises: Adjusting the line width of the active area of ​​the active area configuration test unit so that the length of the polysilicon gate changes following the adjustment of the line width of the active area, so that the line width roughness of the polysilicon gate changes; In the process of the polysilicon gate length changing, the corresponding electrical parameters are tested, and the variable of the polysilicon gate length and the corresponding variable of the line width roughness are calculated; The electrical performance of the MOS device is evaluated based on the variation of the line width roughness of the polysilicon gate and the corresponding electrical parameters.

2. The polysilicon gate line width roughness testing method according to claim 1, characterized in that: Adjusting the line width of the active area of ​​the active area configuration test unit includes: The line widths of multiple active sub-regions of the active region configuration test unit are adjusted, and the line width of each active sub-region is increased while ensuring that the width of the isolation region between every two active sub-regions meets the preset value range.

3. The polysilicon gate line width roughness testing method according to claim 2, characterized in that: When the line width of each active sub-region increases, the length of the polysilicon gate increases, and the line width roughness of the polysilicon gate increases.

4. The polysilicon gate line width roughness testing method according to claim 1, characterized in that: The metal leads include source metal leads and drain metal leads; The source region of each active sub-region is connected to a corresponding source region metal lead, and the drain region of each active sub-region is connected to a corresponding drain region metal lead.

5. The polysilicon gate line width roughness testing method according to claim 1, characterized in that: Every two active sub-regions in the plurality of active sub-regions are isolated from each other by an isolation region.

6. The polysilicon gate line width roughness testing method according to claim 5, characterized in that: The width of the isolation region between every two active sub-regions is the same.

7. The polysilicon gate line width roughness testing method according to claim 1, characterized in that: The multi-layer metal interconnection layer includes a plurality of inner metal layers, and the plurality of inner metal layers are interconnected through through holes; The metal leads connecting the source region and the drain region of each active sub-region are connected to the multi-layer metal interconnection layer through the contact hole.

8. A chip testing method, characterized in that: include: During the chip manufacturing process, an active area configuration test unit is added to the wafer, and the polysilicon gate line width roughness test method according to claim 1 is adopted to perform electrical testing on the MOS devices in the chip through the active area configuration test unit.

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