Semiconductor device

Abstract

A semiconductor device includes: a substrate doped with a first conductivity type impurity; a first well doped with a second conductivity type impurity different from the first conductivity type impurity; a first active region in the first well, the first active region doped with a first conductivity type impurity, and connected to the first pad through a first interconnect; a second active region outside the first well, doped with a second conductivity type impurity, and connected to the second pad through a second interconnect; a third active region surrounding the first active region in the first well and doped with a second conductivity type impurity; and a fourth active region surrounding the second active region outside the first well and doped with a first conductivity type impurity, in which at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnect.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0078162 filed in the Korean Intellectual Property Office on June 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] The semiconductor device may include a plurality of semiconductor elements, and a portion of the plurality of semiconductor elements may include a transmitting circuit for transmitting signals to other external semiconductor devices and a receiving circuit for receiving signals from other external semiconductor devices. The receiving circuit and the transmitting circuit may be connected to a pad for transmitting and receiving signals. In order to protect the semiconductor element from the influence of electrostatic discharge (ESD) that may occur in the pad, the receiving circuit, the transmitting circuit, etc. may be connected to an ESD protection circuit. In order to effectively protect the semiconductor element, it is necessary to implement an ESD protection circuit that operates at an appropriate trigger voltage. Summary of the invention

[0005] According to one aspect of the embodiment, a semiconductor device is provided, including: a substrate doped with a first conductive type impurity; a first well region formed in the substrate and doped with a second conductive type impurity different from the first conductive type impurity; a plurality of first active regions arranged in the first well region, doped with the first conductive type impurity, and connected to a first pad through a first interconnection pattern; a plurality of second active regions arranged outside the first well region in the substrate, doped with the second conductive type impurity, and respectively connected to the second pad through a second interconnection pattern; a plurality of third active regions arranged around the plurality of first active regions in the first well region, and doped with the second conductive type impurity; and a plurality of fourth active regions arranged around the plurality of second active regions outside the first well region of the substrate, and doped with the first conductive type impurity. At least one of the plurality of third active regions and at least one of the plurality of fourth active regions may be electrically connected to each other through a third interconnection pattern.

[0006] According to another aspect of the embodiment, a semiconductor device is provided, including: a substrate doped with a first conductive type impurity; a first well region and a second well region formed in the substrate and doped with a second conductive type impurity different from the first conductive type impurity; a plurality of first active regions arranged in the first well region, doped with the first conductive type impurity, and respectively connected to the first pad through a first interconnection pattern; a plurality of second active regions arranged in the second well region, doped with the second conductive type impurity, and connected to the second pad through a second interconnection pattern; a plurality of third active regions arranged in the first well region around the plurality of first active regions, and doped with the second conductive type impurity; a plurality of fourth active regions arranged between the first well region and the second well region in the substrate, and doped with the first conductive type impurity; a plurality of fifth active regions arranged between the first well region and the second well region in the substrate, and doped with the second conductive type impurity; and a plurality of sixth active regions arranged in the second well region around the plurality of second active regions, and doped with the first conductive type impurity. At least one of the plurality of third active regions and at least one of the plurality of fourth active regions may be electrically connected to each other through a third interconnection pattern. At least one of the plurality of fifth active regions and at least one of the plurality of sixth active regions may be electrically connected to each other through a fourth interconnection pattern.

[0007] According to another aspect of the embodiment, there is provided a semiconductor device, comprising: a first pad, inputting and outputting signals; a second pad, supplied with a reference voltage; a PNP transistor, comprising a first emitter, a first collector and a first base connected to the first pad; and an NPN transistor, comprising a second emitter connected to the second pad, a second collector connected to the first base, and a second base connected to the first collector. The first base may be connected to the second base and connected to a third pad supplied with a power supply voltage through a first diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 is a schematic block diagram illustrating a semiconductor device according to an example embodiment;

[0010] Figure 2 is a schematic diagram showing an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0011] Figure 3 is a diagram showing a structure of an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0012] Figure 4 is along Figure 3A cross-sectional view taken along line II';

[0013] Figure 5 is along Figure 3 A cross-sectional view taken along line II-II';

[0014] Fig. 6A and Figure 6B is a diagram illustrating an operation of an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0015] Figure 7 is a graph illustrating an operation of an ESD protection circuit included in a semiconductor device according to example embodiments;

[0016] Figure 8 is a schematic diagram showing an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0017] Fig. 9 is a diagram showing a structure of an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0018] Fig.10 is along Fig. 9 A cross-sectional view taken along line III-III';

[0019] Fig.11 is a diagram showing a structure of an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0020] Fig.12 is along Fig.11 A cross-sectional view taken along line IV-IV';

[0021] Fig.13 is a diagram showing a structure of an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0022] Fig.14 is along Fig.13 A cross-sectional view taken along line IV-IV';

[0023] Fig.15 is a diagram showing a structure of an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0024] Fig.16A and Fig. 16B are respectively along Fig.15 A cross-sectional view taken along lines V-V' and VI-VI';

[0025] Fig.17 is a diagram showing a structure of an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0026] Fig.18A and Fig.18B are respectively along Fig.17 A cross-sectional view taken along lines V-V' and VI-VI';

[0027] Fig.19 is a schematic diagram showing an ESD protection circuit included in a semiconductor device according to an example embodiment;

[0028] Fig. 20 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments; and

[0029] Fig.21 is along Fig. 20 A cross-sectional view taken along line VII-VII'. DETAILED DESCRIPTION

[0030] Hereinafter, preferred exemplary embodiments among the embodiments will be described with reference to the accompanying drawings.

[0031] Figure 1 is a schematic block diagram illustrating a semiconductor device according to example embodiments.

[0032] refer to Figure 1 , the semiconductor device 10 according to the example embodiment may include signal pads 11 and 12, power pads 13 and 14, a receiving circuit 15, a transmitting circuit 16, and a core circuit 17. The semiconductor device 10 may exchange signals with other external semiconductor devices through the signal pads 11 and 12. For example, the receiving circuit 15 may receive an external input signal through the input pad 11 among the signal pads 11 and 12, and the transmitting circuit 16 may transmit an external output signal through the output pad 12 among the signal pads 11 and 12.

[0033] Each of the receiving circuit 15, the transmitting circuit 16, and the core circuit 17 may include a plurality of semiconductor elements. The receiving circuit 15 may include a receiver, and the transmitting circuit 16 may include a driving circuit. The core circuit 17 may include various circuits required for the semiconductor device 10 to provide a predetermined function, such as a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a neural processing unit (NPU), a modem, a cache memory, etc.

[0034] The receiving circuit 15 may process an external input signal input to the input pad 11 and transmit the external input signal to the core circuit 17. The transmitting circuit 16 may process a signal received from the core circuit 17 to generate an external output signal and may transmit the external output signal through the output pad 12. In an example embodiment, each of the external input signal and the external output signal may be a signal having a predetermined frequency, such as Figure 1 as shown in .

[0035] A power supply voltage VDD and a reference voltage VSS required for the operation of each of the receiving circuit 15, the transmitting circuit 16, and the core circuit 17 may be input to the power supply pads 13 and 14. For example, the power supply voltage VDD may be input to the first power supply pad 13, and a reference voltage VSS having a level lower than that of the power supply voltage VDD may be input to the second power supply pad 14.

[0036] A high voltage caused by ESD or the like may be applied to at least a portion of the pads 11 to 14 of the semiconductor device 10. For example, in an ESD event condition in which a high voltage is applied to at least one of the signal pads 11 and 12 due to ESD or the like, a large amount of current may flow through semiconductor elements included in the receiving circuit 15, the transmitting circuit 16, etc. As a result, the semiconductor elements may be damaged. In an example embodiment, the ESD event may occur in a case where the body is in close proximity to at least one of the pads 11 to 14.

[0037] In order to prevent damage to semiconductor elements that may occur under ESD event conditions, the receiving circuit 15, the transmitting circuit 16, etc. may include an ESD protection circuit that provides a current movement path.

[0038] The ESD protection circuit can provide a path through which current flowing into the semiconductor device 10 flows under an ESD event condition. Ideally, current generated by static electricity around the semiconductor device 10 and flowing into the signal pads 11 and 12 can be discharged to the second power pad 14 through the ESD protection circuit.

[0039] For example, the ESD protection circuit can be implemented as a silicon controlled rectifier (SCR) circuit including a PNP transistor and an NPN transistor. The SCR circuit can have a trigger voltage determined according to the characteristics of the PNP transistor and the NPN transistor. When the potential difference between the static electricity flowing into the signal pads 11 and 12 and the second power pad 14 is higher than the trigger voltage, the static electricity can flow to the second power pad 14 through the ESD protection circuit.

[0040] When the ESD protection circuit is triggered due to avalanche breakdown, the trigger voltage may be higher than the breakdown voltage level. A trigger voltage higher than the breakdown voltage level may make it difficult to effectively protect the internal semiconductor elements of the semiconductor device 10 from the ESD occurring in the signal pads 11 and 12 .

[0041] According to example embodiments, the base of the PNP transistor and the base of the NPN transistor of the ESD protection circuit may be electrically connected to each other through an interconnection pattern, etc. When a current caused by ESD flows through the electrical connection between the bases, the ESD protection circuit may be triggered. Therefore, the trigger voltage of the ESD protection circuit may be reduced, and the internal semiconductor elements of the semiconductor device 10 may be effectively protected from the influence of ESD.

[0042] Figure 2 is a schematic diagram illustrating an ESD protection circuit included in a semiconductor device according to example embodiments.

[0043] refer to Figure 2 , the ESD protection circuit 100 according to example embodiments may include a PNP transistor PNP, an NPN transistor NPN, and a first diode D1.

[0044] The emitter of the PNP transistor PNP may be connected to the first pad P1 to which a signal is input or output. In addition, the emitter of the NPN transistor NPN may be connected to the second pad P2 to which a reference voltage is applied. For example, the reference voltage may be a ground voltage VSS.

[0045] The base of the PNP transistor PNP can be connected to the collector of the NPN transistor NPN. In addition, the collector of the PNP transistor PNP can be connected to the base of the NPN transistor NPN.

[0046] According to example embodiments, a base of the PNP transistor PNP and a base of the NPN transistor NPN may be electrically connected to each other. Figure 2 , a base of the PNP transistor PNP and a base of the NPN transistor NPN may be connected to the first node N1.

[0047] The current caused by the ESD occurring in the first pad P1 may flow to the first node N1 through the PN junction of the PNP transistor PNP, and the current may be applied to the base of the NPN transistor NPN, so that the SCR circuit including the PNP transistor PNP and the NPN transistor NPN may be triggered. Therefore, the SCR circuit may be triggered before avalanche breakdown occurs, and the trigger voltage of the ESD protection circuit 100 may be lower than the breakdown voltage level.

[0048] In addition, according to example embodiments, the base of the PNP transistor PNP may be connected to the third pad P3 to which the power supply voltage VDD is applied through the first diode D1. Therefore, due to the ESD occurring in the first pad P1, a current path may be formed between the first pad P1 and the third pad P3. The current path formed from the first pad P1 to the third pad P3 may improve the conduction performance of the ESD protection circuit 100 and reduce the parasitic capacitance occurring in the first pad P1.

[0049] Figure 3 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments. Figure 4 is along Figure 3 A cross-sectional view taken along line II'. Figure 5 is along Figure 3 A cross-sectional view taken along line II-II'.

[0050] Figures 3 to 5 It can be realized Figure 2 One example of an ESD protection circuit 100. Figures 3 to 5 , a first well region 102 may be formed in a substrate 101. The substrate 101 may be doped with a first conductive type impurity, and the first well region 102 may be doped with a second conductive type impurity different from the first conductive type impurity. The first conductive type impurity may be a P-type impurity, and the second conductive type impurity may be an N-type impurity. Figure 3 , the first well region 102 may extend in a first direction X (eg, longitudinally) parallel to the upper surface of the substrate 101 .

[0051] refer to Figures 3 to 5 In the substrate 101 and the first well region 102, a plurality of active regions 111 to 114 and element isolation films 105 and 106 that isolate the plurality of active regions 111 to 114 from each other may be formed. Figure 3 , the first active region 111 and the third active region 113 may be alternately disposed in the first well region 102 in the first direction X. In addition, the second active region 112 and the fourth active region 114 may be alternately disposed in the substrate 101 in the first direction X. The first active region 111 and the second active region 112 may have the same position in the first direction X, and may be spaced apart from each other in a second direction Y intersecting the first direction X. In addition, the third active region 113 and the fourth active region 114 may have the same position in the first direction X, and may be spaced apart from each other in the second direction Y.

[0052] The first active region 111 and the fourth active region 114 may be doped with first conductive type impurities and may have an impurity concentration higher than that of the substrate 101. The second active region 112 and the third active region 113 may be doped with second conductive type impurities and may have an impurity concentration higher than that of the first well region 102.

[0053] refer to Figure 4 and Figure 5 , the first element isolation film 105 may be formed around the first to fourth active regions 111 to 114 . Figure 3The first element isolation film 105 is omitted. However, referring to Figure 4 and Figure 5 , the first element isolation film 105 may be formed on Figure 3 In the region where the substrate 101 and the first well region 102 are visible, for example, in the region continuously surrounding each well region 102 in the top view. For example, the first element isolation film 105 may be formed between the first active region 111 and the second active region 112, and between the third active region 113 and the fourth active region 114.

[0054] refer to Figure 3 , a cutting region CT is shown between the first active region 111 and the third active region 113, and between the second active region 112 and the fourth active region 114. The second element isolation film 106 may be formed in the cutting region CT. Figure 4 and Figure 5 The second element isolation film 106 formed in the dicing region CT is shown.

[0055] refer to Figure 3 , the ESD protection circuit 100 may further include guard rings 115 and 116 surrounding the plurality of active regions 111 to 114. The first guard ring 115 may be doped with second conductive type impurities, and the second guard ring 116 may be doped with first conductive type impurities.

[0056] According to example embodiments, the first active region 111, the first well region 102, the substrate 101, and the second active region 112 adjacent to each other in the second direction Y may form a PNPN junction, thereby forming an SCR circuit ( Figure 3 depicted with thick lines). Figure 3 A plurality of SCR circuit regions SCR are shown.

[0057] The plurality of SCR circuit regions SCR may share the first well region 102 and the substrate 101. The first active regions 111 included in each of the plurality of SCR circuit regions SCR may be isolated from each other. However, all of the first active regions 111 may be connected to the first pad P1 and may be bonded to the first well region 102. In addition, the second active regions 112 included in each of the plurality of SCR circuit regions SCR may also be isolated from each other. However, all of the second active regions 112 may be connected to the second pad P2 and may be bonded to the substrate 101. Therefore, the plurality of SCR circuit regions SCR may be operated as a single SCR circuit having an enlarged junction area.

[0058] The first interval S1 between the first active region 111 and the second active region 112 may determine a trigger voltage of the SCR circuit. For example, as the first interval S1 increases, a distance between a PN junction formed between the first active region 111 and the first well region 102 and a PN junction formed between the substrate 101 and the second active region 112 may increase, thereby increasing the trigger voltage.

[0059] The following will refer to Figure 4 To describe the reference Figure 2 The electrical connection between the base of the PNP transistor PNP and the base of the NPN transistor NPN is described. Figure 5 To describe the reference Figure 2 An electrical connection between the base of the PNP transistor PNP and the third pad P3 is described.

[0060] refer to Figure 4 , the first active region 111 may provide an emitter of the PNP transistor PNP. In addition, the base of the PNP transistor PNP may be provided by the first well region 102, and the collector of the PNP transistor PNP may be provided by the substrate 101. The emitter of the PNP transistor PNP may be connected to the first pad P1. Figure 4 The connection between the first pad P1 and the first guard ring 115 is also shown.

[0061] The second active region 112 may provide an emitter of the NPN transistor NPN. In addition, the base of the NPN transistor NPN may be provided by the substrate 101, and the collector of the NPN transistor NPN may be provided by the first well region 102. The emitter of the NPN transistor NPN may be connected to the second pad P2. Figure 4 The connection between the second pad P2 and the second guard ring 116 is also shown.

[0062] Figure 4 and Figure 5 The PNP transistor PNP and the NPN transistor NPN shown in FIG. 1 may share the first well region 102 and the substrate 101 , and thus may be operated as a single SCR circuit.

[0063] According to example embodiments, the third active region 113 and the fourth active region 114 may be electrically connected to each other through an interconnection pattern. The third active region 113 may be electrically connected to the first well region 102, and the fourth active region 114 may be electrically connected to the substrate 101, so that the base of the PNP transistor PNP and the base of the NPN transistor NPN may be electrically connected to each other.

[0064] The second element isolation film 106 may have a length shorter than that of the first element isolation film 105 in a third direction perpendicular to the upper surface of the substrate 101 (e.g., in the thickness direction of the substrate 101). For example, the first element isolation film 105 may be a deep trench isolation (DTI), and the second element isolation film 106 may be a shallow trench isolation (STI). Since the thickness of the second element isolation film 106 is reduced, the flow of current in the first active region 111, the first well region 102, and the third active region 113, and the flow of current in the fourth active region 114, the substrate 101, and the second active region 112 may be facilitated.

[0065] refer to Figure 5 , as referenced Figure 4 As described, the first active region 111, the first well region 102, and the substrate 101 may provide a PNP transistor PNP, and the first well region 102, the substrate 101, and the second active region 112 may provide an NPN transistor NPN. According to example embodiments, the third active region 113 may be electrically connected to the third pad P3 through the first diode D1. The third active region 113 may be electrically connected to the first well region 102, so that the base of the PNP transistor PNP may also be electrically connected to the third pad P3 through the first diode D1.

[0066] Fig. 6A and Figure 6B is a diagram illustrating an operation of an ESD protection circuit included in a semiconductor device according to example embodiments. Figure 7 is a graph illustrating an operation of an ESD protection circuit included in a semiconductor device according to example embodiments.

[0067] Fig. 6A is a schematic diagram illustrating a structure of an ESD protection device according to a comparative example different from the example embodiment. Figure 6B is a schematic diagram illustrating a structure of an ESD protection device according to example embodiments.

[0068] refer to Fig. 6A , the ESD protection device according to the comparative example may include an SCR circuit formed by a first P-type structure PS1, a first N-type structure NS1, a second P-type structure PS2, and a second N-type structure NS2 bonded to each other. The first P-type structure PS1 and the first N-type structure NS1 may be connected to a signal pad I / O, and the second P-type structure PS2 and the second N-type structure NS2 may be connected to a ground pad VSS.

[0069] according to Fig. 6A According to the comparative example, the first N-type structure NS1 and the second P-type structure PS2 may not be electrically connected to each other. Therefore, the ESD protection device according to the comparative example may be triggered only by avalanche breakdown.

[0070] refer to Figure 7 The graph of FIG. 1 shows the voltage-current characteristics of the ESD protection device according to the comparative example using a broken line (dashed line). The SCR circuit of the ESD protection device may have a breakdown voltage level V determined according to the characteristics of the PNP transistor and the NPN transistor. B . It can be higher than the breakdown voltage level V B The trigger voltage V T1 Avalanche breakdown occurs under the voltage level, so that the ESD protection device according to the comparative example can be turned on. As the ESD protection device according to the comparative example is turned on, a large amount of current caused by ESD can flow to the ground pad VSS. However, a trigger voltage higher than the breakdown voltage level may be difficult to effectively protect the internal semiconductor element from the influence of ESD.

[0071] refer to Figure 6B , an ESD protection device according to an example embodiment may include an SCR circuit configured by a first active region 111, a first well region 102, a substrate 101, and a second active region 112 bonded to each other. The first active region 111 may be connected to a first pad P1. The first well region 102 and the substrate 101 may be electrically connected to each other. The second active region 112 may be connected to a second pad P2. In addition, the first well region 102 may be connected to a third pad P3 through a first diode D1.

[0072] According to example embodiments, the first well region 102 and the substrate 101 may be electrically connected to each other. Therefore, when the potential difference between the first pad P1 and the second pad P2 has a size sufficient to trigger the PN junction formed between the first active region 111 and the first well region 102 and the PN junction formed between the substrate 101 and the second active region 112, the SCR circuit may be triggered.

[0073] refer to Figure 7 , a solid line is used to show the voltage-current characteristics of the ESD protection device according to the example embodiment. The ESD protection device according to the example embodiment can be lower than the breakdown voltage level V determined according to the characteristics of the PNP transistor and the NPN transistor. B The first trigger voltage V T1 For example, when the ESD protection circuit according to the comparative example has a first trigger voltage of about 10V, the ESD protection circuit according to the example embodiment may have a first trigger voltage of about 2 to 3V.

[0074] Once the SCR circuit is triggered, current may begin to flow between the first well region 102 and the substrate 101 even if avalanche breakdown does not occur between the first well region 102 and the substrate 101. As long as the potential difference between the first pad P1 and the second pad P2 does not drop to the holding voltage V HThen, the ESD protection device according to the exemplary embodiment can maintain the on state. When the current flowing through the ESD protection device does not exceed the trigger current I T2 When the ESD circuit is turned on, a large amount of current caused by ESD applied to the first pad P1 can flow to the second pad P2 without causing damage.

[0075] According to example embodiments, the ESD protection device may have a reduced trigger voltage, and the ESD protection device may effectively protect the semiconductor device from static electricity applied to the first pad P1. Figure 3 As described, the trigger voltage may be adjusted according to the first interval S1 between the first active region 111 and the second active region 112 .

[0076] Even when the ESD protection device is turned off, the ESD protection device may have parasitic capacitance. Even under normal conditions where no ESD event occurs, an input signal or an output signal of a signal pad I / O may pass through the ESD protection device. When the ESD protection device has high parasitic capacitance, the switching speed of the input / output signal passing through the ESD protection device may be reduced, and the high-speed input / output signal may be distorted.

[0077] according to Fig. 6A In the comparative example shown in FIG, the reference voltage VSS may be applied to the second P-type structure PS2 and the second N-type structure NS2. A parasitic capacitance caused by a PN junction formed between the first P-type structure PS1 and the first N-type structure NS1, and a parasitic capacitance caused by an NP junction formed between the first N-type structure NS1 and the second P-type structure PS2 may appear between the signal pad I / O and the reference voltage VSS.

[0078] On the contrary, according to Figure 6B In the example embodiment shown in , the power supply voltage can be applied from the first pad P1 to the third pad P3 connected to the first well region 102. Assuming that the first diode D1 has a sufficiently small parasitic capacitance, only the parasitic capacitance caused by the PN junction formed between the first active region 111 and the first well region 102 may appear between the first pad P1 and the third pad P3. Therefore, the parasitic capacitance occurring in the first pad P1 according to the example embodiment can be reduced, and the distortion of the high-speed input / output signal can be alleviated.

[0079] In addition, according to example embodiments, when the potential difference between the first pad P1 and the third pad P3 is greater than the threshold voltage of the first diode D1 due to ESD occurring in the first pad P1, the first diode D1 may be triggered. Accordingly, the current caused by ESD may be effectively removed through the third pad P3 and the SCR circuit. For example, the current caused by static electricity may also flow through the power clamp circuit connected between the third pad P3 and the second pad P2.

[0080] Figure 8 is a schematic diagram illustrating an ESD protection circuit included in a semiconductor device according to example embodiments.

[0081] refer to Figure 8 , the power clamp circuit can be connected to a reference such as Figure 2 The third pad P3 and the second pad P2 of the ESD protection circuit are described. Figure 8 is an exemplary structure of a power clamp circuit, and shows a structure in which the gate and source of an NMOS transistor are connected through a first resistor R1 and the drain and gate are connected through a first capacitor C1.

[0082] According to example embodiments, when a voltage applied to the first pad P1 due to ESD is greater than a sum of a power supply voltage VDD applied to the third pad P3 and a threshold voltage of the first diode D1, the first diode D1 may be turned on. When the first diode D1 is turned on, a current caused by ESD may be discharged to the second pad P2 not only through the SCR circuit but also through the power clamp circuit.

[0083] According to example embodiments, the ESD protection device can remove the current caused by the ESD occurring in the first pad P1 using a power clamp circuit connected between the third pad P3 and the second pad P2, and an SCR circuit connected between the first pad P1 and the second pad P2. Therefore, the internal semiconductor element can be effectively protected from the influence of the ESD occurring in the first pad P1.

[0084] In addition, the turn-on speed of a general power clamp circuit may be higher than that of an SCR circuit. Therefore, the ESD protection device may be turned on quickly by the ESD occurring in the first pad P1 to more effectively protect the internal semiconductor element.

[0085] For example, Figures 2 to 8 A case where only one first diode D1 is connected between the first node N1 and the third pad P3 is shown. In another example, a plurality of diodes may be connected in series between the first node N1 and the third pad P3. Depending on the number of diodes connected in series, the voltage condition of the first pad P1 for forming a current path from the first pad P1 to the third pad P3 may vary.

[0086] For example, the number of diodes connected between the first node N1 and the third pad P3 can be selected according to the use voltage of the input / output signal. The use voltage of the input / output signal can refer to the maximum voltage in the voltage range used for the input / output signal. For example, when the use voltage of the input / output signal is higher than the sum of the power supply voltage VDD and the threshold voltage of the diode, the input / output signal may leak through the power clamp circuit, and the signal may be distorted. Therefore, the number of diodes can be selected so that the sum of the power supply voltage VDD and the threshold voltage of the diode is higher than the use voltage.

[0087] Fig. 9 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments. Fig.10 is along Fig. 9 A cross-sectional view taken along line III-III'.

[0088] Fig. 9 and Figure 1 The ESD protection circuit 100 shown in FIG. Figures 2 to 5 An ESD protection circuit 100 is described. Fig. 9 and Fig.10 The ESD protection circuit 100 may be an example that implements not only the SCR circuit but also the first diode D1.

[0089] remove Figure 3 In addition to the ESD protection circuit 100 shown in FIG. Fig. 9 The ESD protection circuit 100 shown in FIG. 1 may further include a second well region 103, and may further include a fifth active region 117 and a sixth active region 118 formed in the second well region 103. The second well region 103 may be doped with second conductive type impurities in the same manner as the first well region 102. The fifth active region 117 may be doped with first conductive type impurities, and the sixth active region 118 may be doped with second conductive type impurities.

[0090] refer to Fig. 9 and Fig.10 , the fifth active region 117 may provide an anode of the first diode D1, and the sixth active region 118 may provide a cathode of the first diode D1. The fifth active region 117 may be connected to the third active region 113, and the sixth active region 118 may be connected to the third pad P3. Figures 2 to 8 As described, the first diode D1 can reduce the parasitic capacitance of the ESD protection circuit and improve the turn-on speed of the ESD protection circuit.

[0091] On the contrary, according to example embodiments, the characteristics of the ESD protection circuit can be adjusted by adjusting the size of the SCR circuit included in the ESD protection circuit. Figure 8 As described, the trigger current I T2 .

[0092] Fig.11 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments. Fig.12 is along Fig.11 A cross-sectional view taken along line IV-IV'.

[0093] Fig.11 and Fig.12 The ESD protection circuit 200 shown in FIG. Figure 2 The ESD protection circuit 100 shown in FIG. Fig.11 and Fig.12 The ESD protection circuit 200 shown in FIG. Figures 3 to 5 The dimensions of the ESD protection circuit 100 shown in FIG. 1 are different dimensions.

[0094] refer to Fig.11 , a plurality of first well regions 202 may be formed in a substrate 201. The substrate 201 may be doped with first conductive type impurities, and the first well regions 202 may be doped with second conductive type impurities different from the first conductive type impurities. The first well regions 202 may extend in a first direction X (eg, longitudinally) in the substrate 201.

[0095] refer to Fig.11 and Fig.12 , a plurality of active regions 211 to 214, and element isolation films 205 and 206 isolating the plurality of active regions 211 to 214 from each other may be formed in each of the substrate 201 and the first well region 202. In addition, guard rings 215 and 216 may be formed to surround the first well region 202 and the plurality of active regions 211 to 214. The plurality of active regions 211 to 214, the element isolation films 205 and 206, and the guard rings 215 and 216 may be formed in the same manner as in the above reference. Figures 3 to 5 A pattern similar to the described pattern of the plurality of active regions 111 to 114 , the element isolation films 105 and 106 , and the guard rings 115 and 116 is provided on the substrate 201 or the first well region 202 , thereby forming an SCR circuit.

[0096] refer to Fig.11 , the first active region 211 , the first well region 202 , the substrate 201 , and the second active region 212 that are adjacent to each other in the second direction Y may form an SCR circuit. Fig.11 A plurality of SCR circuit regions SCR are shown.

[0097] refer to Fig.11 and Fig.12 , multiple SCR circuit regions SCR can share the substrate 201. In addition, the first active regions 211 isolated from each other can all be connected to the first pad P1, and the multiple second active regions 212 separated from each other can all be connected to the second pad P2. Therefore, the multiple SCR circuit regions SCR can be operated as a single SCR circuit with an enlarged PNPN junction area.

[0098] According to example embodiments, the trigger current I may be determined according to the number and area of ​​the first well region 202 and the plurality of active regions 211 to 214. T2 In particular, as the number or area of ​​the first well region 202 and the plurality of active regions 211 to 214 increases, the trigger current I T2 Can be enlarged.

[0099] In some example embodiments, the trigger current I T2 The number and area of ​​the first well region 202 and the plurality of active regions 211 to 214 are determined based on the target value of. For example, the target value may be determined based on the ESD performance required by an ESD test model (e.g., a human body model (HBM), a charged device model (CDM), etc.), and the number and area of ​​the first well region 202 and the plurality of active regions 211 to 214 may be determined so that the trigger current I T2 According to example embodiments, internal semiconductor elements of a semiconductor device may be effectively protected from ESD events caused by contact between the semiconductor device and a human body, contact between the semiconductor device and a machine, and the like.

[0100] The ESD protection circuit 200 can prevent the current caused by ESD from leaking through the substrate 201 , thereby more effectively protecting the internal semiconductor elements of the semiconductor device from the influence of the ESD event.

[0101] Fig.13 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments. Fig.14 is along Fig.13 A cross-sectional view taken along line IV-IV'.

[0102] Fig.13 and Fig.14 The ESD protection circuit 200a shown in FIG. Fig.11 and Fig.12 The ESD protection circuit 200 shown in FIG. 1 is substantially the same as that in FIG. 1 , except that it further includes a deep well region 203 . Fig.13 The deep well region 203 may be formed at least (eg, at least partially) in an inner region defined by the guard ring (eg, in Fig.13 The deep well region 203 may be doped with second conductivity type impurities and may be doped at a higher impurity concentration than the first well region 202 (in the region indicated by the dotted box in FIG).

[0103] refer to Fig.14 , the deep well region 203 may be formed below the first well region 202. For example, the deep well region 203 may be formed adjacent to a lower surface of the first well region 202.

[0104] As described above, a portion of the PNP transistor PNP and the NPN transistor NPN provided by the ESD protection circuit 200a may be provided by the substrate 201. Therefore, when the ESD protection circuit 200a is triggered and current flows through the PNP transistor PNP and the NPN transistor NPN, leakage current may occur through the substrate 201. When the leakage current is not effectively blocked, the leakage current may flow into a semiconductor element sharing the substrate 201 with the ESD protection circuit 200a.

[0105] According to example embodiments, current leaking to the side surface of the ESD protection circuit 200a may be blocked by the guard rings 215 and 216. In addition, current leaking to the lower surface of the ESD protection circuit 200a may be blocked by the deep well region 203.

[0106] The holding voltage V of the ESD protection circuit can be controlled by adjusting the area ratio between the first active region and the second active region. H characteristics.

[0107] Fig.15 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments. Fig.16A and Fig. 16B are respectively along Fig.15 A cross-sectional view taken along lines V-V' and VI-VI'.

[0108] Fig.15 , Fig.16A and Fig. 16B The ESD protection circuit 300 may correspond to Figure 2 The ESD protection circuit 100. However, Fig.15 , Fig.16A and Fig. 16B The ESD protection circuit 300 may be similar to the first active region and the second active region in terms of the area ratio between the first active region and the second active region. Figures 3 to 5 The ESD protection circuit 100 shown in FIG. 1 is different.

[0109] refer to Fig.15 , Fig.16A and Fig. 16B, a first well region 302 may be formed in a substrate 301. A plurality of active regions 311 to 314, and element isolation films 305 and 306 isolating the plurality of active regions 311 to 314 from each other may be formed in the substrate 301 and the first well region 302. In addition, guard rings 315 and 316 may be formed in the substrate 301 to surround the first well region 302 and the plurality of active regions 311 to 314.

[0110] According to example embodiments, an SCR circuit may be provided by forming a PNPN junction between the first active region 311, the first well region 302, the substrate 301, and the second active region 312. Figures 3 to 5 In a similar manner to the described ESD protection circuit 100 , the first active region 311 may provide an emitter of a PNP transistor PNP, and the second active region 312 may provide an emitter of an NPN transistor NPN.

[0111] However, when compared with the reference Figures 3 to 5 Compared with the ESD protection circuit 100 described above, in the ESD protection circuit 300, the sum of the areas of the first active regions 311 may be different from the area of ​​the second active regions 312. For example, Fig.15 , Fig.16A and Fig. 16B A case in which the ratio between the sum of the areas of the first active regions 311 and the area of ​​the second active regions 312 is about 2:3 is shown.

[0112] According to example embodiments, the holding voltage V may be controlled by adjusting an area ratio between an emitter of the PNP transistor PNP and an emitter of the NPN transistor NPN. H .

[0113] Fig.17 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments. Fig.18A and Fig.18B are respectively along Fig.17 A cross-sectional view taken along lines V-V' and VI-VI'.

[0114] Fig.17 , Fig.18A and Fig.18B The ESD protection circuit 400 may correspond to Figure 2 The ESD protection circuit 100. However, Fig.17 , Fig.18A and Fig.18B The ESD protection circuit 400 may be similar to the first active region and the second active region in terms of the area ratio between the first active region and the second active region. Figures 3 to 5 The ESD protection circuit 100 shown in FIG. 1 is different.

[0115] refer to Fig.17 , Fig.18A and Fig.18B , a first well region 402 may be formed in a substrate 401. A plurality of active regions 411 to 414, and element isolation films 405 and 406 isolating the plurality of active regions 411 to 414 from each other may be formed in the substrate 401 and the first well region 402. In addition, guard rings 415 and 416 may be formed in the substrate 401 to surround the first well region 402 and the plurality of active regions 411 to 414.

[0116] According to example embodiments, an SCR circuit may be provided by forming a PNPN junction between the first active region 411, the first well region 402, the substrate 401, and the second active region 412. The first active region 411 may provide an emitter of a PNP transistor PNP, and the second active region 412 may provide an emitter of an NPN transistor NPN.

[0117] When with reference Fig.15 , Fig.16A and Fig. 16B Compared with the ESD protection circuit 300 described above, in the ESD protection circuit 400 , the area of ​​the first active region 411 may be greater than the sum of the areas of the second active regions 412 .

[0118] According to example embodiments, the holding voltage V may be controlled by adjusting an area ratio between an emitter of the PNP transistor PNP and an emitter of the NPN transistor NPN. H .

[0119] The first trigger voltage V of the ESD protection circuit can be adjusted by adding components between the base of the PNP transistor PNP and the base of the NPN transistor NPN T1 characteristics.

[0120] Fig.19 is a schematic diagram illustrating an ESD protection circuit included in a semiconductor device according to example embodiments.

[0121] refer to Fig.19 , the ESD protection circuit 500 according to example embodiments may include a PNP transistor PNP, an NPN transistor NPN, a first diode D1, and a second diode D2.

[0122] With reference Figure 2 The ESD protection circuit 100 is described in the same manner as in reference Fig.19In the described ESD protection circuit 500, the emitter of the PNP transistor PNP can be connected to the first pad P1 to which the signal is input or output. In addition, the emitter of the NPN transistor NPN can be connected to the second pad P2 to which the reference voltage is applied. For example, the reference voltage can be the ground voltage VSS. The base of the PNP transistor PNP can be connected to the collector of the NPN transistor NPN. In addition, the collector of the PNP transistor PNP can be connected to the base of the NPN transistor NPN. In addition, the base of the PNP transistor PNP can be connected to the third pad P3 to which the power supply voltage VDD is applied through the first diode D1.

[0123] According to example embodiments, a base of the PNP transistor PNP and a base of the NPN transistor NPN may be electrically connected to each other through a second diode D2 . Fig.19 The second diode D2 is shown connected between the first node N1 to which the base of the PNP transistor PNP is connected and the second node N2 to which the base of the NPN transistor NPN is connected.

[0124] According to example embodiments, a current caused by static electricity introduced through the first pad P1 may flow along the first node N1 and the second node N2 to the second pad P2, so that the SCR circuit may be triggered. When the potential difference between the first pad P1 and the second pad P2 is greater than the sum of the threshold voltages of the PN junction of the PNP transistor PNP, the second diode D2, and the PN junction of the NPN transistor NPN, the SCR circuit may be triggered. That is, Fig.19 The first trigger voltage V of the ESD protection circuit 500 T1 Can be compared Figure 2 The first trigger voltage V of the ESD protection circuit 100 T1 Therefore, the first trigger voltage V can be adjusted by connecting one or more diodes between the base of the PNP transistor PNP and the base of the NPN transistor NPN. T1 .

[0125] Fig. 20 is a diagram illustrating a structure of an ESD protection circuit included in a semiconductor device according to example embodiments. Fig.21 is along Fig. 20 A cross-sectional view taken along line VII-VII'.

[0126] Fig. 20 and Fig.21 It can be realized Fig.19 One example of an ESD protection circuit 500. Fig. 20 and Fig.21, a first well region 502 and a second well region 503 may be formed in a substrate 501. The substrate 501 may be doped with first conductive type impurities, and the first well region 502 and the second well region 503 may be doped with second conductive type impurities. Fig. 20 , the first well region 502 and the second well region 503 may extend from the substrate 501 in a first direction X (eg, longitudinally) and may be spaced apart from each other in a second direction Y.

[0127] refer to Fig. 20 and Fig.21 In each of the substrate 501, the first well region 502, and the second well region 503, a plurality of active regions 511 to 516 and element isolation films 505 and 506 that isolate the plurality of active regions 511 to 516 from each other may be formed. The first active region 511, the fourth active region 514, and the sixth active region 516 may be doped with first conductive type impurities and may have an impurity concentration higher than that of the substrate 501. The second active region 512, the third active region 513, and the fifth active region 515 may be doped with second conductive type impurities and may have an impurity concentration higher than that of the first well region 502 and the second well region 503.

[0128] refer to Fig. 20 , the first active region 511 and the third active region 513 may be alternately disposed in the first well region 502 in the first direction X, and the second active region 512 and the sixth active region 516 may be alternately disposed in the second well region 503 in the first direction X. In addition, the fourth active region 514 and the fifth active region 515 may be alternately disposed in the first direction X in a region of the substrate 501 defined between the first well region 502 and the second well region 503.

[0129] refer to Fig. 20 and Fig.21 , the first element isolation film 505 may be formed on Fig. 20 501, the first well region 502, and the second well region 503. In addition, the second element isolation film 506 can be formed in the cutting region CT, wherein the cutting region CT is shown between the first active region 511 and the third active region 513, between the second active region 512 and the sixth active region 516, and between the fourth active region 514 and the fifth active region 515.

[0130] refer to Fig. 20 , the ESD protection circuit 500 may further include guard rings 517 and 518 surrounding the plurality of active regions 511 to 516. The first guard ring 517 may be doped with second conductive type impurities, and the second guard ring 518 may be doped with first conductive type impurities.

[0131] According to example embodiments, the first active region 511 , the first well region 502 , the substrate 501 , and the second well region 503 may form a PNPN junction, thereby forming an SCR circuit. Fig. 20 The first partial SCR region PSCR1 formed by the first active region 511, the first well region 502 and the substrate 501, and the second partial SCR region PSCR2 formed by the substrate 501 and the second well region 503 are shown. The first partial SCR region PSCR1 and the second partial SCR region PSCR2 are Fig. 20 However, the first partial SCR region PSCR1 and the second partial SCR region PSCR2 may be electrically connected to each other through the substrate 501, thereby forming a single SCR circuit.

[0132] refer to Fig.21 , the first active region 511 may provide an emitter of the PNP transistor PNP. In addition, the base of the PNP transistor PNP may be provided by the first well region 502, and the collector of the PNP transistor PNP may be provided by the substrate 501. The emitter of the PNP transistor PNP may be connected to the first pad P1.

[0133] The second well region 503 may provide an emitter of the NPN transistor NPN. In addition, the base of the NPN transistor NPN may be provided by the substrate 501, and the collector of the NPN transistor NPN may be provided by the first well region 502. The emitter of the NPN transistor may be connected to the second pad P2.

[0134] According to example embodiments, the fourth active region 514 may provide an anode of the second diode D2, and the fifth active region 515 may provide a cathode of the second diode D2. The third active region 513 and the fourth active region 514 may be electrically connected to each other through an interconnection pattern. In addition, the fifth active region 515 and the sixth active region 516 may also be electrically connected to each other through an interconnection pattern. The anode of the second diode D2 may be electrically connected to the base of the PNP transistor PNP through the electrical connection between the third active region 513 and the fourth active region 514. In addition, the cathode of the second diode D2 may be electrically connected to the base of the NPN transistor NPN through the electrical connection between the fifth active region 515 and the sixth active region 516.

[0135] According to example embodiments, the first trigger voltage V may be controlled by connecting the second diode D2 between the base of the PNP transistor PNP and the base of the NPN transistor NPN. T1 .

[0136] According to an example embodiment, the base of the PNP transistor of the ESD protection circuit can be electrically connected to the base of the NPN transistor using an interconnect pattern or the like, so that the ESD protection circuit can be triggered before the potential difference between the ESD applied to the input / output pad and the reference voltage reaches a breakdown voltage level, thereby effectively protecting the internal semiconductor elements of the semiconductor device from the influence of ESD.

[0137] According to an example embodiment, the base of the PNP transistor of the ESD protection circuit can be electrically connected to the power pad, so that the ESD applied to the input / output pad can be quickly removed even through the power pad. In addition, the current path formed from the base of the PNP transistor to the power pad can reduce the parasitic capacitance appearing in the input / output pad, thereby effectively transmitting the high-speed input / output signal of the semiconductor device.

[0138] By way of summary and review, one aspect of the embodiment provides a semiconductor device capable of effectively protecting internal semiconductor elements from ESD by allowing the ESD protection circuit to have a trigger voltage lower than the breakdown voltage level. Another aspect of the embodiment provides a semiconductor device capable of effectively protecting internal semiconductor elements from ESD by quickly turning on the ESD protection circuit. Yet another aspect of the embodiment provides a semiconductor device capable of preventing distortion of input / output signals passing through the ESD protection circuit by reducing parasitic capacitance caused by the ESD protection circuit.

[0139] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general descriptive sense and not for limiting purposes. In some cases, as will be apparent to one of ordinary skill in the art upon filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, include: a substrate doped with first conductivity type impurities; a first well region in the substrate and doped with second conductivity type impurities, the second conductivity type impurities being different from the first conductivity type impurities; a first active region, in the first well region, the first active region being doped with the first conductive type impurities and connected to the first pad through a first interconnect pattern; a second active region, in the substrate outside the first well region, the second active region being doped with the second conductivity type impurities and respectively connected to the second pads through second interconnection patterns; a third active region, surrounding the first active region in the first well region and doped with impurities of the second conductivity type; as well as a fourth active region, surrounding the second active region outside the first well region and doped with impurities of the first conductive type, Wherein, at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnection pattern.

2. The semiconductor device according to claim 1, in: The first active region provides a first emitter of a PNP transistor, the first well region provides a first base of the PNP transistor, and the substrate provides a first collector of the PNP transistor, and The second active region provides a second emitter of the NPN transistor, the substrate provides a second base of the NPN transistor, and the first well region provides a second collector of the NPN transistor. 3 . The semiconductor device according to claim 1 , further comprising a first diode connected between at least one of the third active regions and a third pad. 4 . The semiconductor device according to claim 3 , further comprising a power clamp circuit connected between the third pad and the second pad.

5. The semiconductor device according to claim 1, further comprising: include: a second well region, in the substrate and doped with impurities of the second conductivity type; a fifth active region, in the second well region, and doped with the first conductivity type impurities; as well as a sixth active region doped with the second conductivity type impurities, Wherein, at least one of the third active regions is connected to the fifth active region through a fourth interconnection pattern, and the fifth active region is connected to the sixth active region through a fifth interconnection pattern.

6. The semiconductor device according to claim 1, in: The first active regions and the third active regions are alternately arranged in a first direction parallel to an upper surface of the substrate, The second active regions and the fourth active regions are alternately arranged in the first direction, and The first active regions and the second active regions are alternately arranged in a second direction which is parallel to the upper surface of the substrate and intersects the first direction.

7. The semiconductor device according to claim 6, further comprising: include: a first element isolation film between the first active region and the second active region, and A second element isolation film is provided between the first active region and the third active region, and between the second active region and the fourth active region.

8. The semiconductor device according to claim 7, in, The second element isolation film has a length in a third direction perpendicular to the upper surface of the substrate that is shorter than a length of the first element isolation film. 9 . The semiconductor device of claim 1 , further comprising a guard ring in the substrate, the guard ring surrounding the first well region, the first active region, the second active region, the third active region, and the fourth active region. 10 . The semiconductor device according to claim 9 , further comprising a deep well region in the substrate below the first well region, the deep well region being at least partially in an inner region defined by the guard ring and being doped with impurities of the second conductivity type.

11. The semiconductor device according to claim 1, in: The first active region and the fourth active region have an impurity concentration higher than an impurity concentration of the substrate, and The second active region and the third active region have an impurity concentration higher than an impurity concentration of the first well region.

12. The semiconductor device according to claim 1, in, The sum of the areas of the first active regions is equal to the sum of the areas of the second active regions.

13. The semiconductor device according to claim 1, in, The sum of the areas of the first active regions is different from the sum of the areas of the second active regions.

14. A semiconductor device, include: a substrate doped with first conductivity type impurities; A first well region and a second well region are in the substrate and are doped with second conductivity type impurities, the second conductivity type impurities being different from the first conductivity type impurities; first active regions, in the first well region, the first active regions being doped with the first conductive type impurities and respectively connected to the first pads through first interconnection patterns; a second active region, in the second well region, the second active region being doped with the second conductivity type impurities and connected to the second pad through a second interconnect pattern; a third active region, surrounding the first active region in the first well region and doped with impurities of the second conductivity type; a fourth active region, in the substrate between the first well region and the second well region, and doped with impurities of the first conductivity type; a fifth active region, in the substrate between the first well region and the second well region, and doped with impurities of the second conductivity type; as well as a sixth active region, surrounding the second active region in the second well region and doped with the first conductive type impurities, wherein at least one of the third active regions and at least one of the fourth active regions are electrically connected to each other through a third interconnection pattern, and Wherein, at least one of the fifth active regions and at least one of the sixth active regions are electrically connected to each other through a fourth interconnection pattern.

15. The semiconductor device according to claim 14, in: The first active region provides a first emitter of a PNP transistor, the first well region provides a first base of the PNP transistor, and the substrate provides a first collector of the PNP transistor, and The second well region provides a second emitter of the NPN transistor, the substrate provides a second base of the NPN transistor, and the first well region provides a second collector of the NPN transistor. 16 . The semiconductor device according to claim 14 , further comprising a first diode connected between at least one of the third active regions and a third pad.

17. A semiconductor device, include: The first pad, input and output signal; A second pad is supplied with a reference voltage; A PNP transistor including a first emitter connected to the first pad, a first collector and a first base; as well as an NPN transistor including a second emitter connected to the second pad, a second collector connected to the first base, and a second base connected to the first collector, The first base is connected to the second base and connected to a third pad through a first diode, and the third pad is supplied with a power supply voltage.

18. The semiconductor device according to claim 17, in, The first diode includes a plurality of diodes.

19. The semiconductor device according to claim 17, in, The first base and the second base are connected to each other through a second diode. 20 . The semiconductor device according to claim 17 , further comprising a power clamp circuit connected between the third pad and the second pad.

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