Imaging device

Abstract

An imaging device according to one embodiment of the present disclosure is provided with: a photoelectric conversion unit that converts light into a signal charge; a first diffusion region of a first conductivity type to which the signal charge is input; a second diffusion region of the first conductivity type; a first plug having a first surface in contact with the first diffusion region; and a second plug having a second surface in contact with the second diffusion region, the area of the first surface of the first plug being smaller than the area of the second surface of the second plug in plan view.

Description

[0001] This application was submitted on August 26, 2019, with Chinese patent application number 201910788014.7 and invention name “Camera Device” as a divisional application of the patent application. Technical Field

[0002] The present disclosure relates to an imaging device. Background Art

[0003] CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras, etc. These image sensors have photodiodes formed on a semiconductor substrate.

[0004] On the other hand, for example, as disclosed in International Publication No. 2012 / 147302, an imaging device having a structure in which a photoelectric conversion unit having a photoelectric conversion layer is arranged above a semiconductor substrate is proposed. An imaging device having such a structure is sometimes referred to as a stacked imaging device. In a stacked imaging device, charges generated by photoelectric conversion are accumulated in a charge accumulation region provided on a semiconductor substrate. A signal corresponding to the amount of charge accumulated in the charge accumulation region is read out via a CCD circuit or a CMOS circuit formed on the semiconductor substrate.

[0005] In an imaging device having a charge accumulation region provided on a semiconductor substrate, there is a possibility that an image obtained may be degraded due to leakage current, ie, dark current, flowing from or into the charge accumulation region. Summary of the invention

[0006] A camera device according to one embodiment of the present invention comprises: a photoelectric conversion unit that converts light into signal charges; a first diffusion region of a first conductivity type into which the signal charges are input; a second diffusion region of the first conductivity type; a first plug having a first surface connected to the first diffusion region; and a second plug having a second surface connected to the second diffusion region, wherein the area of ​​the first surface of the first plug is smaller than the area of ​​the second surface of the second plug when viewed in a plan view.

[0007] A camera device according to one embodiment of the present invention comprises: a photoelectric conversion unit that converts light into signal charge; a first diffusion region of a first conductivity type into which the signal charge is input; a second diffusion region of the first conductivity type; a first plug connected to the first diffusion region; and a second plug connected to the second diffusion region, the first plug comprising: a first contact connected to the first diffusion region; and a first pad located on the first contact, the second plug comprising: a second contact connected to the second diffusion region; and a second pad located on the second contact, and the area of ​​the first contact is smaller than the area of ​​the second contact when viewed in a plan view.

[0008] An imaging device according to one aspect of the present disclosure includes a semiconductor substrate including a first diffusion region of a first conductivity type and a second diffusion region of the first conductivity type, a first plug that is in contact with the first diffusion region and includes a semiconductor, a second plug that is in contact with the second diffusion region and includes a semiconductor, and a photoelectric conversion unit that is electrically connected to the first plug. When viewed from a direction perpendicular to the semiconductor substrate, the area of ​​the second plug is larger than the area of ​​the first plug.

[0009] In addition, the general or specific manner may also be implemented by elements, devices, modules, systems or methods. In addition, the general or specific manner may also be implemented by any combination of elements, devices, modules, systems and methods.

[0010] In addition, additional effects and advantages of the disclosed embodiments are clear from the specification and drawings. The effects and / or advantages are provided by various embodiments or features disclosed in the specification and drawings, respectively, and all are not required to obtain one or more effects and / or advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram showing the configuration of an imaging device according to Embodiment 1.

[0012] Figure 2 This is a diagram showing a circuit configuration of an imaging device according to Embodiment 1.

[0013] Figure 3 It is a plan view of the layout within the pixels constituting the imaging device according to the first embodiment.

[0014] Figure 4 This is a schematic cross-sectional view showing the device structure of a pixel of the imaging device according to the first embodiment.

[0015] Figure 5 This is an enlarged cross-sectional view showing the vicinity of two contact plugs of the imaging device according to the first embodiment.

[0016] Figure 6 This is a diagram showing the distribution of electron and hole concentrations near the contact plug of the imaging device according to the first embodiment, for each pad width.

[0017] Figure 7 This is a plan view showing the layout within a pixel of an imaging device according to Modification 1 of Embodiment 1.

[0018] Figure 8 This is a plan view showing the layout within a pixel of an imaging device according to a second variation of the first embodiment.

[0019] Fig. 9 This is a plan view showing the layout within a pixel of the imaging device according to the second embodiment.

[0020] Fig.10 This is a schematic cross-sectional view showing the device structure of a pixel of the imaging device according to the second embodiment.

[0021] Description of Reference Numerals

[0022] 10, 10A, 10B, 10C pixels

[0023] 12 Photoelectric conversion unit

[0024] 12a Pixel electrode

[0025] 12b Photoelectric conversion layer

[0026] 12c Transparent Electrode

[0027] 14 Signal detection circuit

[0028] 16 Feedback Circuit

[0029] 22 Amplifier transistor

[0030] 22e, 24e, 26e gate electrode

[0031] 24 Address transistors

[0032] 26 Reset transistor

[0033] 32 Power Wiring

[0034] 34 address signal lines

[0035] 35 vertical signal line

[0036] 36 Reset signal line

[0037] 39 Accumulation Control Line

[0038] 40 Peripheral Circuit

[0039] 42 Load Circuit

[0040] 44 columns signal processing circuit

[0041] 46 Vertical scanning circuit

[0042] 48 horizontal signal readout circuit

[0043] 49 Horizontal common signal line

[0044] 50 Inverting Amplifier

[0045] 53 Feedback line

[0046] 60 Semiconductor substrate

[0047] 61 Support base plate

[0048] 61p, 63p, 65p p-type semiconductor layer

[0049] 62n n-type semiconductor layer

[0050] 64 p-type region

[0051] 66p p-type impurity region

[0052] 67a Area 1

[0053] 67b Area 2

[0054] 67n 1st diffusion area

[0055] 68an, 68bn, 68dn Second diffusion area

[0056] 68cn 3rd diffusion area

[0057] 69 Component separation area

[0058] 70, 71, 72, 90a, 90b, 90c, 90d insulation layer

[0059] 73, 74 side wall

[0060] 80 Wiring structure

[0061] 80a, 80b, 80c, 80d wiring layer

[0062] 90 Interlayer insulation layer

[0063] 100 Camera Device

[0064] R1 Camera area

[0065] R2 Surrounding Area

[0066] cp1, cp1A, cp1B, cp2, cp3, cp4, cp5, cp6, cp7, cp8 contact plug

[0067] cp1a, cp1Aa, cp3a contact

[0068] cp1b, cp3b pad

[0069] h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11 contact hole

[0070] pa1, pa2, pa3, pa4, pa5, pa6, pa7, pb, pc, pd plug. DETAILED DESCRIPTION

[0071] (Overview of the present disclosure)

[0072] An overview of one aspect of the present disclosure is as follows.

[0073] An imaging device according to one aspect of the present disclosure includes a semiconductor substrate including a first diffusion region of a first conductivity type and a second diffusion region of the first conductivity type, a first plug that is in contact with the first diffusion region and includes a semiconductor, a second plug that is in contact with the second diffusion region and includes a semiconductor, and a photoelectric conversion unit that is electrically connected to the first plug. When viewed from a direction perpendicular to the semiconductor substrate, the area of ​​the second plug is larger than the area of ​​the first plug.

[0074] On the surface of the semiconductor substrate, leakage current caused by crystal defects is likely to flow. The larger the depletion layer that expands along the surface of the semiconductor substrate, the easier it is for the leakage current to flow. In contrast, according to the imaging device of this mode, since the area of ​​the first plug electrically connected to the photoelectric conversion unit becomes smaller, the range on the surface of the semiconductor substrate affected by the potential of the first plug becomes smaller. Therefore, the expansion of the depletion layer from the first diffusion region along the surface of the semiconductor substrate can be suppressed. Therefore, according to the imaging device of this mode, leakage current, that is, dark current, can be suppressed.

[0075] In addition, for example, the camera device of one embodiment of the present invention may also include an insulating film located on the semiconductor substrate, the first plug includes: a first contact connected to the first diffusion region and penetrating the insulating film; and a first soldering pad located on the first contact and having an area larger than the first contact when viewed from a direction perpendicular to the semiconductor substrate, the second plug includes: a second contact connected to the second diffusion region and penetrating the insulating film; and a second soldering pad located on the second contact and having an area larger than the second contact when viewed from a direction perpendicular to the semiconductor substrate, and the area of ​​the second soldering pad is larger than the area of ​​the first soldering pad when viewed from a direction perpendicular to the semiconductor substrate.

[0076] As a result, the area of ​​the first pad of the first plug connected to the first diffusion region is reduced, and thus the range affected by the potential of the first pad is reduced. Therefore, the expansion of the depletion layer from the first diffusion region along the surface of the semiconductor substrate can be suppressed. Therefore, the leakage current flowing out of the first diffusion region or flowing into the first diffusion region can be suppressed.

[0077] In addition, for example, a camera device of one embodiment of the present invention may further include: a first transistor, which includes the first diffusion region as one of a source and a drain, and includes a first gate; and a second transistor, which includes the second diffusion region as one of a source and a drain, and includes a second gate, and the length of the second pad in a direction parallel to the width direction of the second gate is longer than the length of the first pad in a direction parallel to the width direction of the first gate.

[0078] Thus, by shortening the width direction, the area of ​​the first pad can be easily reduced.

[0079] Furthermore, for example, the distance between the second pad and the second gate may be longer than the distance between the first pad and the first gate.

[0080] Thus, since the distance between the first pad and the gate electrode is shortened, the expansion of the depletion layer formed on the gate electrode side can be suppressed. Therefore, leakage current flowing out of the first diffusion region or flowing into the first diffusion region can be suppressed.

[0081] Furthermore, for example, when viewed from a direction perpendicular to the semiconductor substrate, the area of ​​the second contact may be larger than the area of ​​the first contact.

[0082] Thus, since the contact area between the first contact of the first plug and the first diffusion region is reduced, the amount of impurities contained in the first contact diffusing into the first diffusion region can be reduced. Since the concentration of impurities in the junction of the first diffusion region is reduced, the electric field intensity in the junction can be relaxed. Thus, since the expansion of the depletion layer from the first diffusion region can be suppressed, the leakage current can be suppressed.

[0083] Furthermore, for example, the first plug and the second plug may include the first conductivity type impurity, and the concentration of the first conductivity type impurity in the second plug may be higher than the concentration of the first conductivity type impurity in the first plug.

[0084] Thus, since the concentration of impurities contained in the first plug is reduced, the amount of impurities contained in the first plug diffused into the first diffusion region can be reduced. Since the concentration of impurities in the junction of the first diffusion region is reduced, the electric field intensity in the junction can be relaxed. Thus, since the expansion of the depletion layer from the first diffusion region can be suppressed, the leakage current can be suppressed.

[0085] In addition, for example, it is also possible to further include: a first transistor including the first diffusion region as one of a source and a drain, and including a first gate; and a second transistor including the second diffusion region as one of a source and a drain, and including a second gate, wherein the length of the second pad in a direction parallel to the length direction of the second gate is longer than the length of the first pad in a direction parallel to the length direction of the first gate. In addition, when viewed from a direction perpendicular to the semiconductor substrate, the length direction of the gate is a direction orthogonal to the width direction of the gate.

[0086] In the present disclosure, all or part of a circuit, unit, device, component or part, or all or part of a functional module of a block diagram can be performed by one or more electronic circuits including a semiconductor device, a semiconductor integrated circuit (IC), or an LSI (large scale integration). LSI or IC can be integrated into one chip or composed of multiple chips. For example, functional modules other than storage elements can also be integrated into one chip. Here, although it is called LSI or IC, the name changes according to the degree of integration, and it can also be called a system LSI, VLSI (very large scale integration), or ULSI (ultralarge scale integration) circuit. A field programmable gate array (FPGA) programmed after the manufacture of LSI, or a reconfigurable logic device capable of reconstructing the bonding relationship inside LSI or setting the circuit division inside LSI can also be used for the same purpose.

[0087] Furthermore, all or part of the functions or operations of a circuit, unit, device, component or part may also be executed by software processing. In this case, the software is recorded on one or more non-volatile recording media such as ROMs, optical disks, hard disk drives, etc. When the software is executed by a processing device (processor), the functions specific to the software are executed by the processing device (processor) and peripheral devices. The system or device may also have one or more non-volatile recording media, a processing device (processor), and required hardware devices, such as interfaces, on which the software is recorded.

[0088] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, the embodiments described below all represent general or specific examples. The numerical values, shapes, materials, constituent elements, configurations of constituent elements, connection forms, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present disclosure. The various methods described in this specification can be combined with each other as long as no contradiction occurs. In addition, the constituent elements in the following embodiments that are not described in the independent claims are described as arbitrary constituent elements. In each figure, constituent elements that actually have the same function are represented by common reference numerals, and repeated descriptions are sometimes omitted or simplified.

[0089] In addition, the various elements shown in the drawings are only schematically illustrated for understanding the present disclosure, and the size ratio and appearance may be different from the actual object. In other words, each figure is a schematic diagram and is not necessarily a strict illustration. Therefore, for example, the scale in each figure is not necessarily the same.

[0090] In addition, in this specification, terms such as parallel or consistent that indicate the relationship between elements, terms such as circular or rectangular that indicate the shape of elements, and numerical ranges are not expressions in a strict sense, but also include actually equivalent ranges, such as expressions with differences of several percent.

[0091] In addition, in this specification, the terms "above" and "below" do not refer to the upper direction (vertically above) and the lower direction (vertically below) in absolute spatial recognition, but are used as terms specified by the relative positional relationship based on the stacking order in the stacking structure. Specifically, the light-receiving side of the camera device is set to "above", and the side opposite to the light-receiving side is set to "below". The same is true for the "upper surface" and "lower surface" of each component. The surface opposite to the light-receiving side of the camera device is set to "upper surface", and the surface opposite to the opposite side of the light-receiving side is set to "lower surface". In addition, the terms "above", "below", "upper surface" and "lower surface" are only used to specify the mutual configuration between components, and are not intended to limit the posture of the camera device when in use. In addition, the terms "above" and "below" are not only applicable to the case where two components are arranged at a distance from each other and there are other components between the two components, but also to the case where two components are arranged close to each other and the two components are connected. In addition, in this specification, "top view (planar view)" refers to when observed from a direction perpendicular to the semiconductor substrate.

[0092] (Implementation Method 1)

[0093] Figure 1 FIG. 2 is a diagram showing the configuration of the imaging device according to the present embodiment. Figure 1 As shown, the imaging device 100 of this embodiment includes a plurality of pixels 10 formed on a semiconductor substrate 60 and a peripheral circuit 40. Each pixel 10 includes a photoelectric conversion unit 12 disposed above the semiconductor substrate 60. In other words, as an example of the imaging device of the present disclosure, a stacked imaging device 100 is described.

[0094] exist Figure 1 In the example shown, the pixels 10 are arranged in a matrix of m rows and n columns. Here, m and n are integers greater than 2. The pixels 10 are arranged, for example, two-dimensionally on the semiconductor substrate 60, thereby forming an imaging region R1. As described above, each pixel 10 includes a photoelectric conversion unit 12 arranged above the semiconductor substrate 60. Therefore, the imaging region R1 is defined as the area of ​​the semiconductor substrate 60 covered by the photoelectric conversion unit 12. In addition, Figure 1 In the figure, for ease of explanation, the photoelectric conversion sections 12 of the pixels 10 are shown as being spatially separated from each other, but the photoelectric conversion sections 12 of a plurality of pixels 10 can be arranged on the semiconductor substrate 60 without being spaced apart from each other.

[0095] The number and arrangement of the pixels 10 are not limited to the example shown in the figure. For example, the number of pixels 10 included in the imaging device 100 may be one. In this example, the center of each pixel 10 is located at a grid point of a square grid, but the arrangement of the pixels 10 may be in other forms. For example, a plurality of pixels 10 may be arranged in such a manner that each center is located at a grid point of a triangular grid, a hexagonal grid, or the like. In addition, for example, by arranging the pixels 10 in one dimension, the imaging device 100 can be used as a linear sensor.

[0096] exist Figure 1 In the illustrated configuration, the peripheral circuit 40 includes a vertical scanning circuit 46 and a horizontal signal readout circuit 48. The vertical scanning circuit 46 is also called a row scanning circuit, and is connected to the address signal lines 34 provided corresponding to the rows of the plurality of pixels 10. The horizontal signal readout circuit 48 is also called a column scanning circuit, and is connected to the vertical signal lines 35 provided corresponding to the columns of the plurality of pixels 10. Figure 1 As shown in the figure, these circuits are arranged in the peripheral region R2 outside the imaging region R1. The peripheral circuit 40 may further include a signal processing circuit, an output circuit, a control circuit, and a power supply for supplying a predetermined voltage to each pixel 10. A part of the peripheral circuit 40 may also be arranged on a substrate different from the semiconductor substrate 60 on which the pixel 10 is formed.

[0097] Figure 2 FIG. 2 is a diagram showing a circuit configuration of the imaging device 100 according to the present embodiment. Figure 2 In order to avoid the complexity of the drawings, Figure 1 Among the plurality of pixels 10 shown, four pixels 10 are arranged in two rows and two columns.

[0098] The photoelectric conversion unit 12 of each pixel 10 generates positive and negative charges, typically hole-electron pairs, upon receiving incident light. The photoelectric conversion unit 12 of each pixel 10 is connected to the accumulation control line 39, and a predetermined voltage is applied to the accumulation control line 39 when the imaging device 100 is in operation. By applying a predetermined voltage to the accumulation control line 39, one of the positive and negative charges generated by photoelectric conversion can be selectively accumulated in the charge accumulation region. The following is an example of using the positive charge of the positive and negative charges generated by photoelectric conversion as a signal charge.

[0099] Each pixel 10 includes a signal detection circuit 14 electrically connected to the photoelectric conversion unit 12. Figure 2In the illustrated configuration, the signal detection circuit 14 includes an amplifier transistor 22 and a reset transistor 26. In this example, the signal detection circuit 14 also includes an address transistor 24. As described in detail later with reference to the accompanying drawings, the amplifier transistor 22, the reset transistor 26, and the address transistor 24 of the signal detection circuit 14 are typically field effect transistors (FET: Field Effect Transistor) formed on a semiconductor substrate 60 supporting the photoelectric conversion unit 12. In the following, unless otherwise specified, an example using an N-channel MOSFET (metal oxide FET) as a transistor is described. In addition, which of the two diffusion layers of the FET corresponds to the source and the drain is determined by the polarity of the FET and the potential at that moment. Therefore, which one is the source and the drain may change depending on the operating state of the FET.

[0100] like Figure 2 As shown schematically in FIG. 1 , the gate of the amplifier transistor 22 is electrically connected to the photoelectric converter 12. The signal charge generated by the photoelectric converter 12 is accumulated in a charge accumulation region connected to a charge accumulation node ND between the photoelectric converter 12 and the amplifier transistor 22. The charge accumulation node ND corresponds to a wiring that electrically connects the charge accumulation region, the gate of the amplifier transistor 22, and the lower electrode of the photoelectric converter 12, and the charge accumulation region.

[0101] The drain of the amplifier transistor 22 is connected to a power supply wiring 32 that supplies a predetermined power supply voltage VDD to each pixel 10 when the imaging device 100 is in operation. The power supply (not shown) connected to the power supply wiring 32 is also called a source follower power supply. The power supply voltage VDD is, for example, about 3.3 V, but is not limited thereto. The amplifier transistor 22 outputs a signal voltage corresponding to the amount of signal charge generated by the photoelectric conversion unit 12. The source of the amplifier transistor 22 is connected to the drain of the address transistor 24.

[0102] The source of the address transistor 24 is connected to a vertical signal line 35. Figure 1 as well as Figure 2 As shown, the vertical signal line 35 is provided for each column of the plurality of pixels 10, and the vertical signal line 35 is respectively connected to the load circuit 42 and the column signal processing circuit 44. The load circuit 42 and the amplifier transistor 22 form a source follower circuit.

[0103] The gate of the address transistor 24 is connected to an address signal line 34. The address signal line 34 is provided for each row of a plurality of pixels 10. The address signal line 34 is connected to a vertical scanning circuit 46, and the vertical scanning circuit 46 applies a row selection signal for controlling the on and off state of the address transistor 24 to the address signal line 34. Thus, the row to be read out is scanned in the column direction as the vertical direction to select the row to be read out. By controlling the on and off state of the address transistor 24 via the address signal line 34 by the vertical scanning circuit 46, the output of the amplifier transistor 22 of the selected pixel 10 can be read out to the corresponding vertical signal line 35. The configuration of the address transistor 24 is not limited to Figure 2 In the example shown, the connection may be between the drain of the amplifier transistor 22 and the power supply wiring 32 .

[0104] The signal voltage from the pixel 10 output to the vertical signal line 35 via the address transistor 24 is input to a corresponding column signal processing circuit 44 among a plurality of column signal processing circuits 44 provided for each column of a plurality of pixels 10 corresponding to the vertical signal line 35. The column signal processing circuit 44 and the load circuit 42 may be part of the peripheral circuit 40 described above.

[0105] The column signal processing circuit 44 performs noise suppression signal processing represented by correlated double sampling, analog-to-digital conversion, etc. The column signal processing circuit 44 is connected to the horizontal signal readout circuit 48. The horizontal signal readout circuit 48 sequentially reads out signals from a plurality of column signal processing circuits 44 to a horizontal common signal line 49.

[0106] exist Figure 2 In the illustrated configuration, the signal detection circuit 14 includes a reset transistor 26 whose drain is connected to the charge accumulation node ND. A reset signal line 36 connected to a vertical scanning circuit 46 is connected to the gate of the reset transistor 26. The reset signal line 36 is provided for each row of a plurality of pixels 10, similarly to the address signal line 34. A row selection signal is applied to the address signal line 34 by the vertical scanning circuit 46, so that the pixel 10 to be reset can be selected in units of rows. In addition, the vertical scanning circuit 46 applies a reset signal for controlling the conduction and cutoff of the reset transistor 26 to the gate of the reset transistor 26 via the reset signal line 36, so that the reset transistor 26 of the selected row can be turned on. By turning on the reset transistor 26, the potential of the charge accumulation node ND is reset.

[0107] In this example, the source of the reset transistor 26 is connected to one of the feedback lines 53 provided for each column of the plurality of pixels 10. That is, in this example, the voltage of the feedback line 53 is supplied to the charge accumulation node ND as a reset voltage for initializing the charge of the photoelectric conversion unit 12. Here, the feedback line 53 is connected to an output terminal of a corresponding one of the inverting amplifiers 50 provided for each column of the plurality of pixels 10. The inverting amplifier 50 may be a part of the peripheral circuit 40 described above.

[0108] Focus on one of the columns of the plurality of pixels 10. Figure 2 As shown, the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of the column. In addition, the output terminal of the inverting amplifier 50 is connected to one or more pixels 10 belonging to the column via a feedback line 53. When the imaging device 100 is in operation, a predetermined voltage Vref is supplied to the non-inverting input terminal of the inverting amplifier 50. By selecting one of the one or more pixels 10 belonging to the column, the address transistor 24 and the reset transistor 26 are turned on, so that a feedback path for negatively feeding back the output of the pixel 10 can be formed. By forming the feedback path, the voltage of the vertical signal line 35 converges to the input voltage Vref of the non-inverting input terminal of the inverting amplifier 50. In other words, by forming the feedback path, the voltage of the charge accumulation node ND is reset to a voltage such that the voltage of the vertical signal line 35 becomes Vref. As the voltage Vref, a voltage of any magnitude within the range of the power supply voltage and the ground voltage can be used. For example, the voltage Vref is a voltage within the range of 0V or more and 3.3V or less. As an example, the voltage Vref is a positive voltage of 1V or about 1V. The inverting amplifier 50 may also be referred to as a feedback amplifier. In this way, the imaging device 100 includes the feedback circuit 16 including the inverting amplifier 50 in a part of the feedback path.

[0109] As is well known, thermal noise called kTC noise is generated when a transistor is turned on or off. The noise generated when the reset transistor 26 is turned on or off is called reset noise. After the potential of the charge accumulation region is reset, the reset noise generated by turning off the reset transistor 26 remains in the charge accumulation region before the accumulation of the signal charge. However, the reset noise generated when the reset transistor 26 is turned off can be reduced by using the feedback circuit 16. The details of suppressing the reset noise using the feedback circuit 16 are described in International Publication No. 2012 / 147302. The entire disclosure of International Publication No. 2012 / 147302 is cited in this specification for reference.

[0110] exist Figure 2 In the illustrated configuration, the AC component of the thermal noise is fed back to the source of the reset transistor 26 by forming a feedback path. Figure 2 In the illustrated configuration, since the feedback path is formed until immediately before the reset transistor 26 is turned off, the reset noise generated when the reset transistor 26 is turned off can be reduced.

[0111] Figure 3 It is a plan view showing the layout inside the pixel 10 of the imaging device 100 according to the present embodiment. Figure 3 Schematically showing the semiconductor substrate 60 viewed from a direction perpendicular to the semiconductor substrate 60 Figure 4 The arrangement of each element formed on the semiconductor substrate 60 in the pixel 10 shown in FIG. Figure 3 The figure shows the arrangement of the amplifier transistor 22, the address transistor 24, and the reset transistor 26 included in the pixel 10. Here, the amplifier transistor 22 and the address transistor 24 are arranged in a straight line in the vertical direction on the paper.

[0112] Figure 4 1 is a schematic cross-sectional view showing the device structure of the pixel 10 of the imaging device 100 according to the present embodiment. Figure 4 It is along Figure 3 The pixel 10 is cut along the IV-IV line in FIG. 1 and is developed in the direction of the arrow.

[0113] In addition, Figure 3 as well as Figure 4 In FIG. 6 , the first diffusion region 67 n which is an n-type impurity region is a drain region of the reset transistor 26 and is a charge accumulation region.

[0114] like Figure 3 as well as Figure 4 As shown in FIG. 1 , the pixel 10 in the image pickup device 100 of the present embodiment includes a reset transistor 26 including, as one of a source and a drain, a first diffusion region 67n that includes impurities of the first conductivity type and accumulates signal charges converted by the photoelectric conversion unit 12, and including, as the other of a source and a drain, a second diffusion region 68an that includes impurities of the first conductivity type. The reset transistor 26 is an example of a first transistor that includes the first diffusion region as one of a source and a drain and includes a first gate.

[0115] In this embodiment, the first conductivity type is n-type. In other words, the first diffusion region 67n and the second diffusion region 68an are n-type impurity regions. For example, the concentration of n-type impurities in the first diffusion region 67n is lower than the concentration of n-type impurities in the second diffusion region 68an. The first diffusion region 67n and the second diffusion region 68an are respectively provided at different positions in the semiconductor substrate 60.

[0116] Furthermore, the pixel 10 includes an amplifier transistor 22 and an address transistor 24. The amplifier transistor 22 and the address transistor 24 are examples of a second transistor including a second diffusion region as one of a source and a drain and including a second gate. The amplifier transistor 22 includes a second diffusion region 68bn including an n-type impurity as one of a source and a drain, and includes a third diffusion region 68cn including an n-type impurity as the other of a source and a drain. The address transistor 24 includes a second diffusion region 68dn including an n-type impurity as one of a source and a drain, and includes a third diffusion region 68cn including an n-type impurity as the other of a source and a drain. The second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn are examples of n-type impurity regions provided at different positions in the semiconductor substrate 60, respectively.

[0117] At this time, the concentration of n-type impurities in the first diffusion region 67n can be lower than the concentration of n-type impurities in the second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn. As a result, since the junction concentration in the junction (junction) between the first diffusion region 67n and the semiconductor substrate 60 becomes smaller, the electric field strength in the junction can be relaxed. Therefore, the leakage current flowing out of the first diffusion region 67n as a charge accumulation region or flowing into the first diffusion region 67n is reduced.

[0118] In the imaging device 100 of the present embodiment, the semiconductor substrate 60 contains impurities of the second conductivity type. The second conductivity type is a conductivity type different from the first conductivity type, and is the p-type in the present embodiment. The concentration of the n-type impurities contained in the first diffusion region 67n and the p-type impurities contained in the semiconductor substrate 60 can be, for example, 1×10 16 atoms / cm 3 Above and 5×10 16 atoms / cm 3 As a result, the junction concentration between the first diffusion region 67n and the semiconductor substrate 60 is reduced, and the increase in the electric field intensity in the junction can be suppressed. Therefore, the leakage current in the junction can be reduced.

[0119] like Figure 4As shown schematically, the pixel 10 generally includes a portion of a semiconductor substrate 60, a photoelectric conversion unit 12 disposed above the semiconductor substrate 60, and a wiring structure 80. The wiring structure 80 is disposed in an interlayer insulating layer 90 formed between the photoelectric conversion unit 12 and the semiconductor substrate 60, and includes a structure for electrically connecting the amplifier transistor 22 formed on the semiconductor substrate 60 to the photoelectric conversion unit 12. Here, the interlayer insulating layer 90 has a stacked structure of insulating layers including four layers of insulating layers 90a, 90b, 90c, and 90d. The wiring structure 80 has four wiring layers of wiring layers 80a, 80b, 80c, and 80d, and plugs pa1, pa2, pa3, pa4, pa5, pa6, pa7, pb, pc, and pd disposed between these wiring layers.

[0120] In addition, the wiring layer 80a is the layer closest to the semiconductor substrate 60 among the plurality of wiring layers included in the wiring structure 80. Specifically, the wiring layer 80a includes contact plugs cp1, cp2, cp3, and cp4, as well as gate electrodes 22e, 24e, and 26e. It is needless to say that the number of insulating layers in the interlayer insulating layer 90 and the number of wiring layers in the wiring structure 80 are not limited to this example, and can be set arbitrarily.

[0121] The photoelectric conversion unit 12 is arranged on the interlayer insulating layer 90. The photoelectric conversion unit 12 includes a pixel electrode 12a formed on the interlayer insulating layer 90, a transparent electrode 12c opposite to the pixel electrode 12a, and a photoelectric conversion layer 12b arranged between the pixel electrode 12a and the transparent electrode 12c. The photoelectric conversion layer 12b of the photoelectric conversion unit 12 is formed of an organic material or an inorganic material such as amorphous silicon, receives light incident through the transparent electrode 12c, and generates positive and negative charges by photoelectric conversion. The photoelectric conversion layer 12b is typically formed continuously over a plurality of pixels 10. The photoelectric conversion layer 12b is formed in a flat plate shape covering most of the imaging region R1 of the semiconductor substrate 60 in a plan view. In other words, the photoelectric conversion layer 12b is shared by a plurality of pixels 10. In other words, the photoelectric conversion unit 12 provided for each pixel 10 has a different portion of the photoelectric conversion layer 12b for each pixel 10. In addition, the photoelectric conversion layer 12b may also include a layer composed of an organic material and a layer composed of an inorganic material. The photoelectric conversion layer 12 b may be provided separately for each pixel 10 .

[0122] The transparent electrode 12c is formed of a transparent conductive material such as ITO (Indium Tin Oxide) and is disposed on the light-receiving surface side of the photoelectric conversion layer 12b. The transparent electrode 12c is typically formed continuously over a plurality of pixels 10, similarly to the photoelectric conversion layer 12b. In other words, the transparent electrode 12c is shared by a plurality of pixels 10. In other words, the photoelectric conversion unit 12 provided for each pixel 10 has a different portion of the transparent electrode 12c for each pixel 10. The transparent electrode 12c may also be provided separately for each pixel 10.

[0123] exist Figure 4 Although not shown in the figure, the transparent electrode 12c is connected to the above-mentioned accumulation control line 39. When the camera device 100 is in operation, the potential of the accumulation control line 39 is controlled so that the potential of the transparent electrode 12c is different from the potential of the pixel electrode 12a, so that the signal charge generated by photoelectric conversion can be collected by the pixel electrode 12a. For example, the potential of the accumulation control line 39 is controlled in such a way that the potential of the transparent electrode 12c is higher than the potential of the pixel electrode 12a. Specifically, for example, a positive voltage of about 10V is applied to the accumulation control line 39. As a result, the holes in the hole-electron pairs generated in the photoelectric conversion layer 12b can be collected as signal charges by the pixel electrode 12a. The signal charges collected by the pixel electrode 12a are accumulated in the first diffusion region 67n via the wiring structure 80.

[0124] The pixel electrode 12a is an electrode formed of a metal such as aluminum or copper, a metal nitride, or polysilicon that has been given conductivity by doping with impurities. The pixel electrode 12a is spatially separated from the pixel electrodes 12a of other adjacent pixels 10, thereby being electrically separated from the pixel electrodes 12a of other pixels 10.

[0125] like Figure 4 As shown in FIG. 1 , the semiconductor substrate 60 includes a support substrate 61 and one or more semiconductor layers formed on the support substrate 61. Here, a p-type silicon (Si) substrate is exemplified as the support substrate 61. In this example, the semiconductor substrate 60 includes a p-type semiconductor layer 61p on the support substrate 61, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, a p-type semiconductor layer 63p on the n-type semiconductor layer 62n, and a p-type semiconductor layer 65p on the p-type semiconductor layer 63p. The p-type semiconductor layer 63p is formed on the entire surface of the support substrate 61. The p-type semiconductor layer 65p includes a p-type impurity region 66p having a lower impurity concentration than the p-type semiconductor layer 65p, a first diffusion region 67n formed in the p-type impurity region 66p, a second diffusion region 68an, a second diffusion region 68bn, and a second diffusion region 68dn, a third diffusion region 68cn, and an element isolation region 69.

[0126] Each of the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p is typically formed by ion implantation of impurities into a semiconductor layer formed by epitaxial growth. The impurity concentrations in the p-type semiconductor layer 63p and the p-type semiconductor layer 65p are of the same level and higher than the impurity concentration in the p-type semiconductor layer 61p. The n-type semiconductor layer 62n disposed between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p suppresses the inflow of a small amount of carriers from the support substrate 61 or the peripheral circuit 40 into the first diffusion region 67n, which is a charge accumulation region for accumulating signal charges. When the imaging device 100 is in operation, the potential of the n-type semiconductor layer 62n is adjusted via the voltage set at Figure 1 The imaging region R1 is shown to be controlled by a well contact (not shown) outside the imaging region R1.

[0127] In addition, in this example, the semiconductor substrate 60 has a p-type region 64 provided between the p-type semiconductor layer 63p and the support substrate 61 so as to penetrate the p-type semiconductor layer 61p and the n-type semiconductor layer 62n. The p-type region 64 has a higher impurity concentration than the p-type semiconductor layer 63p and the p-type semiconductor layer 65p, and electrically connects the p-type semiconductor layer 63p and the support substrate 61. When the imaging device 100 is in operation, the potential of the p-type semiconductor layer 63p and the support substrate 61 is controlled via a substrate contact (not shown) provided outside the imaging region R1. By configuring the p-type semiconductor layer 65p in contact with the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can be controlled via the p-type semiconductor layer 63p when the imaging device 100 is in operation.

[0128] The amplifier transistor 22, the address transistor 24, and the reset transistor 26 are formed on the semiconductor substrate 60. The reset transistor 26 includes a first diffusion region 67n and a second diffusion region 68an, a portion of an insulating layer 70 formed on the semiconductor substrate 60, and a gate electrode 26e on the insulating layer 70. The gate electrode 26e is an example of a first gate, and specifically functions as a gate of the reset transistor 26. The first diffusion region 67n and the second diffusion region 68an function as a drain region and a source region of the reset transistor 26, respectively. The first diffusion region 67n functions as a charge accumulation region that temporarily accumulates signal charges generated by the photoelectric conversion unit 12.

[0129] The amplifier transistor 22 includes a second diffusion region 68bn and a third diffusion region 68cn, a portion of the insulating layer 70, and a gate electrode 22e on the insulating layer 70. The gate electrode 22e is an example of a second gate, and specifically functions as a gate of the amplifier transistor 22. The second diffusion region 68bn and the third diffusion region 68cn function as a drain region and a source region of the amplifier transistor 22, respectively.

[0130] An element isolation region 69 is disposed between the second diffusion region 68bn and the first diffusion region 67n. The element isolation region 69 is, for example, a p-type impurity diffusion region. The impurity concentration of the element isolation region 69 is higher than the impurity concentration of the p-type semiconductor layer 65p and the p-type impurity region 66p. The element isolation region 69 electrically isolates the amplifier transistor 22 and the reset transistor 26.

[0131] like Figure 4 As shown in the schematic diagram, the first diffusion region 67n is formed in the p-type impurity region 66p, so that the first diffusion region 67n and the element isolation region 69 are arranged not in contact with each other. For example, when a p-type impurity region is used as the element isolation region 69, if the first diffusion region 67n is in contact with the element isolation region 69, both the p-type impurity concentration and the n-type impurity concentration in the junction portion increase. Therefore, leakage current caused by the high junction concentration is likely to occur around the junction portion between the first diffusion region 67n and the element isolation region 69. In other words, by arranging the first diffusion region 67n and the element isolation region 69 not in contact with each other, even if a high-concentration p-type impurity region is used for the element isolation region 69, the increase in pn junction concentration can be suppressed, and leakage current can be suppressed. In addition, although there is a method of using STI (Shallow Trench Isolation) as the element isolation region 69, in this case, in order to reduce the leakage current caused by the crystal defects in the STI sidewall portion, the first diffusion region 67n and the STI can also be arranged in a manner that they are not in contact with each other.

[0132] The element isolation region 69 is also disposed between adjacent pixels 10 to electrically isolate the signal detection circuits 14 between the pixels 10. Here, the element isolation region 69 is provided around the group of the amplifier transistor 22 and the address transistor 24 and around the reset transistor 26.

[0133] The address transistor 24 includes a third diffusion region 68cn and a second diffusion region 68dn, a portion of the insulating layer 70, and a gate electrode 24e on the insulating layer 70. The gate electrode 24e is an example of a second gate, and specifically functions as a gate of the address transistor 24. In this example, the address transistor 24 shares the third diffusion region 68cn with the amplifier transistor 22, thereby being electrically connected to the amplifier transistor 22. The third diffusion region 68cn functions as a drain region of the address transistor 24, and the second diffusion region 68dn functions as a source region of the address transistor 24.

[0134] In this example, an insulating layer 71 is provided to cover the gate electrode 26e of the reset transistor 26, the gate electrode 22e of the amplifier transistor 22, and the gate electrode 24e of the address transistor 24. The insulating layer 71 is, for example, a silicon oxide film and may have a stacked structure including a plurality of insulating layers.

[0135] like Figure 4 as well as Figure 5 As shown in FIG. 1 , the side wall 73 of the contact plug cp1 and the side wall 74 of the gate electrode 26e are located on the insulating layer 71. The side wall 73 and the side wall 74 are formed of, for example, a silicon nitride film. The side wall 73 and the side wall 74 are embedded between the contact plug cp1 and the gate electrode 26e. In other words, in the portion between the contact plug cp1 and the gate electrode 26e, the side wall 73 and the side wall 74 cover the first diffusion region 67n in a plan view.

[0136] Therefore, compared with the case where the first diffusion region 67n is covered only by the insulating layer 70 and the insulating layer 71 in the portion between the contact plug cp1 and the gate electrode 26e, damage to the first diffusion region 67n and contamination caused by diffusion of the metal can be reduced. The damage to the first diffusion region 67n refers to damage caused by, for example, using plasma in a process after the formation of the first diffusion region 67n. The damage caused by plasma refers to physical damage caused by, for example, collision of accelerated ions and generation of photo-induced defects. The light refers to, for example, ultraviolet rays. In this embodiment, as described later, the distance between the pad cp1b and the gate electrode 26e is made close. Accordingly, it is easy to bury the portion between the contact plug cp1 and the gate electrode 26e by the side wall 73 and the side wall 74. It is also possible to bury only the portion between the contact plug cp1 and the gate electrode 26e by the side wall without providing the side wall 73. It is also possible to bury between other contact plugs and the gate electrode by the side wall. In this case, the same effect can be obtained for other impurity regions.

[0137] The insulating layer 70 and the insulating layer 71 have a plurality of contact holes. Figure 4As shown, contact holes h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, and h11 are provided in the insulating layer 70 and the insulating layer 71. When the contact holes h1-h4 are viewed from a direction perpendicular to the semiconductor substrate 60, they are located at positions overlapping the first diffusion region 67n and the second diffusion region 68an, the second diffusion region 68bn, and the second diffusion region 68dn, respectively. The contact holes h1-h4 are through holes penetrating the insulating layer 70. Contact plugs cp1-cp4 are arranged at the positions of the contact holes h1-h4, respectively. The film thickness of the insulating layer 70 is, for example, 10 nm, but is not limited thereto.

[0138] The contact holes h5-h7 are formed at positions overlapping the gate electrodes 26e, 22e, and 24e, respectively, when viewed from a direction perpendicular to the semiconductor substrate 60. The contact holes h5-h7 are through holes penetrating the insulating layer 71. The plugs pa3, pa2, and pa4 are arranged at the positions of the contact holes h5-h7, respectively.

[0139] The contact holes h8-h11 are formed at positions overlapping the contact plugs cp1-cp4 when viewed from a direction perpendicular to the semiconductor substrate 60. The contact holes h8-h11 are through holes penetrating the insulating layer 71. Plugs pa1, pa5, pa6, and pa7 are arranged at the positions of the contact holes h8-h11.

[0140] exist Figure 4 In the illustrated configuration, the wiring layer 80a is a layer having contact plugs cp1-cp4 and gate electrodes 22e, 24e and 26e, and is typically a polysilicon layer doped with n-type impurities. The wiring layer 80a is disposed at a position closest to the semiconductor substrate 60 among the wiring layers included in the wiring structure 80.

[0141] The wiring layer 80b and the plugs pa1-pa7 are arranged in the insulating layer 90a. The wiring layer 80b is arranged in the insulating layer 90a and can partially include the vertical signal line 35, the address signal line 34, the power supply line 32, the reset signal line 36, and the feedback line 53 described above.

[0142] Plug pa1 connects contact plug cp1 to wiring layer 80b. Plug pa2 connects gate electrode 22e to wiring layer 80b. In other words, first diffusion region 67n and gate electrode 22e of amplifier transistor 22 are electrically connected to each other via contact plug cp1, plug pa1 and plug pa2, and wiring layer 80b.

[0143] The plug pa3 connects the reset signal line 36 included in the wiring layer 80b to the gate electrode 26e. The plug pa4 connects the address signal line 34 included in the wiring layer 80b to the gate electrode 24e. The plug pa5 connects the feedback line 53 included in the wiring layer 80b to the contact plug cp2. The plug pa6 connects the power supply wiring 32 included in the wiring layer 80b (in Figure 4 The plug pa7 connects the vertical signal line 35 included in the wiring layer 80b to the contact plug cp4.

[0144] According to this configuration, the vertical signal line 35 is connected to the second diffusion region 68dn via the plug pa7 and the contact plug cp4. The address signal line 34 is connected to the gate electrode 24e via the plug pa4. The power supply wiring 32 is connected to the second diffusion region 68bn via the plug pa6 and the contact plug cp3. The reset signal line 36 is connected to the gate electrode 26e via the plug pa3. The feedback line 53 is connected to the second diffusion region 68an via the plug pa5 and the contact plug cp2.

[0145] Furthermore, at least one of the vertical signal line 35 , the address signal line 34 , the power supply line 32 , the reset signal line 36 , and the feedback line 53 may be included in the wiring layer 80 c or 80 d instead of being included in the wiring layer 80 b .

[0146] The plug pb disposed in the insulating layer 90b connects the wiring layer 80b to the wiring layer 80c. Similarly, the plug pc disposed in the insulating layer 90c connects the wiring layer 80c to the wiring layer 80d. The plug pd disposed in the insulating layer 90d connects the wiring layer 80d to the pixel electrode 12a of the photoelectric conversion unit 12. The wiring layers 80b-80d, the plugs pa1-pa7, and the plugs pb-pd are typically formed of a metal such as copper or tungsten, a metal nitride, or a metal compound such as a metal oxide.

[0147] The plug pa1, the plug pa2, the plugs pb-pd, the wiring layers 80b-80d, and the contact plug cp1 electrically connect the photoelectric converter 12 to the signal detection circuit 14 formed on the semiconductor substrate 60. The plug pa1, the plug pa2, the plugs pb-pd, the wiring layers 80b-80d, the contact plug cp1, the pixel electrode 12a of the photoelectric converter 12, the gate electrode 22e of the amplifier transistor 22, and the first diffusion region 67n function as a charge accumulation node for accumulating signal charges generated by the photoelectric converter 12.

[0148] Here, attention is paid to the n-type impurity region formed in the semiconductor substrate 60. The first diffusion region 67n formed in the n-type impurity region of the semiconductor substrate 60 is arranged in the p-type impurity region 66p formed in the p-type semiconductor layer 65p as a p-well. The first diffusion region 67n is formed near the surface of the semiconductor substrate 60, and at least a part of it is located on the surface of the semiconductor substrate 60. The junction (junction) capacitance formed by the pn junction between the p-type impurity region 66p and the first diffusion region 67n functions as a capacitance that accumulates at least a part of the signal charge, and constitutes a part of the charge accumulation node.

[0149] exist Figure 4 In the illustrated configuration, the first diffusion region 67n includes the first region 67a and the second region 67b. The impurity concentration of the first region 67a of the first diffusion region 67n is lower than that of the second diffusion region 68an, the second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn. The second region 67b of the first diffusion region 67n is formed in the first region 67a and has a higher impurity concentration than that of the first region 67a. In addition, the contact hole h1 is located on the second region 67b, and the contact plug cp1 is connected to the second region 67b via the contact hole h1.

[0150] As described above, by arranging the p-type semiconductor layer 65p adjacent to the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can be controlled via the p-type semiconductor layer 63p during the operation of the imaging device 100. By adopting such a structure, the first region 67a, which is a region with a relatively low impurity concentration, and the p-type impurity region 66p can be arranged around the second region 67b, which is the first diffusion region 67n, which is the portion that contacts the semiconductor substrate 60 and is electrically connected to the photoelectric conversion unit 12. By relatively increasing the impurity concentration of the second region 67b, which is the connection portion between the contact plug cp1 and the semiconductor substrate 60, it is possible to obtain an effect of suppressing the expansion of the depletion layer around the connection portion between the contact plug cp1 and the semiconductor substrate 60, that is, depletion.

[0151] In this way, by suppressing depletion around the portion where the contact plug cp1 contacts the semiconductor substrate 60, leakage current caused by defect levels of the semiconductor substrate 60 at the interface between the contact plug cp1 and the semiconductor substrate 60 can be suppressed. In addition, by connecting the contact plug cp1 to the second region 67b having a high impurity concentration, the effect of reducing contact resistance can be obtained.

[0152] The contact plug cp1 is an example of a first plug made of a semiconductor and is connected to the first diffusion region 67n. The contact plug cp1 is electrically connected to the photoelectric converter 12. Here, electrical connection means that the potential is substantially equal to that of the pixel electrode 12a of the photoelectric converter 12. In addition, wiring resistance is not considered.

[0153] The contact plug cp2, the contact plug cp3, and the contact plug cp4 are each an example of a second plug including a semiconductor. The contact plug cp2 is connected to the second diffusion region 68an. The contact plug cp3 is connected to the second diffusion region 68bn. The contact plug cp4 is connected to the second diffusion region 68dn. The contact plug cp3 and the contact plug cp4 are not electrically connected to the photoelectric conversion unit 12. In this embodiment, the contact plug cp2, the contact plug cp3, and the contact plug cp4 have the same structure as each other. Figure 5 , the specific structures of the contact plug cp1 and the contact plug cp3 are described.

[0154] Figure 5 2 is a cross-sectional view showing an enlarged view of the vicinity of two contact plugs of the imaging device of this embodiment. Specifically, Figure 5 Will Figure 4 In the cross-sectional view shown, a range including the contact plug cp1 and the contact plug cp3 is shown in an enlarged manner.

[0155] like Figure 5 As shown, the contact plug cp1 has a contact cp1a and a pad cp1b. The contact cp1a and the pad cp1b are each a part of the contact plug cp1. The contact plug cp1 is formed using a conductive semiconductor material such as polysilicon. The contact plug cp1 contains a first conductive type impurity. The first conductive type impurity is, for example, an n-type impurity such as phosphorus.

[0156] The contact cp1a is an example of the first contact, and is in contact with the first diffusion region 67n and penetrates the insulating layer 70. Specifically, the contact cp1a is provided so as to fill the contact hole h1. The top view shape of the contact cp1a is consistent with the top view shape of the contact hole h1. Figure 3 As shown, the top view shape of the contact cp1a is, for example, circular, but may also be rectangular.

[0157] The pad cp1b is an example of a first pad, is located on the contact cp1a, and has a larger area than the contact cp1a when viewed from a direction perpendicular to the semiconductor substrate 60. Figure 3 As shown, the pad cp1b completely covers the contact cp1a in a top view. The contact cp1a is located in the center of the pad cp1b. The top view shape of the pad cp1b is, for example, a rectangle, but is not limited thereto. The top view shape of the pad cp1b is consistent with the top view shape of the plug cp1.

[0158] like Figure 5 As shown, the contact plug cp3 has a contact cp3a and a pad cp3b. The contact cp3a and the pad cp3b are respectively a part of the contact plug cp3. The contact plug cp3 is formed using a conductive semiconductor material such as polysilicon. The contact plug cp3 contains impurities of the first conductive type. The impurities of the first conductive type are, for example, n-type impurities such as phosphorus. In this embodiment, the concentration of the impurities of the contact plug cp3 is equal to the concentration of the impurities of the contact plug cp1.

[0159] The contact cp3a is an example of the second contact, and is in contact with the second diffusion region 68bn and penetrates the insulating layer 70. Specifically, the contact cp3a is provided in a manner to fill the contact hole h3. The top view shape of the contact cp3a is consistent with the top view shape of the contact hole h3. Figure 3 As shown, the top view shape of the contact cp3a is, for example, circular, but may also be rectangular.

[0160] The pad cp3b is an example of a second pad, is located on the contact cp3a, and has a larger area than the contact cp3a when viewed from a direction perpendicular to the semiconductor substrate 60. Figure 3 As shown, the pad cp3b completely covers the contact cp3a in a top view. The contact cp3a is located in the center of the pad cp3b. The top view shape of the pad cp3b is, for example, a rectangle, but is not limited thereto. The top view shape of the pad cp3b is consistent with the top view shape of the plug cp3.

[0161] In this embodiment, if Figure 3 As shown, in a top view, the area of ​​the contact plug cp1 is smaller than the areas of the contact plugs cp2, cp3, and cp4. In other words, when viewed from a direction perpendicular to the semiconductor substrate 60, the areas of the contact plugs cp2, cp3, and cp4 are larger than the area of ​​the contact plug cp1. For example, in a top view, the contact plug cp1 has the smallest area among the multiple plugs included in the pixel 10.

[0162] For example, in a plan view, the area of ​​the pad cp1b is smaller than the area of ​​the pad cp3b. In the present embodiment, the area of ​​the contact cp1a is equal to the area of ​​the contact cp3a.

[0163] In addition, in this embodiment, if Figure 3As shown, the width W3 of the pad cp3b is longer than the width W1 of the pad cp1b. The width W1 is the length of the pad cp1b in a direction parallel to the width direction of the gate electrode 26e of the reset transistor 26. The width W3 is the length of the pad cp3b in a direction parallel to the width direction of the gate electrode 22e of the amplifying transistor 22. For example, the width W1 is shorter than the width of any pad of the other contact plugs cp2, contact plugs cp3, and contact plugs cp4 included in the pixel 10.

[0164] As described above, the contact plug cp1 is connected to the second region 67b of the first diffusion region 67n. The second region 67b contains impurities thermally diffused from the contact plug cp1 via the contact hole h1. The impurities are, for example, n-type impurities. The n-type impurities are, for example, phosphorus. As described above, in a top view, the area of ​​the contact plug cp1 is smaller than the areas of the contact plug cp2, the contact plug cp3, and the contact plug cp4. Therefore, the amount of impurities contained in the contact plug cp1 can be made smaller than the amount of impurities contained in the contact plug cp2, the contact plug cp3, and the contact plug cp4. Therefore, the impurity concentration of the second region 67b formed under the contact plug cp1 can be made lower than the impurity concentration of the regions respectively formed under the contact plug cp2, the contact plug cp3, and the contact plug cp4. Thus, the junction leakage around the second region 67b can be suppressed.

[0165] In this example, the first region 67a having a lower impurity concentration than the second region 67b is interposed between the second region 67b and the p-type impurity region 66p, and the first region 67a is also interposed between the second region 67b and the p-type semiconductor layer 65p. By arranging the first region 67a having a relatively low impurity concentration around the second region 67b, the electric field strength formed by the pn junction between the first diffusion region 67n and the p-type semiconductor layer 65p or the p-type impurity region 66p can be relaxed. By relaxing the electric field strength, leakage current caused by the electric field formed by the pn junction can be suppressed.

[0166] Figure 6 1 is a diagram showing the concentration distribution of electrons and holes near the contact plug cp1 when the width of the pad cp1b of the imaging device 100 according to the present embodiment is changed. Figure 6 The concentration distribution shown in part (a) of FIG. 1 shows a case where the contact plug cp1 does not have the pad cp1b, in other words, a case where the width W1 of the pad cp1b is equal to the width of the contact cp1a. Figure 6 The concentration distributions shown in parts (b), (c) and (d) respectively show the cases where the distance between the pad cp1b and the surface of the semiconductor substrate 60 is 50nm, and the width W1 of the pad cp1b is 90nm, 200nm, 300nm and 400nm. Figure 6The concentration distribution shown in part (e) shows a case where the width W1 of the pad cp1b is sufficiently large relative to the width of the contact cp1a, and specifically, can be regarded as infinite in simulation. Figure 6 The concentration distributions shown in parts (f), (g), and (h) respectively show the case where the distance between the pad cp1b and the surface of the semiconductor substrate 60 is 10nm, and the width W1 of the pad cp1b is 200nm, 300nm, and 400nm. Figure 6 In the example shown, a voltage of 0.5 V is applied to each pad.

[0167] In addition, Figure 6 In each concentration distribution, a region with more electrons is plotted with a higher density of dots, and a region with more holes is plotted with a lower density of dots. The solid lines drawn in each region are the isoconcentration lines of electrons or holes. Specifically, the region with more electrons is the region with an electron concentration of 1×10 14 / cm3 or more. Specifically, the area containing more holes is the area with a hole concentration of 1×10 14 It is found that the region containing many electrons expands from the contact cp1a of the contact plug cp1 toward the inside of the first diffusion region 67n.

[0168] The area between the region containing more electrons and the region containing more holes corresponds to the depletion layer. The width of the depletion layer on the surface of the semiconductor substrate 60 is indicated by a double arrow, and the width of the depletion layer in each distribution diagram is shown in a numerical diagram.

[0169] like Figure 6 As shown, it can be seen that the larger the width of the pad cp1b, that is, the larger the area of ​​the pad cp1b, the larger the width of the depletion layer. In other words, the smaller the width of the pad cp1b, that is, the smaller the area of ​​the pad cp1b, the smaller the width of the depletion layer. The same trend can be observed in any case where the distance between the pad cp1b and the surface of the semiconductor substrate 60 is 50nm and 10nm. Therefore, by reducing the area of ​​the contact plug cp1, the area of ​​the depletion layer on the surface of the semiconductor substrate 60 can be reduced.

[0170] In addition, the reason why the width of the depletion layer is smaller as the area of ​​the pad cp1b is smaller can be inferred as follows. The signal charge among the charges generated by the photoelectric conversion unit 12 is accumulated in the first diffusion region 67n via the contact plug cp1. When the signal charge is, for example, a hole, the contact plug cp1 is positively charged. In other words, the potential of the contact plug cp1 rises. At this time, a positive electric field is applied to the surface of the semiconductor substrate 60 from the pad cp1b. Due to the influence of the positive electric field, the holes, which are the majority carriers in the semiconductor substrate 60, are pushed outward from the pad cp1b in a plan view. As a result, the area of ​​the depletion layer on the surface of the semiconductor substrate 60 increases.

[0171] In addition, in this embodiment, if Figure 3 As shown, the distance L3 is longer than the distance L1. The distance L1 is the distance between the pad cp1b and the gate electrode 26e. The distance L3 is the distance between the pad cp3b and the gate electrode 22e. For example, the distance L1 is shorter than any of the distances between the pads of the other contact plugs cp2, cp3, and cp4 included in the pixel 10 and the gate electrode closest to each pad.

[0172] By shortening the distance between the contact plug cp1 connected to the first diffusion region 67n functioning as a charge accumulation region and the gate electrode 26e of the reset transistor 26 including the first diffusion region 67n as a drain or source, the depletion layer can be prevented from expanding toward the gate electrode 26e.

[0173] In this way, a depletion layer region is formed between the first diffusion region 67n and the p-type impurity region 66p. Generally, the crystal defect density near the surface of the semiconductor substrate 60 is higher than the crystal defect density inside the semiconductor substrate 60. Therefore, among the depletion layer regions formed at the pn junction (junction) portion where the first diffusion region 67n and the p-type impurity region 66p are joined, the depletion layer region formed at the junction near the surface of the semiconductor substrate 60 has a larger leakage current than the depletion layer region formed at the pn junction portion inside the semiconductor substrate 60.

[0174] In addition, if the area of ​​the depletion layer region (hereinafter referred to as "interface depletion layer") formed at the junction of the surface of the semiconductor substrate 60 increases, the leakage current tends to increase. In other words, the leakage current can be suppressed by reducing the area of ​​the interface depletion layer exposed on the surface of the semiconductor substrate 60. For example, the area of ​​the interface depletion layer can be minimized.

[0175] In this embodiment, as described above, in a plan view, the area of ​​the contact plug cp1 connected to the first diffusion region 67n is smaller than the area of ​​the contact plug cp3 connected to the second diffusion region 68bn. Figure 6As shown in FIG. 6 , the area of ​​the interface depletion layer that expands toward the vicinity of the first diffusion region 67 n can be reduced. Therefore, leakage current flowing out of the first diffusion region 67 n or flowing into the first diffusion region 67 n can be suppressed.

[0176] In order to reduce the area of ​​the interface depletion layer, the area of ​​the first diffusion region 67n may be formed smaller than the area of ​​the second diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60. For example, the area of ​​the first diffusion region 67n may be less than 1 / 2 of the area of ​​the second diffusion region 68an when viewed from the direction perpendicular to the semiconductor substrate 60. In addition, in this case, the width of the first diffusion region 67n in the channel width direction may be less than 1 / 2 of the width of the second diffusion region 68an in the channel width direction. In addition, the first diffusion region 67n and the second diffusion region 68an may have the same size in either the width in the channel width direction or the length in the channel length direction. In addition, the area of ​​the first diffusion region 67n may be formed smaller than the areas of the other second diffusion regions 68bn and 68dn, and the third diffusion region 68cn when viewed from the direction perpendicular to the semiconductor substrate 60.

[0177] In addition, consider the case where the element isolation region 69 is formed after the gate and the contact plug are formed around the first diffusion region 67n and the p-type impurity region 66p. The element isolation region 69 is formed after the first diffusion region 67n and the contact plug cp1 are formed. The element isolation region 69 is formed outside the first diffusion region 67n and the contact plug cp1. Therefore, if the area of ​​the contact plug cp1 is large, the interval between the first diffusion region 67n and the p-type impurity region 66p and the element isolation region 69 is expanded. Therefore, the depletion layer area is expanded and the junction leakage increases. In addition, it is possible that impurities with opposite polarity to the contact plug cp1 for forming the element isolation region 69 are introduced into the contact plug cp1. As a result, for example, a problem of increased contact resistance occurs. In the case where the area of ​​the contact plug cp1 is large, it is considered that the amount of impurities introduced is also increased, so the degree of increase in contact resistance is also increased. On the other hand, by reducing the area of ​​the contact plug cp1, the increase in junction leakage and the increase in contact resistance can be suppressed.

[0178] Furthermore, the areas of the first diffusion region 67n and the second diffusion region 68an may be obtained by excluding the areas of the portions overlapping with the gate electrode 26e of the reset transistor 26 when viewed from the direction perpendicular to the semiconductor substrate 60. Similarly, the areas of the second diffusion region 68bn, the second diffusion region 68dn, and the third diffusion region 68cn may be obtained by excluding the areas of the portions overlapping with the gate electrode 22e of the amplifier transistor 22 and the gate electrode 24e of the address transistor 24 when viewed from the direction perpendicular to the semiconductor substrate 60. The portions overlapping with the gate electrode 22e, the gate electrode 24e, and the gate electrode 26e when viewed from the direction perpendicular to the semiconductor substrate 60 are less likely to be damaged during manufacturing than the portions not overlapping with the gate electrode 22e, the gate electrode 24e, and the gate electrode 26e. Examples of damage during manufacturing include damage caused by plasma processing used in a dry etching process and damage caused by ashing processing when stripping the resist. Therefore, it is difficult for leakage current to occur in the portion overlapping with the gate electrode 22e, the gate electrode 24e, and the gate electrode 26e. Therefore, in terms of reducing the area of ​​the interface depletion layer, for the first diffusion region 67n, the second diffusion region 68bn and the second diffusion region 68dn, and the third diffusion region 68cn, only the influence of the area of ​​the portion not overlapping with the gate electrode 22e, the gate electrode 24e, and the gate electrode 26e is considered.

[0179] Furthermore, by reducing the area of ​​the first diffusion region 67n, the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e is shorter than the distance between the contact hole h2 formed in the second diffusion region 68an and the gate electrode 26e. Figure 3 As shown in FIG. 1 , the distance L1 between the pad cp1b of the contact plug cp1 and the gate electrode 26e is shorter than the distance between the pad of the contact plug cp2 and the gate electrode 26e. As described above, since the impurity concentration of the first diffusion region 67n is low, the resistance value is higher than that of the second diffusion region 68an. Therefore, by shortening the distance between the contact hole h1 and the gate electrode 26e, the current path in the first diffusion region 67n becomes shorter, and thus the resistance value in the first diffusion region 67n becomes smaller.

[0180] Furthermore, the distance between the contact hole h1 formed in the first diffusion region 67n and the gate electrode 26e may be shorter than the distance between the contact hole h3 formed in the second diffusion region 68bn and the gate electrode 22e, or shorter than the distance between the contact hole h4 formed in the second diffusion region 68dn and the gate electrode 24e. In other words, the distance L1 may be shorter than the distance L3 between the pad cp3b of the contact plug cp3 and the gate electrode 22e. Alternatively, the distance L1 may be shorter than the distance between the pad of the contact plug cp4 and the gate electrode 24e.

[0181] (Variant 1)

[0182] Next, Modification 1 of the present embodiment will be described. Hereinafter, the description will be mainly focused on the differences from Embodiment 1, and the description of the common points will be omitted or simplified.

[0183] Figure 7 1 is a plan view showing the layout in a pixel 10A of the imaging device according to the present modification. The pixel 10A is different from the pixel 10 according to the first embodiment in the area of ​​the contact cp1Aa.

[0184] Specifically, Figure 7 As shown, the pixel 10A includes a contact plug cp1A instead of the contact plug cp1, compared with the pixel 10 of Embodiment 1. The contact plug cp1A includes a contact cp1Aa and a pad cp1b.

[0185] When viewed from a direction perpendicular to the semiconductor substrate 60, the area of ​​the contact cp1Aa is smaller than the area of ​​the contact cp3a. For example, the area of ​​the contact cp1Aa may be less than half the area of ​​the contact cp3. In addition, the area of ​​the contact cp1Aa may be smaller than the area of ​​each contact of the contact plug cp2 and the contact plug cp4. In other words, the area of ​​the contact cp1Aa may be the smallest area among the contacts of all the contact plugs included in the pixel 10A.

[0186] Thus, by making the contact cp1Aa smaller than the contacts of the other contact plugs cp2, cp3, and cp4, the concentration of impurities thermally diffused to the first diffusion region 67n through the contact cp1Aa can be reduced. As a result, in the first diffusion region 67n directly below the contact plug cp1A, the expansion of the region where the impurities contained in the contact plug cp1A diffuse is suppressed. Specifically, the high concentration region of n-type impurities is difficult to expand in the first diffusion region 67n. Therefore, for example, even if the p-type element isolation region 69 is brought close to the first diffusion region 67n, the electric field strength at the interface between the high concentration region of n-type impurities in the first diffusion region 67n and the p-type element isolation region 69 can be suppressed to a certain value or less. Therefore, the electric field strength at the interface between the high concentration region of n-type impurities in the first diffusion region 67n and the p-type element isolation region 69 can be suppressed to a certain value or less, and the distance between the high concentration region of n-type impurities and the p-type element isolation region 69 can be set to a certain value or less. This can suppress the expansion of the interface depletion layer, and thus suppress the increase in leakage current.

[0187] (Variant 2)

[0188] Next, a modification example 2 of the present embodiment will be described. Hereinafter, the description will be mainly focused on the differences from the first embodiment, and the description of the common points will be omitted or simplified.

[0189] Figure 8 1 is a plan view showing the layout in a pixel 10B of the imaging device according to the present modification. The pixel 10B is different from the pixel 10 according to the first embodiment in the concentration of impurities in the contact plug cp1.

[0190] Specifically, if Figure 8 As shown, the pixel 10B includes a contact plug cp1B instead of the contact plug cp1, as compared to the pixel 10 of the first embodiment. The concentration of impurities contained in the contact plug cp1B is lower than the concentration of impurities contained in the contact plug cp3. In addition, for example, the concentration of impurities contained in the contact plug cp1B may also be lower than the concentration of impurities contained in each of the contact plug cp2 and the contact plug cp4. In other words, the concentration of impurities in the contact plug cp1B may be the minimum concentration among the concentrations of each impurity in all the contact plugs contained in the pixel 10B.

[0191] Thus, by making the impurity concentration in the contact plug cp1 lower than the impurity concentrations in the other contact plugs cp2, cp3, and cp4, the concentration of impurities thermally diffused from the contact plug cp1 to the first diffusion region 67n can be reduced. Thus, for the same reason as in the first modification, an increase in leakage current can be suppressed.

[0192] (Implementation Method 2)

[0193] Next, Embodiment 2 will be described. Hereinafter, the description will be mainly focused on the differences from Embodiment 1, and the description of the common points will be omitted or simplified.

[0194] Fig. 9 It is a plan view showing the layout in the pixel 10C of the imaging device according to the present embodiment. Fig.10 1 is a schematic cross-sectional view showing a device structure of a pixel 10C of the imaging device according to the present embodiment. Fig.10 is along Fig. 9 This is a cross-sectional view of a pixel 10C cut along line XX in FIG. 1 and developed in the direction of arrows. Fig.10 The pixel 10C shown in FIG. Figure 4 The main difference between the illustrated pixels 10 is that the gate electrode and the contact plug are formed in different wiring layers.

[0195] Specifically, if Fig. 9 as well as Fig.10 As shown, the pixel 10C is different from the pixel 10 of the first embodiment in that contact plugs cp5 , cp6 , and cp7 and an insulating layer 72 are newly provided.

[0196] The insulating layer 72 is provided on the insulating layer 71. In the present embodiment, the contact holes h1-h7 are through holes that penetrate not only the insulating layer 71 but also the insulating layer 72. Contact plugs cp5, cp6, and cp7 are respectively arranged at the positions of the contact holes h5, h6, and h7. The insulating layer 72 is, for example, a silicon oxide film. The insulating layer 72 may also have a stacked structure including a plurality of insulating layers.

[0197] The contact plug cp5 connects the plug pa3 to the gate electrode 26e. Fig. 9 As shown, the contact plug cp5 is provided at a position overlapping with the gate electrode 26e in a plan view.

[0198] The contact plug cp6 connects the plug pa2 to the gate electrode 22e. Fig. 9 As shown, the contact plug cp6 is arranged at a position where the gate electrode 22e overlaps when viewed from above.

[0199] The contact plug cp7 connects the plug pa4 to the gate electrode 24e. Fig. 9 As shown, the contact plug cp7 is arranged at a position overlapping with the gate electrode 24e in a plan view.

[0200] For example, in Embodiment 1, the contact plugs cp1-cp4 and the gate electrodes 22e, 24e, and 26e are formed in the same wiring layer and made of a material containing the same impurities. In contrast, in this embodiment, the contact plugs cp1-cp7 and the gate electrodes 22e, 24e, and 26e are formed in different wiring layers.

[0201] In addition, the material of the contact plugs cp1-cp7 and the materials of the gate electrodes 22e, 24e and 26e may be the same or different. In addition, for example, when the contact plugs cp1-cp7 and the gate electrodes 22e, 24e and 26e are formed of polysilicon material, the concentration of impurities in the polysilicon may be different.

[0202] In this embodiment, as in the first embodiment, the area of ​​the contact plug cp1 is made smaller than those of the contact plugs cp2, cp3, and cp4 in a plan view, thereby reducing the influence of the contact plug cp1 on the electric field and reducing the area of ​​the interface depletion layer of the semiconductor substrate 60. Thus, the leakage current flowing out of the first diffusion region 67n or flowing into the first diffusion region 67n can be reduced.

[0203] (Other embodiments)

[0204] The above describes the camera device of the present disclosure based on the embodiments and variations, and the present disclosure is not limited to these embodiments and variations. As long as it does not depart from the main purpose of the present disclosure, various variations that can be thought of by those skilled in the art are implemented on the embodiments and variations, and other forms constructed by combining some of the constituent elements in the embodiments and variations are also included in the scope of the present disclosure.

[0205] For example, the photoelectric conversion unit 12 may be a photodiode formed in the semiconductor substrate 60. In other words, the imaging device 100 may not be a stacked-type imaging device.

[0206] In addition, for example, the width W1 of the pad cp1b of the contact plug cp1 connected to the first diffusion region 67n and the width W3 of the pad cp3b of the contact plug cp3 connected to the second diffusion region 68bn may be equal. In this case, the length L1 of the pad cp1b may be shorter than the length L3 of the pad cp3b. Here, the length L1 is the length of the pad cp1b in a direction parallel to the length direction of the gate electrode 26e. The length L3 is the length of the pad cp3b in a direction parallel to the length direction of the gate electrode 22e. Thus, the area of ​​the pad cp1b may be smaller than the area of ​​the pad cp3b. In addition, the width W1 and the length L1 of the pad cp1b may be shorter than the width W3 and the length L3 of the pad cp3b, respectively. The pads of the pad cp1b and the contact plug cp2 and the contact plug cp4 may have the same relationship.

[0207] Furthermore, for example, the configurations of the plurality of pixels included in the imaging device 100 may not be equal to each other. For example, the imaging device 100 may include at least two of the pixel 10, the pixel 10A, the pixel 10B, and the pixel 10C.

[0208] In addition, according to the embodiments and variations of the present disclosure, the influence of leakage current can be reduced, so that a camera device capable of taking pictures with high image quality can be provided. In addition, each of the above-mentioned amplifier transistors 22, address transistors 24, and reset transistors 26 can be either an N-channel MOSFET or a P-channel MOSFET. In the case where each transistor is a P-channel MOSFET, the impurity of the first conductivity type is a p-type impurity, and the impurity of the second conductivity type is an n-type impurity. These transistors do not all need to be unified as either an N-channel MOSFET or a P-channel MOSFET. When the transistors in the pixel are respectively set as N-channel MOSFETs and electrons are used as signal charges, the configurations of the source and drain in each of these transistors can be replaced with each other.

[0209] Furthermore, various changes, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

Claims

1. A camera device comprising: A photoelectric conversion unit converts light into signal charges; a first diffusion region of the first conductivity type into which the signal charge is input; a second diffusion region of the first conductivity type; a first plug having a first surface in contact with the first diffusion region; and a second plug having a second surface in contact with the second diffusion region, In a plan view, an area of ​​the first surface of the first plug is smaller than an area of ​​the second surface of the second plug.

2. The imaging device according to claim 1, further comprising: a first transistor including the first diffusion region as one of a source and a drain and including a first gate; and The second transistor includes the second diffusion region as one of a source and a drain, and includes a second gate.

3. The camera device according to claim 2, The second gate is electrically connected to the first diffusion region.

4. The imaging device according to claim 2 or 3, In a plan view, a distance between the first surface of the first plug and the first gate is shorter than a distance between the second surface of the second plug and the second gate.

5. The imaging device according to any one of claims 1 to 3, The first plug and the second plug contain impurities of the first conductivity type, The concentration of the first conductivity type impurity in the first plug is lower than the concentration of the first conductivity type impurity in the second plug.

6. The imaging device according to any one of claims 1 to 3, The camera device includes a plurality of pixels. The photoelectric conversion portion, the first diffusion region, the second diffusion region, the first plug, and the second plug are included in one pixel among the plurality of pixels.

7. The imaging device according to any one of claims 1 to 3, The first plug comprises: a first contact having the first surface in contact with the first diffusion region; and a first pad, located on the first contact, The second plug comprises: a second contact having the second surface in contact with the second diffusion region; and a second pad located on the second contact, When viewed in plan, the area of ​​the first pad is larger than the area of ​​the first contact. In a plan view, the area of ​​the second pad is larger than the area of ​​the second contact.

8. A camera device comprising: A photoelectric conversion unit converts light into signal charges; a first diffusion region of the first conductivity type into which the signal charge is input; a second diffusion region of the first conductivity type; a first plug connected to the first diffusion region; and a second plug connected to the second diffusion region, The first plug comprises: a first contact connected to the first diffusion region; and a first pad, located on the first contact, The second plug comprises: a second contact connected to the second diffusion region; and a second pad located on the second contact, In a plan view, the area of ​​the first contact is smaller than the area of ​​the second contact.

9. The imaging device according to claim 8, When viewed in plan, the area of ​​the first pad is larger than the area of ​​the first contact. In a plan view, the area of ​​the second pad is larger than the area of ​​the second contact.

10. The imaging device according to claim 8 or 9, further comprising: a first transistor including the first diffusion region as one of a source and a drain and including a first gate; and The second transistor includes the second diffusion region as one of a source and a drain, and includes a second gate.

11. The imaging device according to claim 10, The second gate is electrically connected to the first diffusion region.

Images