High-working-temperature IGBT (Insulated Gate Bipolar Translator) device containing N + well region and tunnel junction and preparation method thereof

Abstract

The invention discloses a high-working-temperature IGBT (Insulated Gate Bipolar Translator) device containing an N + well region and a tunnel junction and a preparation method of the high-working-temperature IGBT device. The IGBT device sequentially comprises a collector electrode, a P + collector region containing an N + well region, an N + doped tunneling layer, an N-type field stop layer, an N-type drift region, an N-type carrier storage layer and a P-type base region from bottom to top, the trench gate penetrates through the P-type base region and the N-type carrier storage layer, the N + emitter regions are formed on the upper portion of the P-type base region and located on the two sides of the trench gate, and the emitter covers the surface of the device; wherein in the P + collector region containing the N + well region, the thickness of the N + well region is smaller than that of the P + collector region, the lower part of the N + well region is flush with the P + collector region and is externally connected with a collector potential, and the thin P + collector region is arranged above the N + well region; and the N + doped tunneling layer and the P + collector region form a tunneling junction. The N + well mixed collector structure and the heavily doped tunneling junction collector structure cooperate to reduce the device leakage current of the IGBT, so that the working temperature is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit power devices, and specifically relates to a + A high operating temperature IGBT device with a well region and a tunnel junction and a method for preparing the same. Background Art

[0002] With the rapid development of power electronics technology, carrier storage trench gate IGBT (CSTBT) is increasingly used as a power device in power conversion and control systems. As the core component of the power conversion system, the rated power of IGBT devices can increase by 25-35% for every 25°C increase in operating temperature Tj. However, with the continuous development of applications, IGBT is difficult to meet the market's requirements for higher operating temperatures. The main reason is that the current generated by CSTBT in the blocking state increases exponentially with the increase in temperature, and the internal parasitic BJT will further amplify the generated current, which ultimately leads to excessive leakage current density at high temperatures, causing device failure.

[0003] In the high-voltage blocking state, the leakage current (IL) of the IGBT can be regarded as the leakage current of the parasitic PNP transistor. The leakage current comes from the space charge generation current (Ig) generated by intrinsic excitation and amplified by the PNP tube. Therefore, reducing the current of the PNP tube is a common research direction for high-operating-temperature IGBTs.

[0004] There are few studies on silicon-based high-temperature IGBTs, most of which focus on the collector structure. Some scholars have proposed using deep-level impurities to make field stop layers. The principle is to use the characteristic that deep-level impurities are gradually ionized as the temperature rises, so that the base region doping NB of the parasitic transistor pnp transistor increases with the temperature rise, thereby reducing the emission efficiency and the amplification factor of the leakage current. Other scholars have improved the high-temperature characteristics of IGBT from the perspective of back-end packaging heat dissipation. Summary of the invention

[0005] The present invention provides an improved IGBT device structure and a preparation method thereof, and has N + The well-mixed collector structure and the heavily doped tunnel junction collector structure work together to reduce the device leakage current of the IGBT, thereby increasing the operating temperature.

[0006] Specifically, the present invention discloses a method comprising N + The high operating temperature IGBT device with well region and tunnel junction includes collector, N + P + Collector area, N + doped tunneling layer, N-type field stop layer, N-type drift region, N-type carrier storage layer, P-type base region; the trench gate penetrates the P-type base region and the N-type carrier storage layer, N +The emitter region is formed on the upper part of the P-type base region and located on both sides of the trench gate. The emitter covers the surface of the device; + P + In the collector region, N + The thickness of the well region is less than P + The collector region, the lower part of which is connected to P + The collector region is flush with the external collector potential, and above it is a thin layer of P + Collector area; N + The tunneling layer doped with P + The collector region forms a tunnel junction.

[0007] The present invention contains N + In a high operating temperature IGBT device with a well region and a tunnel junction, preferably, the P + The doping concentration of the collector region is 1e18~3e19 cm -3 .

[0008] The present invention contains N + In a high operating temperature IGBT device with a well region and a tunnel junction, preferably, the N + The doping concentration of the well region is 7e18~7e21 cm -3 .

[0009] The present invention contains N + In a high operating temperature IGBT device with a well region and a tunnel junction, preferably, the N + The doping concentration of the doped tunneling layer is 1e18~3e19 cm -3 .

[0010] The present invention contains N + In a high operating temperature IGBT device with a well region and a tunnel junction, preferably, the N + The thickness of the doped tunneling layer is 0.01-0.1 μm.

[0011] The present invention contains N + In a high operating temperature IGBT device with a well region and a tunnel junction, preferably, the N + The thickness of the well region is less than P + The thickness difference of the collector region ranges from 0.01 to 0.2 μm.

[0012] The present invention also discloses a method containing N + The method for preparing a high operating temperature IGBT device with a well region and a tunnel junction includes conventional CSTBT device manufacturing steps and the following steps: + N is performed before ion implantation in the collector region + Medium energy ion implantation to produce N + Tunneling layer; in P +After the collector region is ion implanted, low energy N-type impurity ions are implanted under the photolithography mask in the P + N + well region, and N + The thickness of the well region is less than P + Collector area.

[0013] The present invention contains N + In the method for preparing a high operating temperature IGBT device of a well region and a tunnel junction, N + Medium energy ion implantation forms N + Tunneling layer, wherein the ion implantation energy is 50-200 keV, the N + The doping concentration of the doped tunneling layer ranges from 1e18 to 3e19 cm -3 .

[0014] The present invention contains N + In the method for preparing a high operating temperature IGBT device having a well region and a tunnel junction, preferably, low energy N-type impurity implantation is performed to produce N + Well region, where the ion implantation energy is 10 to 80 keV and the doping concentration ranges from 7e18 to 7e21 cm -3 .

[0015] The present invention contains N + In the method for preparing a high operating temperature IGBT device with a well region and a tunnel junction, preferably, the N + Well region and P + The thickness difference of the collector region ranges from 0.01 to 0.2 μm.

[0016] Beneficial effects:

[0017] The high-temperature characteristics of the IGBT are greatly improved: through the combined effect of the depletion region punch-through of the N-type well region and the tunnel junction, the off-state leakage current of the IGBT is effectively reduced, allowing the IGBT to be used in higher temperature working scenarios.

[0018] The manufacturing process of the new structure device is fully compatible with the original CSTBT process flow, with almost no redundant process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the traditional CSTBT device structure.

[0020] Figure 2 Contains N + Schematic diagram of the high operating temperature IGBT device structure with well region and tunnel junction.

[0021] Figure 3 Schematic diagram of the amplification effect of parasitic pnp transistor on the leakage current of traditional IGBT.

[0022] Figure 4 and Figure 5 Contains N + Schematic diagram of the working principle of high operating temperature IGBT device with well region and tunnel junction.

[0023] Figure 6 Contains N + Flow chart of the fabrication process of a high operating temperature IGBT device with well region and tunnel junction. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0026] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of the device, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention can be implemented without following these specific details. Unless otherwise specified below, the various parts of the device can be made of materials known to those skilled in the art, or can be made of materials with similar functions developed in the future.

[0027] Figure 1 This is a schematic diagram of the structure of a traditional CSTBT device. Figure 1 As shown, the conventional CSTBT device includes, from bottom to top, a collector 100ˊ, a P-type collector region 101ˊ, an N-type field stop layer 102ˊ, an N-type drift region 103ˊ, an N-type carrier storage layer 108ˊ, a P-type base region 104ˊ, a trench gate 106ˊ penetrating the P-type base region 104ˊ and the N-type carrier storage layer 108ˊ, and an N-type gate electrode 106ˊ. +The emitter region 107 is formed on the upper part of the P-type base region 104 and on both sides of the trench gate 106. The emitter 105 covers the surface of the device. The doping concentration of the P-type collector region of the conventional CSTBT is in the range of 1e16 to 1e18 cm -3 .

[0028] Figure 2 The present invention contains N + Schematic diagram of the high operating temperature IGBT device structure of the well region and tunnel junction. Figure 2 As shown, from bottom to top, it includes a collector 100, containing N + The P of the well region 110 + Collector region 101, N + doped tunneling layer 109, N-type field stop layer 102, N-type drift region 103, N-type carrier storage layer 108, P-type base region 104, trench gate 106 penetrates P-type base region 104 and N-type carrier storage layer 108, N + The emitter region 107 is formed on the upper part of the P-type base region 104 and located on both sides of the trench gate 106 , and the emitter 105 covers the surface of the device.

[0029] Among them, N + The P of the well region 110 + The collector region 101 is N + The well region 110 and the P + Hybrid structure of collector area, N + The thickness of the well region 110 is less than P + The collector region 101, whose lower part is connected to P + The lower part of the collector region 101 is flush with the collector electrode 100 and has a doping concentration ranging from 7e18 to 7e21 cm -3 ; N + The well region is topped by a thin P + Collector area, N + Well region and P + The thickness difference of the collector area ranges from 0.01 to 0.2 μm; P + The doping concentration of the collector region is much higher than that of the P-type collector region of the conventional CSTBT, and its range is 1e18~3e19cm -3 ; N + The tunneling layer 109 doped with P + The collector region 101 is doped to form a tunnel junction, and its doping concentration ranges from 1e18 to 3e19 cm -3 , thickness range is 0.01~0.1μm.

[0030] Figure 3The figure shows the amplification effect of parasitic pnp transistor on the leakage current of traditional IGBT. The amplification principle of parasitic pnp transistor on the leakage current of traditional IGBT is consistent with the bipolar working mode under normal conduction of IGBT: the electron current is injected into the N-type field stop layer to reduce its potential, thereby turning on the forward PN junction and injecting holes from the P-type collector into the drift region. In the high-temperature off-state device, the leakage current is first generated by intrinsic excitation in the drift region, in which the electron current injected into the collector causes the hole injection into the drift region, forming the amplification effect of pnp transistor on the leakage current, causing the device to break down quickly.

[0031] Figure 4 and Figure 5 Contains N + Schematic diagram of the working principle of the high operating temperature IGBT device with well region and tunnel junction. Figure 4 As shown in the figure, in the off state, the reverse biased N-well-P junction bears a large external reverse bias voltage, which causes the depletion region to expand upward, resulting in complete depletion of the P-type region above the N-well, making the N + The well region and the N-type field stop layer are punched through. After the punch-through, the device electron leakage current (black line) generated by intrinsic excitation directly flows from the N + The well region is absorbed by the collector and the device operates in unipolar mode, thereby eliminating the parasitic PNP transistor of the IGBT and its amplification effect on the leakage current and improving high-temperature characteristics.

[0032] N + Tunneling layer and P + The collector region forms a tunnel junction. In the off state, the generated electron current flowing from the drift region to the collector enters the N-type well region through the tunnel effect, reducing the reverse injection of holes from the P-type collector into the drift region. The parasitic PNP transistor of the IGBT and its amplification effect on the leakage current are suppressed, and the high-temperature characteristics are improved.

[0033] like Figure 5 As shown, in the on state (left figure), since the reverse bias voltage borne by the reverse biased NP junction is very small, the depletion region is not enough to completely deplete the P-type region above the N well, and the device works normally in bipolar mode.

[0034] The present invention contains N + The manufacturing process of high operating temperature IGBT devices in the well region and tunnel junction is fully compatible with the existing CSTBT process. Only the following two process steps need to be added to the existing CSTBT process: + N is injected before the collector region + Medium energy injection to make N + Tunneling layer, wherein the ion implantation energy is 50 to 200 KeV; + After the collector region is implanted, low-energy N-type impurities are implanted under the photolithography mask to make N+ Well region, where the ion implantation energy is 10 to 80 keV. + The collector region can be annealed together without adding additional annealing steps. The annealing is divided into two anneals, including a rapid high-temperature annealing and a long low-temperature annealing; the temperature range of the rapid high-temperature annealing is 900-1300°C, and the time range is 1e-6-1e-4s; the temperature range of the long low-temperature annealing is 200-400°C, and the time range is 30-120min.

[0035] In a specific embodiment, Figure 6 The following steps are shown:

[0036] Step S1, in N - A P-well region is formed on the upper portion of the doped silicon substrate;

[0037] Step S2, forming an N-type doped carrier storage layer below the P-well region;

[0038] Step S3, etching the silicon substrate to form mutually spaced trenches so as to penetrate the P-well region and the N-type doped carrier storage layer;

[0039] Step S4, forming a gate dielectric layer and a gate electrode in the trench;

[0040] Step S5, forming an N-type P-well region on the upper part of the P-well region on both sides of the trench. + Launch area;

[0041] Step S6, forming an oxide layer above the trench;

[0042] Step S7, then depositing the emitter to cover the upper surface of the device;

[0043] Step S8, performing ion implantation on the back of the silicon substrate to form an N-type field stop layer;

[0044] Step S9, perform N + Medium energy injection to make N + The doped tunneling layer has an ion implantation energy of 50 to 200 keV and a doping concentration range of 1e18 to 3e19 cm -3 ;

[0045] Step S10, ion implantation is performed to form P + Collector region, doping concentration is 1e18~3e19 cm -3 ;

[0046] Step S11, low energy N-type impurity implantation is performed under the photolithography mask in the P + The central area of ​​the collector is made of N +Well region, where the ion implantation energy is 10 to 80 keV and the doping concentration ranges from 7e18 to 7e21 cm -3 , and N + The well thickness is less than P + Collector area, N + Well region and P + The thickness difference of the collector region ranges from 0.01 to 0.2 μm; the mask is then removed and annealed;

[0047] Step S12, performing chemical mechanical masking on the back of the silicon substrate to form a collector electrode.

[0048] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A kind of + High operating temperature IGBT devices with well region and tunnel junction, It is characterized in that From bottom to top, it includes the collector, N + P + Collector area, N + doped tunneling layer, N-type field stop layer, N-type drift region, N-type carrier storage layer, P-type base region; The trench gate penetrates the P-type base region and the N-type carrier storage layer. + The emitter region is formed on the upper part of the P-type base region and located on both sides of the trench gate, and the emitter covers the surface of the device; Among them, N + P + In the collector region, N + The thickness of the well region is less than P + The collector region, the lower part of which is connected to P + The collector region is flush with the external collector potential, and above it is a thin layer of P + Collector area; N + The tunneling layer doped with P + The collector region forms a tunnel junction.

2. The N-containing compound according to claim 1 + High operating temperature IGBT devices with well region and tunnel junction, It is characterized in that The P + The doping concentration of the collector region is 1e18~3e19 cm -3 .

3. The N-containing compound according to claim 1. + High operating temperature IGBT devices with well region and tunnel junction, It is characterized in that The N + The doping concentration of the well region is 7e18~7e21 cm -3 .

4. The N-containing compound according to claim 1. + High operating temperature IGBT devices with well region and tunnel junction, It is characterized in that The N + The doping concentration of the doped tunneling layer is 1e18~3e19 cm -3 .

5. The N-containing compound according to claim 1. + High operating temperature IGBT devices with well region and tunnel junction, It is characterized in that The N + The thickness of the doped tunneling layer is 0.01-0.1 μm.

6. The N-containing compound according to claim 1 + High operating temperature IGBT devices with well region and tunnel junction, It is characterized in that The N + The thickness of the well region is less than P + The thickness difference of the collector region ranges from 0.01 to 0.2 μm.

7. A kind of + A method for preparing a high operating temperature IGBT device with a well region and a tunnel junction includes conventional CSTBT device manufacturing steps, It is characterized in that The following steps are also included: In the process of P + N is performed before ion implantation in the collector region + Ion implantation to produce N + a doped tunneling layer; In P + After the collector region is ion implanted, N-type impurity ions are implanted under the photolithography mask in the P + N + well region, and N + The thickness of the well region is less than P + Collector area.

8. The N-containing compound according to claim 7. + Method for preparing high operating temperature IGBT device with well region and tunnel junction, It is characterized in that Perform N + Medium energy ion implantation forms N + doped tunneling layer, wherein the ion implantation energy is 50 to 200 keV, the N + The doping concentration of the doped tunneling layer ranges from 1e18 to 3e19 cm -3 .

9. The N-containing compound according to claim 7. + Method for preparing high operating temperature IGBT device with well region and tunnel junction, It is characterized in that Low energy N-type impurity implantation is performed to produce N + Well region, where the ion implantation energy is 10 to 80 keV and the doping concentration ranges from 7e18 to 7e21 cm -3 .

10. The N-containing compound according to claim 7. + Method for preparing high operating temperature IGBT device with well region and tunnel junction, It is characterized in that The N + Well region and P + The thickness difference of the collector region ranges from 0.01 to 0.2 μm.

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