Gallium nitride-based P-type transistor, CMOS (complementary metal oxide semiconductor) device and preparation method thereof

Abstract

The invention provides a gallium nitride-based P-type transistor and a preparation method thereof, and a gallium nitride-based CMOS device and a preparation method thereof, and relates to the technical field of semiconductor devices. The forbidden bandwidths of the first P-type semiconductor layer and the second P-type semiconductor layer are different, and a polarization effect exists between the first P-type semiconductor layer and the second P-type semiconductor layer, so that high-concentration two-dimensional hole gas is generated at the interface of the first P-type semiconductor layer and the second P-type semiconductor layer to reduce on-resistance. Therefore, the gallium nitride-based P-type transistor provided by the invention has the advantages of high current density and low on resistance, so that the gallium nitride-based CMOS device provided by the invention has shorter transmission delay and higher switching speed, and the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a P-type transistor based on gallium nitride and a method for preparing the same, and a CMOS device based on gallium nitride and a method for preparing the same. Background Art

[0002] III-nitride materials have a large bandgap and high critical breakdown field strength. In addition, due to the existence of spontaneous polarization effect and piezoelectric polarization effect, high-concentration, high-mobility two-dimensional electron gas (2DEG) can be generated at the interface of its heterostructure. Gallium nitride (GaN) high electron mobility transistors (HEMTs) based on 2DEG conductive channels have excellent performance such as low on-resistance, high switching speed, and high energy conversion efficiency, and are widely used in power electronic devices.

[0003] At present, GaN power devices need to be used in combination with silicon-based complementary metal oxide semiconductor (CMOS) peripheral circuits. This heterogeneous integration scheme will introduce large inter-chip parasitic inductance, thereby limiting the operating frequency of GaN power devices. Therefore, it is of great significance to study GaN-based CMOS devices that can be monolithically integrated with GaN power devices. This "all-GaN" circuit is conducive to leveraging the advantages of high operating frequency of GaN devices, improving the stability of power electronic systems, and realizing the miniaturization of the entire system. At present, the technology related to GaN-based N-type transistors is relatively mature. Therefore, in order to realize GaN-based CMOS devices, the research and development of GaN-based P-type transistors has become one of the main research and development directions of technicians today. Summary of the invention

[0004] In view of this, the present application provides a gallium nitride-based P-type transistor and a method for preparing the same, and a gallium nitride-based CMOS device and a method for preparing the same, which effectively solve the technical problems existing in the prior art. The gallium nitride-based P-type transistor provided in the present application has the advantages of high current density and low on-resistance, so that the gallium nitride-based CMOS device provided in the present application has a shorter transmission delay and a faster switching speed, thereby improving the performance of the device.

[0005] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0006] A gallium nitride-based P-type transistor, the P-type transistor comprising:

[0007] A substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer;

[0008] a gate dielectric layer located on a side of the second P-type semiconductor layer facing away from the substrate;

[0009] A source electrode and a drain electrode located on a side of the second P-type semiconductor layer away from the substrate and respectively located on two sides of the active region;

[0010] A gate electrode is located on a side of the gate dielectric layer away from the substrate, and the gate electrode is located between the source electrode and the drain electrode.

[0011] Optionally, the bandgap width of the first P-type semiconductor layer is greater than the bandgap width of the second P-type semiconductor layer;

[0012] And / or, the bandgap width of the channel layer is greater than the bandgap width of the second P-type semiconductor layer.

[0013] Optionally, the barrier layer is a stacked structure of at least one sub-layer, and the bandgap width of the material of at least one of the sub-layers in the barrier layer is greater than the bandgap width of the material of the channel layer.

[0014] Optionally, the second P-type semiconductor layer further includes a gate groove on a side facing away from the substrate, and the gate is located in the region of the gate groove;

[0015] And / or, the gate dielectric layer is a physical layer at a position corresponding to the gate or includes a gate hollowing.

[0016] Based on the same inventive concept, the present application also provides a method for preparing a P-type transistor based on gallium nitride, which is used to prepare the above-mentioned P-type transistor based on gallium nitride, wherein the preparation method comprises:

[0017] providing a substrate;

[0018] In a direction perpendicular to the plane where the substrate is located, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer are sequentially stacked on the substrate, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer;

[0019] forming a gate dielectric layer on a side of the second P-type semiconductor layer away from the substrate;

[0020] Etching the gate dielectric layer to form a source hollowing out exposing the second P-type semiconductor layer in the source region, and forming a drain groove exposing the second P-type semiconductor layer in the drain region, wherein the source hollowing out and the drain hollowing out are respectively located on two sides of the active region;

[0021] Depositing metal at the source and drain hollows to form a source and a drain;

[0022] forming a device isolation region between different P-type transistors;

[0023] A gate is formed on the side of the gate dielectric layer facing away from the substrate, and the gate is located between the source and the drain.

[0024] Based on the same inventive concept, the present application also provides a gallium nitride-based CMOS device, the CMOS device comprising:

[0025] An epitaxial structure, the epitaxial structure comprising a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; the epitaxial structure is divided into an N-tube region and a P-tube region, the N-tube region comprises an N-tube gate region and an N-tube source region and an N-tube drain region located on both sides of the N-tube gate region, the P-tube region comprises a P-tube gate region and a P-tube source region and a P-tube drain region located on both sides of the P-tube gate region, the first P-type semiconductor layer comprises an N-tube first P-type semiconductor layer located at the N-tube gate region and a P-tube first P-type semiconductor layer located at the P-tube region, and the second P-type semiconductor layer comprises an N-tube second P-type semiconductor layer located at the N-tube gate region and a P-tube second P-type semiconductor layer located at the P-tube region;

[0026] A first dielectric layer located on a side of the second P-type semiconductor layer away from the substrate and covering an exposed surface of the epitaxial structure;

[0027] an electrode layer located on a side of the first dielectric layer away from the substrate, the electrode layer comprising an N-tube gate, an N-tube source, an N-tube drain, a P-tube source and a P-tube drain, the N-tube gate contacts the N-tube second P-type semiconductor layer through the first dielectric layer, the N-tube source contacts the barrier layer through the first dielectric layer, the N-tube drain contacts the barrier layer through the first dielectric layer, the P-tube source contacts the P-tube second P-type semiconductor layer through the first dielectric layer, and the P-tube drain contacts the P-tube second P-type semiconductor layer through the first dielectric layer; an isolation region located at the junction of the N-tube region and the P-tube region;

[0028] a second gate dielectric layer located on a side of the electrode layer away from the substrate and covering exposed surfaces of the first dielectric layer and the electrode layer;

[0029] A connecting electrode layer located on a side of the second gate dielectric layer away from the substrate, the connecting electrode layer comprising an N-tube gate connecting electrode, an N-tube source connecting electrode, an interconnecting electrode, a P-tube gate connecting electrode and a P-tube source connecting electrode, the N-tube gate connecting electrode contacts the N-tube gate through the second gate dielectric layer, the N-tube source connecting electrode contacts the N-tube source through the second gate dielectric layer, the interconnecting electrode contacts both the N-tube drain and the P-tube drain through the second gate dielectric layer, the P-tube gate connecting electrode is located at the P-tube gate region, and the P-tube source connecting electrode contacts the P-tube source through the second gate dielectric layer.

[0030] Optionally, the bandgap width of the first P-type semiconductor layer is greater than the bandgap width of the second P-type semiconductor layer;

[0031] And / or, the bandgap width of the channel layer is greater than the bandgap width of the second P-type semiconductor layer.

[0032] Optionally, the barrier layer is a stacked structure of at least one sub-layer, and the bandgap width of the material of at least one of the sub-layers in the barrier layer is greater than the bandgap width of the material of the channel layer.

[0033] Optionally, the second P-type semiconductor layer of the P-tube further includes a gate groove on a side facing away from the substrate, and the P-tube gate connection electrode is located in the region of the gate groove;

[0034] And / or, at least one of the first dielectric layer and the second gate dielectric layer includes a P-tube gate hollowing out at a location corresponding to the P-tube gate region.

[0035] Based on the same inventive concept, the present application also provides a method for preparing a gallium nitride-based CMOS device, which is used to prepare the above-mentioned gallium nitride-based CMOS device, wherein the preparation method comprises:

[0036] An epitaxial structure is provided, the epitaxial structure comprising a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; the epitaxial structure is divided into an N-tube region and a P-tube region, the N-tube region comprises an N-tube gate region and an N-tube source region and an N-tube drain region located on both sides of the N-tube gate region, and the P-tube region comprises a P-tube gate region and a P-tube source region and a P-tube drain region located on both sides of the P-tube gate region;

[0037] Etching the first P-type semiconductor layer and the second P-type semiconductor layer so that the first P-type semiconductor layer includes an N-tube first P-type semiconductor layer located at the N-tube gate region and a P-tube first P-type semiconductor layer located at the P-tube region, and the second P-type semiconductor layer includes an N-tube second P-type semiconductor layer located at the N-tube gate region and a P-tube second P-type semiconductor layer located at the P-tube region;

[0038] forming a first dielectric layer covering an exposed surface of the epitaxial structure on a side of the second P-type semiconductor layer away from the substrate;

[0039] Etching the first dielectric layer to form a first N-tube source hollow at the N-tube source region, and forming a first N-tube drain hollow at the N-tube drain region;

[0040] A first electrode layer is formed on a side of the first dielectric layer away from the substrate, the first electrode layer comprising an N-tube source and an N-tube drain, the N-tube source is located in the N-tube source region and contacts the barrier layer through the first N-tube source hollowing, the N-tube drain is located in the N-tube drain region and contacts the barrier layer through the first N-tube drain hollowing;

[0041] forming an isolation region at the junction of the N-tube region and the P-tube region;

[0042] Etching the first dielectric layer to form a first N-tube gate hollow at the N-tube gate region, a first P-tube source hollow at the P-tube source region, and a first P-tube drain hollow at the P-tube drain region;

[0043] A second electrode layer is formed on a side of the first dielectric layer away from the substrate, the second electrode layer comprising an N-tube gate, a P-tube source and a P-tube drain, the N-tube gate is located in the N-tube gate region and contacts the N-tube second P-type semiconductor layer through the first N-tube gate hollowing out, the P-tube source is located in the P-tube source region and contacts the P-tube second P-type semiconductor layer through the first P-tube source hollowing out, and the P-tube drain is located in the P-tube drain region and contacts the P-tube second P-type semiconductor layer through the first P-tube drain hollowing out;

[0044] On the side of the first electrode layer and the second electrode layer facing away from the substrate, a second gate dielectric layer is formed to cover the exposed surfaces of the first dielectric layer, the first electrode layer and the second electrode layer;

[0045] Etching the second gate dielectric layer to form a second N-tube source hollow at the N-tube source, a second N-tube gate hollow at the N-tube gate, a second N-tube drain hollow at the N-tube drain, a second P-tube source hollow at the P-tube source, and a second P-tube drain hollow at the P-tube drain;

[0046] A connection electrode layer is formed on a side of the second gate dielectric layer away from the substrate, the connection electrode layer comprising an N-tube gate connection electrode, an N-tube source connection electrode, an interconnection electrode, a P-tube gate connection electrode and a P-tube source connection electrode, the N-tube gate connection electrode contacts the N-tube gate through the second N-tube gate hollowing out, the N-tube source connection electrode contacts the N-tube source through the second N-tube source hollowing out, the interconnection electrode contacts both the N-tube drain and the P-tube drain through the second N-tube drain hollowing out and the second P-tube drain hollowing out, the P-tube gate connection electrode is located at the P-tube gate region, and the P-tube source connection electrode contacts the P-tube source through the second P-tube source hollowing out.

[0047] Compared with the prior art, the technical solution provided by this application has at least the following advantages:

[0048] The present application provides a gallium nitride-based P-type transistor and a preparation method thereof, and a gallium nitride-based CMOS device and a preparation method thereof, wherein the P-type transistor comprises: a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; a gate dielectric layer located on a side of the second P-type semiconductor layer away from the substrate; a source and a drain located on a side of the second P-type semiconductor layer away from the substrate and respectively located on both sides of an active region; and a gate located on a side of the gate dielectric layer away from the substrate, the gate being located between the source and the drain.

[0049] From the above content, it can be seen that in the technical solution provided by the present application, the bandgap widths of the first P-type semiconductor layer and the second P-type semiconductor layer are different, and there is a polarization effect between the first P-type semiconductor layer and the second P-type semiconductor layer, so that a high concentration of two-dimensional hole gas is generated at the interface between the two to reduce the on-resistance. Therefore, the gallium nitride-based P-type transistor provided by the present application has the advantages of high current density and low on-resistance, so that the gallium nitride-based CMOS device provided by the present application has a shorter transmission delay and a faster switching speed, thereby improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0051] Figure 1 A schematic diagram of the structure of a P-type transistor based on gallium nitride provided in an embodiment of the present application;

[0052] Figure 2 A schematic structural diagram of another gallium nitride-based P-type transistor provided in an embodiment of the present application;

[0053] Figure 3 A flow chart of a method for preparing a P-type transistor based on gallium nitride provided in an embodiment of the present application;

[0054] Figure 4 A flow chart of another method for preparing a P-type transistor based on gallium nitride provided in an embodiment of the present application;

[0055] Figure 5a to Figure 5h for Figure 4 The corresponding structural schematic diagram of each step in FIG.

[0056] Figure 6 A schematic diagram of the structure of a gallium nitride-based CMOS device provided in an embodiment of the present application;

[0057] Figure 7 A flow chart of a method for preparing a gallium nitride-based CMOS device provided in an embodiment of the present application;

[0058] Figures 8a to 8k for Figure 7 Schematic diagram of the corresponding structure of each step. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] As described in the background technology, GaN power devices currently need to be used in combination with silicon-based CMOS peripheral circuits. This heterogeneous integration scheme will introduce large inter-chip parasitic inductance, thereby limiting the operating frequency of GaN power devices. Therefore, it is of great significance to study GaN-based CMOS devices that can be monolithically integrated with GaN power devices. This "all-GaN" circuit is conducive to leveraging the advantages of the high operating frequency of GaN devices, improving the stability of power electronic systems, and realizing the miniaturization of the entire system. At present, the technology related to GaN-based N-type transistors is relatively mature. Therefore, in order to realize GaN-based CMOS devices, the research and development of GaN-based P-type transistors has become one of the main research and development directions of technicians today.

[0061] Based on this, the embodiments of the present application provide a gallium nitride-based P-type transistor and a method for preparing the same, and a gallium nitride-based CMOS device and a method for preparing the same, which effectively solve the technical problems existing in the prior art. The gallium nitride-based P-type transistor provided in the embodiments of the present application has the advantages of high current density and low on-resistance, so that the gallium nitride-based CMOS device provided in the embodiments of the present application has a shorter transmission delay and a faster switching speed, thereby improving the performance of the device.

[0062] To achieve the above purpose, the technical solution provided in the embodiment of the present application is as follows, specifically combined with Figure 1 to Figure 8k The technical solution provided in the embodiments of the present application is described in detail.

[0063] refer to Figure 1, which is a schematic diagram of the structure of a gallium nitride-based P-type transistor provided in an embodiment of the present application, wherein the P-type transistor provided in an embodiment of the present application includes:

[0064] A substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a first P-type semiconductor layer 5, and a second P-type semiconductor layer 6 are stacked in sequence, wherein the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 have different bandgap widths, and the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 deplete the two-dimensional electron gas at the interface between the channel layer 3 and the barrier layer 4. A gate dielectric layer 7 located on the side of the second P-type semiconductor layer 6 away from the substrate 1. A source electrode 8 and a drain electrode 9 located on the side of the second P-type semiconductor layer 6 away from the substrate 1 and located on both sides of the active region respectively; a gate electrode 11 located on the side of the gate dielectric layer 7 away from the substrate 1, and the gate electrode 11 is located between the source electrode 8 and the drain electrode 9. Optionally, the gate 11, the source 8 and the drain 9 are all located on the side of the gate dielectric layer 7 away from the substrate 1, the source 8 and the drain 9 are respectively located on both sides of the gate 11, and the source 8 contacts the second P-type semiconductor layer 6 through the gate dielectric layer 7, and the drain 9 contacts the second P-type semiconductor layer 6 through the gate dielectric layer 7.

[0065] The gate dielectric layer 7 provided in the embodiment of the present application can be etched to form a hollowing out that exposes the second P-type semiconductor layer 6, and the rear electrode contacts the second P-type semiconductor layer 6 through the hollowing out. That is, the gate dielectric layer 7 provided in the embodiment of the present application includes a gate region and a source region and a drain region located on both sides of the gate region, and the gaps between adjacent regions in the gate region, the source region and the drain region and the area of ​​each region are not specifically limited. The gate dielectric layer 7 includes a source hollowing out at the source region, and the gate dielectric layer 7 includes a drain hollowing out at the drain region; wherein the source 8 is located in the source region and contacts the second P-type semiconductor layer 6 through the source hollowing out, and the drain 9 is located in the drain region and contacts the second P-type semiconductor layer 6 through the drain hollowing out.

[0066] It can be understood that in the technical solution provided in the embodiment of the present application, the bandgap widths of the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 are different, and there is a polarization effect between the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6, so that a high concentration of two-dimensional hole gas is generated at the interface between the two to reduce the on-resistance. Therefore, the gallium nitride-based P-type transistor provided in the embodiment of the present application has the advantages of high current density and low on-resistance, so that the gallium nitride-based CMOS device provided in the embodiment of the present application has a shorter transmission delay and a faster switching speed, thereby improving the performance of the device.

[0067] In one embodiment of the present application, the bandgap width of the first P-type semiconductor layer 5 provided in the embodiment of the present application is greater than the bandgap width of the second P-type semiconductor layer 6, so that the activation energy of the acceptor impurities in the material of the second P-type semiconductor layer 6 is lower and the hole concentration is higher. And / or, the bandgap width of the channel layer 3 is greater than the bandgap width of the second P-type semiconductor layer 6.

[0068] refer to Figure 2 As shown, it is a schematic diagram of the structure of another gallium nitride-based P-type transistor provided in an embodiment of the present application, wherein the second P-type semiconductor layer 6 provided in an embodiment of the present application further includes a gate groove on the side away from the substrate 1, and the gate 11 is located in the region of the gate groove. That is, a gate groove is formed on the side of the second P-type semiconductor layer 6 away from the substrate 1 and corresponding to the gate region, and then after the gate dielectric layer 7 is formed, the gate dielectric layer 7 also forms a groove structure at the gate groove, and the gate 11 is prepared in the groove structure, thereby reducing the number of holes by removing part of the thickness of the second P-type semiconductor layer 6, thereby forming an enhanced gate. At the same time, the heterogeneous interface between the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 is retained, so that a high-density hole conductive channel can be formed in the gate region after the P-type transistor is turned on again.

[0069] In one embodiment of the present application, the gate dielectric layer provided in the present application is a physical layer or includes a gate hollowing at the gate location. Specifically, when the gate dielectric layer provided in the embodiment of the present application includes a gate hollowing at the gate location, the gate is in direct contact with the second P-type semiconductor layer, thereby forming a Schottky gate. Also, when the gate dielectric layer is a physical layer at the gate location, the gate is isolated from the second P-type semiconductor layer by the gate dielectric layer, thereby forming a metal-insulator-semiconductor (MIS) gate.

[0070] Continue as Figure 2 As shown, the P-type transistor provided in the embodiment of the present application further includes: a device isolation region 10 located in the edge region of the P-type transistor, wherein the device isolation region 10 is used to electrically isolate the P-type transistors on the same wafer.

[0071] Based on the same inventive concept, the present application also provides a method for preparing a P-type transistor based on gallium nitride, which is used to prepare the P-type transistor based on gallium nitride provided by any of the above embodiments. Figure 3 FIG. 1 is a flow chart of a method for preparing a P-type transistor based on gallium nitride provided in an embodiment of the present application, wherein the preparation method comprises:

[0072] S1. Provide a substrate.

[0073] S2. In a direction perpendicular to the plane of the substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer are stacked in sequence on the substrate, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer.

[0074] S3, forming a gate dielectric layer on the side of the second P-type semiconductor layer away from the substrate. Optionally, the gate dielectric layer includes a gate region and a source region and a drain region located on both sides of the gate region.

[0075] S4, etching the gate dielectric layer to form a source hollow exposing the second P-type semiconductor layer in the source region, and a drain hollow exposing the second P-type semiconductor layer in the drain region, wherein the source hollow and the drain hollow are respectively located on both sides of the active region.

[0076] S5, depositing metal at the source hollowing-out and the drain hollowing-out to form a source and a drain.

[0077] S6. Forming a device isolation region between different P-type transistors.

[0078] S7, forming a gate on the side of the gate dielectric layer away from the substrate, the gate being located between the source and the drain, wherein the gate is located at the gate region, the source is located at the source region and contacts the second P-type semiconductor layer through the source hollowing, and the drain is located at the drain region and contacts the second P-type semiconductor layer through the drain hollowing.

[0079] Furthermore, the second P-type semiconductor layer provided in the embodiment of the present application may further include a gate groove, and the gate groove may be formed by etching the second P-type semiconductor layer after forming the second P-type semiconductor layer and before forming the gate dielectric layer. Figure 4 to Figure 5h The preparation method provided in the examples of the present application is described in more detail. Figure 4 A flowchart of another method for preparing a P-type transistor based on gallium nitride provided in an embodiment of the present application, Figure 5a to Figure 5h for Figure 4 Schematic diagram of the corresponding structure of each step.

[0080] like Figure 5a As shown, corresponding to step S1, a substrate 1 is provided.

[0081] In one embodiment of the present application, the substrate 1 provided in the embodiment of the present application may be a Si substrate, a SiC substrate, a Sapphire substrate or a GaN substrate, etc., and the present application does not make any specific limitation on this.

[0082] like Figure 5b As shown, corresponding to step S2, a buffer layer 2, a channel layer 3, a barrier layer 4, a first P-type semiconductor layer 5 and a second P-type semiconductor layer 6 are sequentially stacked on the substrate 1 in a direction perpendicular to the plane where the substrate 1 is located, wherein the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 have different bandgap widths, and the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 deplete the two-dimensional electron gas at the interface between the channel layer 3 and the barrier layer 4.

[0083] In one embodiment of the present application, the buffer layer 2 provided in the embodiment of the present application can reduce the off-state leakage current of the GaN device and increase the breakdown voltage, and can also improve the preparation quality of the subsequent epitaxial layer, wherein the material of the buffer layer 2 can be a combination of one or more materials such as GaN, AlN, InGaN, AlGaN, AlInGaN, etc. The channel layer 3 is used to provide an electronic conductive channel, and the material of the channel layer 3 can be GaN, InGaN, AlGaN, AlInGaN, etc., which is not specifically limited in the present application. There is a polarization effect at the interface between the barrier layer 4 and the channel layer 3, and a two-dimensional electron gas can be generated. However, after the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 continue to grow on the barrier layer 4, the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 will deplete the two-dimensional electron gas at the interface between the barrier layer 4 and the channel layer 3, thereby forming a gallium nitride P-type transistor while also being able to realize the integration of a gallium nitride N-type transistor on the same epitaxy, and providing a basis for realizing an enhanced gate for a gallium nitride N-type transistor. The material of the barrier layer 4 can be a combination of one or more materials such as GaN, AlN, InGaN, AlGaN, AlInGaN, etc.; wherein, the barrier layer 4 can be a stacked structure of at least one sublayer (when the barrier layer 4 includes multiple sublayers, the multiple sublayers are stacked above the plane where the substrate 1 is located), and the bandgap width of the material of at least one sublayer in the barrier layer 4 is greater than the bandgap width of the material of the channel layer 3. The first P-type semiconductor layer 5 and the second P-type semiconductor layer 6 can deplete the two-dimensional electron gas, the bandgap width of the first P-type semiconductor layer 5 is greater than the bandgap width of the second P-type semiconductor layer 6, there is a polarization effect between the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6, and because the bandgap width of the channel layer 3 is greater than the bandgap width of the second P-type semiconductor layer 6, there is a net negative polarization charge at the interface between the first P-type semiconductor layer 5 and the second P-type semiconductor layer 6, generating a high concentration of two-dimensional hole gas, thereby obtaining a lower on-resistance and a higher current density, wherein the material of the first P-type semiconductor layer 5 can be P-GaN, and the material of the second P-type semiconductor layer 6 can be P-InGaN, and the present application does not make any specific restrictions on this.

[0084] like Figure 5c As shown, corresponding to step S21, the second P-type semiconductor layer 6 is etched to form a gate groove.

[0085] like Figure 5d As shown, corresponding to step S3, a gate dielectric layer 7 is formed on the side of the second P-type semiconductor layer 6 away from the substrate 1. Optionally, the gate dielectric layer 7 includes a gate region and a source region and a drain region located on both sides of the gate region, wherein the gate groove is located at the gate region.

[0086] In one embodiment of the present application, the material of the gate dielectric layer 7 provided in the embodiment of the present application can be Al2O3, Si3N4, SiO2, etc., and the present application does not make any specific limitation on this.

[0087] like Figure 5e As shown, corresponding to step S4, the gate dielectric layer 7 is etched to form a source hollow exposing the second P-type semiconductor layer 6 in the source region, and a drain hollow exposing the second P-type semiconductor layer 6 in the drain region, and the source hollow and the drain hollow are respectively located on both sides of the active area.

[0088] like Figure 5f As shown, corresponding to step S5, metal is deposited at the source hollowing and the drain hollowing to form a source 8 and a drain 9. That is, a source 8 and a drain 9 are formed on the side of the gate dielectric layer 7 away from the substrate 1, the source 8 is located in the source region and contacts the second P-type semiconductor layer 6 through the source hollowing, and the drain 9 is located in the drain region and contacts the second P-type semiconductor layer 6 through the drain hollowing. The source 8 and the drain 9 can be made of metal, and the source 8 and the drain 9 can be formed by a deposition process.

[0089] like Figure 5g As shown, corresponding to step S6, a device isolation region 10 is formed between different P-type transistors. Wherein, the preparation of the P-type transistor is carried out on the substrate 1, so a plurality of P-type transistors can be prepared on the substrate 1, and in order to avoid crosstalk between adjacent P-type transistors, it is necessary to isolate adjacent P-type transistors. The specific device isolation region 10 can be an ion implantation isolation region, wherein ion implantation is performed from one side of the gate dielectric layer 7 to form the ion implantation isolation region 10, wherein the ion implantation can adopt one or more combinations of F, N, B, Ar, Fe ions, etc. Alternatively, the device isolation region 10 can also be an etched isolation region, that is, etching is performed from one side of the gate dielectric layer 7 to form an etched isolation region, and the present application does not make specific restrictions on this.

[0090] like Figure 5hAs shown, corresponding to step S7, a gate 11 is formed on the side of the gate dielectric layer 7 away from the substrate 1, the gate 11 is located between the source 8 and the drain 9, and the gate 11 is located in the gate groove, and finally a P-type transistor based on gallium nitride is formed.

[0091] Based on the same inventive concept, the embodiment of the present application further provides a gallium nitride-based CMOS device, wherein the CMOS device includes a gallium nitride-based P-type transistor provided by any of the above embodiments. Figure 6 , which is a schematic structural diagram of a gallium nitride-based CMOS device provided in an embodiment of the present application, wherein the CMOS device includes:

[0092] An epitaxial structure, the epitaxial structure comprising a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer 3 and the barrier layer 4; the epitaxial structure is divided into an N-tube region and a P-tube region, the N-tube region comprises an N-tube gate region and an N-tube source region and an N-tube drain region located on both sides of the N-tube gate region, the P-tube region comprises a P-tube gate region and a P-tube source region and a P-tube drain region located on both sides of the P-tube gate region, the first P-type semiconductor layer comprises an N-tube first P-type semiconductor layer 51 located at the N-tube gate region and a P-tube first P-type semiconductor layer 52 located at the P-tube region, and the second P-type semiconductor layer comprises an N-tube second P-type semiconductor layer 61 located at the N-tube gate region and a P-tube second P-type semiconductor layer 62 located at the P-tube region.

[0093] a first dielectric layer 71 located on a side of the second P-type semiconductor layer away from the substrate 1 and covering the exposed surface of the epitaxial structure; a first electrode layer located on a side of the first dielectric layer 71 away from the substrate 1, the first electrode layer comprising an N-tube source 81 and an N-tube drain 91, the N-tube source 81 located in the N-tube source region and in contact with the barrier layer 4 through the first dielectric layer 71, the N-tube drain 91 located in the N-tube drain region and in contact with the barrier layer 4 through the first dielectric layer 71; a first electrode layer located on a side of the first dielectric layer 71 away from the substrate 1, the first electrode layer comprising an N-tube source 81 and an N-tube drain 91, the N-tube source 81 located in the N-tube source region and in contact with the barrier layer 4 through the first dielectric layer 71; The second electrode layer on one side of the substrate 1 comprises an N-tube gate 111, a P-tube source 82 and a P-tube drain 92. The N-tube gate 111 is located in the N-tube gate region and contacts the N-tube second P-type semiconductor layer 61 through the first dielectric layer 71. The P-tube source 82 is located in the P-tube source region and contacts the P-tube second P-type semiconductor layer 62 through the first dielectric layer 71. The P-tube drain 92 is located in the P-tube drain region and contacts the P-tube second P-type semiconductor layer 62 through the first dielectric layer 71.

[0094] The isolation region 101 is located at the junction of the N-tube region and the P-tube region, wherein the isolation region 101 may be an ion implantation isolation region or an etching isolation region.

[0095] The second gate dielectric layer 72 is located on a side of the first electrode layer and the second electrode layer away from the substrate 1 and covers the exposed surfaces of the first dielectric layer 71 , the first electrode layer and the second electrode layer.

[0096] A connection electrode layer located on a side of the second gate dielectric layer 72 away from the substrate 1, the connection electrode layer comprising an N-tube gate connection electrode 1110, an N-tube source connection electrode 810, an interconnection electrode 912, a P-tube gate connection electrode 1120 and a P-tube source connection electrode 820, the N-tube gate connection electrode 1110 contacts the N-tube gate 111 through the second gate dielectric layer 72, the N-tube source connection electrode 810 contacts the N-tube source 81 through the second gate dielectric layer 72, the interconnection electrode 912 contacts both the N-tube drain 91 and the P-tube drain 92 through the second gate dielectric layer 72, the P-tube gate connection electrode 1120 is located at the P-tube gate region, and the P-tube source connection electrode 820 contacts the P-tube source 82 through the second gate dielectric layer 72.

[0097] In one embodiment of the present application, the electrode provided in the embodiment of the present application contacts other structural layers through the dielectric layer, and the dielectric layer may be etched to form a hollow, and then the electrode contacts and connects with other structural layers through the hollow. Figure 6As shown, the first dielectric layer 71 provided in the embodiment of the present application includes a first N-tube gate hollowing out at the N-tube gate region, the first dielectric layer 71 includes a first N-tube source hollowing out at the N-tube source region, the first dielectric layer 71 includes a first N-tube drain hollowing out at the N-tube drain region, the first dielectric layer 71 includes a first P-tube source hollowing out at the P-tube source region, and the first dielectric layer 71 includes a first P-tube drain hollowing out at the P-tube drain region; the N-tube gate 111 is located in the N-tube gate region and is connected to the N-tube gate 111 through the first N-tube gate hollowing out. The N-tube second P-type semiconductor layer 61 is in contact with the N-tube source electrode 81, the N-tube source electrode 81 is located in the N-tube source electrode region and is in contact with the barrier layer 4 through the first N-tube source electrode hollowing out, the N-tube drain electrode 91 is located in the N-tube drain electrode region and is in contact with the barrier layer 4 through the first N-tube drain electrode hollowing out, the P-tube source electrode 82 is located in the P-tube source electrode region and is in contact with the P-tube second P-type semiconductor layer 62 through the first P-tube source electrode hollowing out, and the P-tube drain electrode 92 is located in the P-tube drain electrode region and is in contact with the P-tube second P-type semiconductor layer 62 through the first P-tube drain electrode hollowing out.

[0098] Furthermore, the second gate dielectric layer 72 provided in the embodiment of the present application includes a second N-tube source hollowing out at the N-tube source 81, the second gate dielectric layer 72 includes a second N-tube gate hollowing out at the N-tube gate 111, the second gate dielectric layer 72 includes a second N-tube drain hollowing out at the N-tube drain 91, the second gate dielectric layer 72 includes a second P-tube source hollowing out at the P-tube source 82, and the second gate dielectric layer 72 includes a second P-tube drain hollowing out at the P-tube drain 92; the N-tube gate connection electrode 1110 contacts the N-tube gate 111 through the second N-tube gate hollowing out, the N-tube source connection electrode 810 contacts the N-tube source 81 through the second N-tube source hollowing out, the interconnect electrode 912 contacts both the N-tube drain 91 and the P-tube drain 92 through the second N-tube drain hollowing out and the second P-tube drain hollowing, and the P-tube source connection electrode 820 contacts the P-tube source 82 through the second P-tube source hollowing out.

[0099] Furthermore, the N-tube drain region and the P-tube drain region provided in the embodiment of the present application are adjacent to each other, so that the N-tube drain 91 and the P-tube drain 92 are adjacent to each other, which facilitates the interconnection electrode 912 to connect the N-tube drain 91 and the P-tube drain 92. Also, the bandgap width of the first P-type semiconductor layer provided in the embodiment of the present application is greater than the bandgap width of the second P-type semiconductor layer; and / or, the bandgap width of the channel layer 3 is greater than the bandgap width of the second P-type semiconductor layer. There is a polarization effect between the first P-type semiconductor layer and the second P-type semiconductor layer, and there is a net negative polarization charge at the interface between the two, so that a high concentration of two-dimensional hole gas is generated at the interface between the two to reduce the on-resistance. Therefore, the P-type transistor corresponding to the P-tube region provided in the embodiment of the present application has the advantages of high current density and low on-resistance, so that the gallium nitride-based CMOS device provided in the embodiment of the present application has a shorter transmission delay and a faster switching speed, thereby improving the performance of the device.

[0100] In an embodiment provided in the present application, at least one of the first dielectric layer and the second gate dielectric layer provided in the embodiment of the present application includes a P-tube gate hollowing at the location corresponding to the P-tube gate region. Specifically, the first dielectric layer and the second gate dielectric layer provided in the embodiment of the present application both include a P-tube gate hollowing at the locations corresponding to the P-tube gate region, so that the P-tube gate connection electrode is in direct contact with the second P-type semiconductor layer, thereby forming a Schottky gate. Also, one of the first dielectric layer and the second gate dielectric layer includes a P-tube gate hollowing at the location corresponding to the P-tube gate region, so that the P-tube gate connection electrode is isolated from the second P-type semiconductor layer by another dielectric layer, thereby forming a metal-insulator-semiconductor (MIS) gate. Continuing as Figure 6 As shown, the first dielectric layer 71 can be configured to include a hollow design at the P-tube gate region, so that the second gate dielectric layer 72 is in contact with the P-tube second P-type semiconductor layer 62 .

[0101] Furthermore, the second P-type semiconductor layer 62 of the P-tube provided in the embodiment of the present application further includes a gate groove on the side facing away from the substrate 1, and the gate connection electrode 1120 of the P-tube is located in the region of the gate groove, thereby reducing the number of holes by removing part of the thickness of the second P-type semiconductor layer 62 of the P-tube, thereby forming an enhanced gate. At the same time, the heterogeneous interface between the first P-type semiconductor layer 52 of the P-tube and the second P-type semiconductor layer 62 of the P-tube is retained, so that a high-density hole conductive channel can be formed at the gate region after the P-type transistor is turned on again. Alternatively, the second P-type semiconductor layer 62 of the P-tube provided in the embodiment of the present application may not be grooved on the side facing away from the substrate 1, and as Figure 1 The planar structure similar to the second P-type semiconductor layer 6 shown is not specifically limited in this application.

[0102] Based on the same inventive concept, the present application embodiment also provides a method for preparing a gallium nitride-based CMOS device, which is used to prepare a gallium nitride-based CMOS device provided by any of the above embodiments. Figure 7 FIG. 1 is a flow chart of a method for preparing a gallium nitride-based CMOS device provided in an embodiment of the present application, wherein the preparation method comprises:

[0103] S10. Provide an epitaxial structure, comprising a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; the epitaxial structure is divided into an N-tube region and a P-tube region, the N-tube region comprises an N-tube gate region and an N-tube source region and an N-tube drain region located on both sides of the N-tube gate region, and the P-tube region comprises a P-tube gate region and a P-tube source region and a P-tube drain region located on both sides of the P-tube gate region.

[0104] S20, etching the first P-type semiconductor layer and the second P-type semiconductor layer, so that the first P-type semiconductor layer includes an N-tube first P-type semiconductor layer located at the N-tube gate region and a P-tube first P-type semiconductor layer located at the P-tube region, and the second P-type semiconductor layer includes an N-tube second P-type semiconductor layer located at the N-tube gate region and a P-tube second P-type semiconductor layer located at the P-tube region.

[0105] S30. Form a first dielectric layer covering the exposed surface of the epitaxial structure (it should be noted that the epitaxial structure is the structure after the above steps, and “epitaxial structure” is directly cited for the convenience of description) on the side of the second P-type semiconductor layer away from the substrate.

[0106] S40 , etching the first dielectric layer to form a first N-tube source hollow in the N-tube source region, and to form a first N-tube drain hollow in the N-tube drain region.

[0107] S50. Form a first electrode layer on a side of the first dielectric layer away from the substrate, the first electrode layer comprising an N-tube source and an N-tube drain, the N-tube source being located in the N-tube source region and contacting the barrier layer through the first N-tube source hollowing out, the N-tube drain being located in the N-tube drain region and contacting the barrier layer through the first N-tube drain hollowing out.

[0108] S60 , forming an isolation region outside the N-transistor active region and the P-transistor active region.

[0109] S70, etching the first dielectric layer to form a first N-tube gate hollow in the N-tube gate region, a first P-tube source hollow in the P-tube source region, and a first P-tube drain hollow in the P-tube drain region.

[0110] S80. Form a second electrode layer on a side of the first dielectric layer away from the substrate, the second electrode layer comprising an N-tube gate, a P-tube source and a P-tube drain, the N-tube gate being located in the N-tube gate region and contacting the N-tube second P-type semiconductor layer through the first N-tube gate hollowing out, the P-tube source being located in the P-tube source region and contacting the P-tube second P-type semiconductor layer through the first P-tube source hollowing out, the P-tube drain being located in the P-tube drain region and contacting the P-tube second P-type semiconductor layer through the first P-tube drain hollowing out.

[0111] S90 , forming a second gate dielectric layer covering exposed surfaces of the first dielectric layer, the first electrode layer, and the second electrode layer on a side of the first electrode layer and the second electrode layer facing away from the substrate.

[0112] S100, etching the second gate dielectric layer to form a second N-tube source hollow at the N-tube source, a second N-tube gate hollow at the N-tube gate, a second N-tube drain hollow at the N-tube drain, a second P-tube source hollow at the P-tube source, and a second P-tube drain hollow at the P-tube drain.

[0113] S110. Form a connection electrode layer on a side of the second gate dielectric layer away from the substrate, the connection electrode layer comprising an N-tube gate connection electrode, an N-tube source connection electrode, an interconnection electrode, a P-tube gate connection electrode and a P-tube source connection electrode, the N-tube gate connection electrode contacts the N-tube gate through the second N-tube gate hollowing out, the N-tube source connection electrode contacts the N-tube source through the second N-tube source hollowing out, the interconnection electrode contacts both the N-tube drain and the P-tube drain through the second N-tube drain hollowing out and the second P-tube drain hollowing out, the P-tube gate connection electrode is located at the P-tube gate region, and the P-tube source connection electrode contacts the P-tube source through the second P-tube source hollowing out.

[0114] Furthermore, the second P-type semiconductor layer of the P-tube provided in the embodiment of the present application may further include a gate groove, wherein when the first dielectric layer is etched to be hollowed out at the gate region of the P-tube, the gate groove may be formed by etching the second P-type semiconductor layer of the P-tube while continuing to etch the first dielectric layer after forming the device isolation region. Figure 7 to Figure 8k The preparation method provided in the examples of the present application is described in more detail. Figures 8a to 8k for Figure 7Schematic diagram of the corresponding structure of each step.

[0115] like Figure 8a As shown, corresponding to step S10, an epitaxial structure is provided, the epitaxial structure comprising a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer 3 and the barrier layer 4; the epitaxial structure is divided into an N-tube region and a P-tube region, the N-tube region comprising an N-tube gate region and an N-tube source region and an N-tube drain region located on both sides of the N-tube gate region, and the P-tube region comprising a P-tube gate region and a P-tube source region and a P-tube drain region located on both sides of the P-tube gate region.

[0116] In one embodiment of the present application, the substrate 1 provided in the embodiment of the present application may be a Si substrate, a SiC substrate, a Sapphire substrate or a GaN substrate, etc., and the present application does not make any specific restrictions on this. The buffer layer 2 provided in the embodiment of the present application can reduce the off-state leakage current of the GaN device and increase the breakdown voltage, and can also improve the preparation quality of the subsequent epitaxial layer, wherein the material of the buffer layer 2 may be a combination of one or more materials such as GaN, AlN, InGaN, AlGaN, AlInGaN, etc. The channel layer 3 is used to provide an electronic conductive channel, and the material of the channel layer 3 may be GaN, InGaN, AlGaN, AlInGaN, etc., and the present application does not make any specific restrictions on this. There is a polarization effect at the interface between the barrier layer 4 and the channel layer 3, which can generate a two-dimensional electron gas. However, after the first P-type semiconductor layer and the second P-type semiconductor layer continue to grow on the barrier layer 4, the first P-type semiconductor layer and the second P-type semiconductor layer will deplete the two-dimensional electron gas at the interface between the barrier layer 4 and the channel layer 3, thereby forming a gallium nitride P-type transistor while also being able to integrate a gallium nitride N-type transistor on the same epitaxy, and providing a basis for realizing an enhanced gate of the gallium nitride N-type transistor. The material of the barrier layer 4 can be a combination of one or more materials such as GaN, AlN, InGaN, AlGaN, and AlInGaN; wherein, the barrier layer 4 can be a stacked structure of at least one sublayer (when the barrier layer 4 includes multiple sublayers, the multiple sublayers are stacked along the upper side of the plane where the vertical substrate 1 is located), and the bandgap width of the material of at least one sublayer in the barrier layer 4 is greater than the bandgap width of the material of the channel layer 3. The first P-type semiconductor layer and the second P-type semiconductor layer can deplete the two-dimensional electron gas, the bandgap width of the first P-type semiconductor layer is greater than the bandgap width of the second P-type semiconductor layer, there is a polarization effect between the first P-type semiconductor layer and the second P-type semiconductor layer, and because the bandgap width of the channel layer 3 is greater than the bandgap width of the second P-type semiconductor layer, there is a net negative polarization charge at the interface between the first P-type semiconductor layer and the second P-type semiconductor layer, generating a high concentration of two-dimensional hole gas, thereby obtaining a lower on-resistance and a higher current density, wherein the material of the first P-type semiconductor layer can be P-GaN, and the material of the second P-type semiconductor layer can be P-InGaN, and the present application does not make any specific restrictions on this.

[0117] like Figure 8b As shown, corresponding to step S20, the first P-type semiconductor layer and the second P-type semiconductor layer are etched so that the first P-type semiconductor layer includes an N-tube first P-type semiconductor layer 51 located at the N-tube gate region and a P-tube first P-type semiconductor layer 52 located at the P-tube region, and the second P-type semiconductor layer includes an N-tube second P-type semiconductor layer 61 located at the N-tube gate region and a P-tube second P-type semiconductor layer 62 located at the P-tube region.

[0118] like Figure 8c As shown, corresponding to step S30, a first dielectric layer 71 covering the exposed surface of the epitaxial structure is formed on the side of the second P-type semiconductor layer away from the substrate, wherein the first dielectric layer 71 may be a passivation layer.

[0119] In one embodiment of the present application, the material of the first dielectric layer 71 provided in the embodiment of the present application can be Al2O3, Si3N4, SiO2, etc., and the present application does not make any specific limitation on this.

[0120] like Figure 8d As shown, corresponding to step S40, the first dielectric layer 71 is etched to form a first N-tube source hollow at the N-tube source region, and a first N-tube drain hollow at the N-tube drain region.

[0121] like Figure 8e As shown, corresponding to step S50, a first electrode layer is formed on the side of the first dielectric layer 71 away from the substrate 1, and the first electrode layer includes an N-tube source 81 and an N-tube drain 91. The N-tube source 81 is located in the N-tube source region and contacts the barrier layer 4 through the first N-tube source hollowing. The N-tube drain 91 is located in the N-tube drain region and contacts the barrier layer 4 through the first N-tube drain hollowing. The N-tube source 81 and the N-tube drain 91 can be made of metal, and can be formed by a deposition process.

[0122] like Figure 8f As shown, corresponding to step S60, an isolation region 101 is formed at the junction of the N-tube region and the P-tube region. The isolation region 101 may be an ion implantation device isolation region, wherein the ion implantation may be a combination of one or more of F, N, B, Ar, Fe ions, etc. Alternatively, the isolation region 101 may also be an etched isolation region, which is formed by etching from one side of the first dielectric layer 71, and the present application does not make any specific restrictions on this.

[0123] like Figure 8g As shown, corresponding to step S70, the first dielectric layer 71 is etched to form a first N-tube gate hollow at the N-tube gate region, a first P-tube source hollow at the P-tube source region, and a first P-tube drain hollow at the P-tube drain region;

[0124] like Figure 8hAs shown, corresponding to step S80, a second electrode layer is formed on the side of the first dielectric layer 71 away from the substrate 1, and the second electrode layer includes an N-tube gate 111, a P-tube source 82 and a P-tube drain 92. The N-tube gate 111 is located in the N-tube gate region and contacts the N-tube second P-type semiconductor layer 61 through the first N-tube gate hollowing out. The P-tube source 82 is located in the P-tube source region and contacts the P-tube second P-type semiconductor layer 62 through the first P-tube source hollowing out. The P-tube drain 92 is located in the P-tube drain region and contacts the P-tube second P-type semiconductor layer 62 through the first P-tube drain hollowing out. The N-tube gate 111, the P-tube source 82 and the P-tube drain 92 can be made of metal, and the N-tube gate 111, the P-tube source 82 and the P-tube drain 92 can be formed by a deposition process.

[0125] Furthermore, after forming the second electrode layer, the first dielectric layer 71 is etched to be hollowed out at the region corresponding to the P-tube gate, and the P-tube second P-type semiconductor layer 62 is etched to form a gate groove.

[0126] like Figure 8i As shown, corresponding to step S90, a second gate dielectric layer 72 is formed on the side of the first electrode layer and the second electrode layer facing away from the substrate 1, covering the exposed surfaces of the first dielectric layer 71, the first electrode layer and the second electrode layer, and the second gate dielectric layer 72 also covers the inner wall of the gate groove.

[0127] In one embodiment of the present application, the material of the second gate dielectric layer 72 provided in the embodiment of the present application can be Al2O3, Si3N4, SiO2, etc., and the present application does not make any specific limitation on this.

[0128] like Figure 8j As shown, corresponding to step S100, the second gate dielectric layer 72 is etched to form a second N-tube source hollow at the N-tube source 81, a second N-tube gate hollow at the N-tube gate 111, a second N-tube drain hollow at the N-tube drain 91, a second P-tube source hollow at the P-tube source 82, and a second P-tube drain hollow at the P-tube drain 92;

[0129] like Figure 8kAs shown, corresponding to step S110, a connection electrode layer is formed on the side of the second gate dielectric layer 72 away from the substrate 1, and the connection electrode layer includes an N-tube gate connection electrode 1110, an N-tube source connection electrode 810, an interconnection electrode 912, a P-tube gate connection electrode 1120 and a P-tube source connection electrode 820. The N-tube gate connection electrode 1110 contacts the N-tube gate 111 through the second N-tube gate hollowing, the N-tube source connection electrode 810 contacts the N-tube source 81 through the second N-tube source hollowing, the interconnection electrode 912 contacts both the N-tube drain 91 and the P-tube drain 92 through the second N-tube drain hollowing and the second P-tube drain hollowing, the P-tube source connection electrode 820 contacts the P-tube source 82 through the second P-tube source hollowing, and the P-tube gate connection electrode 1120 is located at the P-tube gate region. Among them, the N-tube source connection electrode 810 is used for external grounding signal, the interconnection electrode 912 is used as the output terminal to output the signal, the P-tube source connection electrode 820 is used for external power supply voltage, and the N-tube gate connection electrode 1110 and the P-tube gate connection electrode are connected through a connecting line to access the control signal.

[0130] The embodiment of the present application provides a P-type transistor based on gallium nitride and a preparation method thereof, and a CMOS device based on gallium nitride and a preparation method thereof, wherein the P-type transistor comprises: a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; a gate dielectric layer located on a side of the second P-type semiconductor layer away from the substrate; a source and a drain located on a side of the second P-type semiconductor layer away from the substrate and respectively located on both sides of an active region; and a gate located on a side of the gate dielectric layer away from the substrate, the gate being located between the source and the drain.

[0131] From the above content, it can be seen that in the technical solution provided in the embodiment of the present application, the bandgap widths of the first P-type semiconductor layer and the second P-type semiconductor layer are different, and there is a polarization effect between the first P-type semiconductor layer and the second P-type semiconductor layer, so that a high concentration of two-dimensional hole gas is generated at the interface between the two to reduce the on-resistance. Therefore, the gallium nitride-based P-type transistor provided in the embodiment of the present application has the advantages of high current density and low on-resistance, so that the gallium nitride-based CMOS device provided in the embodiment of the present application has a shorter transmission delay and a faster switching speed, thereby improving the performance of the device.

[0132] In the description of the embodiments of the present application, it needs to be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0133] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0134] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0135] In the embodiments of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0136] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples without contradiction.

[0137] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A P-type transistor based on gallium nitride, characterized in that: The P-type transistor comprises: A substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; a gate dielectric layer located on a side of the second P-type semiconductor layer facing away from the substrate; A source electrode and a drain electrode located on a side of the second P-type semiconductor layer away from the substrate and respectively located on two sides of the active region; A gate electrode is located on a side of the gate dielectric layer away from the substrate, and the gate electrode is located between the source electrode and the drain electrode.

2. The gallium nitride-based P-type transistor according to claim 1, characterized in that: The bandgap width of the first P-type semiconductor layer is greater than the bandgap width of the second P-type semiconductor layer; And / or, the bandgap width of the channel layer is greater than the bandgap width of the second P-type semiconductor layer.

3. The gallium nitride-based P-type transistor according to claim 1, characterized in that: The barrier layer is a stacked structure of at least one sub-layer, and the bandgap width of the material of at least one of the sub-layers in the barrier layer is greater than the bandgap width of the material of the channel layer.

4. The gallium nitride-based P-type transistor according to claim 1, characterized in that: The second P-type semiconductor layer further includes a gate groove on a side facing away from the substrate, and the gate is located in the region of the gate groove; And / or, the gate dielectric layer is a physical layer at a position corresponding to the gate or includes a gate hollowing.

5. A method for preparing a P-type transistor based on gallium nitride, characterized in that: Used to prepare the gallium nitride-based P-type transistor according to any one of claims 1 to 4, wherein the preparation method comprises: providing a substrate; In a direction perpendicular to the plane where the substrate is located, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer are sequentially stacked on the substrate, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; forming a gate dielectric layer on a side of the second P-type semiconductor layer facing away from the substrate; Etching the gate dielectric layer to form a source hollowing out exposing the second P-type semiconductor layer in the source region, and forming a drain hollowing out exposing the second P-type semiconductor layer in the drain region, wherein the source hollowing out and the drain hollowing out are respectively located on two sides of the active region; Depositing metal at the source and drain hollows to form a source and a drain; forming a device isolation region between different P-type transistors; A gate is formed on the side of the gate dielectric layer facing away from the substrate, and the gate is located between the source and the drain.

6. A gallium nitride-based CMOS device, characterized in that: The CMOS device comprises: An epitaxial structure, the epitaxial structure comprising a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; the epitaxial structure is divided into an N-tube region and a P-tube region, the N-tube region comprises an N-tube gate region and an N-tube source region and an N-tube drain region located on both sides of the N-tube gate region, the P-tube region comprises a P-tube gate region and a P-tube source region and a P-tube drain region located on both sides of the P-tube gate region, the first P-type semiconductor layer comprises an N-tube first P-type semiconductor layer located at the N-tube gate region and a P-tube first P-type semiconductor layer located at the P-tube region, and the second P-type semiconductor layer comprises an N-tube second P-type semiconductor layer located at the N-tube gate region and a P-tube second P-type semiconductor layer located at the P-tube region; A first dielectric layer located on a side of the second P-type semiconductor layer away from the substrate and covering an exposed surface of the epitaxial structure; an electrode layer located on a side of the first dielectric layer away from the substrate, the electrode layer comprising an N-tube gate, an N-tube source, an N-tube drain, a P-tube source and a P-tube drain, the N-tube gate contacts the N-tube second P-type semiconductor layer through the first dielectric layer, the N-tube source contacts the barrier layer through the first dielectric layer, the N-tube drain contacts the barrier layer through the first dielectric layer, the P-tube source contacts the P-tube second P-type semiconductor layer through the first dielectric layer, and the P-tube drain contacts the P-tube second P-type semiconductor layer through the first dielectric layer; an isolation region located at the junction of the N-tube region and the P-tube region; a second gate dielectric layer located on a side of the electrode layer away from the substrate and covering exposed surfaces of the first dielectric layer and the electrode layer; A connecting electrode layer located on a side of the second gate dielectric layer away from the substrate, the connecting electrode layer comprising an N-tube gate connecting electrode, an N-tube source connecting electrode, an interconnecting electrode, a P-tube gate connecting electrode and a P-tube source connecting electrode, the N-tube gate connecting electrode contacts the N-tube gate through the second gate dielectric layer, the N-tube source connecting electrode contacts the N-tube source through the second gate dielectric layer, the interconnecting electrode contacts both the N-tube drain and the P-tube drain through the second gate dielectric layer, the P-tube gate connecting electrode is located at the P-tube gate region, and the P-tube source connecting electrode contacts the P-tube source through the second gate dielectric layer.

7. The gallium nitride-based CMOS device according to claim 6, characterized in that: The bandgap width of the first P-type semiconductor layer is greater than the bandgap width of the second P-type semiconductor layer; And / or, the bandgap width of the channel layer is greater than the bandgap width of the second P-type semiconductor layer.

8. The gallium nitride-based CMOS device according to claim 6, characterized in that: The barrier layer is a stacked structure of at least one sub-layer, and the bandgap width of the material of at least one of the sub-layers in the barrier layer is greater than the bandgap width of the material of the channel layer.

9. The gallium nitride-based CMOS device according to claim 6, characterized in that: The second P-type semiconductor layer of the P-tube further includes a gate groove on the side facing away from the substrate, and the gate connection electrode of the P-tube is located in the region of the gate groove; And / or, at least one of the first dielectric layer and the second gate dielectric layer includes a P-tube gate hollowing out at a location corresponding to the P-tube gate region.

10. A method for preparing a gallium nitride-based CMOS device, characterized in that: Used to prepare the gallium nitride-based CMOS device according to any one of claims 6 to 9, wherein the preparation method comprises: An epitaxial structure is provided, the epitaxial structure comprising a substrate, a buffer layer, a channel layer, a barrier layer, a first P-type semiconductor layer and a second P-type semiconductor layer stacked in sequence, wherein the first P-type semiconductor layer and the second P-type semiconductor layer have different bandgap widths, and the first P-type semiconductor layer and the second P-type semiconductor layer deplete the two-dimensional electron gas at the interface between the channel layer and the barrier layer; the epitaxial structure is divided into an N-tube region and a P-tube region, the N-tube region comprises an N-tube gate region and an N-tube source region and an N-tube drain region located on both sides of the N-tube gate region, and the P-tube region comprises a P-tube gate region and a P-tube source region and a P-tube drain region located on both sides of the P-tube gate region; Etching the first P-type semiconductor layer and the second P-type semiconductor layer so that the first P-type semiconductor layer includes an N-tube first P-type semiconductor layer located at the N-tube gate region and a P-tube first P-type semiconductor layer located at the P-tube region, and the second P-type semiconductor layer includes an N-tube second P-type semiconductor layer located at the N-tube gate region and a P-tube second P-type semiconductor layer located at the P-tube region; forming a first dielectric layer covering an exposed surface of the epitaxial structure on a side of the second P-type semiconductor layer away from the substrate; Etching the first dielectric layer to form a first N-tube source hollow at the N-tube source region, and forming a first N-tube drain hollow at the N-tube drain region; A first electrode layer is formed on a side of the first dielectric layer away from the substrate, the first electrode layer comprising an N-tube source and an N-tube drain, the N-tube source is located in the N-tube source region and contacts the barrier layer through the first N-tube source hollowing, the N-tube drain is located in the N-tube drain region and contacts the barrier layer through the first N-tube drain hollowing; forming an isolation region at the junction of the N-tube region and the P-tube region; Etching the first dielectric layer to form a first N-tube gate hollow at the N-tube gate region, a first P-tube source hollow at the P-tube source region, and a first P-tube drain hollow at the P-tube drain region; A second electrode layer is formed on a side of the first dielectric layer away from the substrate, the second electrode layer comprising an N-tube gate, a P-tube source and a P-tube drain, the N-tube gate is located in the N-tube gate region and contacts the N-tube second P-type semiconductor layer through the first N-tube gate hollowing out, the P-tube source is located in the P-tube source region and contacts the P-tube second P-type semiconductor layer through the first P-tube source hollowing out, and the P-tube drain is located in the P-tube drain region and contacts the P-tube second P-type semiconductor layer through the first P-tube drain hollowing out; On the side of the first electrode layer and the second electrode layer facing away from the substrate, a second gate dielectric layer is formed to cover the exposed surfaces of the first dielectric layer, the first electrode layer and the second electrode layer; Etching the second gate dielectric layer to form a second N-tube source hollow at the N-tube source, a second N-tube gate hollow at the N-tube gate, a second N-tube drain hollow at the N-tube drain, a second P-tube source hollow at the P-tube source, and a second P-tube drain hollow at the P-tube drain; A connection electrode layer is formed on a side of the second gate dielectric layer away from the substrate, the connection electrode layer comprising an N-tube gate connection electrode, an N-tube source connection electrode, an interconnection electrode, a P-tube gate connection electrode and a P-tube source connection electrode, the N-tube gate connection electrode contacts the N-tube gate through the second N-tube gate hollowing out, the N-tube source connection electrode contacts the N-tube source through the second N-tube source hollowing out, the interconnection electrode contacts both the N-tube drain and the P-tube drain through the second N-tube drain hollowing out and the second P-tube drain hollowing out, the P-tube gate connection electrode is located at the P-tube gate region, and the P-tube source connection electrode contacts the P-tube source through the second P-tube source hollowing out.

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