Power stage and output driver for data line

Abstract

The invention relates to a power stage and an output driver for a data line. The differential input stages of the output driver for the data lines are asymmetrically configured. A very large gain is provided in one branch of the input stage by a current source as a working resistor. The large gain is also coupled to the other branch. The bridge resistor reduces the gain by about one time. Therefore, the bandwidth is greatly improved.

Description

[0001] This application is a divisional application of a patent application with application number 202010504597.9, whose application date is June 5, 2020 and invention name is “Input stage of a high-voltage amplifier for controlling data lines”. Technical Field

[0002] The invention relates to an input stage of an output driver for a data line, wherein the input stage feeds a current to a common node with a power stage. Here, the current fed from the input stage to the common node depends on the voltage difference between the positive input terminal and the negative input terminal of the input stage. As a result, the power stage generates a potential at the output node, which, ignoring parasitic effects, depends only on the current fed from the input stage to the common node. Background Art

[0003] In order to control the data lines via an integrated circuit, a bus driver is required. The bus driver should be small and robust. Usually, the bus voltage is significantly higher than the voltages handled in modern digital units of integrated circuits. Therefore, such integrated circuits usually have multiple voltage supplies. In the example of the DSI3 bus driver discussed here, a voltage of 30V is required on the data bus, while the input stage must work with 5V.

[0004] The power stage requires high-voltage transistors that can handle the rated data bus voltage and any possible overshoot and meet the corresponding reliability requirements. These high-voltage transistors are relatively densely packed in order to maintain a limited electric field strength when stepping down the voltage. Therefore, the number of these high-voltage transistors should be minimized in such a bus driver.

[0005] When describing the invention in detail, it has been shown that all other attempts to implement an AB output stage for controlling a data line in a current-limited manner have without exception either oscillations caused by the control loop or do not have the required bandwidth.

[0006] US2016 / 0 164 517A1 discloses a differential amplifier stage (US2016 / 0 164 517A1 Figure 6The differential amplifier stage of US2016 / 0 164 517A1 includes a negative input terminal (reference numeral Vinn of US2016 / 0 164 517A1), a positive input terminal (reference numeral Vinp of US2016 / 0 164 517A1), a first transistor (reference numeral Q2 of US2016 / 0 164 517A1), a second transistor (reference numeral Q1 of US2016 / 0 164 517A1), a third transistor (reference numeral Q3 of US2016 / 0164 517A1), a first current source (reference numeral 602 of US2016 / 0 164 517A1), a zero current source (reference numeral I of US2016 / 0 164 517A1), a first node (US2016 / 0 164 517A1), a second node (a node between the source of the third transistor (reference numeral Q3 of US2016 / 0164 517A1) and the drain of the second transistor (reference numeral Q1 of US2016 / 0 164 517A1)), and a seventh node (a feeding point of the current source I of US2016 / 0 164 517A1). The first transistor (reference numeral Q2 of US2016 / 0 164 517A1) has a first terminal, a second terminal, and a control terminal. The second transistor (reference numeral Q1 of US2016 / 016517A1) has a first terminal, a second terminal, and a control terminal. The third transistor (reference numeral Q3 of US 2016 / 016517A1) has a first terminal, a second terminal, and a control terminal. The zeroth current source (reference numeral I of US2016 / 0164517A1) draws the zeroth current from the seventh node (feeding point of the current source I of US2016 / 0164517A1). The first terminal of the first transistor (reference numeral Q2 of US2016 / 0164517A1) is connected to the seventh node (feeding point of the current source I of US2016 / 0164517A1). The first terminal of the second transistor (reference numeral Q1 of US2016 / 0164517A1) is connected to the seventh node (feeding point of the current source I of US2016 / 0164517A1). The control terminal of the first transistor (reference numeral Q2 of US2016 / 0164517A1) is connected to the negative input terminal (reference numeral Vinn of US2016 / 0164517A1). The control terminal of the second transistor (reference symbol Q1 of US2016 / 0164517A1) is connected to the positive input terminal (reference symbol Vinp of US2016 / 0164517A1). The second terminal of the first transistor (reference symbol Q2 of US2016 / 0164517A1) is connected to the first node (reference symbol Vout of US2016 / 0164517A1).The second terminal of the second transistor (reference numeral Q2 of US2016 / 0 164 517A1) is connected to the second node (a node between the source of the third transistor (reference numeral Q3 of US2016 / 0 164 517A1) and the drain of the second transistor (reference numeral Q1 of US2016 / 0 164 517A1)). The first node (reference numeral Vout of US2016 / 0164 517A1) is connected to the output of the first current source (reference numeral I / 2 of US 2016 / 0 164 517A1). The first current source (reference numeral 602 of US2016 / 0 164517A1) feeds the first current into the first node (K1) (reference numeral Vout of US2016 / 0 164 517A1). The second terminal of the third transistor (reference numeral Q3 of US2016 / 0 164 517A1) is connected to the second node (a node between the source of the third transistor (reference numeral Q3 of US2016 / 0 164 517A1) and the drain of the second transistor (reference numeral Q1 of US2016 / 0 164 517A1)). The first terminal of the third transistor (reference numeral Q3 of US2016 / 0164 517A1) is connected to a reference potential (a voltage supply in the case of US2016 / 0 164 517A). The control terminal of the third transistor (reference numeral Q3 of US2016 / 0 164 517A1) is connected to the first node (reference numeral Vout of US2016 / 0 164 517A1).

[0007] US2016 / 0 164 517A1 in particular Figure 6 A differential amplifier stage implemented by a field effect transistor is disclosed, the source of which is fed with current from a zero current source (reference numeral I of US2016 / 0164517A1). A third transistor (reference numeral Q3 of US2016 / 0164517A1) is located in the drain line of the second transistor (reference numeral Q2 of US2016 / 016517A1). A first current source (reference numeral 602 of US2016 / 0164517A1) is located in the drain line of the first transistor (reference numeral Q2 of US2016 / 0164517A1).

[0008] The disadvantages of this structure are that a) it provides an output voltage but not the required output current as the output signal and b) it does not have the required bandwidth.

[0009] US Pat. No. 6,859,075 B1 discloses a differential amplifier stage which is implemented by field effect transistors and in which a "bleeder resistor" (reference numeral 125 or 126 of US Pat. No. 6,859,075 B1) is provided. Summary of the invention

[0010] The object of the present invention is therefore to provide a solution which requires as few high-voltage transistors as possible and at the same time has a wide bandwidth with a low oscillation tendency. In this case, the output stage of the circuit of the solution should have an integrated current limitation. In this case, the oscillation capability of the control loop for power limitation should be minimized depending on the application.

[0011] This object is achieved by a differential amplifier stage according to the present invention. The differential amplifier stage comprises a negative input terminal, a positive input terminal, a first transistor, a second transistor, a third transistor, a first current source, a first resistor, a zero current source, a first node, a second node and a seventh node. The first transistor has a first terminal, a second terminal and a control terminal. The second transistor has a first terminal, a second terminal and a control terminal. The third transistor has a first terminal, a second terminal and a control terminal. The first resistor has a first terminal and a second terminal. The zero current source feeds a zero current to the seventh node. The first terminal of the first transistor is connected to the seventh node. The first terminal of the second transistor is connected to the seventh node. The control terminal of the first transistor is connected to the negative input terminal. The control terminal of the second transistor is connected to the positive input terminal. The second terminal of the first transistor is connected to the first node. The second terminal of the second transistor is connected to the second node. The first terminal of the first resistor is connected to the first node. The second terminal of the first resistor is connected to the second node. The first node is connected to the output terminal of the first current source. The first current source draws a first current from the first node. The second terminal of the third transistor is connected to the second node. The first terminal of the third transistor is directly or indirectly connected to a reference potential. The control terminal of the third transistor is connected to the first node. The second node feeds the output signal of the differential amplifier stage.

[0012] Beneficial Effects

[0013] The present arrangement allows wideband driving of large combinations of inductive and capacitive loads such as used in automotive bus systems.

[0014] The invention is described with the aid of the accompanying drawings. The claims are decisive for the scope of protection sought. In this regard, the drawings only show exemplary embodiments of the invention. It is clear to a person skilled in the art that the circuit symbols shown in the drawings may also be interconnections of a plurality of microelectronic functional elements, with effects substantially equivalent to the corresponding effects of the individual circuit symbols used. These equivalent functional elements as interconnections of a plurality of microelectronic functional elements are expressly included in the scope of protection sought. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 An input stage PA according to the invention is shown.

[0016] Figure 2 A power stage PS according to the invention is shown.

[0017] Figure 3 An output driver according to the invention is shown which consists of an output stage PA and a power stage PS.

[0018] Figure 4 It is shown that according to the present invention, Figure 3 has Figure 1 and Figure 2 The exemplary circuit comprises an input stage PA and a power stage PS forming an output driver.

[0019] Figure 5 An output driver according to the invention is shown, which consists of an input stage PA and a power stage PS. In this case, the fourth transistor T4 as a current source transistor is replaced by the first current source I1.

[0020] Figure 6 A substantially simplified schematic diagram of an input stage PA according to the invention is shown, wherein the reference numerals correspond to the calculations in the appendix.

[0021] Figure 7 An equivalent circuit diagram of the input stage PA according to the present invention is shown, wherein the reference numerals are as follows: Figure 6 The same corresponds to the calculation in the Appendix.

[0022] Figure 8 An exemplary circuit of a power stage PS is shown.

[0023] Fig. 9 An output driver according to the invention is shown which consists of an output stage PA and a power stage PS.

[0024] Fig.10 An output driver according to the invention is shown which consists of an output stage PA and a power stage PS. DETAILED DESCRIPTION

[0025] The circuit according to the present invention is divided into two parts. The first part is an input stage (PA) used as a preamplifier. The second part is a power stage PS for controlling the data bus at the output node Outp. Therefore, the circuit relates to a low-voltage / low-side input differential amplifier (i.e., input stage PA) and a subsequent high-voltage output stage (i.e., power stage PS), wherein the input stage PA has a first voltage power line Vdd5V, and the first voltage power line Vdd5V has a lower operating voltage (e.g., 5V); and the power stage PS has a high-voltage transistor and a second voltage power line Vdd30V, and the second voltage power line Vdd30V has a higher operating voltage (e.g., 30V).

[0026] Input Stage

[0027] The input stage includes a differential stage, and the differential stage includes a first transistor T1 of a first conductivity type and a second transistor T2 of a first conductivity type. Here, for example, the transistor of the first conductivity type is a P-channel transistor. Correspondingly, for example, the transistor of the second conductivity type is an N-channel transistor, wherein the second conductivity type is always different from the first conductivity type. As in a conventional differential stage, the sources of the two differential stage transistors, the first transistor T1 and the second transistor T2, are connected to a common node. Here, the common node is the seventh node K7. The zero current source I0 feeds the zero current i0 to the seventh node K7. The zero current i0 is divided into a first branch current id1 and a second branch current id2. The first branch current id1 flows through the first transistor T1. The second branch current id2 flows through the second transistor T2. The first current i1 of the first current source I1 is presented as a first part of the first branch current id1, and the second part of the first branch current id1 flows through the first resistor R1 and is fed to the second node K2. For this purpose, the drain terminal of the first transistor T1 is connected to the first node K1. The first terminal of the first resistor R1 is connected to the first node K1. The second terminal of the first resistor R1 is connected to the second node K2. The drain terminal of the second transistor T2 is connected to the second node K2. The second branch current id2 is also fed to the second node K2. The third transistor T3 of the second conductivity type dissipates a portion of the current fed to the second node K2 to the reference potential GND. To this end, the drain terminal of the third transistor T3 is connected to the second node K2, and the source terminal is connected to the reference potential GND. The first current source I1 feeds the first current i1 from the first current source I1 to the first node K1. The control input terminal (gate) of the third transistor T3 is connected to the first node K1. Therefore, the gate-source voltage of the third transistor T3 directly depends on the differential internal resistance of the first current source I1. Now, the larger gain finally obtained is fed back through the link composed of the differential stage T1, T2 and the first resistor R1, thereby converting the larger gain into a wider bandwidth of the input stage PA.

[0028] If the third transistor T3 as current source is connected to a MOS diode instead of the first current source I1 as known in the prior art, this will become a conventional input stage. However, in the above form, with the first current source I1 replacing the ordinary MOS diode, there are two consecutive inverter stages. A larger gain of the input stage PA would be disadvantageous because it would reduce the phase margin of the entire system, thus leading to oscillations. Here, a jumper resistor in the form of a first resistor R1 is used to reduce the gain to a value that usually results in a standard differential input stage. According to this purpose, the input stage PA should have a wide bandwidth.

[0029] For example, the first current source I1 may be composed of a fifth transistor T5 of the second conductivity type and a fourth transistor T4 of the second conductivity type. Here, the fifth transistor T5 may be connected as a MOS diode so as to be connected to the reference resistor R ref The first reference current i is generated according to the first power supply voltage Vdd5V usually used in the integrated circuit. ref1 , and then the first reference current is converted into a first current i1 of the first current source I1 through an exemplary current mirror structure composed of a fifth transistor T5 and a fourth transistor T4.

[0030] Therefore, the current mirror is composed of the fourth transistor T4 and the fifth transistor T5. The current mirrors T4 and T5 forming the first current source I1 have large parasitic capacitances, thereby limiting the bandwidth. The first node K1 is capacitively charged by the parasitic capacitance of the first current source, and thus its transient change of potential relative to the reference potential GND is relatively slow. However, the second node K2 benefits from the function of the differential stage composed of the first transistor T1 and the second transistor T2. The second node K2 is not capacitively charged by the parasitic capacitance of the first current source I1, and thus its transient change of potential relative to the reference potential GND is faster. The resulting wider bandwidth is exactly the purpose of the input stage PA.

[0031] The output signal of the input stage PA is the current signal at the second node K2. By using the input stage, for example, in a conventional CMOS circuit, the bandwidth is improved by a factor of about 1.8. The input stage PA is a low voltage amplifier coupled only on the low side.

[0032] Power Level PS

[0033] Figure 8 , Fig. 9 and Fig.10 An exemplary circuit of a power stage PS is shown. Figure 2 , Figure 4 and Figure 5 A highly simplified circuit of the power stage PS is shown.

[0034] Just because the transistors shown can be replaced by other microelectronic components with equivalent functions, the high degree of simplification is clear to the person skilled in the art. These relationships are generally known to the person skilled in the art from the teachings of circuit technology. The simplifications mentioned here are briefly explained below.

[0035] Figure 2 , Figure 4 and Figure 5 A seventh transistor T7 , a fourteenth transistor T14 , a fifteenth transistor T15 , and a sixteenth transistor T16 are shown. Figure 8 , Fig. 9 and Fig.10 A seventeenth transistor T17 , an eighteenth transistor T18 , a nineteenth transistor T19 , a twentieth transistor T20 , a twenty-first transistor T21 , a twenty-second transistor T22 , a twenty-third transistor T23 , and a twenty-fourth transistor T24 are shown.

[0036] The fourteenth transistor T14 represents the interconnection of the eighteenth transistor T18 and the twenty-second transistor T22.

[0037] Here, the eighteenth transistor T18 is necessary for the correct adjustment of the operating point of the twenty-second transistor T22, because without the eighteenth transistor, the twenty-second transistor T22 cannot be properly turned on. However, this is clear to those skilled in the art, so in Figure 2 Only the fourteenth transistor T14 is shown in simplified form.

[0038] The other above-mentioned simplifications are similarly justified.

[0039] The fifteenth transistor T15 represents an interconnection of the seventeenth transistor T17 and the twenty-first transistor T21.

[0040] The sixteenth transistor T16 represents the interconnection of the nineteenth transistor T19 and the twenty-third transistor T23.

[0041] The seventh transistor T7 represents the interconnection of the twentieth transistor T20 and the twenty-fourth transistor T24.

[0042] In the following, for ease of reading, Figure 2 Figure 4 and Figure 5 For illustration purposes, a simplified diagram is used.

[0043] When discussing the power stage PS, it should be considered that the thirteenth transistor T13, the ninth transistor T9 and the sixth transistor T6 have a power limiting function.

[0044] The eighth transistor T8 represents the low side part of the AB output stage. The twelfth transistor T12 represents the high side part of the AB output stage.

[0045] The current flowing through the twelfth transistor T12 is limited by the ninth transistor T9. The current flowing through the eighth transistor T8 is limited by the thirteenth transistor T13.

[0046] According to the prior art, a symmetrical input stage must be provided on the high side of the power stage PS instead of the input stage PA proposed here, which feeds the third node K3 in a complementary manner to the fourth node K4 .

[0047] The disadvantage of this case is that the input amplifier must operate at a relatively high voltage (here, for example, 30V) of the second voltage supply line of the power stage, rather than at a lower internal operating voltage (here, for example, 5V) of the first voltage supply line (Vdd5V) of the proposed integrated circuit. This will require more voltage-resistant transistors in the preprocessing of the input stage PA, resulting in a larger chip area. In addition, such transistors will lead to a large number of restrictions on the frequency characteristics of the input stage PA due to the increased parasitic capacitance.

[0048] When using the technical teaching according to the invention, the use of these high-voltage transistors can be omitted. At the second node K2, the current feeding of the current output signal of the input stage PA takes place via the input differential amplifier only on the low side of the power stage PS.

[0049] As described above, the ninth transistor T9 limits the current flowing through the twelfth transistor T12. Here, this current is determined by the fifth current source I5, which draws the fifth current i5 from the fifteenth transistor T15 connected as a MOS diode and feeds the fifth current i5 to the sixteenth transistor T16 also connected as a MOS diode.

[0050] The thus dropped reference voltage across the sixteenth transistor T16 connected as a MOS diode subsequently regulates the current flowing through the ninth transistor T9 and thereby the current flowing through the twelfth transistor T12.

[0051] The reference voltage dropped due to the fifth current i5 across the fifteenth transistor T15 connected as a MOS diode subsequently regulates the current flowing through the thirteenth transistor T13 and thereby regulates the current flowing through the ninth transistor T9.

[0052] The ninth transistor T9 ensures isolation between the low voltage region with the low operating voltage Vdd5V and the high voltage region with the high operating voltage Vdd30V. The input stage PA pulls up the gate of the tenth transistor T10, and the sixth transistor T6 limits the maximum voltage of the fourth node K4 relative to the reference potential GND. The fourth node K4 is connected to the gate of the tenth transistor T10. Here, the gate potential of the sixth transistor T6 is adjusted so that the limit voltage value on the fourth node K4 corresponds to the desired current limit, because the sixteenth transistor T16 and the sixth transistor T6 form a current mirror.

[0053] The structure proposed here that the input stage PA and the sixth transistor T6 are formed together on one side is equivalent to the structure that the fourth current source I4 and the twelfth transistor T12 and the ninth transistor T9 are formed together on the other side and connected in parallel. In a broad sense, the zeroth current source corresponds to the fourth current source I4, the twelfth transistor T12 corresponds to the second transistor T2, and the ninth transistor T9 corresponds to the sixth transistor T6. Both structures achieve the desired current limitation.

[0054] The transistor pair consisting of the thirteenth transistor T13 and the eleventh transistor T11 is functionally equivalent to the aforementioned transistor pair consisting of the sixth transistor T6 and the tenth transistor T10 .

[0055] In the figure, all output stage transistors T6 to T16 of the power stage PS are preferably high voltage transistors, while all transistors T1 , T2 , T3 , T4 , T5 of the input stage PA are preferably low voltage transistors.

[0056] Thus, the ninth transistor T9 limits the current of the tenth transistor T10. Similarly, the thirteenth transistor T13 limits the current of the eleventh transistor T11.

[0057] Features of the invention

[0058] Firstly, the invention is characterized by a differential amplifier stage PA, in particular a broadband one, with a current output terminal, the output current i PADepends on the potential difference between the positive input terminal INP and the negative input terminal INN. Thus, the differential amplifier stage PA according to the present invention includes a negative input terminal INN and a positive input terminal INP. In addition, the differential amplifier stage PA also includes a first transistor T1, a second transistor T2 and a third transistor T3. The differential amplifier stage PA has a first current source I1 as a load resistor in a branch opposite to the second node K2 as an output node, and therefore has a larger differential load resistor that maximizes the gain. In addition, the differential amplifier stage PA also has a first resistor R1, which is used to perform voltage negative feedback using the potential of the output contact K2. Like a conventional differential stage, the proposed differential stage has a zero current source I0 as a common current source for two branches. The differential stage has a first node K1, a second node K2 and a seventh node K7. The first transistor T1 has a first terminal, a second terminal and a control terminal. The second transistor T2 has a first terminal, a second terminal and a control terminal. The third transistor T3 has a first terminal, a second terminal and a control terminal. The first resistor R1 has a first terminal and a second terminal. The zero current source I0 feeds the zero current i0 to the seventh node K7, and the zero current is shunted between the two branches of the differential stage by the first transistor T1 and the second transistor T2. The first terminal of the first transistor T1 is connected to the seventh node K7. The first terminal of the second transistor T2 is connected to the seventh node K7. The control terminal of the first transistor T1 is connected to the negative input terminal INN. The control terminal of the second transistor T2 is connected to the positive input terminal INP. The second terminal of the first transistor T1 is connected to the first node K1. The second terminal of the second transistor T2 is connected to the second node K2. The first terminal of the first resistor R1 is connected to the first node K1. The second terminal of the first resistor R1 is connected to the second node K2. The first contact K1 is connected to the output end of the first current source I1. The first current source I1 obtains the first current i1 from the first node K1. The second terminal of the third transistor T3 is connected to the second node K2. The first terminal of the third transistor T3 is directly or indirectly connected to the reference potential GND. The control terminal of the third transistor T3 is connected to the first node K1. The second node K2 feeds the output signal of the differential amplifier stage PA.

[0059] In addition, the present invention is characterized in that the power stage PS. For the circuit contacts, the power stage includes a second node K2 (as an input node), a third node K3, a fourth node K4, a fifth node K5, a sixth node K6, an eighth node K8, a ninth node K9, a tenth node K10 and an eleventh node K11. Typically, for the current source, the power stage PS includes a second current source I2 and a fourth current source I4. The output end of the power stage PS forms an output node Outp. In addition, for the transistor, the power stage includes a sixth transistor T6, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13. Power is supplied from the second voltage power supply line Vdd30V by means of a reference potential line GND. Internally, the power stage has a first dual reference voltage source. Preferably, the first dual reference voltage source has a fifteenth transistor T15, a sixteenth transistor T16 and a fifth current source I5. Preferably, the fifth current source I5 is connected in series between the fifteenth transistor T15 and the sixteenth transistor T16. Preferably, the fifteenth transistor T15 is connected to form a MOS diode. Preferably, the sixteenth transistor T16 is also connected to form a MOS diode. Preferably, the fifteenth transistor T15 and the fifth current source I5 are connected to each other through the sixth node K6. Preferably, the sixteenth transistor T16 and the fifth current source I5 are connected to each other through the fifth node K5. Preferably, the first terminal of the fifteenth transistor T15 is connected to the second voltage supply line Vdd30V. Preferably, the first terminal of the sixteenth transistor T16 is connected to the reference potential line GND. Preferably, the power stage includes a second dual reference voltage source. In addition, preferably, the second dual reference voltage source includes a fourteenth transistor T14, a seventh transistor T7 and a third current source I3. Preferably, the third current source I3 is connected in series between the fourteenth transistor T14 and the seventh transistor T7. Preferably, the fourteenth transistor T14 is connected to form a MOS diode. Preferably, the seventh transistor T7 is also connected to form a MOS diode. Preferably, the fourteenth transistor T14 and the third current source I3 are connected to each other through the eighth node K8. Preferably, the seventh transistor T7 and the third current source I3 are connected to each other through the ninth node K9. The first terminal of the fourteenth transistor T14 is connected to the second voltage power supply line Vdd30V. The first terminal of the seventh transistor T7 is connected to the reference potential GND. The sixth transistor T6 has a first terminal, a control terminal and a second terminal. The eighth transistor T8 has a first terminal, a control terminal and a second terminal. The ninth transistor T9 has a first terminal, a control terminal and a second terminal. The tenth transistor T10 has a first terminal, a control terminal and a second terminal. The eleventh transistor T11 has a first terminal, a control terminal and a second terminal. The twelfth transistor T12 has a first terminal, a control terminal and a second terminal. The thirteenth transistor T13 has a first terminal, a control terminal and a second terminal. The second terminal of the sixth transistor T6 is connected to the fourth node K4.The second terminal of the eighth transistor T8 is connected to the fourth node K4. The second terminal of the ninth transistor T9 is connected to the fourth node K4. The first terminal of the sixth transistor T6 is connected to the second input node K2. The first terminal of the eighth transistor T8 is connected to the eleventh node K11. The first terminal of the ninth transistor T9 is connected to the tenth node K10. The control terminal of the sixth transistor T6 is connected to the fifth node K5. The control terminal of the eighth transistor T8 is connected to the eighth node K8. The control terminal of the ninth transistor T9 is connected to the fifth node K5. The second current source I2 draws the second current i2 from the fourth node K4. The control terminal of the tenth transistor T10 is connected to the fourth node K4. The first terminal of the tenth transistor T10 is directly or indirectly connected to the reference potential GND. The second terminal of the tenth transistor T10 is connected to the output node Outp. The second terminal of the eleventh transistor T11 is connected to the output node Outp. The first terminal of the eleventh transistor T11 is directly or indirectly connected to the second voltage supply line Vdd30V. The control terminal of the eleventh transistor T11 is connected to the third node K3. The fourth current source I4 feeds the third current i4 to the third node K3. The first terminal of the twelfth transistor T12 is connected to the third node K3. The second terminal of the twelfth transistor T12 is connected to the tenth node K10. The control terminal of the twelfth transistor T12 is connected to the ninth node K9. The first terminal of the thirteenth transistor T13 is connected to the third node K3. The second terminal of the thirteenth transistor T13 is connected to the eleventh node K11. The control terminal of the thirteenth transistor T13 is connected to the sixth node K6.

[0060] Therefore, the first dual reference voltage source sets the sixth node K6 to a reference potential compared to the potential of the second voltage supply line Vdd30V, and sets the fifth node K5 to a reference potential compared to the reference potential GND. Therefore, the second dual reference voltage source sets the ninth node K9 to a reference potential compared to the potential of the second voltage supply line Vdd30V, and sets the eighth node K8 to a reference potential compared to the reference potential GND.

[0061] In general, the present specification describes an output driver for a data line according to the present invention, the output driver having a positive input terminal INP, a negative input terminal INN, an output node Outp, a second node K2, an input stage PA and a power stage PS. Here, the input stage PA feeds an output current iPA of the input stage PA to the second node K2, wherein the output current iPA of the input stage PA fed to the second node K2 PA The power stage PS generates a potential at the output connection Outp with a voltage relative to the reference potential GND, which potential depends on the current i of the input stage PA fed into the second node K2.PA Preferably, the input stage PA is arranged as described above. Also preferably, the power stage PS is arranged as described above.

[0062] In the aforementioned output driver for data lines, the input stage PA is usually powered by the first voltage supply line Vdd5V and the reference potential GND, and the power stage PS is usually powered by the second voltage supply line Vdd30V and the reference potential GND. Here, preferably, when used as intended in at least one operating voltage configuration, the voltage difference between the potential of the first voltage supply line Vdd5V and the reference potential GND is at least 3 times smaller than the potential difference between the second voltage supply line Vdd30V and the reference potential GND.

[0063] Evaluation of frequency characteristics of input stage

[0064] 0.1.1 Considerations of the Quasi-Static Basic Circuit of the Input Amplifier

[0065] With the help of Figure 6 and Figure 7 Evaluation is performed. It starts with the basic circuit of the device according to the invention. Figure 6 The basic circuit is shown again. For clarity, the indexes are subscripted here to achieve better transparency in the formulas. Figure 7 The small signal equivalent circuit diagram is shown. First, the current equation is established:

[0066]

[0067] g4 is ignored here because the current source I q1 should be constant and therefore have no small signal components.

[0068] The node equation is:

[0069] i1-i x -i4=0 (6)

[0070] i1-i2=0 (7)

[0071] i2-i3+i x =0 (8)

[0072] We substitute the current equation into the node equation and obtain:

[0073]

[0074] First, we solve Equation 10 for v T :

[0075]

[0076] This is equivalent to:

[0077]

[0078] Substituting in:

[0079]

[0080] We assume that g1=g2:

[0081]

[0082] Solving it gives:

[0083]

[0084] Substituting in:

[0085]

[0086] This yields:

[0087]

[0088] For the output voltage, we obtain:

[0089]

[0090] This is equivalent to:

[0091]

[0092] If r1 is chosen to be a low enough resistance, then the equation simplifies to:

[0093] v i ·g1·r1=v out (twenty three)

[0094] 0.1.2 Discussion of parasitic gate capacitance

[0095] Now let's discuss parasitic gate capacitance.

[0096] The first transistor T1

[0097] from Figure 6 and Figure 7 It can be easily seen that if control by an ideal voltage source is assumed, the parasitic gate-source capacitance of the first transistor T1 can be neglected. The parasitic source-drain capacitance of the first transistor T1 can be reflected in the conductance value s1. The parasitic gate-drain capacitance can be overwritten as the dominant gate-source-Miller capacitance by an ideal external voltage source.

[0098] The second transistor T2

[0099] from Figure 6 and Figure 7 It can be easily seen that if control by an ideal voltage source is assumed, the parasitic gate-source capacitance of the second transistor T2 can be neglected. The parasitic source-drain capacitance of the second transistor T2 can be reflected in the conductance value s2. The parasitic gate-drain capacitance can be overwritten as the dominant gate-source-Miller capacitance by an ideal external voltage source.

[0100] The third transistor T3

[0101] from Figure 6 and Figure 7 It can be easily seen that the parasitic gate-source capacitance of the third transistor T3 can be integrated in the complex conductance s4. The parasitic source-drain capacitance of the third transistor T3 can be reflected in the conductance value s3. The parasitic gate-drain capacitance can be integrated again as a large gate-source-Miller capacitance in the jumper resistor r1 by a parallel connection.

[0102] Current Source I q1

[0103] from Figure 6 and Figure 7 It can be easily seen that the parasitic capacitance of the current source Iq1 is integrated in the complex conductance s4.

[0104] 0.1.3 Evaluation

[0105] Therefore, all capacitive parasitic elements can be integrated into the corresponding conductances (s1; s2; s3; s4) without changing the previous results. This means that all resistances r1 remain in equation 23. However, the differential resistance r1 is the gate-drain capacitance C of the third transistor T3. gd3 The parallel connection structure with the actual differential jumper resistor. Therefore, replace the variable r1 in Formula 23 with this parallel connection structure:

[0106]

[0107] This is equivalent to:

[0108]

[0109] The cut-off frequency ω is obtained from g :

[0110]

[0111] This shows that a large cutoff frequency ω can be generated by using a small r1. g If the gain is chosen to be 1, this is equivalent to:

[0112]

[0113] It is then seen that for very small r1, it makes sense to make the mutual conductance g1 of the first transistor T1 and the differential cross-resistance r1 have the same value. This corresponds to Since the mutual conductance g1 of the first transistor T1 is preferably very large, a very low cross-resistance r1 results when this condition is met, resulting in a very strong negative feedback. Therefore, as long as the negative feedback via the cross-resistance R1 is strong enough, the input stage performs a current-to-voltage conversion with a cut-off frequency that is independent of the current drawn at the output of the input stage. Thus, it is ensured that the voltage-to-current conversion has no phase error, and thereby reduces the oscillation tendency of the target circuit, of which the device in question is a component.

[0114] Reference numerals list

[0115] K1 first node;

[0116] K2 second node;

[0117] K3 third node;

[0118] K4 fourth node;

[0119] K5 fifth node;

[0120] K6 sixth node;

[0121] K7 seventh node;

[0122] K8 eighth node;

[0123] K9 ninth node;

[0124] K10 tenth node;

[0125] K11 eleventh node;

[0126] K12 12th node;

[0127] K13 13th node;

[0128] K14 14th node;

[0129] K15 15th node;

[0130] GND reference potential;

[0131] I0 zero current source;

[0132] i0 the zeroth current of the zeroth current source I0;

[0133] I1 first current source;

[0134] i1 first current;

[0135] I2 second current source;

[0136] i2 second current;

[0137] I3 third current source;

[0138] i3 third current;

[0139] I4 fourth current source;

[0140] i4 fourth current;

[0141] I5 fifth current source;

[0142] i5 fifth current;

[0143] id1 first branch current;

[0144] id2 second branch current;

[0145] ik2 is the current flowing into the second node;

[0146] i PA The output current i of the input stage PA PA , which is the input current of the power stage PS;

[0147] i ref1 a first reference current;

[0148] INN negative input terminal INN of INN input stage PA;

[0149] INP positive input terminal INP of the input stage PA;

[0150] Outp output node;

[0151] PA input stage, here the differential amplifier stage;

[0152] PS power level;

[0153] R1 first resistor;

[0154] R ref Reference resistor;

[0155] T1 first transistor;

[0156] T2 second transistor;

[0157] T3 the third transistor;

[0158] T4 fourth transistor;

[0159] T5 fifth transistor;

[0160] T6 sixth transistor, which is a high voltage transistor;

[0161] T7 is a seventh transistor, which is a high voltage transistor;

[0162] T8 is an eighth transistor, which is a high voltage transistor;

[0163] T9 is a ninth transistor, which is a high voltage transistor;

[0164] T10 is a tenth transistor, which is a high voltage transistor;

[0165] T11 is an eleventh transistor, which is a high voltage transistor;

[0166] T12 is a twelfth transistor, which is a high voltage transistor;

[0167] T13 is a thirteenth transistor, which is a high voltage transistor;

[0168] T14 is a fourteenth transistor, which is a high voltage transistor;

[0169] T15 is a fifteenth transistor, which is a high voltage transistor;

[0170] T16 is a sixteenth transistor, which is a high voltage transistor;

[0171] T17 is a seventeenth transistor, which is a high voltage transistor;

[0172] T18 is an eighteenth transistor, which is a high voltage transistor;

[0173] T19 is a nineteenth transistor, which is a high voltage transistor;

[0174] T20 is a twentieth transistor, which is a high voltage transistor;

[0175] T21 is a twenty-first transistor, which is a high-voltage transistor;

[0176] T22 is a 22nd transistor, which is a high voltage transistor;

[0177] T23 is a twenty-third transistor, which is a high-voltage transistor;

[0178] T24 is a twenty-fourth transistor, which is a high-voltage transistor;

[0179] Vdd5V has a first voltage supply line Vdd5V with a lower operating voltage, for example, 5V;

[0180] Vdd30V is a second voltage power supply line Vdd30V having a higher operating voltage of, for example, 30V.

Claims

1. A power stage (PS), comprising: The second node (K2) as an input node; The third node (K3); The fourth node (K4); The fifth node (K5); The sixth node (K6); Node 8 (K8); Node 9 (K9); The tenth node (K10); 11th node (K11); 12th node (K12); 13th node (K13); Node 14 (K14); 15th node (K15); a second current source (I2); a fourth current source (I4); Output node (Outp); a sixth transistor (T6); an eighth transistor (T8); a ninth transistor (T9); a tenth transistor (T10); an eleventh transistor (T11); a twelfth transistor (T12); a thirteenth transistor (T13); Second voltage power line (Vdd 30V); Reference potential (GND); The first dual reference voltage source, wherein the first dual reference voltage source has a seventeenth transistor (T17), wherein the first dual reference voltage source has a twenty-first transistor (T21), wherein the first dual reference voltage source has a nineteenth transistor (T19), wherein the first dual reference voltage source has a twenty-third transistor (T23), wherein the first dual reference voltage source has a fifth current source (I5), The fifth current source (I5) is connected in series between the twenty-first transistor (T21) and the twenty-third transistor (T23), The seventeenth transistor (T17) is connected as a MOS diode. wherein the twenty-first transistor (T21) is connected as a MOS diode, wherein the nineteenth transistor (T19) is connected as a MOS diode, wherein the twenty-third transistor (T23) is connected as a MOS diode, wherein the twenty-first transistor (T21) and the fifth current source (I5) are connected to each other via the sixth node (K6), wherein the twenty-third transistor (T23) and the fifth current source (I5) are connected to each other via the fifth node (K5), wherein the first terminal of the seventeenth transistor (T17) is connected to the second voltage power line (Vdd30V), wherein the second terminal of the seventeenth transistor (T17) is connected to the first terminal of the twenty-first transistor (T21) at the twelfth node (K12), wherein the first terminal of the nineteenth transistor (T19) is connected to the reference potential (GND), and wherein the second terminal of the nineteenth transistor (T19) is connected to the second terminal of the twenty-third transistor (T23) at the fourteenth node (K14); and The second dual reference voltage source, The second dual reference voltage source has an eighteenth transistor (T18), The second dual reference voltage source has a twenty-second transistor (T22), The second dual reference voltage source has a twentieth transistor (T20), wherein the second dual reference voltage source has a twenty-fourth transistor (T24), wherein the second dual reference voltage source has a third current source (I3), The third current source (I3) is connected in series between the 22nd transistor (T22) and the 24th transistor (T24), Wherein, the eighteenth transistor (T18) is connected as a MOS diode, wherein the 22nd transistor (T22) is connected as a MOS diode, wherein the 20th transistor (T20) is connected as a MOS diode, wherein the twenty-fourth transistor (T24) is connected as a MOS diode, wherein the twenty-second transistor (T22) and the third current source (I3) are connected to each other via the ninth node (K9), wherein the twenty-fourth transistor (T24) and the third current source (I3) are connected to each other via the eighth node (K8), wherein the first terminal of the eighteenth transistor (T18) is connected to the second voltage power line (Vdd30V), wherein the second terminal of the eighteenth transistor (T18) is connected to the first terminal of the twenty-second transistor (T22) at the thirteenth node (K13), wherein a first terminal of the twentieth transistor (T20) is connected to the reference potential (GND), wherein the second terminal of the twentieth transistor (T20) is connected to the second terminal of the twenty-fourth transistor (T24) at the fifteenth node (K15), wherein the sixth transistor (T6) has a first terminal, a control terminal, and a second terminal, wherein the eighth transistor (T8) has a first terminal, a control terminal, and a second terminal, wherein the ninth transistor (T9) has a first terminal, a control terminal, and a second terminal, wherein the tenth transistor (T10) has a first terminal, a control terminal, and a second terminal, wherein the eleventh transistor (T11) has a first terminal, a control terminal, and a second terminal, wherein the twelfth transistor (T12) has a first terminal, a control terminal, and a second terminal, wherein the thirteenth transistor (T13) has a first terminal, a control terminal, and a second terminal, wherein the second terminal of the sixth transistor (T6) is connected to the fourth node (K4), wherein the second terminal of the eighth transistor (T8) is connected to the the fourth node (K4), wherein the second terminal of the ninth transistor (T9) is connected to the fourth node (K4), wherein the first terminal of the sixth transistor (T6) is connected to the second node (K2), wherein the first terminal of the eighth transistor (T8) is connected to the eleventh node (K11), wherein the first terminal of the ninth transistor (T9) is connected to the tenth node (K10), wherein the control terminal of the sixth transistor (T6) is connected to the fifth node (K5), wherein the control terminal of the eighth transistor (T8) is connected to the eighth node (K8), wherein the control terminal of the ninth transistor (T9) is connected to the fifth node (K5), wherein the second current source (I2) draws a second current (i2) from the fourth node (K4), wherein the control terminal of the tenth transistor (T10) is connected to the fourth node (K4), wherein the first terminal of the tenth transistor (T10) is directly or indirectly connected to the reference potential (GND), wherein the second terminal of the tenth transistor (T10) is connected to the output node (Outp), wherein the second terminal of the eleventh transistor (T11) is connected to the output node (Outp), wherein the first terminal of the eleventh transistor (T11) is directly or indirectly connected to the second voltage power line (Vdd30V), wherein a control terminal of the eleventh transistor (T11) is connected to the third node (K3), wherein the fourth current source (I4) feeds a fourth current (i4) to the third node (K3), wherein a first terminal of the twelfth transistor (T12) is connected to the third node (K3), wherein the second terminal of the twelfth transistor (T12) is connected to the tenth node (K10), wherein the control terminal of the twelfth transistor (T12) is connected to the ninth node (K9), wherein the first terminal of the thirteenth transistor (T13) is connected to the third node (K3), wherein the second terminal of the thirteenth transistor (T13) is connected to the eleventh node (K11), and Wherein, the control terminal of the thirteenth transistor (T13) is connected to the sixth node (K6).

2. A power stage (PS), comprising: The second node (K2) as an input node; The third node (K3); The fourth node (K4); The fifth node (K5); The sixth node (K6); Node 8 (K8); Node 9 (K9); The tenth node (K10); 11th node (K11); a second current source (I2); a fourth current source (I4); Output node (Outp); a sixth transistor (T6); an eighth transistor (T8); a ninth transistor (T9); a tenth transistor (T10); an eleventh transistor (T11); a twelfth transistor (T12); a thirteenth transistor (T13); Second voltage power line (Vdd 30V); Reference potential (GND); The first dual reference voltage source; and The second dual reference voltage source, wherein the first dual reference voltage source sets the sixth node (K6) to a reference potential compared to the potential of the second voltage supply line (Vdd30V), wherein the first dual reference voltage source sets the fifth node (K5) to a reference potential compared to the reference potential (GND), wherein the second dual reference voltage source sets the ninth node (K9) to a reference potential compared to the potential of the second voltage supply line (Vdd30V), wherein the second dual reference voltage source sets the eighth node (K8) to a reference potential compared to the reference potential (GND), The sixth transistor (T6) has a first terminal, a control terminal and a second terminal. The eighth transistor (T8) has a first terminal, a control terminal and a second terminal. The ninth transistor (T9) has a first terminal, a control terminal and a second terminal. The tenth transistor (T10) has a first terminal, a control terminal and a second terminal. The eleventh transistor (T11) has a first terminal, a control terminal and a second terminal. The twelfth transistor (T12) has a first terminal, a control terminal and a second terminal. The thirteenth transistor (T13) has a first terminal, a control terminal and a second terminal. wherein the second terminal of the sixth transistor (T6) is connected to the fourth node (K4), wherein the second terminal of the eighth transistor (T8) is connected to the fourth node (K4), wherein the second terminal of the ninth transistor (T9) is connected to the fourth node (K4), wherein the first terminal of the sixth transistor (T6) is connected to the second node (K2), wherein the first terminal of the eighth transistor (T8) is connected to the eleventh node (K11), wherein the first terminal of the ninth transistor (T9) is connected to the tenth node (K10), wherein the control terminal of the sixth transistor (T6) is connected to the fifth node (K5), wherein the control terminal of the eighth transistor (T8) is connected to the ninth node (K9), wherein the control terminal of the ninth transistor (T9) is connected to the fifth node (K5), The second current source (I2) draws a second current (i2) from the fourth node (K4), wherein the control terminal of the tenth transistor (T10) is connected to the fourth node (K4), wherein the first terminal of the tenth transistor (T10) is directly or indirectly connected to the reference potential (GND), wherein the second terminal of the tenth transistor (T10) is connected to the output node (Outp), wherein the second terminal of the eleventh transistor (T11) is connected to the output node (Outp), wherein the first terminal of the eleventh transistor (T11) is directly or indirectly connected to the second voltage power line (Vdd30V), wherein the control terminal of the eleventh transistor (T11) is connected to the third node (K3), wherein the fourth current source (I4) feeds a fourth current (i4) to the third node (K3), wherein the first terminal of the twelfth transistor (T12) is connected to the third node (K3), wherein the second terminal of the twelfth transistor (T12) is connected to the tenth node (K10), wherein the control terminal of the twelfth transistor (T12) is connected to the eighth node (K8), wherein the first terminal of the thirteenth transistor (T13) is connected to the third node (K3), wherein the second terminal of the thirteenth transistor (T13) is connected to the eleventh node (K11), and Wherein, the control terminal of the thirteenth transistor (T13) is connected to the sixth node (K6).

3. An output driver for a data line, comprising: Positive input terminal (INP); Negative input terminal (INN); Output node (Outp); The second node (K2); Input stage (PA); and Power stage (PS), Wherein, the input stage (PA) converts the output current (i PA ) is fed to the second node (K2), Wherein, the output current (i PA ) depends on the voltage difference between the positive input terminal (INP) and the negative input terminal (INN), and wherein the power stage (PS) generates at the output node (Outp) the output current (i PA )'s potential.

4. The output driver for a data line according to claim 3, in, The power stage (PS) is a power stage according to claim 1 or 2.

5. The output driver for a data line according to claim 3 or 4, in, The input stage (PA) is powered by a first voltage supply line (Vdd5V) and a reference potential (GND), wherein the power stage (PS) is powered by a second voltage power line (Vdd30V) and the reference potential (GND), and The voltage difference between the potential of the first voltage power line (Vdd5V) and the reference potential (GND) is smaller than the voltage difference between the potential of the second voltage power line (Vdd30V) and the reference potential (GND).

6. The output driver for a data line according to claim 3 or 4, in, The input stage (PA) is powered by a first voltage supply line (Vdd5V) and a reference potential (GND), wherein the power stage (PS) is powered by a second voltage power line (Vdd30V) and the reference potential (GND), and Wherein, when used as intended in at least one operating voltage configuration, the potential difference between the potential of the first voltage supply line (Vdd5V) and the reference potential (GND) is at least 3 times smaller than the voltage difference between the potential of the second voltage supply line (Vdd30V) and the reference potential (GND).

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