Normalized block LMS (Least Mean Square) adaptive filter with zero delay characteristic

Abstract

The invention discloses a normalized block LMS adaptive filter with zero delay characteristic, which comprises an input FIFO module, a filtering module, an iteration module, a modulo module and an output FIFO module, and is characterized in that the input FIFO module is used for caching an input signal and an expected signal, the filtering module is used for performing FIR filtering on the input signal, and the iteration module is used for performing iteration on the input signal; the iteration module is used for iteratively calculating a weight coefficient of the FIR filter, the modulo module is used for calculating a square norm modulus value of an input signal vector, the output FIFO module is used for caching an FIR filtering output result, the input FIFO module is connected with the filtering module and the iteration module, the filtering module is connected with the iteration module and the output FIFO module, and the iteration module is connected with the output FIFO module. And the iteration module is connected with the modulo module. By improving the processing clock frequency, the filter has the zero delay characteristic, the convergence speed and stability of the filter are improved, and meanwhile the filter has the advantages of being stable in power consumption and saving logic resources.

Description

Technical Field

[0001] The present invention relates to the technical field of filters, and more specifically, to a normalized block LMS adaptive filter with zero-delay characteristics. Background Art

[0002] In the field of adaptive signal processing, the LMS algorithm has the characteristics of simple structure and easy hardware implementation, and has been widely studied and used. The LMS algorithm is based on the Wiener filtering theory, uses the instantaneous value to estimate the gradient vector, and uses the power criterion of minimizing the error signal to adaptively update the weight coefficients of the filter. The filter coefficient update frequency of the traditional LMS algorithm is the sampling rate of the sample point, but there is a large error between the estimated gradient based on each sample point and the true gradient, so the convergence path will deviate and become unstable, and the tracking stability is poor. The normalized block LMS algorithm updates the filter coefficient once every L sample points. By averaging the errors of the L sample points, the accuracy of the gradient estimation can be improved; by normalizing the input signal by the square norm, the amplification effect of the input signal on the gradient estimation error can be eliminated. Therefore, the normalized block LMS algorithm can improve the convergence speed and make the convergence path stable. The iterative equation of the normalized block LMS algorithm is:

[0003]

[0004] is the weight coefficient of the filter, M*1 column vector, M is the number of taps of the filter, j is the number of iterations, L is the number of samples of each block data, k is the block index number, i is the sample index number, is the input signal vector composed of the internal delay unit of the filter, and the expression is:

[0005]

[0006] e(kL+i) is the filter output error, expressed as:

[0007] e(kL+i)=s(kL+i)-y(kL+i)

[0008] s(kL+i) is the expected output signal of the filter, and y(kL+i) is the actual output signal of the filter. The expression is:

[0009]

[0010] In conventional filter implementation structures, the normalized block LMS algorithm usually uses pipeline processing, and the processing clock is consistent with the sampling rate. The iterative estimation of the filter coefficients involves a large number of multiplication and division operations, which will result in a large processing delay, causing the iteratively updated filter coefficients to not act on the next data block in a timely manner. When the signal has a large time-varying characteristic, the filter becomes unstable and the convergence speed deteriorates. For this reason, it is necessary to develop a normalized block LMS adaptive filter with zero delay characteristics. Summary of the invention

[0011] The object of the present invention is to provide a normalized block LMS adaptive filter with zero delay characteristics to overcome the defects of the prior art.

[0012] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0013] A normalized block LMS adaptive filter with zero delay characteristics comprises an input FIFO module, a filtering module, an iteration module, a modulus module and an output FIFO module, wherein the input FIFO module is used to cache input signals and expected signals, the filtering module is used to perform FIR filtering on the input signal, the iteration module is used to iteratively calculate weight coefficients of the FIR filter, the modulus module is used to calculate the square norm modulus value of the input signal vector, the output FIFO module is used to cache FIR filtering output results, the input FIFO module is connected to the filtering module and the iteration module, the filtering module is connected to the iteration module and the output FIFO module, and the iteration module is connected to the modulus module.

[0014] Furthermore, the input FIFO module is configured to receive the data clock f sig Driven by , the input signal r(kL+i) and the expected signal s(kL+i) are continuously written into the input FIFO, where L is the length of each data block, k is the block index number, and i is the sample point index number. When the input FIFO is full of L samples, the processing clock f s Driven by , L samples are read out in burst mode, and then the input FIFO is filled with L samples again.

[0015] Furthermore, the filtering module includes M filter delay units, M filter multiplication units and filter accumulation units, M is the number of taps of the filter, the filter delay units, filter multiplication units and filter accumulation units are connected in sequence, each filter delay unit delays one sampling point, and the M delayed sampling points constitute the input signal vector L is the length of each data block, k is the block index number, i is the sample point index number, the vector is connected to the iteration module, and the last delayed sample point r (kL + iM) is connected to the modulo module; each filter multiplication unit performs conjugate complex multiplication on the input signal vector and the filter weight coefficient; the filter accumulation unit adds the results of the filter multiplication unit in parallel to obtain the filter output signal y (kL + i), which is connected to the iteration module and the output FIFO module.

[0016] Further, the iteration module includes an expected signal delay unit, an error subtraction unit, an input signal delay unit, M error multiplication units, M error division units, M error accumulation units and M coefficient iteration units, the expected signal delay unit, the error subtraction unit and the error multiplication unit are connected in sequence, and the input signal delay unit, the M error multiplication units, the M error division units, the M error accumulation units and the M coefficient iteration units are connected in sequence;

[0017] The expected signal delay unit is used to perform a number of sample point delay processing on the expected signal s(kL+i) to obtain a delayed expected signal s d (kL+i), so that it keeps synchronization with the filter output signal y(kL+i), L is the length of each data block, k is the block index number, and i is the sample point index number;

[0018] The error subtraction unit is used to delay the expected signal s d (kL+i) is subtracted from the filter output signal y(kL+i) to obtain the filter output error e(kL+i);

[0019] The input signal delay unit is used to delay the input signal vector Perform delay processing on several sample points to obtain the delayed input signal vector Make it synchronized with the filter output error e(kL+i);

[0020] The M error multiplication units are used to multiply the delayed input signal vector Conjugate multiply with the filter output error e(kL+i) to output the gradient vector estimate j is the number of iterations;

[0021] M error division units are used to estimate the gradient vector The square norm modulus of the input signal vector Divide and output the normalized gradient vector estimate

[0022] M error accumulation units are used to estimate the normalized gradient vector Accumulate L sample points, and output the mean vector after the accumulation is completed. The mean vector is the weight update vector

[0023] M coefficient iteration units are used to calculate the weight coefficient vector Update and output the updated weight coefficient vector This vector is connected to the filter module.

[0024] Furthermore, the modulo module comprises a modulo multiplication unit, a modulo subtraction unit, a modulo accumulation unit and a modulo delay unit connected in sequence;

[0025] The two modular multiplication units respectively perform conjugate multiplication on the two input signal scalars r(kL+i) and r(kL+iM), and output the square norm modulus value of the scalar r(kL+i) ||r(kL+i)|| 2 and the squared norm modulus of the scalar r(kL+iM)||r(kL+iM)|| 2 , L is the length of each data block, k is the block index number, and i is the sample point index number;

[0026] The modular subtraction unit is used to subtract the outputs of the two modular multiplication units and output the difference Δ of the square norm modular value. norm2 =||r(kL+i)|| 2 -||r(kL+iM)|| 2 ;

[0027] The modulo accumulation unit is used to norm2 Accumulate and output the square norm modulus value

[0028] The modulus delay unit is used to Perform delay processing on several sample points to obtain the delay square norm modulus value Synchronize it with j is the number of iterations, and the output of the modulo module is connected to the iteration module.

[0029] Furthermore, the modulus module processes the clock f s The square norm of the input signal vector is taken modulo in a burst manner under the drive of , and after the modulo operation is completed, it enters the silent waiting mode. The modulo module adopts the recursive calculation formula as follows:

[0030]

[0031] Where L is the length of each data block, k is the block index number, i is the sample point index number, and M is the number of filter taps.

[0032] Furthermore, the output FIFO module processes the clock fs Driven by the filter output y(kL+i), the filter output result y(kL+i) is written into the output FIFO in burst mode. When the FIFO is full of L samples, the data clock f sig Driven by, each filtering result is output continuously.

[0033] Compared with the prior art, the advantages of the present invention are: the present invention improves the processing clock frequency, performs block-by-block pipeline processing on the data, completes filtering and weight coefficient update within each L sample point time period, and ensures that the updated weight coefficient can act on the next data block in time. Assuming the sample point rate is f sig , the high-speed processing clock frequency is f s , the data time length of L sample points corresponds to L fs =f s / f sig *L high-speed processing clock cycles, as long as the filter can fs The data filtering and weight update operations are completed within a cycle. When the next block of data arrives, the updated coefficients can be used for data filtering, which makes the filter have zero delay characteristics at the signal level, further improving the convergence speed and stability of the algorithm. In the structural design of the filter, each module enters a silent waiting state immediately after completing the operation in a burst manner. Therefore, the increase in the processing clock frequency does not increase the power consumption of the filter. At the same time, the structure of sharing data between modules also enables the filter to save logic resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 It is a principle diagram of a normalized block LMS adaptive filter with zero delay characteristics of the present invention. DETAILED DESCRIPTION

[0036] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0037] In this embodiment, assuming that the sampling rate is 100 MHz, the processing clock frequency is 200 MHz, the processing clock period Ts is 5 ns, the number of samples L of each block of data is 128, and the number of taps M of the filter is 12, then 128 data samples correspond to 256 Ts, and the filtering module requires 128 Ts to filter the data. The remaining 128 Ts are used for iterative updating of coefficients. If the filter can complete the coefficient update within 128 Ts, the filter will have the characteristic of zero delay.

[0038] See also Figure 1 As shown, this embodiment discloses a normalized block LMS adaptive filter with zero delay characteristics, including an input FIFO module 1, a filtering module 2, an iteration module 3, a modulo module 4 and an output FIFO module 5, wherein the input FIFO module 1 is used to cache input signals and expected signals, the filtering module 2 is used to perform FIR filtering on the input signal, the iteration module 3 is used to iteratively calculate the weight coefficients of the FIR filter, the modulo module 4 is used to calculate the square norm modulus value of the input signal vector, and the output FIFO module 5 is used to cache the FIR filtering output result. The input FIFO module 1 is connected to the filtering module 2 and the iteration module 3, the filtering module 2 is connected to the iteration module 3 and the output FIFO module 5, and the iteration module 3 is connected to the modulo module 4.

[0039] In this embodiment, the input FIFO module 1 is at the data clock f sig Driven by, the input signal r(kL+i) and the expected signal s(kL+i) are continuously written into the input FIFO. When the input FIFO is full of 128 samples, the processing clock f s Driven by , L128 samples are read out in a burst manner (when FIFO is full of L samples, L samples are read out in a burst manner. Since the write clock data is slow and the read clock is fast, it is called "burst-wise"), and then wait for the input FIFO to be full of 128 samples again, and then cycle in sequence, where L is the length of each data block, k is the block index number, and i is the sample index number.

[0040] In this embodiment, the filter module 2 processes the clock f at a high speed. s The filter module 2 includes 12 filter delay units 21, 12 filter multiplication units 22 and 1 filter accumulation unit 23, and the filter delay unit 21, the filter multiplication unit 22 and the filter accumulation unit 23 are connected in sequence.

[0041] Each filter delay unit 21 delays 1Ts, and 12 delayed sample points constitute the input signal vector L is the length of each data block, k is the block index number, i is the sample point index number, the vector is connected to the iteration module 3, and the last delayed sample point r (kL + iM) is connected to the modulo module 4; each filter multiplication unit 22 performs conjugate complex multiplication on the input signal vector and the filter weight coefficient, and the processing delay is 5Ts; the filter accumulation unit 23 adds the results of the filter multiplication unit in parallel (using a parallel addition tree structure, with a processing delay of 8Ts) to obtain the filter output signal y (kL + i), which is connected to the iteration module 3 and the output FIFO module 5.

[0042] In this embodiment, the iteration module 3 processes the clock f at a high speed. s The weight coefficient is iteratively updated in a burst manner under the drive of , and enters a silent waiting mode after the iteration is completed, including 1 expected signal delay unit 31, delay 13Ts, 1 error subtraction unit 32, processing delay 2Ts, 1 input signal delay unit 33, delay 13Ts, 12 error multiplication units 34, processing delay 5Ts, 12 error division units 35, processing delay 55Ts, 12 error accumulation units 36 processing delay 4Ts; 12 coefficient iteration units 37, processing delay 3Ts, the expected signal delay unit 31, the error subtraction unit 32 and the error multiplication unit 34 are connected in sequence, and the input signal delay unit 33, M error multiplication units 34, M error division units 35, M error accumulation units 36 and M coefficient iteration units 37 are connected in sequence;

[0043] The expected signal delay unit 31 is used to perform a number of sample point delay processing on the expected signal s(kL+i) to obtain a delayed expected signal s d (kL+i), so that it is synchronized with the filter output signal y(kL+i); the error subtraction unit 32 is used to delay the expected signal s d (kL+i) is subtracted from y(kL+i) to obtain the filter output error e(kL+i); the input signal delay unit 33 is used to delay the input signal vector Perform delay processing on several sample points and obtain to synchronize it with e(kL+i); the 12 error multiplication units are used to delay the input signal vector Conjugate multiply with the filter output error e(kL+i) to output the gradient vector estimate j is the number of iterations; 12 error division units are used to The square norm modulus of the input signal vector Divide and output the normalized gradient vector estimate 12 error accumulation units are used to Accumulate L sample points, and output the mean vector after the accumulation is completed. The mean vector is the weight update vector 12 coefficient iteration units are used to adjust the weight coefficient vector Update and output the updated weight coefficient vector This vector is connected to the filtering module 2.

[0044] In this embodiment, the modulo module 4 processes the clock f s The square norm of the input signal vector is taken modulo in a burst manner under the drive of , and after the modulo operation is completed, it enters the silent waiting mode. The modulo module 4 adopts the recursive calculation formula as follows:

[0045]

[0046] The modulo module 4 includes a processing delay of 5Ts, a modulo subtraction unit 42, a processing delay of 2Ts, a modulo accumulation unit 43, a processing delay of 3Ts, and a modulo delay unit 45, with a delay of 10Ts.

[0047] The two modular multiplication units 41 perform conjugate multiplication on the two input signal scalars r(kL+i) and r(kL+iM) respectively, and output the square norm modulus value of the scalar r(kL+i) ||r(kL+i)|| 2 and the squared norm modulus of the scalar r(kL+iM)||r(kL+iM)|| 2 The modulus subtraction unit 42 is used to subtract the outputs of the two modulus multiplication units and output the difference Δ of the square norm modulus value. norm2 =||r(kL+i)|| 2 -||r(kL+iM)|| 2 ; The modulus accumulation unit 43 is used to calculate the difference Δ of the square norm modulus value norm2 Accumulate and output the square norm modulus value The modulus delay unit 44 is used to obtain the modulus value of the square norm of the delay Perform delay processing on several sample points to obtain Synchronize it with j is the number of iterations, and the output of the modulo module 4 is connected to the iteration module 3.

[0048] In this embodiment, the output FIFO module 5 processes the clock f s Driven by the filter output, the filter output result is written to the output FIFO in burst mode. When the FIFO is full of 128 samples, the data clock f sig Driven by, each filtering result is output continuously.

[0049] The total processing delay of filter module 2 and iteration module 3 is 128Ts+82Ts=210Ts, so the filtering and coefficient iterative update operations can be completed within 256 Ts. The filter will have a zero-delay characteristic at the signal level, which will improve the convergence speed and stability of the filter. After the filter module 2, iteration module 3 and modulus module 4 complete the operation in a burst, they immediately enter the silent waiting state, so the increase in the processing clock frequency will not increase the power consumption of the filter. At the same time, the modulus module adopts an efficient recursive structure, and the structure of sharing data between modules also enables the filter to save logic resources.

[0050] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, the patent owner may make various variations or modifications within the scope of the appended claims. As long as they do not exceed the protection scope described in the claims of the present invention, they should be within the protection scope of the present invention.

Claims

1. A normalized block LMS adaptive filter with zero delay characteristics, characterized in that: The invention comprises an input FIFO module, a filtering module, an iteration module, a modulo module and an output FIFO module. The input FIFO module is used to cache input signals and expected signals. The filtering module is used to perform FIR filtering on the input signal. The iteration module is used to iteratively calculate the weight coefficients of the FIR filter. The modulo module is used to calculate the square norm modulus value of the input signal vector. The output FIFO module is used to cache the FIR filtering output result. The input FIFO module is connected with the filtering module and the iteration module. The filtering module is connected with the iteration module and the output FIFO module. The iteration module is connected with the modulo module.

2. The normalized block LMS adaptive filter with zero delay characteristics according to claim 1, characterized in that: The input FIFO module is clocked at the data clock f sig Driven by , the input signal r(kL+i) and the expected signal s(kL+i) are continuously written into the input FIFO, where L is the length of each data block, k is the block index number, and i is the sample point index number. When the input FIFO is full of L samples, the processing clock f s Driven by , L samples are read out in burst mode, and then the input FIFO is filled with L samples again.

3. The normalized block LMS adaptive filter with zero delay characteristics according to claim 1, characterized in that: The filtering module includes M filter delay units, M filter multiplication units and filter accumulation units, where M is the number of taps of the filter. The filter delay units, filter multiplication units and filter accumulation units are connected in sequence, and each filter delay unit delays one sampling point. The M delayed sampling points constitute the input signal vector L is the length of each data block, k is the block index number, i is the sample point index number, the vector is connected to the iteration module, and the last delayed sample point r (kL + iM) is connected to the modulo module; each filter multiplication unit performs conjugate complex multiplication on the input signal vector and the filter weight coefficient; the filter accumulation unit adds the results of the filter multiplication unit in parallel to obtain the filter output signal y (kL + i), which is connected to the iteration module and the output FIFO module.

4. The normalized block LMS adaptive filter with zero delay characteristics according to claim 1, characterized in that: The iteration module includes an expected signal delay unit, an error subtraction unit, an input signal delay unit, M error multiplication units, M error division units, M error accumulation units and M coefficient iteration units, wherein the expected signal delay unit, the error subtraction unit and the error multiplication unit are connected in sequence, and the input signal delay unit, the M error multiplication units, the M error division units, the M error accumulation units and the M coefficient iteration units are connected in sequence; The expected signal delay unit is used to perform a number of sample point delay processing on the expected signal s(kL+i) to obtain a delayed expected signal s d (kL+i), so that it keeps synchronization with the filter output signal y(kL+i), L is the length of each data block, k is the block index number, and i is the sample point index number; The error subtraction unit is used to delay the expected signal s d (kL+i) is subtracted from the filter output signal y(kL+i) to obtain the filter output error e(kL+i); The input signal delay unit is used to delay the input signal vector Perform delay processing on several sample points to obtain the delayed input signal vector Make it synchronized with the filter output error e(kL+i); The M error multiplication units are used to multiply the delayed input signal vector Conjugate multiply with the filter output error e(kL+i) to output the gradient vector estimate j is the number of iterations; M error division units are used to estimate the gradient vector The square norm modulus of the input signal vector Divide and output the normalized gradient vector estimate M error accumulation units are used to estimate the normalized gradient vector Accumulate L sample points, and output the mean vector after the accumulation is completed. The mean vector is the weight update vector M coefficient iteration units are used to calculate the weight coefficient vector Update and output the updated weight coefficient vector This vector is connected to the filter module.

5. The normalized block LMS adaptive filter with zero delay characteristics according to claim 1, characterized in that: The modular module comprises a modular multiplication unit, a modular subtraction unit, a modular accumulation unit and a modular delay unit connected in sequence; The two modular multiplication units respectively perform conjugate multiplication on the two input signal scalars r(kL+i) and r(kL+iM), and output the square norm modulus value of the scalar r(kL+i) ||r(kL+i)|| 2 and the squared norm modulus of the scalar r(kL+iM)||r(kL+iM)|| 2 , L is the length of each data block, k is the block index number, and i is the sample point index number; The modular subtraction unit is used to subtract the outputs of the two modular multiplication units and output the difference Δ of the square norm modular value. norm2 =||r(kL+i)|| 2 -||r(kL+iM)|| 2 ; The modulo accumulation unit is used to norm2 Accumulate and output the square norm modulus value The modulus delay unit is used to Perform delay processing on several sample points to obtain the delay square norm modulus value Synchronize it with j is the number of iterations, and the output of the modulo module is connected to the iteration module.

6. The normalized block LMS adaptive filter with zero delay characteristics according to claim 1, characterized in that: The modulo module processes the clock f s The square norm of the input signal vector is taken modulo in a burst manner under the drive of , and after the modulo operation is completed, it enters the silent waiting mode. The modulo module adopts the recursive calculation formula as follows: Where L is the length of each data block, k is the block index number, i is the sample point index number, and M is the number of filter taps.

7. The normalized block LMS adaptive filter with zero delay characteristics according to claim 1, characterized in that: The output FIFO module processes the clock f s Driven by the filter output y(kL+i), the filter output result y(kL+i) is written into the output FIFO in burst mode. When the FIFO is full of L samples, the data clock f sig Driven by, each filtering result is output continuously.

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