High-speed driving circuit with full duty ratio

Abstract

A full-duty-ratio high-speed driving circuit disclosed by the present invention comprises a driving circuit module, a bootstrap boost circuit module and a voltage stabilizing circuit module, the driving circuit module is composed of a first driving circuit and a second driving circuit, and the first driving circuit and the second driving circuit are driven by an input signal IN1 and an input signal IN2. The input signal IN1 and the input signal IN2 are in control connection with the first driving circuit and the second driving circuit at the same time; according to the driving circuit, two paths of driving circuits are controlled to realize full duty ratio output through high and low level change states of an input signal IN1 and an input signal IN2. According to the high-speed driving circuit, advanced devices and circuit topological structures are adopted, high-speed and high-performance driving signal output is achieved, and the high-speed driving circuit is suitable for various high-performance application scenes including the fields of digital signal processing, communication systems, power electronics and the like.

Description

Technical Field

[0001] The invention relates to the technical field of high-performance drive circuits, in particular to a high-speed drive circuit with high power and full duty cycle. Background Art

[0002] In modern electronic devices, the demand for high-speed drive circuits is growing, especially in the fields of digital signal processing, communication systems, power electronics, etc. However, traditional drive circuits often face the problem of duty cycle limitation when achieving high frequency and high performance, which limits their use in certain applications.

[0003] Traditional drive circuit design is often limited by the range of duty cycle, that is, it is difficult to achieve full duty cycle output at a certain frequency. Duty cycle refers to the ratio of the time that the signal is high level in a cycle to the total time of the cycle, usually expressed as a percentage. Full duty cycle means that the signal high level occupies the entire cycle time, which is particularly important in some high-performance applications.

[0004] In this context, this patent proposes an innovative full-duty-cycle high-speed drive circuit design. The design adopts advanced circuit topology and device configuration, and through careful circuit design and signal processing technology, it realizes the output of full-duty-cycle drive signals at high frequencies. Specifically, the design utilizes a combination of high-performance power switching devices and precision control circuits to ensure high-speed, stable and full-duty-cycle output of the drive signal. Summary of the invention

[0005] A high-speed driving circuit with a full duty cycle proposed by the present invention can at least solve one of the technical problems in the background technology.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A high-speed driving circuit with a full duty cycle, comprising a driving circuit module, wherein the driving circuit module comprises a first driving circuit, a second driving circuit, an input signal IN1 and an input signal IN2, wherein the first driving circuit and the second driving circuit are both driven by the input signal IN1 and the input signal IN2, and the input signal IN1 and the input signal IN2 are simultaneously controlled and connected to the first driving circuit and the second driving circuit;

[0008] The input signal IN1 and the input signal IN2 are in high and low level change states, and are used to control the first drive circuit and the second drive circuit to achieve full duty cycle output.

[0009] Further, the first driving circuit of the present invention includes a driving chip G1, a driving chip G2, a high-end MOS tube Q1, a low-end MOS tube Q2, a filter capacitor C1, a filter capacitor C2, a filter capacitor C4, a filter capacitor C5, a bootstrap capacitor C3, a voltage regulator diode D4, a diode D1, a diode D2, a diode D3, a diode D5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, and a resistor R19; wherein the six ports of the driving chip are specifically two input terminals, namely, an ANODE terminal and a CATHODE terminal; two output terminals, namely, an OUTH terminal and an OUTL terminal; a power supply terminal VCC, and a negative voltage power supply terminal VEE;

[0010] The power supply terminal VCC of the driving chip G1 is connected to the cathode of the diode D1 and the diode D2, wherein the anode of the diode D1 is connected to the resistor R19, and the other end of the resistor R19 is connected to the +15V voltage source; the filter capacitor C1 and the filter capacitor C2 are connected in parallel between the +15V voltage source and GND, and the ends of the filter capacitors C1 and C2 connected to the +15V voltage source are simultaneously connected to the resistor R19; wherein the anode of the diode D2 is connected to the resistor R1, and the other end of the resistor R1 is connected to the voltage source VB; the cathode of the voltage regulator diode D4 is connected to the anode of the diode D2, and the anode of the voltage regulator diode D4 is connected to the negative voltage power supply terminal VEE;

[0011] The bootstrap capacitor is connected in parallel between the power supply terminal VCC and the negative voltage supply terminal VEE, one end of which is connected to the positive electrode of the voltage stabilizing diode D4, and the other end is connected to the negative electrode of the diode D2;

[0012] The output terminal OUTH of the driver chip G1 is connected to the resistor R2, and the output terminal OUTL is connected to the resistor R3. The resistors R2 and R3 are both connected to the gate of the high-end MOS tube Q1;

[0013] The source of the high-end MOS tube is connected to the negative voltage supply terminal VEE, the drain is connected to the voltage source VS, the cathode of the diode D3 is connected to the drain of the high-end MOS tube, and the anode of the diode D3 is connected to the source of the high-end MOS tube;

[0014] The power supply terminal VCC of the driver chip G2 is connected to a +15V voltage source, and is also connected to a filter capacitor C5, and the other end of the filter capacitor C5 is connected to GND; the output terminal OUTH is connected to a resistor R4, and the output terminal OUTL is connected to a resistor R5, and the resistors R4 and R5 are both connected to the gate of the low-end MOS tube Q2; the negative voltage power supply terminal VEE is connected to GND;

[0015] The source of the low-end MOS tube is connected to GND, and the drain is connected to the negative voltage supply terminal VEE of the driving chip G1 as the output of the first driving circuit; the cathode of the diode D5 is connected to the source of the low-end MOS tube, and the anode of the diode D5 and the source of the low-end MOS tube are grounded; one end of the filter capacitor C4 is connected to VS, and the other end is connected to GND.

[0016] Furthermore, the control method of the first driving circuit and the second driving circuit of the present invention is specifically as follows:

[0017] When the input signal IN1 is at a high level and the input signal IN2 is at a low level, the MOS tubes Q1 and Q4 are turned on, so that the driving chip G1 and the driving chip G4 are in an active state, and the first driving circuit and the second driving circuit are controlled to work simultaneously. When the input signal IN1 is at a low level and the input signal IN2 is at a high level, the MOS tubes Q2 and Q3 are turned on, so that the driving chip G2 and the driving chip G3 are in an active state, and the first driving circuit and the second driving circuit are controlled to work simultaneously.

[0018] Furthermore, the full-duty-cycle high-speed driving circuit described in the present invention also includes a bootstrap boost circuit module and a voltage stabilizing circuit module, wherein the bootstrap boost circuit module is connected to the voltage stabilizing circuit module, and the voltage stabilizing circuit module is connected to the driving circuit; the bootstrap boost circuit boosts the +8V voltage to the +15V voltage, and inputs the +15V voltage to the voltage stabilizing circuit module, the voltage stabilizing circuit module processes the unstable +15V voltage, and transmits the processed +15V voltage to the driving circuit module.

[0019] Further, the bootstrap boost circuit module of the present invention includes a 555 timer chip U2, a clamping diode D15, a filter capacitor C16, a filter capacitor C21, a coupling capacitor C22, a resistor R16, a resistor R17, a resistor R18 and a boost unit;

[0020] The 555 timer chip U2 includes 8 ports, specifically GND terminal, trigger input terminal TRIG, output terminal OUT, reset terminal RESET, power terminal VCC, control terminal DIS, threshold input terminal THR, and control voltage terminal CON;

[0021] The reset terminal RESET is connected to the power supply terminal VCC, the power supply terminal VCC is connected to the resistor R16, and the 8V voltage source provided by the voltage stabilizing circuit at the other end of the resistor R16 plays a current limiting protection role;

[0022] The trigger input terminal TRIG is connected to the threshold input terminal THR, and then connected to the connection point between the resistor R18 and the coupling capacitor C22; the coupling capacitor C22 is connected to the resistor R18, and the other end of the resistor R18 is connected to the resistor R17, and the resistor R17 is connected to the resistor R16, and the filter capacitor C16 is connected in parallel to both ends of the coupling capacitor C22 and the resistor R17;

[0023] The control terminal DIS is connected to the connection point of the resistor R17 and the resistor R18;

[0024] The control voltage terminal CON is connected to the filter capacitor C21, and the other end of the filter capacitor C21 is connected to the positive electrode of the clamping diode D15 and is grounded at the same time;

[0025] The output terminal OUT is connected to the positive electrode of the clamping diode D15 and the boost unit.

[0026] Further, the boost unit of the present invention includes a bootstrap boost capacitor C17, a bootstrap boost capacitor C18, a bootstrap boost capacitor C19, a bootstrap boost capacitor C20, a bootstrap boost diode D11, a bootstrap boost diode D12, a bootstrap boost diode D13, and a bootstrap boost diode D14;

[0027] In the boost unit, the bootstrap boost diode D11, the bootstrap boost diode D12, the bootstrap boost diode D13, and the bootstrap boost diode D14 are connected in sequence, and the positive electrode of the bootstrap boost diode D14 is connected to the power supply VS end; after the bootstrap boost capacitor C17 is connected to the capacitor C19, it is connected in parallel to the bootstrap boost diode D11 and the bootstrap boost diode D12; after the bootstrap boost capacitor C18 is connected to the capacitor C20, it is connected in parallel to the bootstrap boost diode D12 and the bootstrap boost diode D13, wherein one end of the bootstrap boost capacitor is connected to the cathode of the clamping diode D15.

[0028] It can be seen from the above technical solution that the full duty cycle high-speed driving circuit of the present invention has the following advantages compared with the traditional driving circuit:

[0029] 1) High performance: The use of advanced devices and circuit topology achieves high-speed and high-performance drive signal output.

[0030] 2) Full duty cycle output: Through precise circuit design and control technology, full duty cycle output at high frequency is achieved, which improves the application range and effect of the drive circuit.

[0031] 3) Stability and reliability: The circuit design takes into account the stability and reliability requirements under various working conditions, ensuring the stability and reliability of the driving signal.

[0032] 4) Strong adaptability: The design is suitable for various high-performance application scenarios, including digital signal processing, communication systems, power electronics and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a structural diagram of a driving circuit of the present invention;

[0034] Figure 2 It is a structural diagram of the bootstrap boost circuit of the present invention;

[0035] Figure 3 It is a structural diagram of the voltage stabilizing circuit of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0037] A full-duty-cycle high-speed driving circuit described in an embodiment of the present invention comprises a driving circuit module, a voltage stabilizing circuit module, and a bootstrap boosting circuit module; the bootstrap boosting circuit module is connected to the voltage stabilizing circuit module, and the voltage stabilizing circuit module is connected to the driving circuit; the bootstrap boosting circuit boosts the +8V voltage to the +15V voltage, and inputs the +15V voltage to the voltage stabilizing circuit module, the voltage stabilizing circuit module processes the unstable +15V voltage, and transmits the processed +15V voltage to the driving circuit module.

[0038] The driving circuit module is specifically as follows Figure 1 As shown, it includes a first driving circuit, a second driving circuit, an input signal IN1 and an input signal IN2; the first driving circuit includes a driving chip G1, a driving chip G2, a high-end MOS tube Q1, a low-end MOS tube Q2, a filter capacitor C1, a filter capacitor C2, a filter capacitor C4, a filter capacitor C5, a bootstrap capacitor C3, a voltage regulator diode D4, a diode D1, a diode D2, a diode D3, a diode D5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, and a resistor R19;

[0039] Among them, the six ports of the driver chip are specifically two input terminals, namely ANODE terminal and CATHODE terminal; two output terminals, namely OUTH terminal and OUTL terminal; power supply terminal VCC and negative voltage supply terminal VEE.

[0040] The power supply terminal VCC of the driver chip G1 is connected to the cathode of the diode D1 and the diode D2, wherein the anode of the diode D1 is connected to the resistor R19, and the other end of the resistor R19 is connected to the +15V voltage source; the filter capacitor C1 and the filter capacitor C2 are connected in parallel between the +15V voltage source and GND, and the ends where the filter capacitors C1 and C2 are connected to the +15V voltage source are simultaneously connected to the resistor R19. The anode of the diode D2 is connected to the resistor R1, and the other end of the resistor R1 is connected to the voltage source VB; the cathode of the voltage zener diode D4 is connected to the anode of the diode D2, and the anode of the voltage zener diode D4 is connected to the negative voltage power supply terminal VEE;

[0041] The bootstrap capacitor is connected in parallel between the power supply terminal VCC and the negative voltage supply terminal VEE, one end of which is connected to the positive electrode of the voltage stabilizing diode D4, and the other end of which is connected to the negative electrode of the diode D2.

[0042] The output terminal OUTH of the driver chip G1 is connected to the resistor R2, and the output terminal OUTL is connected to the resistor R3. The resistors R2 and R3 are both connected to the gate of the high-end MOS tube Q1;

[0043] The source of the high-end MOS tube is connected to the negative voltage supply terminal VEE, the drain is connected to the voltage source VS, the cathode of the diode D3 is connected to the drain of the high-end MOS tube, and the anode of the diode D3 is connected to the source of the high-end MOS tube;

[0044] The power supply terminal VCC of the driver chip G2 is connected to a +15V voltage source, and is also connected to a filter capacitor C5, and the other end of the filter capacitor C5 is connected to GND; the output terminal OUTH is connected to a resistor R4, and the output terminal OUTL is connected to a resistor R5, and the resistors R4 and R5 are both connected to the gate of the low-end MOS tube Q2; the negative voltage power supply terminal VEE is connected to GND;

[0045] The source of the low-end MOS tube is connected to GND, and the drain is connected to the negative voltage supply terminal VEE of the driving chip G1 as the output of the first driving circuit; the cathode of the diode D5 is connected to the source of the low-end MOS tube, and the anode of the diode D5 and the source of the low-end MOS tube are grounded;

[0046] One end of the filter capacitor C4 is connected to VS, and the other end is connected to GND.

[0047] The second driving circuit includes two driving chips G3 and G4, a high-end MOS tube Q3, a low-end MOS tube Q4, filter capacitors C6, C7, C9, C23, a bootstrap capacitor C8, a voltage regulator diode D9, a diode D6, a diode D7, a diode D8, a diode D10, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, and a resistor R20;

[0048] The specific structure of the second driving circuit is the same as that of the first driving circuit.

[0049] The input signal IN1 is connected to the input terminal ANODE of the driving chip G1, the input terminal CATHODE of the driving chip G2, the input terminal CATHODE of the driving chip G3, and the input terminal ANODE of the driving chip G4 through the resistor R6;

[0050] The input signal IN2 is connected to the input terminal CATHODE of the driving chip G1 , the input terminal ANODE of the driving chip G2 , the input terminal ANODE of the driving chip G3 , and the input terminal CATHODE of the driving chip G4 .

[0051] The drive circuit module adopts the design concept of H-bridge and uses 4 half-bridge drive chips. According to the high and low levels of the input signal, the drive chip increases the voltage and current output capacity to control the on and off of the high-end MOS tubes Q1, Q3 and the low-end MOS tubes Q2, Q4. The input adopts an interlocking design, that is, when the input signal IN1 is high and IN2 is low, the MOS tubes Q1 and Q4 are turned on, making the drive chip G1 and the drive chip G4 active, and controlling the first drive circuit and the second drive circuit to work simultaneously.

[0052] When the input signal IN1 is at a low level and IN2 is at a high level, MOS tubes Q2 and Q3 are turned on, making the driver chip G2 and the driver chip G3 active, and controlling the first drive circuit and the second drive circuit to work simultaneously. In this way, the interlocking design can ensure that only two corresponding driver chips are active under certain conditions, thereby avoiding circuit short circuits or other safety problems caused by different chips outputting signals at the same time. This design can effectively protect circuits and related equipment and improve the safety of the system. The input signal is output to the gate resistor to the NMOS tube through the driver chip, a diode is connected in parallel between the MOS drain and source, and an absorption capacitor is connected in parallel to the output part to increase the switching speed of the MOS tube and optimize the output waveform. The HO and LO high and low level signals given by the driver chip respectively control the conduction of the upper MOS tube and the lower MOS tube of the H bridge to generate control signals to drive the load.

[0053] The input signal PWM wave is input to the driver chip through the current limiting resistor R6 and the interlocking circuit. Filter capacitors C5 and C9 are set between the VCC terminal and the ground of the driver chip. Bootstrap capacitors C3 and C8 and voltage regulator tubes are set at the VCC and VEEE terminals of the driver chip to ensure that the voltage between the VCC and VEE of the driver chip is the specified value in the user manual. Voltage clamping is achieved through two diodes to prepare for the realization of a 100% duty cycle output signal.

[0054] like Figure 2 The structure diagram of the bootstrap boost module in the high-speed drive circuit shown in FIG. 1 includes a 555 timer chip U2. 、 Clamping diode D15, filter capacitors C16, C21, coupling capacitor C22, resistor R16, resistor R17, resistor R18 and boost unit, the boost unit includes bootstrap boost capacitor C17, bootstrap boost capacitor C18, bootstrap boost capacitor C19, bootstrap boost capacitor C20, bootstrap boost diode D11, bootstrap boost diode D12, bootstrap boost diode D13, bootstrap boost diode D14;

[0055] The 555 timer chip U2 includes 8 ports, specifically a GND terminal, a trigger input terminal TRIG, an output terminal OUT, a reset terminal RESET, a power terminal VCC, a control terminal DIS, a threshold input terminal THR, and a control voltage terminal CON.

[0056] The reset terminal RESET is connected to the power supply terminal VCC, the power supply terminal VCC is connected to the resistor R16, and the 8V voltage source provided by the voltage stabilizing circuit at the other end of the resistor R16 plays a current limiting protection role;

[0057] The trigger input terminal TRIG is connected to the threshold input terminal THR, and then connected to the connection point between the resistor R18 and the coupling capacitor C22; the coupling capacitor C22 is connected to the resistor R18, and the other end of the resistor R18 is connected to the resistor R17, and the resistor R17 is connected to the resistor R16, and the filter capacitor C16 is connected in parallel to both ends of the coupling capacitor C22 and the resistor R17;

[0058] The control terminal DIS is connected to the connection point of the resistors R17 and R18;

[0059] The control voltage terminal CON is connected to the filter capacitor C21, and the other end of the filter capacitor C21 is connected to the positive electrode of the clamping diode D15 and is grounded at the same time.

[0060] The output terminal OUT is connected to the positive electrode of the clamping diode D15 and the boost unit;

[0061] In the boost unit, the bootstrap boost diode D11, the bootstrap boost diode D12, the bootstrap boost diode D13, and the bootstrap boost diode D14 are connected in sequence, and the positive electrode of the bootstrap boost diode D14 is connected to the power supply VS end; after the bootstrap boost capacitor C17 is connected to the capacitor C19, it is connected in parallel to the bootstrap boost diode D11 and the bootstrap boost diode D12; after the bootstrap boost capacitor C18 is connected to the capacitor C20, it is connected in parallel to the bootstrap boost diode D12 and the bootstrap boost diode D13, wherein one end of the bootstrap boost capacitor is connected to the cathode of the clamping diode D15.

[0062] The working principle of the bootstrap boost module in the high-speed drive circuit is as follows:

[0063] After the power supply terminal VCC of the 555 timer chip is connected to the 8V voltage output by the voltage regulator chip, the capacitor C22 is charged by VCC through the external resistors R17 and R18. The voltage across the capacitor C22 rises to the turn-on threshold voltage of the threshold input terminal THR, thus triggering the OUT pin of the 555 timer chip to output a low level. At the same time, the discharge crystal inside the chip is driven and turned on, making the chip control terminal DIS output low, forming a potential difference between capacitor C22 and DIS, and C22 discharges through R18. The capacitor potential begins to drop until the turn-off threshold of the threshold input terminal THR is triggered. The flip-flop inside the chip is triggered, making the OUT pin output high, and the discharge transistor inside the chip is cut off. The capacitor C22 is charged again through R17 and R18. By repeating these actions, the OUT end of the chip can output an oscillating waveform of a specific frequency.

[0064] In this design, the OUT pin of the chip outputs an oscillating waveform of a square wave from 0V to 8V. When the OUT output is a low level of 0V, the power supply VS charges capacitors C17, C18, C19, and C20 to the voltage of VS through diodes D14, D13, D12, and D11. When the OUT pin output is 8V, the voltages of C20 and C18 are VS+8V. At this time, the voltages of capacitors C20 and C18 are higher than those of capacitors C19 and C17, respectively. Due to the unidirectional conductivity of the diode, capacitors C20 and C18 share the charge with capacitors C19 and C17, respectively. When the OUT pin output is a low level again, the above process is repeated. In this process, the voltage of capacitor C17 will gradually increase until it is infinitely close to the voltage of VS plus 4 times the voltage when the OUT output is high.

[0065] The output capability of the circuit outputting PWM wave with 100% duty cycle cannot be realized by simply relying on the driver chip itself with the bootstrap capacitor. The main reason is that the rate of charging and discharging of the bootstrap capacitor and the voltage output fluctuation of the driver chip itself limit this output capability. Therefore, the circuit of the present invention integrates a bootstrap boost circuit designed for the 555 timer. The 555 timer is powered by a voltage stabilizer to convert the power supply voltage. The fixed frequency output by the 555 timer, the energy storage characteristics of the capacitor and the unidirectional conductivity of the diode are utilized to convert the low voltage input into a high voltage output under the action of the square wave signal output by the timer. The high voltage VB output by the bootstrap boost is applied to the VCC end of the motor driver chip, and the voltage regulator tube is used to ensure that the voltage difference between VCC and VEE is within the specified range of the driver chip. In this way, after the circuit reaches stability, the influence of the capacitor charging and discharging rate can be ignored to realize a high-speed driving circuit with full duty cycle.

[0066] like Figure 3The structure diagram of the voltage stabilizing circuit module in the high-speed driving circuit shown in the figure, the voltage stabilizing circuit module includes a first voltage stabilizing circuit and a second voltage stabilizing circuit; the output end of the first voltage stabilizing circuit is connected to the input end of the second voltage stabilizing circuit, wherein the first voltage stabilizing circuit includes a voltage stabilizing chip U1, a filter capacitor C10, a filter capacitor C11, a filter capacitor C12 and resistors R12 and R13;

[0067] The voltage stabilizing chip includes an enable control terminal EN, four input terminals IN, four output terminals OUT, a voltage control terminal ADJ, and a GND terminal; wherein the enable control terminal EN and the four input terminals IN are all connected to the voltage source VS, and the four output terminals OUT are connected in parallel to jointly provide a stable 15V output; the filter capacitor C11 and the filter capacitor C12 are connected in parallel between the +15V output voltage and GND; the voltage control terminal ADJ is connected to the resistor R13, the other end of the resistor R13 is connected to the output voltage +15V, and the resistor R12 is connected in parallel to both ends of the resistor R13.

[0068] The second voltage stabilizing circuit includes a voltage stabilizing chip U3, a filter capacitor C13, a filter capacitor C14, a filter capacitor C15 and resistors R14 and R15; its circuit structure is exactly the same as the first voltage stabilizing circuit; its second voltage stabilizing circuit reduces the 15V voltage output by the first voltage stabilizing circuit to 8V voltage to provide a boost voltage for the bootstrap boost circuit module.

[0069] The voltage stabilization circuit uses two voltage stabilization chips. Through the reasonable combination of resistors and capacitors, a TVS tube can be added between the output end of the voltage stabilizer and the ground to prevent the high-speed drive circuit from generating a large surge when driving an inductive load, which may damage the voltage stabilization chip and greatly improve the stability of the circuit.

[0070] Through Figure 3 The voltage regulator circuit shown converts the VS power supply into 15V and 8V voltages. The 15V voltage is used to power the driver chip and the 555 chip. A bypass capacitor is added to the power supply port of the chip to filter out noise and ensure the voltage stability of the chip output. The bootstrap boost circuit boosts the 8V voltage to VB = 8V + power supply voltage VS and adds it to the VCC terminal of the driver chip. The conduction of the high-end and low-end MOS is controlled by the high and low input signals.

[0071] In summary, a high-speed driving circuit with full duty cycle of the present invention includes a driving circuit module, a bootstrap boosting circuit module, and a voltage stabilizing circuit module. The driving circuit module is composed of a first driving circuit and a second driving circuit. The first driving circuit and the second driving circuit are both driven by input signals IN1 and IN2, and the input signals IN1 and IN2 are simultaneously controlled and connected with the first driving circuit and the second driving circuit; through the high and low level change states of the input signals IN1 and IN2, the two driving circuits are controlled to realize the driving circuit with full duty cycle output. The high-speed driving circuit of the present invention adopts advanced devices and circuit topology to realize high-speed and high-performance driving signal output, which is suitable for various high-performance application scenarios, including digital signal processing, communication systems, power electronics and other fields.

[0072] The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form; any technician familiar with the art can make many possible changes and modifications to the technical solution of the present invention by using the above disclosed methods and technical contents without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent replacement, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A high-speed driving circuit with full duty cycle, comprising a driving circuit module, characterized in that: The driving circuit module includes a first driving circuit, a second driving circuit, an input signal IN1 and an input signal IN2, the first driving circuit and the second driving circuit are both driven by the input signal IN1 and the input signal IN2, and the input signal IN1 and the input signal IN2 are simultaneously controlled and connected to the first driving circuit and the second driving circuit; The input signal IN1 and the input signal IN2 are in high and low level change states, and are used to control the first drive circuit and the second drive circuit to achieve full duty cycle output.

2. A high-speed driving circuit with full duty cycle according to claim 1, characterized in that: The first driving circuit includes a driving chip G1, a driving chip G2, a high-end MOS tube Q1, a low-end MOS tube Q2, a filter capacitor C1, a filter capacitor C2, a filter capacitor C4, a filter capacitor C5, a bootstrap capacitor C3, a voltage regulator diode D4, a diode D1, a diode D2, a diode D3, a diode D5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, and a resistor R19; wherein the six ports of the driving chip are specifically two input terminals, namely, an ANODE terminal and a CATHODE terminal; two output terminals, namely, an OUTH terminal and an OUTL terminal; a power supply terminal VCC, and a negative voltage supply terminal VEE; The power supply terminal VCC of the driving chip G1 is connected to the cathode of the diode D1 and the diode D2, wherein the anode of the diode D1 is connected to the resistor R19, and the other end of the resistor R19 is connected to the +15V voltage source; the filter capacitor C1 and the filter capacitor C2 are connected in parallel between the +15V voltage source and GND, and the ends of the filter capacitors C1 and C2 connected to the +15V voltage source are simultaneously connected to the resistor R19; wherein the anode of the diode D2 is connected to the resistor R1, and the other end of the resistor R1 is connected to the voltage source VB; the cathode of the voltage regulator diode D4 is connected to the anode of the diode D2, and the anode of the voltage regulator diode D4 is connected to the negative voltage power supply terminal VEE; The bootstrap capacitor is connected in parallel between the power supply terminal VCC and the negative voltage supply terminal VEE, one end of which is connected to the positive electrode of the voltage stabilizing diode D4, and the other end is connected to the negative electrode of the diode D2; The output terminal OUTH of the driver chip G1 is connected to the resistor R2, and the output terminal OUTL is connected to the resistor R3. The resistors R2 and R3 are both connected to the gate of the high-end MOS tube Q1; The source of the high-end MOS tube is connected to the negative voltage supply terminal VEE, the drain is connected to the voltage source VS, the cathode of the diode D3 is connected to the drain of the high-end MOS tube, and the anode of the diode D3 is connected to the source of the high-end MOS tube; The power supply terminal VCC of the driver chip G2 is connected to a +15V voltage source, and is also connected to a filter capacitor C5, and the other end of the filter capacitor C5 is connected to GND; the output terminal OUTH is connected to a resistor R4, and the output terminal OUTL is connected to a resistor R5, and the resistors R4 and R5 are both connected to the gate of the low-end MOS tube Q2; the negative voltage power supply terminal VEE is connected to GND; The source of the low-end MOS tube is connected to GND, and the drain is connected to the negative voltage supply terminal VEE of the driving chip G1 as the output of the first driving circuit; the cathode of the diode D5 is connected to the source of the low-end MOS tube, and the anode of the diode D5 and the source of the low-end MOS tube are grounded; one end of the filter capacitor C4 is connected to VS, and the other end is connected to GND.

3. A high-speed driving circuit with full duty cycle according to claim 1, characterized in that: The control method of the first driving circuit and the second driving circuit is specifically as follows: When the input signal IN1 is at a high level and the input signal IN2 is at a low level, the MOS tubes Q1 and Q4 are turned on, so that the driving chip G1 and the driving chip G4 are in an active state, and the first driving circuit and the second driving circuit are controlled to work simultaneously. When the input signal IN1 is at a low level and the input signal IN2 is at a high level, the MOS tubes Q2 and Q3 are turned on, so that the driving chip G2 and the driving chip G3 are in an active state, and the first driving circuit and the second driving circuit are controlled to work simultaneously.

4. A high-speed driving circuit with full duty cycle according to claim 1, characterized in that: It also includes a bootstrap boost circuit module and a voltage stabilizing circuit module, wherein the bootstrap boost circuit module is connected to the voltage stabilizing circuit module, and the voltage stabilizing circuit module is connected to the driving circuit; the bootstrap boost circuit boosts the +8V voltage to the +15V voltage, and inputs the +15V voltage to the voltage stabilizing circuit module, the voltage stabilizing circuit module processes the unstable +15V voltage, and transmits the processed +15V voltage to the driving circuit module.

5. The high-speed driving circuit with full duty cycle according to claim 4, characterized in that: The bootstrap boost circuit module includes a 555 timer chip U2, a clamping diode D15, a filter capacitor C16, a filter capacitor C21, a coupling capacitor C22, a resistor R16, a resistor R17, a resistor R18 and a boost unit; The 555 timer chip U2 includes 8 ports, specifically GND terminal, trigger input terminal TRIG, output terminal OUT, reset terminal RESET, power terminal VCC, control terminal DIS, threshold input terminal THR, and control voltage terminal CON; The reset terminal RESET is connected to the power supply terminal VCC, the power supply terminal VCC is connected to the resistor R16, and the 8V voltage source provided by the voltage stabilizing circuit at the other end of the resistor R16 plays a current limiting protection role; The trigger input terminal TRIG is connected to the threshold input terminal THR, and then connected to the connection point between the resistor R18 and the coupling capacitor C22; the coupling capacitor C22 is connected to the resistor R18, and the other end of the resistor R18 is connected to the resistor R17, and the resistor R17 is connected to the resistor R16, and the filter capacitor C16 is connected in parallel to both ends of the coupling capacitor C22 and the resistor R17; The control terminal DIS is connected to the connection point of the resistor R17 and the resistor R18; The control voltage terminal CON is connected to the filter capacitor C21, and the other end of the filter capacitor C21 is connected to the positive electrode of the clamping diode D15 and is grounded at the same time; The output terminal OUT is connected to the positive electrode of the clamping diode D15 and the boost unit.

6. A high-speed driving circuit with full duty cycle according to claim 5, characterized in that: The boost unit includes a bootstrap boost capacitor C17, a bootstrap boost capacitor C18, a bootstrap boost capacitor C19, a bootstrap boost capacitor C20, a bootstrap boost diode D11, a bootstrap boost diode D12, a bootstrap boost diode D13, and a bootstrap boost diode D14; In the boost unit, the bootstrap boost diode D11, the bootstrap boost diode D12, the bootstrap boost diode D13, and the bootstrap boost diode D14 are connected in sequence, and the positive electrode of the bootstrap boost diode D14 is connected to the power supply VS end; after the bootstrap boost capacitor C17 is connected to the capacitor C19, it is connected in parallel to the two ends of the bootstrap boost diodes D11 and D12; after the bootstrap boost capacitor C18 is connected to the capacitor C20, it is connected in parallel to the two ends of the bootstrap boost diodes D12 and D13, wherein one end of the bootstrap boost capacitor is connected to the negative electrode of the clamping diode D15.

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