Analog switch circuit, multi-path selection change-over switch and electronic equipment

Abstract

The invention discloses an analog switch circuit, a multi-path selection change-over switch and electronic equipment. The analog switch circuit comprises a switch unit, a first dynamic bias unit, a second dynamic bias unit and a control signal unit, wherein the control signal unit is used for generating a first control signal and a second control signal according to a system control signal; the switch unit is used for connecting or disconnecting a transmission path of an analog signal according to the first control signal and the second control signal; the first dynamic bias unit and the second dynamic bias unit are respectively used for selecting output voltage according to the first control signal and the second control signal so as to control bias voltage of the first bias end and the second bias end of the switch unit. According to the analog switch circuit, the working performance of an analog switch is greatly improved while rapid on-off switching is realized.

Description

Technical Field

[0001] The present invention relates to an analog switch circuit, and also to a multi-way selection switch and electronic equipment comprising the analog switch circuit, belonging to the technical field of analog integrated circuits. Background Art

[0002] In the field of integrated circuits, analog switches play a vital role. Their main function is to control the transmission path of analog signals or power signals, and to manage the transmission of signals by opening or closing these paths. With the development of technology and the complexity of application systems, such as audio, video, and RF circuits, the performance requirements for analog switches are also increasing. These systems require analog switches to ensure the high quality of signals during transmission, while being able to flexibly select and switch multiple analog signals or power signals. Therefore, the characteristics of analog switches such as low resistance and high isolation become particularly important to meet these growing performance requirements.

[0003] In the prior art, PMOS and NMOS transistors working in the linear region are usually used as analog switches. Due to the CMOS substrate effect (also known as the body effect), the threshold voltage of the PMOS and NMOS transistors will change with the input voltage, and the on-resistance will also increase, reducing the working performance of the analog switch. At the same time, the analog switch of this structure cannot meet the flexibility requirements of the application system, and cannot achieve lossless transmission and selective switching of multiple different voltage signals.

[0004] In the Chinese patent application with application number 202111203030.9, a low-voltage analog switch circuit is disclosed, including a switch unit, a first substrate control unit and a second substrate control unit respectively connected to the switch unit. Although the low-voltage analog switch circuit solves the problems of driving power consumption and threshold voltage stability through substrate selection, in the application scenario of multi-channel different voltage signal transmission, the auxiliary switch will leak signals, and it is impossible to realize the transmission and selection switching of multiple different voltage signals. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide an analog switch circuit.

[0006] Another technical problem to be solved by the present invention is to provide a multi-way selection switch including the analog switch circuit.

[0007] Another technical problem to be solved by the present invention is to provide an electronic device including the analog switch circuit.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, an analog switch circuit is provided, comprising a switch unit, a first dynamic bias unit, a second dynamic bias unit and a control signal unit; wherein:

[0010] The switch unit is used to connect or disconnect the transmission path of the analog signal according to the first control signal and the second control signal; the input end of the switch unit is connected to the external analog signal end;

[0011] The first dynamic bias unit is used to select an output voltage according to the first control signal and the second control signal to control the bias voltage of the first bias terminal of the switch unit; the first input terminal of the first dynamic bias unit is connected to the power supply voltage terminal, the second input terminal is connected to the input terminal of the switch unit, and the output terminal is connected to the first bias terminal of the switch unit;

[0012] The second dynamic bias unit is used to select an output voltage according to the first control signal and the second control signal to control the bias voltage of the second bias terminal of the switch unit; the first input terminal of the second dynamic bias unit is connected to the ground potential terminal, the second input terminal is connected to the input terminal of the switch unit, and the output terminal is connected to the second bias terminal of the switch unit;

[0013] The control signal unit is used to generate the first control signal and the second control signal according to the system control signal, and provide them to the switch unit, the first dynamic bias unit and the second dynamic bias unit; the input end of the control signal unit is connected to the system control signal end, and the output end is connected to the control ends of the switch unit, the first dynamic bias unit and the second dynamic bias unit respectively;

[0014] When the analog switch circuit is turned on or off, the first dynamic bias unit and the second dynamic bias unit respectively perform corresponding voltage bias on the switch unit.

[0015] Preferably, the switch unit includes a first PMOS tube and a first NMOS tube; wherein,

[0016] The source ends of the first PMOS tube and the first NMOS tube are connected in parallel to serve as the input end of the switch unit, and are respectively connected to the second input ends of the first dynamic bias unit and the second dynamic bias unit; the drain ends of the first PMOS tube and the first NMOS tube are connected in parallel to serve as the output end of the switch unit; the gate end of the first PMOS tube is connected to the first control signal end as the first control end, and the gate end of the first NMOS tube is connected to the second control signal end as the second control end; the body end of the first PMOS tube is connected to the output end of the first dynamic bias unit as the first bias end; and the body end of the first NMOS tube is connected to the output end of the second dynamic bias unit as the second bias end.

[0017] Preferably, the first dynamic bias unit includes a second PMOS transistor, a third PMOS transistor and a fourth NMOS transistor; wherein,

[0018] The source ends of the third PMOS tube and the fourth NMOS tube are connected in parallel and connected to the input end of the switch unit as the second input end; the drain ends of the third PMOS tube and the fourth NMOS tube and the drain end of the second PMOS tube are connected in parallel and connected to the first bias end of the switch unit as the output end; the gate end of the third PMOS tube is connected to the first control signal end, and the body end of the third PMOS tube is connected to the power supply voltage end; the gate end of the fourth NMOS tube is connected to the second control signal end, and the body end of the fourth NMOS tube is connected to the ground potential end; the gate end of the second PMOS tube is connected to the second control signal end, and the body end and the source end of the second PMOS tube are connected in parallel and connected to the power supply voltage end as the first input end.

[0019] Preferably, the second dynamic bias unit includes a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor; wherein,

[0020] The source ends of the fourth PMOS tube and the third NMOS tube are connected in parallel and connected to the input end of the switch unit as the second input end; the drain ends of the fourth PMOS tube, the third NMOS tube and the second NMOS tube are connected in parallel and connected to the second bias end of the switch unit as the output end; the gate end of the fourth PMOS tube is connected to the first control signal end, and the body end of the fourth PMOS tube is connected to the power supply voltage end; the gate end of the third NMOS tube is connected to the second control signal end, and the body end of the third NMOS tube is connected to the ground potential end; the gate end of the second NMOS tube is connected to the first control signal end, and the body end and the source end of the second NMOS tube are connected in parallel and connected to the ground potential end as the first input end.

[0021] Preferably, the control signal unit includes a tenth PMOS tube, an eleventh PMOS tube and a tenth NMOS tube, an eleventh NMOS tube; wherein,

[0022] The tenth PMOS tube and the tenth NMOS tube form a first inverter, and the eleventh PMOS tube and the eleventh NMOS tube form a second inverter; the input end of the first inverter is connected to the system control signal end, and the output end of the first inverter is connected to the input end of the second inverter.

[0023] Preferably, when the analog switch circuit is in an on state, the first dynamic bias unit biases the first bias terminal voltage of the switch unit to the input analog signal voltage; and the second dynamic bias unit biases the second bias terminal voltage of the switch unit to the input analog signal voltage.

[0024] Preferably, when the analog switch circuit is in an off state, the first dynamic bias unit biases the first bias terminal voltage of the switch unit to a power supply voltage; and the second dynamic bias unit biases the second bias terminal voltage of the switch unit to a ground potential voltage.

[0025] Preferably, the power supply voltage is not lower than the input analog signal voltage.

[0026] Preferably, the control signal unit includes an enabling subunit and a controlling subunit; wherein the enabling subunit is used to generate an enabling signal and its inverse signal; and the controlling subunit is used to generate a first control signal and a second control signal.

[0027] Preferably, the enabling subunit includes a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube and a twelfth NMOS tube, as well as a third inverter and a fourth inverter; wherein the gate terminals of the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube, the fifteenth PMOS tube and the twelfth NMOS tube are all connected to the system control voltage terminal; the drain terminals and source terminals of the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube are connected in series in sequence, the source terminal of the fifteenth PMOS tube is connected to the highest voltage terminal of the system, the drain terminal of the twelfth PMOS tube is connected to the drain terminal of the twelfth NMOS tube and the input terminal of the third inverter, and the source terminal of the twelfth NMOS tube is connected to the ground potential terminal; the output terminal of the third inverter is connected to the output terminal of the enable signal and the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the output terminal of the inverse signal of the enable signal.

[0028] Preferably, the control subunit includes a sixteenth PMOS tube, a seventeenth PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, a first NOR gate and a fifth inverter; wherein the gate of the thirteenth NMOS tube is connected to the inverted signal end of the system control signal, the source end is connected to the ground potential end, and the drain end is connected to the source end of the fifteenth PMOS tube; the gate end of the fifteenth PMOS tube is connected to the enable signal end, and the drain end is connected to the drain end of the sixteenth PMOS tube, the gate end of the seventeenth PMOS tube and the drain end of the seventeenth NMOS tube; the gate end of the seventeenth NMOS tube is connected to the inverted signal end of the enable signal The gate terminal of the sixteenth PMOS tube is connected to the system control signal terminal, the source terminal is connected to the ground potential terminal, the source terminal of the sixteenth PMOS tube and the seventeenth PMOS tube are both connected to the highest voltage terminal of the system; the gate terminal of the fourteenth NMOS tube is connected to the system control signal terminal, the source terminal is connected to the ground potential terminal, and the drain terminal is connected to the source terminal of the sixteenth NMOS tube; the gate terminal of the sixteenth NMOS tube is connected to the enable signal terminal, the drain terminal is connected to the gate terminal of the sixteenth PMOS tube, the drain terminal of the seventeenth PMOS tube and the first input terminal of the first NOR gate; the second input terminal of the first NOR gate is connected to the inverted signal terminal of the enable signal, and the output terminal is connected to the output terminal of the second control signal and the input terminal of the fifth inverter; the output terminal of the fifth inverter is connected to the output terminal of the first control signal.

[0029] According to a second aspect of an embodiment of the present invention, a multi-way selection switch is provided, comprising at least two of the above-mentioned analog switch circuits; wherein:

[0030] The input end of each analog switch circuit is connected to an analog signal input end respectively, and the output ends of each analog switch circuit are connected in parallel to serve as the output end of the multi-way selection switch.

[0031] According to a third aspect of an embodiment of the present invention, there is provided an electronic device, comprising the above-mentioned analog switch circuit.

[0032] Compared with the prior art, the analog switch circuit provided by the present invention improves the working performance of the analog switch circuit in the on or off state by adopting the technical solution of the first dynamic bias unit and the second dynamic bias unit to perform voltage bias on the switch unit respectively. When the analog switch circuit is in the on state, there will be no changes in the switch threshold voltage and on-resistance due to the body effect; the analog switch circuit will not generate leakage current in the off state. At the same time, by forming a multi-way selection switching switch in a combined form, the selective transmission of multiple analog signals of different amplitudes can be realized. Therefore, the analog switch circuit provided by the present invention has the beneficial effects of ingenious and reasonable circuit design, low design cost, high flexibility, and excellent working performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A circuit schematic diagram of an analog switch circuit provided by an embodiment of the present invention;

[0034] Figure 2 This is a circuit schematic diagram of a first embodiment of a control signal unit in an embodiment of the present invention;

[0035] Figure 3 is a circuit schematic diagram of a switch unit, a first dynamic bias unit, and a second dynamic bias unit in an embodiment of the present invention;

[0036] Figure 4A and Figure 4B : is a circuit schematic diagram of a second embodiment of a control signal unit in an embodiment of the present invention; wherein: Figure 4A The enabling subunit is shown. Figure 4B Shown is the control subunit;

[0037] Figure 5 A circuit schematic diagram of a multi-way selection switch provided by an embodiment of the present invention;

[0038] Figure 6 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] like Figure 1 As shown, an analog switch circuit provided by an embodiment of the present invention includes a switch unit, a first dynamic bias unit, a second dynamic bias unit and a control signal unit. Among them, the input terminal VIN of the switch unit is connected to the external analog signal input terminal; the first input terminal of the first dynamic bias unit is connected to the power supply voltage VPH terminal, the second input terminal is connected to the input terminal VIN of the switch unit, and the output terminal is connected to the first bias terminal of the switch unit; the first input terminal of the second dynamic bias unit is connected to the ground potential terminal, the second input terminal is connected to the input terminal VIN of the switch unit, and the output terminal is connected to the second bias terminal of the switch unit; the input terminal ON_IN of the control signal unit is connected to the system control signal terminal, and the output terminal is respectively connected to the control terminals of the switch unit, the first dynamic bias unit, and the second dynamic bias unit.

[0041] The control signal unit is used to generate a first control signal and a second control signal according to a system control signal, and provide the first control signal and the second control signal to the switch unit, the first dynamic bias unit and the second dynamic bias unit.

[0042] The switch unit is used to connect or disconnect the transmission path of the analog signal according to the first control signal and the second control signal.

[0043] The first dynamic bias unit is used to select an output voltage according to a first control signal and a second control signal to control a bias voltage of a first bias terminal of the switch unit in an on state and an off state.

[0044] The second dynamic bias unit is used to select an output voltage according to the first control signal and the second control signal to control the bias voltage of the second bias terminal of the switch unit in the on and off states.

[0045] When the analog switch circuit is switched on or off, the first dynamic bias unit and the second dynamic bias unit respectively perform corresponding voltage biases on the switch unit, thereby improving the working performance of the analog switch.

[0046] In one embodiment of the present invention, Figure 2 As shown, the control signal unit includes the tenth PMOS tube MPS0, the eleventh PMOS tube MPS1, the tenth NMOS tube MNS0, and the eleventh NMOS tube MNS1. The tenth PMOS tube MPS0 and the tenth NMOS tube MNS0 form a first inverter, and the eleventh PMOS tube MPS1 and the eleventh NMOS tube MNS1 form a second inverter; the input end of the first inverter is connected to the system control signal end, and the output end of the first inverter is connected to the input end of the second inverter.

[0047] The control signal unit generates a first control signal ON_B at the output end of the first inverter and generates a second control signal ON at the output end of the second inverter according to the input system control signal ON_IN. When the system control signal ON_IN is at a high level, the first control signal ON_B is at a low level and the second control signal ON is at a high level; when the system control signal ON_IN is at a low level, the first control signal ON_B is at a high level and the second control signal ON is at a low level.

[0048] In one embodiment of the present invention, the circuit structures of the switch unit, the first dynamic bias unit and the second dynamic bias unit are as follows: Figure 3 shown.

[0049] The switch unit includes a first PMOS tube MP0 and a first NMOS tube MN0. The source terminals of the first PMOS tube MP0 and the first NMOS tube MN0 are connected in parallel to serve as the input terminal VIN of the switch unit, and are respectively connected to the second input terminals of the first dynamic bias unit and the second dynamic bias unit; the drain terminals of the first PMOS tube MP0 and the first NMOS tube MN0 are connected in parallel to serve as the output terminal VOUT of the switch unit; the gate terminal of the first PMOS tube MP0 is connected to the first control signal ON_B terminal as the first control terminal, and the gate terminal of the first NMOS tube MN0 is connected to the second control signal ON terminal as the second control terminal; the body terminal of the first PMOS tube MP0 is connected to the output terminal of the first dynamic bias unit as the first bias terminal Sub_P; and the body terminal of the first NMOS tube MN0 is connected to the output terminal of the second dynamic bias unit as the second bias terminal Sub_N.

[0050] The first dynamic bias unit includes a second PMOS transistor MP1, a third PMOS transistor MP2 and a fourth NMOS transistor MN3. The source terminals of the third PMOS transistor MP2 and the fourth NMOS transistor MN3 are connected in parallel and connected to the input terminal of the switch unit as a second input terminal; the drain terminals of the third PMOS transistor MP2 and the fourth NMOS transistor MN3 and the drain terminal of the second PMOS transistor MP1 are connected in parallel and connected to the first bias terminal of the switch unit as an output terminal; the gate terminal of the third PMOS transistor MP2 is connected to the first control signal ON_B terminal, and the body terminal of the third PMOS transistor MP2 is connected to the power supply voltage VPH terminal; the gate terminal of the fourth NMOS transistor MN3 is connected to the second control signal ON terminal, and the body terminal of the fourth NMOS transistor MN3 is connected to the ground potential terminal; the gate terminal of the second PMOS transistor MP1 is connected to the second control signal ON terminal, and the body terminal and the source terminal of the second PMOS transistor MP1 are connected in parallel and connected to the power supply voltage VPH terminal as a first input terminal.

[0051] The second dynamic bias unit includes a fourth PMOS transistor MP3, a second NMOS transistor MN1, and a third NMOS transistor MN2. The source terminals of the fourth PMOS transistor MP3 and the third NMOS transistor MN2 are connected in parallel and connected to the input terminal of the switch unit as the second input terminal; the drain terminals of the fourth PMOS transistor MP3, the third NMOS transistor MN2, and the second NMOS transistor MN1 are connected in parallel and connected to the second bias terminal of the switch unit as the output terminal; the gate terminal of the fourth PMOS transistor MP3 is connected to the first control signal ON_B terminal, and the body terminal of the fourth PMOS transistor MP3 is connected to the power supply voltage VPH terminal; the gate terminal of the third NMOS transistor MN2 is connected to the second control signal ON terminal, and the body terminal of the third NMOS transistor MN2 is connected to the ground potential terminal; the gate terminal of the second NMOS transistor MN1 is connected to the first control signal ON_B terminal, and the body terminal of the second NMOS transistor MN1 is connected to the source terminal and connected in parallel as the first input terminal and connected to the ground potential terminal.

[0052] In the design of the analog switch circuit, the power supply voltage VPH is the highest voltage of the system, and the highest voltage VPH of the system needs to satisfy the condition of VPH ≥ VIN, that is, the power supply voltage VPH is not lower than the voltage amplitude of the transmitted analog signal.

[0053] When the analog switch circuit needs to connect the transmission path of the analog signal, the system control signal ON_IN is at a high level. At this time, the first control signal ON_B generated by the control signal unit is at a low level, and the second control signal ON is at a high level.

[0054] After the switch unit receives the first control signal ON_B and the second control signal ON, the gate terminal of the first PMOS tube MP0 is at a low level, so the first PMOS tube MP0 is in a conductive state; the gate terminal of the first NMOS tube MN0 is at a high level, so the first NMOS tube MN0 is also in a conductive state; the switch unit connects the analog signal transmission path.

[0055] At the same time, after the first dynamic bias unit receives the first control signal ON_B and the second control signal ON, the gate terminal of the third PMOS tube MP2 is at a low level, and the gate terminal of the fourth NMOS tube MN3 is at a high level, so the third PMOS tube MP2 and the fourth NMOS tube MN3 are both in the on state, which short-circuits the body terminal (i.e., the first bias terminal Sub_P) of the first PMOS tube MP0 in the switch unit to the input terminal VIN, so that the body terminal and the source terminal of the first PMOS tube MP0 have the same potential, so the first PMOS tube MP0 will not have a body effect phenomenon, and its threshold voltage will not change with the change of the input voltage. At the same time, the gate terminal of the second PMOS tube MP1 is at a high level, so the second PMOS tube MP1 is in a cut-off state, disconnecting the output path of the power supply voltage VPH. The first dynamic bias unit realizes biasing the voltage of the first bias terminal Sub_P of the switch unit to the voltage value of the input analog signal.

[0056] At the same time, after the second dynamic bias unit receives the first control signal ON_B and the second control signal ON, the gate terminal of the fourth PMOS tube MP3 is at a low level, and the gate terminal of the third NMOS tube MN2 is at a high level, so the fourth PMOS tube MP3 and the third NMOS tube MN2 are both in the on state, which short-circuits the body terminal (i.e., the second bias terminal Sub_N) of the first NMOS tube MN0 in the switch unit to the input terminal VIN, so that the body terminal and the source terminal of the first NMOS tube MN0 have the same potential, so the first NMOS tube MN0 will not have a body effect phenomenon, and its threshold voltage will not change with the change of the input voltage. At the same time, the gate terminal of the second NMOS tube MN1 is at a low level, so the second NMOS tube MN1 is in the off state, disconnecting the output path of the ground potential voltage. The second dynamic bias unit realizes biasing the voltage of the second bias terminal Sub_N of the switch unit to the voltage value of the input analog signal.

[0057] When the analog switch circuit is in the on state, the on resistance of the first PMOS tube MP0 is:

[0058]

[0059] Among them, μ p is the hole mobility, Cox is the gate capacitance, (W / L)p is the total width-to-length ratio of the first PMOS tube MP0, V IN is the input voltage, V THP is the threshold voltage of the first PMOS tube MP0.

[0060] The on-resistance of the first NMOS tube MN0 is:

[0061]

[0062] Among them, μ n is the hole mobility, Cox is the gate capacitance, (W / L)n is the total width-to-length ratio of the NMOS tube, V IN is the input voltage, V THN is the threshold voltage of the first NMOS transistor MN0, and VPH is the power supply voltage.

[0063] The total on-resistance R of the analog switch circuit on =R on，p / / R on，n It can be seen from formulas (1) and (2) that since the body terminal and source terminal potentials of the first PMOS tube MP0 are the same, the body terminal and source terminal potentials of the first NMOS tube MN0 are also the same, that is, Vb=Vs. Therefore, the change of the body terminal bias voltage of the first PMOS tube MP0 and the first NMOS tube MN0 has no effect on the on-resistance.

[0064] When the analog switch circuit needs to disconnect the transmission path of the analog signal, the system control signal ON_IN is at a low level. At this time, the first control signal ON_B generated by the control signal unit is at a high level, and the second control signal ON is at a low level.

[0065] After the switch unit receives the first control signal ON_B and the second control signal ON, the gate terminal of the first PMOS tube MP0 is at a high level, so the first PMOS tube MP0 is in a cut-off state; the gate terminal of the first NMOS tube MN0 is at a low level, so the first NMOS tube MN0 is also in a cut-off state; the switch unit disconnects the analog signal transmission path.

[0066] At the same time, after the first dynamic bias unit receives the first control signal ON_B and the second control signal ON, the gate terminal of the third PMOS tube MP2 is at a high level, and the gate terminal of the fourth NMOS tube MN3 is at a low level, so the third PMOS tube MP2 and the fourth NMOS tube MN3 are both in a cut-off state, so that the first bias terminal Sub_P of the switch unit is disconnected from the analog signal input terminal; at the same time, the gate terminal of the second PMOS tube MP1 is at a low level, so the second PMOS tube MP1 is in a conducting state, which short-circuits the body terminal (i.e., the first bias terminal Sub_P) of the first PMOS tube MP0 in the switch unit with the power supply voltage VPH terminal. Since the system maximum voltage VPH satisfies VPH≥VIN, the body terminal voltage of the first PMOS tube MP0 is greater than the source terminal voltage, so that the first PMOS tube MP0 has no conduction path and does not generate leakage current. The first dynamic bias unit realizes biasing the voltage of the first bias terminal Sub_P of the switch unit to the power supply voltage VPH.

[0067] At the same time, after the second dynamic bias unit receives the first control signal ON_B and the second control signal ON, the gate terminal of the fourth PMOS tube MP3 is at a high level, and the gate terminal of the third NMOS tube MN2 is at a low level, so the fourth PMOS tube MP3 and the third NMOS tube MN2 are both in a cut-off state, so that the second bias terminal Sub_N of the switch unit is disconnected from the analog signal input terminal; at the same time, the gate terminal of the second NMOS tube MN1 is at a high level, so the second NMOS tube MN1 is in a conducting state, which short-circuits the body terminal (i.e., the second bias terminal Sub_N) of the first NMOS tube MN0 in the switch unit to the ground potential terminal. Since the voltage value VIN of the input analog signal is ≥ GND (ground potential), the source terminal voltage of the first NMOS tube MN0 is greater than the body terminal voltage, so that the first NMOS tube MN0 has no conduction path and does not generate leakage current. The second dynamic bias unit realizes biasing the voltage of the second bias terminal Sub_N of the switch unit to the ground potential voltage.

[0068] In summary, the analog switch circuit provided by the embodiment of the present invention performs different voltage biases on the switch unit through the first dynamic bias unit and the second dynamic bias unit, so that when the analog switch circuit is in the on state, the first PMOS tube MP0 and the first NMOS tube MN0 of the switch unit will not have body effect phenomenon, and their threshold voltage will not change with the change of input voltage; when the analog switch circuit is in the off state, the first PMOS tube MP0 and the first NMOS tube MN0 of the switch unit are both in the off state, and no leakage current is generated in the circuit. While achieving fast on-off switching, the working performance of the analog switch is greatly improved.

[0069] It should be noted that in other embodiments of the present invention, the first dynamic bias unit, the second dynamic bias unit and the control signal unit can adopt other circuit structures or existing technical structures to achieve corresponding functions, and the present invention does not limit the specific circuit structure of each unit. For example, in an application scenario where the swing of the system control signal is significantly different from the swing of the system maximum voltage VPH, assuming that the system control voltage VDD is 1.8V and the system maximum voltage VPH is 5V, the control signal unit can adopt the following Figure 4A and Figure 4B The circuit structure of the second embodiment is shown. In the second embodiment, the control signal unit includes an enabling subunit and a control subunit; wherein the enabling subunit is used to generate an enabling signal OE and its inverse signal OEN; and the control subunit is used to generate a first control signal ON_B and a second control signal ON.

[0070] like Figure 4AAs shown, the enabling subunit includes a twelfth PMOS tube MPS2, a thirteenth PMOS tube MPS3, a fourteenth PMOS tube MPS4, a fifteenth PMOS tube MPS5 and a twelfth NMOS tube MNS2, as well as a third inverter Inv0 and a fourth inverter Inv1. Among them, the gate terminals of the twelfth PMOS tube MPS2, the thirteenth PMOS tube MPS3, the fourteenth PMOS tube MPS4, the fifteenth PMOS tube MPS5 and the twelfth NMOS tube MNS2 are all connected to the system control voltage VDD terminal; the drain terminals and source terminals of the twelfth PMOS tube MPS2, the thirteenth PMOS tube MPS3, the fourteenth PMOS tube MPS4 and the fifteenth PMOS tube MPS5 are connected in series in sequence, the source terminal of the fifteenth PMOS tube MPS5 is connected to the system highest voltage VPH terminal, the drain terminal of the twelfth PMOS tube MPS2 is connected to the drain terminal of the twelfth NMOS tube MNS2 and the input terminal of the third inverter Inv0, and the source terminal of the twelfth NMOS tube MNS2 is connected to the ground potential terminal GND; the output terminal of the third inverter Inv0 is connected to the output terminal of the enable signal OE and the input terminal of the fourth inverter Inv1, and the output terminal of the fourth inverter Inv1 is connected to the output terminal of the inverse signal OEN of the enable signal OE.

[0071] Since the system control voltage VDD is less than the system maximum voltage VPH, the twelfth PMOS tube MPS2, the thirteenth PMOS tube MPS3, the fourteenth PMOS tube MPS4, the fifteenth PMOS tube MPS5 and the twelfth NMOS tube MNS2 are all turned on, and the input end of the third inverter Inv0 is at a low level. Therefore, the enable signal OE is at a high level, and the inverse signal OEN of the enable signal OE is at a low level, and both are provided to the control subunit as enable signals. Among them, the number of PMOS tubes connected in series can be adjusted according to the realization of VDD and VPH.

[0072] like Figure 4BAs shown, the control subunit includes a sixteenth PMOS tube MPS6, a seventeenth PMOS tube MPS7, a thirteenth NMOS tube MNS3, a fourteenth NMOS tube MNS4, a fifteenth NMOS tube MNS5, a sixteenth NMOS tube MNS6, a seventeenth NMOS tube MNS7, a first NOR gate Nor and a fifth inverter Inv2. Among them, the gate of the thirteenth NMOS tube MNS3 is connected to the inverted signal ON_INB terminal of the system control signal ON_IN, the source terminal is connected to the ground potential terminal, and the drain terminal is connected to the source terminal of the fifteenth PMOS tube MPS5; the gate terminal of the fifteenth PMOS tube MPS5 is connected to the enable signal OE terminal, and the drain terminal is connected to the drain terminal of the sixteenth PMOS tube MPS6, the gate terminal of the seventeenth PMOS tube MPS7, and the drain terminal of the seventeenth NMOS tube MNS7; the gate terminal of the seventeenth NMOS tube MNS7 is connected to the inverted signal OEN terminal of the enable signal OE, and the source terminal is connected to the ground potential terminal GND; the source terminals of the sixteenth PMOS tube MPS6 and the seventeenth PMOS tube MPS7 are both connected to the system highest voltage VPH The gate terminal of the fourteenth NMOS tube MNS4 is connected to the system control signal ON_IN terminal, the source terminal is connected to the ground potential terminal, and the drain terminal is connected to the source terminal of the sixteenth NMOS tube MNS6; the gate terminal of the sixteenth NMOS tube MNS6 is connected to the enable signal OE terminal, and the drain terminal is connected to the gate terminal of the sixteenth PMOS tube MPS6, the drain terminal of the seventeenth PMOS tube MPS7 and the first input terminal of the first NOR gate Nor; the second input terminal of the first NOR gate Nor is connected to the inverted signal OEN terminal of the enable signal OE, and the output terminal is connected to the output terminal of the second control signal ON and the input terminal of the fifth inverter Inv2; the output terminal of the fifth inverter Inv2 is connected to the output terminal of the first control signal ON_B.

[0073] The enable signal OE provided by the enable subunit is at a high level, and the inverse signal OEN of the enable signal OE is at a low level. When the system control signal ON_IN is at a high level and its inverse signal ON_INB is at a low level, the fourteenth NMOS tube MNS4, the fifteenth NMOS tube MNS5 and the sixteenth NMOS tube MNS6 are turned on, and the thirteenth NMOS tube MNS3 and the seventeenth NMOS tube MNS7 are turned off. Therefore, the first input end of the first NOR gate Nor is at a low level, so that the seventeenth PMOS tube MPS7 is turned off after the sixteenth PMOS tube MPS6 is turned on; the second input end of the first NOR gate Nor is also at a low level (OEN), so the output end of the first NOR gate Nor is at a high level, that is, the second control signal ON is at a high level, and the first control signal ON_B is at a low level. Similarly, when the system control signal ON_IN is at a low level, the first control signal ON_B is at a high level, and the second control signal ON is at a low level.

[0074] In addition, the analog switch circuit provided in the embodiment of the present invention can also be combined to form a multi-way selection switch to implement selection and switching operations on multiple analog signals or power supply voltages with different voltage amplitudes.

[0075] like Figure 5 As shown, a multi-way selection switch provided by an embodiment of the present invention includes at least two analog switches (SW_0, SW_1...SW_i), wherein the input end of each analog switch is respectively connected to an analog signal input end, and the output end of each analog switch is connected in parallel to serve as the output end of the multi-way selection switch. The input analog signal may also be a power supply voltage signal, and the voltage amplitudes VIN_0, VIN_1...VIN_i of multiple analog signals may be the same or different. Under the condition that the voltage amplitudes of multiple analog signals are less than or equal to the highest voltage VPH of the system, the multi-way selection switch can realize the selective output of multiple analog signals with high working performance and high flexibility, and each path will not have a body effect phenomenon, and will not generate leakage current. It is suitable for lossless transmission or selective switching application scenarios of multiple analog signals with different amplitudes.

[0076] Based on the above-mentioned analog switch circuit, an embodiment of the present invention further provides an electronic device, which includes the above-mentioned analog switch circuit, and the analog switch circuit is used to connect or disconnect the transmission path of the analog signal; and when multiple analog switch circuits are included, the selection output of multiple analog signals or power supply voltages can also be realized in a combined form.

[0077] In one embodiment of the present invention, Figure 6 As shown, the electronic device at least includes a processor, a memory and an analog switch circuit, and the analog switch circuit can be integrated in the corresponding functional unit; according to actual needs, the electronic device can further include a communication component, a sensor component, a power component, a multimedia component and an input / output interface. Among them, the memory, the communication component, the sensor component, the power component, the multimedia component and the input / output interface are all connected to the processor. The memory can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. can all be implemented using general components, which will not be specifically described here.

[0078] In summary, compared with the prior art, the analog switch circuit provided by the present invention improves the working performance of the analog switch circuit in the on or off state by adopting the technical solution of the first dynamic bias unit and the second dynamic bias unit to perform voltage bias on the switch unit respectively. When the analog switch circuit is in the on state, there will be no changes in the switch threshold voltage and on-resistance due to the body effect; the analog switch circuit will not generate leakage current in the off state. At the same time, by forming a multi-way selection switching switch in a combined form, the selective transmission of multiple analog signals of different amplitudes can be realized. Therefore, the analog switch circuit provided by the present invention has the beneficial effects of ingenious and reasonable circuit design, low design cost, high flexibility, and excellent working performance.

[0079] It should be noted that the above embodiments are only examples, and the technical solutions of the various embodiments can be combined, all within the protection scope of the present invention.

[0080] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0081] The above is a detailed description of the analog switch circuit, multi-way selection switch and electronic device provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. An analog switch circuit, characterized in that It includes a switch unit, a first dynamic bias unit, a second dynamic bias unit and a control signal unit; wherein, The switch unit is used to connect or disconnect the transmission path of the analog signal according to the first control signal and the second control signal; the input end of the switch unit is connected to the external analog signal end; The first dynamic bias unit is configured to select an output voltage according to the first control signal and the second control signal to control the bias voltage of the first bias terminal of the switch unit; a first input terminal of the first dynamic bias unit is connected to a power supply voltage terminal, a second input terminal is connected to an input terminal of the switch unit, and an output terminal is connected to the first bias terminal of the switch unit; The second dynamic bias unit is configured to select an output voltage according to the first control signal and the second control signal to control the bias voltage of the second bias terminal of the switch unit; the first input terminal of the second dynamic bias unit is connected to the ground potential terminal, the second input terminal is connected to the input terminal of the switch unit, and the output terminal is connected to the second bias terminal of the switch unit; The control signal unit is configured to generate the first control signal and the second control signal according to the system control signal, and provide the first control signal and the second control signal to the switch unit, the first dynamic bias unit, and the second dynamic bias unit; an input end of the control signal unit is connected to the system control signal end, and an output end of the control signal unit is connected to the control ends of the switch unit, the first dynamic bias unit, and the second dynamic bias unit, respectively; When the analog switch circuit performs an on-or off operation, the first dynamic bias unit and the second dynamic bias unit respectively perform corresponding voltage bias on the switch unit.

2. The analog switch circuit according to claim 1, wherein: The switch unit includes a first PMOS tube and a first NMOS tube; wherein, The source terminals of the first PMOS transistor and the first NMOS transistor are connected in parallel and serve as the input terminal of the switch unit, and are also connected to the second input terminals of the first dynamic bias unit and the second dynamic bias unit respectively; the drain terminals of the first PMOS transistor and the first NMOS transistor are connected in parallel and serve as the output terminal of the switch unit; the gate terminal of the first PMOS transistor serves as the first control terminal and is connected to the first control signal terminal, and the gate terminal of the first NMOS transistor serves as the second control terminal and is connected to the second control signal terminal; the body terminal of the first PMOS transistor serves as the first bias terminal and is connected to the output terminal of the first dynamic bias unit; and the body terminal of the first NMOS transistor serves as the second bias terminal and is connected to the output terminal of the second dynamic bias unit.

3. The analog switch circuit according to claim 1, wherein: The first dynamic bias unit includes a second PMOS transistor, a third PMOS transistor and a fourth NMOS transistor; wherein, The source terminals of the third PMOS transistor and the fourth NMOS transistor are connected in parallel and connected to the input terminal of the switch unit as a second input terminal; the drain terminals of the third PMOS transistor, the fourth NMOS transistor, and the drain terminal of the second PMOS transistor are connected in parallel and connected to the first bias terminal of the switch unit as an output terminal; the gate terminal of the third PMOS transistor is connected to the first control signal terminal, and the body terminal of the third PMOS transistor is connected to the power supply voltage terminal; the gate terminal of the fourth NMOS transistor is connected to the second control signal terminal, and the body terminal of the fourth NMOS transistor is connected to the ground potential terminal; the gate terminal of the second PMOS transistor is connected to the second control signal terminal, and the body terminal and source terminal of the second PMOS transistor are connected in parallel and connected to the power supply voltage terminal as a first input terminal.

4. The analog switch circuit according to claim 1, wherein: The second dynamic bias unit includes a fourth PMOS transistor, a second NMOS transistor, and a third NMOS transistor; wherein, The source terminals of the fourth PMOS transistor and the third NMOS transistor are connected in parallel and connected to the input terminal of the switch unit as a second input terminal; the drain terminals of the fourth PMOS transistor, the third NMOS transistor and the second NMOS transistor are connected in parallel and connected to the second bias terminal of the switch unit as an output terminal; the gate terminal of the fourth PMOS transistor is connected to the first control signal terminal, and the body terminal of the fourth PMOS transistor is connected to the power supply voltage terminal; the gate terminal of the third NMOS transistor is connected to the second control signal terminal, and the body terminal of the third NMOS transistor is connected to the ground potential terminal; the gate terminal of the second NMOS transistor is connected to the first control signal terminal, and the body terminal and source terminal of the second NMOS transistor are connected in parallel and connected to the ground potential terminal as a first input terminal.

5. The analog switch circuit according to claim 1, wherein: The control signal unit includes a tenth PMOS transistor, an eleventh PMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor; wherein, The tenth PMOS transistor and the tenth NMOS transistor form a first inverter, and the eleventh PMOS transistor and the eleventh NMOS transistor form a second inverter; the input end of the first inverter is connected to the system control signal end, and the output end of the first inverter is connected to the input end of the second inverter.

6. The analog switch circuit according to claim 1, wherein: When the analog switch circuit is in an on state, the first dynamic bias unit biases the first bias terminal voltage of the switch unit to the input analog signal voltage; the second dynamic bias unit biases the second bias terminal voltage of the switch unit to the input analog signal voltage.

7. The analog switch circuit according to claim 1, wherein: When the analog switch circuit is in an off state, the first dynamic bias unit biases the voltage of the first bias terminal of the switch unit to the power supply voltage; and the second dynamic bias unit biases the voltage of the second bias terminal of the switch unit to the ground potential voltage.

8. The analog switch circuit according to claim 6 or 7, wherein: The power supply voltage must not be lower than the input analog signal voltage.

9. The analog switch circuit according to claim 1, wherein: The control signal unit includes an enabling subunit and a controlling subunit; wherein the enabling subunit is used to generate an enabling signal and its inverse signal; and the controlling subunit is used to generate a first control signal and a second control signal.

10. The analog switch circuit according to claim 9, wherein: The enabling subunit includes a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, and a twelfth NMOS transistor, as well as a third inverter and a fourth inverter; wherein the gate terminals of the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor, and the twelfth NMOS transistor are all connected to the system control voltage terminal; the drain terminals and source terminals of the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, and the fifteenth PMOS transistor are connected in series in sequence, the source terminal of the fifteenth PMOS transistor is connected to the system highest voltage terminal, the drain terminal of the twelfth PMOS transistor is connected to the drain terminal of the twelfth NMOS transistor and the input terminal of the third inverter, and the source terminal of the twelfth NMOS transistor is connected to the ground potential terminal; the output terminal of the third inverter is connected to the output terminal of the enable signal and the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the output terminal of the inverse signal of the enable signal.

11. The analog switch circuit according to claim 9, wherein: The control subunit includes a sixteenth PMOS transistor, a seventeenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, a first NOR gate, and a fifth inverter; wherein the gate of the thirteenth NMOS transistor is connected to the inverted signal terminal of the system control signal, the source terminal is connected to the ground potential terminal, and the drain terminal is connected to the source terminal of the fifteenth PMOS transistor; the gate terminal of the fifteenth PMOS transistor is connected to the enable signal terminal, and the drain terminal is connected to the drain terminal of the sixteenth PMOS transistor, the gate terminal of the seventeenth PMOS transistor, and the drain terminal of the seventeenth NMOS transistor; the gate terminal of the seventeenth NMOS transistor is connected to the inverted signal terminal of the enable signal , the source end is connected to the ground potential end; the source ends of the sixteenth PMOS tube and the seventeenth PMOS tube are both connected to the system highest voltage end; the gate end of the fourteenth NMOS tube is connected to the system control signal end, the source end is connected to the ground potential end, and the drain end is connected to the source end of the sixteenth NMOS tube; the gate end of the sixteenth NMOS tube is connected to the enable signal end, the drain end is connected to the gate end of the sixteenth PMOS tube, the drain end of the seventeenth PMOS tube and the first input end of the first NOR gate; the second input end of the first NOR gate is connected to the inverted signal end of the enable signal, the output end is connected to the output end of the second control signal and the input end of the fifth inverter; the output end of the fifth inverter is connected to the output end of the first control signal.

12. A multi-way selection switch, characterized in that The analog switch circuit comprises at least two of any one of claims 1 to 11; wherein, The input end of each analog switch circuit is connected to an analog signal input end respectively, and the output ends of each analog switch circuit are connected in parallel to serve as the output end of the multi-way selection switch.

13. An electronic device, characterized in that The analog switch circuit comprises the analog switch circuit according to any one of claims 1 to 11.

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