Successive approximation sampling method and device applied to equivalent sampling system

Abstract

The invention discloses a successive approximation sampling method and device applied to an equivalent sampling system. The successive approximation sampling method comprises the following steps that S1, sampling pulses output by a time base module are fanned out into three paths of signals; s2, the MCU generates an initial control word and writes the initial control word into a DAC chip, and an output voltage is generated in the DAC chip; s3, the output voltage of the DAC is transmitted to the reference signal input end VREF of the comparator, and the analog input voltage to be sampled is transmitted to the signal input end VIN of the comparator; s4, under the control of three paths of signals output by the fan-out device, the comparator outputs a stable level signal to be received by the D trigger, and the MCU reads an output signal of the D trigger and then stores the output signal into a shift register in the MCU; s5, the MCU generates a DAC control word according to the stored signal until the shift register is fully stored or reaches a preset bit number; and S6, changing the delay amount of the sampling pulse output by the time base module, and completing the sampling of all sampling points. The method can be applied to a high-bandwidth equivalent sampling system, and meets the high-resolution requirement of the equivalent sampling system.

Description

Technical Field

[0001] The present invention relates to an ADC sampling method and system, and in particular to a successive approximation sampling method and device applied to an equivalent sampling system. Background Art

[0002] Equivalent sampling is a sampling method that collects samples and reconstructs the waveform within multiple repetition cycles of the measured signal. This sampling method can use a lower sampling rate analog-to-digital converter to achieve data acquisition of high-frequency signals. Traditional equivalent sampling systems must use additional sample-and-hold circuits when collecting high-bandwidth signals, and high-bandwidth sample-and-hold circuits are very expensive, making the cost of the entire sampling system high. In addition, high-bandwidth sample-and-hold circuits have high requirements for the sampling rate of the back-end analog-to-digital converter.

[0003] Successive-Approximation Analog to Digital Converter (SAR-ADC) is a commonly used A / D conversion structure that can achieve extremely high-resolution sampling. The resolution and sampling rate of this type of ADC are contradictory. When the resolution is low, the sampling rate is high. To improve the resolution, the sampling rate will be limited. SAR-ADC is generally not applicable to high-bandwidth sampling systems, which brings many inconveniences to the equivalent sampling system when collecting high-bandwidth signals. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a successive approximation sampling method and device applied to an equivalent sampling system, which can be applied to a high-bandwidth equivalent sampling system and can adapt to the high-resolution requirements of the equivalent sampling system.

[0005] The object of the present invention is achieved through the following technical scheme: a successive approximation sampling method applied to an equivalent sampling system, which performs successive approximation sampling based on the sampling pulse output by the time base module in the equivalent sampling system, comprising the following steps:

[0006] S1. Fan out the sampling pulse output by the time base module of the equivalent sampling system into three signals, which are respectively used as the comparator latch clock LE_CLK, the D-type flip-flop clock signal D_CLK and the MCU sampling clock signal MCU_CLK, and MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK;

[0007] S2. In the initial state, the MCU generates the initial control word DAC_data1 and writes it into the DAC chip. In the DAC chip, the reference voltage V ref Generates output voltage V dac1 :

[0008]

[0009] DAC_data1 = 2 n-1

[0010] Where n is the resolution of the DAC;

[0011] S3. The output voltage of the DAC is transmitted to the reference signal input terminal VREF of the comparator, and the analog input voltage to be sampled is transmitted to the signal input terminal VIN of the comparator;

[0012] S4. When the comparator latch clock signal LE_CLK is valid, the comparator outputs a stable level signal; when the D flip-flop clock signal D_CLK is valid, the D flip-flop receives the stable level signal, and the MCU reads the output signal of the D flip-flop when the sampling clock is valid and stores the signal in the shift register inside the MCU;

[0013] S5. MCU generates a DAC control word according to the signal stored in the shift register, controls the DAC output voltage value, and then repeats steps S3 to S4; until the shift register is full or the preset number of bits has been reached, at which time, the sampling result of the analog input signal at the first sampling point is obtained;

[0014] S6. Change the delay amount of the sampling pulse output by the time base module, and repeat steps S2-S5 until the sampling of all sampling points is completed.

[0015] A successive approximation sampling device applied to an equivalent sampling system, the device comprising a fan-out device, an MCU, a DAC, a comparator and a D flip-flop;

[0016] The output end of the MCU is connected to the control input end of the DAC, the reference signal input port of the DAC is used to receive an external reference signal, the output end of the DAC is connected to the reference signal input end of the comparator, the signal input end of the comparator is used to input an analog input voltage to be sampled, the output end of the comparator is connected to a D flip-flop, and the output end of the D flip-flop is connected to the MCU;

[0017] The fan-out device is used to fan out the sampling pulse output by the time base module of the equivalent sampling system into three signals, which are respectively used as the comparator latch clock LE_CLK, the D-type flip-flop clock signal D_CLK and the sampling clock signal MCU_CLK of the microprocessor, and MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK. The fan-out device is connected to the comparator, the D-type flip-flop and the MCU through signal lines, and the delay is adjusted by using signal lines of different lengths, so that MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK.

[0018] The beneficial effects of the present invention are as follows: when the resolution is improved, the sampling rate will not be limited, the present invention can be applied to a high-bandwidth equivalent sampling system, and can adapt to the high-resolution requirements of the equivalent sampling system, and has low cost, high sampling resolution, and a larger sampling bandwidth than a finished SAR-ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a flow chart of the method of the present invention;

[0020] Figure 2 It is a schematic diagram of the device principle of the present invention. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0022] like Figure 1 As shown, a successive approximation sampling method applied to an equivalent sampling system performs successive approximation sampling based on a sampling pulse output by a time base module in the equivalent sampling system, comprising the following steps:

[0023] S1. Fan out the sampling pulse output by the time base module of the equivalent sampling system into three signals, which are respectively used as the comparator latch clock LE_CLK, the D-type flip-flop clock signal D_CLK and the microprocessor sampling clock signal MCU_CLK, and MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK;

[0024] S2. In the initial state, the MCU generates the initial control word DAC_data1 and writes it into the DAC chip. In the DAC chip, the reference voltage V ref Generates output voltage V dac1 :

[0025]

[0026] DAC_data1 = 2 n-1

[0027] Where n is the resolution of the DAC;

[0028] S3. The output voltage of the DAC is transmitted to the reference signal input terminal VREF of the comparator, and the analog input voltage to be sampled is transmitted to the signal input terminal VIN of the comparator;

[0029] S4. When the comparator latch clock signal LE_CLK is valid, the comparator outputs a stable level signal; when the D flip-flop clock signal D_CLK is valid, the D flip-flop receives the stable level signal, and the MCU reads the output signal of the D flip-flop when the sampling clock is valid and stores the signal in the shift register inside the MCU;

[0030] S5. MCU generates a DAC control word according to the signal stored in the shift register, controls the DAC output voltage value, and then repeats steps S3 to S4; until the shift register is full or the preset number of bits has been reached, at which time, the sampling result of the analog input signal at the first sampling point is obtained;

[0031] S6. Change the delay amount of the sampling pulse output by the time base module, and repeat steps S2-S5 until the sampling of all sampling points is completed.

[0032] When the latch clock signal LE_CLK is invalid, the comparator starts to compare the signals at the signal input terminal VIN and the reference signal input terminal VREF and outputs the comparison result. When the latch clock signal LE_CLK is valid, the comparator keeps outputting the comparison result as a stable level signal.

[0033] In step S4, the MCU generates a DAC control word according to the signal stored in the shift register, and controlling the DAC output voltage value includes the following sub-steps:

[0034] S401. When the first read clock is valid, the MCU reads the output D1 of the D flip-flop for the first time, and changes the control word of the DAC to:

[0035] DAC_data2 = 2 n-1 D1+2 n-2

[0036] This changes the DAC's voltage output to:

[0037]

[0038] S402. When the second read clock is valid, the MCU reads the output D2 of the D flip-flop read for the first time, and changes the control word of the DAC to:

[0039] DAC_data3 = 2 n-1 D1+2 n-2 D2+2 n-3

[0040] This changes the DAC's voltage output to:

[0041]

[0042] S403. The MCU repeats the change of the DAC output voltage by adjusting the control word when each read clock is valid, until the n-1th read clock is valid, and then changes the DAC control word to:

[0043] DAC_datan=2 n-1 D1+2 n-2 D2+2 n-3 ·D3+...+2 1 ·D n-1 +2 0

[0044] This changes the DAC output voltage to:

[0045]

[0046] In step S4, when the shift register is full or has reached the preset number of bits, the MCU reads n sampling clocks, and reads the last comparison result D when the nth reading clock is valid. n , then the digital value of the sampling result of the analog input signal at the first sampling point is:

[0047]

[0048] like Figure 2 As shown, a successive approximation sampling device applied to an equivalent sampling system includes a fan-out device, an MCU, a DAC, a comparator and a D flip-flop;

[0049] The output end of the MCU is connected to the control input end of the DAC, the reference signal input port of the DAC is used to receive an external reference signal, the output end of the DAC is connected to the reference signal input end of the comparator, the signal input end of the comparator is used to input an analog input voltage to be sampled, the output end of the comparator is connected to a D flip-flop, and the output end of the D flip-flop is connected to the MCU;

[0050] The fan-out device is used to fan out the sampling pulse output by the time base module of the equivalent sampling system into three signals, which are respectively used as the comparator latch clock LE_CLK, the D-type flip-flop clock signal D_CLK and the sampling clock signal MCU_CLK of the MCU, and MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK. In an embodiment of the present application, the fan-out device is connected to the comparator, the D-type flip-flop and the MCU through a signal line, and the delay is adjusted by using signal lines of different lengths so that MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK.

[0051] The above description shows and describes a preferred embodiment of the present invention, but as mentioned above, it should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the invention concept described herein through the above teachings or the technology or knowledge of the relevant field. And the changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A successive approximation sampling method applied to an equivalent sampling system, which performs successive approximation sampling based on a sampling pulse output by a time base module in the equivalent sampling system, and is characterized by: The following steps are involved: S1. Fan out the sampling pulse output by the time base module of the equivalent sampling system into three signals, which are respectively used as the comparator latch clock LE_CLK, the D-type flip-flop clock signal D_CLK and the MCU sampling clock signal MCU_CLK, and MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK; S2. In the initial state, the MCU generates the initial control word DAC_data1 and writes it into the DAC chip. In the DAC chip, the reference voltage V ref Generates output voltage V dac1 : DAC_data1=2 n-1 Where n is the resolution of the DAC; S3. The output voltage of the DAC is transmitted to the reference signal input terminal VREF of the comparator, and the analog input voltage to be sampled is transmitted to the signal input terminal VIN of the comparator; S4. When the comparator latch clock signal LE_CLK is valid, the comparator outputs a stable level signal; when the D flip-flop clock signal D_CLK is valid, the D flip-flop receives the stable level signal, and the MCU reads the output signal of the D flip-flop when the sampling clock is valid and stores the signal in the shift register inside the MCU; S5. MCU generates a DAC control word according to the signal stored in the shift register, controls the DAC output voltage value, and then repeats steps S3 to S4; until the shift register is full or the preset number of bits has been reached, at which time, the sampling result of the analog input signal at the first sampling point is obtained; S6. Change the delay amount of the sampling pulse output by the time base module, and repeat steps S2-S5 until the sampling of all sampling points is completed.

2. The successive approximation sampling method applied to an equivalent sampling system according to claim 1, characterized in that: When the latch clock signal LE_CLK is invalid, the comparator starts to compare the signals at the signal input terminal VIN and the reference signal input terminal VREF and outputs the comparison result. When the latch clock signal LE_CLK is valid, the comparator keeps outputting the comparison result as a stable level signal.

3. The successive approximation sampling method applied to an equivalent sampling system according to claim 1, characterized in that: In step S4, the MCU generates a DAC control word according to the signal stored in the shift register, and controlling the DAC output voltage value includes the following sub-steps: S401. When the first read clock is valid, the MCU reads the output D1 of the D flip-flop for the first time, and changes the control word of the DAC to: DAC_data2=2 n-1 ·D1+2 n-2 This changes the DAC's voltage output to: S402. When the second read clock is valid, the MCU reads the output D2 of the D flip-flop read for the first time, and changes the control word of the DAC to: DAC_data3=2 n-1 ·D1+2 n-2 ·D2+2 n-3 This changes the DAC's voltage output to: S403. The MCU repeats the change of the DAC output voltage by adjusting the control word when each read clock is valid, until the n-1th read clock is valid, and then changes the DAC control word to: <h2 style=";text-align:left;direction:ltr">DAC_data = 2<h2 style=";text-align:left;direction:ltr"> n-1 <h2 style=";text-align:left;direction:ltr"> D1+2<h2 style=";text-align:left;direction:ltr"> n-2 <h2 style=";text-align:left;direction:ltr"> D2+2<h2 style=";text-align:left;direction:ltr"> n-3 <h2 style=";text-align:left;direction:ltr"> D3+...+2<h2 style=";text-align:left;direction:ltr"> 1 <h2 style=";text-align:left;direction:ltr"> ·D<h2 style=";text-align:left;direction:ltr"> n-1 <h2 style=";text-align:left;direction:ltr"> +2<h2 style=";text-align:left;direction:ltr"> 0 This changes the DAC output voltage to: When the shift register is full or has reached the preset number of bits, the MCU reads n sampling clocks and reads the last comparison result D when the nth reading clock is valid. n , then the digital value of the sampling result of the analog input signal at the first sampling point is:

4. A successive approximation sampling device applied to an equivalent sampling system, based on the method according to any one of claims 1 to 3, characterized in that: The device includes a fan-out device, an MCU, a DAC, a comparator and a D flip-flop; The output end of the MCU is connected to the control input end of the DAC, the reference signal input port of the DAC is used to receive an external reference signal, the output end of the DAC is connected to the reference signal input end of the comparator, the signal input end of the comparator is used to input an analog input voltage to be sampled, the output end of the comparator is connected to a D flip-flop, and the output end of the D flip-flop is connected to the MCU; The fan-out device is used to fan out the sampling pulse output by the time base module of the equivalent sampling system into three signals, which are respectively used as the comparator latch clock LE_CLK, the D-type flip-flop clock signal D_CLK and the MCU sampling clock signal MCU_CLK, and MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK.

5. The successive approximation sampling device applied to an equivalent sampling system according to claim 4, characterized in that: The fan-out device is connected to the comparator, the D flip-flop and the MCU through signal lines. The delay is adjusted by using signal lines of different lengths so that MCU_CLK lags behind D_CLK, and D_CLK lags behind LE_CLK.

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