RS485 bus automatic transceiver control device and computing equipment

By designing a strobe signal control module and a receiving timing control module in the FPGA chip, the strobe signal output of the RS485 bus interface is automatically controlled, which solves the problem of manual control of the strobe signal in the existing technology, realizes automatic switching of data transmission and reception of the RS485 bus interface, and improves data transmission efficiency and reliability.

CN119172197BActive Publication Date: 2025-09-26TIANJIN JINHANG COMP TECH RES INST
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
CN202411475216.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-10-22
Publication Date
2025-09-26
Estimated Expiration
2044-10-22

AI Technical Summary

Technical Problem

The existing RS485 bus interface requires manual control of the high and low levels of the selection signal when sending and receiving data, and cannot directly send and receive data like other serial ports.

Method used

An RS485 bus automatic transceiver control device is designed. By introducing a strobe signal control module and a receiving timing control module into the FPGA chip, the strobe signal output of the RS485 bus interface is automatically controlled to achieve automatic switching of data transmission and reception.

Benefits of technology

It realizes the automatic switching of data transmission and reception of RS485 bus interface, simplifies the data transmission process, and improves the data transmission efficiency and reliability.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN119172197B_ABST
    Figure CN119172197B_ABST
Patent Text Reader

Abstract

The present application discloses an RS485 bus automatic transceiver control device and computing equipment, relating to the field of communication technology. The device includes: a selector, a strobe signal control module, and a receive timing control module. The strobe signal control module has internal functions including buffering and sending UART transmit signals, RS485 start transmission detection, and an RS485 strobe signal control state machine. RS485 data is sent and received by switching between different states through the state machine. The selector outputs different UART transmit signals based on the RS485 receive enable signal sent by the strobe signal control module. The receive timing control module sends a data reception completion signal to the strobe signal control module based on the UART transmit signal and baud rate. The method realizes automatic switching of data transmission and reception by designing a strobe signal control module in an FPGA chip to automatically control the output of the strobe signal of the RS485 bus interface.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an RS485 bus automatic transceiver control device and computing equipment. Background Art

[0002] The RS485 bus interface is a communication interface widely used in industry. It generally includes a UART controller and an RS485 transceiver. The UART controller outputs the RS485_tx signal, RS485_rx signal, and RS485_de signal, and transmits these three signals to the RS485 transceiver. The de signal is a selection control signal used to control the transmission and reception of data.

[0003] However, when sending and receiving data, the select signal needs to be pulled high when sending data and pulled low when receiving signals. That is, the select signal needs to be operated before sending and receiving data, and it is not possible to send and receive data directly like other serial ports. Summary of the Invention

[0004] The present application provides an RS485 bus automatic transceiver control device and computing equipment, which can automatically control the output of the selection signal of the RS485 bus interface by designing a selection signal control module, a reception timing control module and a selector in an FPGA chip, thereby realizing automatic switching of data transmission and reception.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect, the present application provides an RS485 bus automatic transceiver control device, wherein a first end of the control device is connected to a UART controller, a second end of the control device is connected to an RS485 transceiver, and the control device comprises: a strobe signal control module;

[0007] The strobe signal control module is configured to cache a preset number of UART transmit signals in a cache array, wherein the last UART transmit signal in the cache array is output; determine whether a first preset condition is met, the first preset condition being that the UART transmit signal sent by the UART controller changes from a high level to a low level; if so, enter an RS485 receive closed state, reset a first counter, set an RS485 receive enable signal to a low level, switch to a strobe enable state, and then set the strobe signal in the RS485 transceiver to a high level to receive a data packet sent by the UART controller; determine whether a second preset condition is met, the second preset condition being that the control device has completed receiving the data packet sent by the UART controller; if so, enter a closed timing state; determine whether a third preset condition is met, the third preset condition being that in the closed timing state, a first count of the first counter exceeds a first preset count threshold; if so, set the strobe signal in the RS485 transceiver to a low level, and enter an RS485 receive enable state. In some possible implementations, the selection signal control module is further used to reset the second counter after entering the RS485 reception enabled state; determine whether a fourth preset condition is met, and the fourth preset condition is that in the RS485 reception enabled state, the second count of the second counter exceeds a second preset count threshold; if the fourth preset condition is met, return to the initial idle state.

[0008] In some possible implementations, the selection signal control module is further configured to determine whether a first preset condition is satisfied after entering the closed timing state, and enter the RS485 receiving closed state if the first preset condition is satisfied.

[0009] In some possible implementations, the selection signal control module is further configured to determine whether a first preset condition is satisfied after entering the RS485 reception enabled state, and enter the RS485 reception disabled state if the first preset condition is satisfied.

[0010] In some possible implementations, the control device further includes a receiving timing control module;

[0011] The receiving timing control module is used to determine whether the control device has completed receiving the data packet sent by the UART controller based on the baud rate and the UART transmission signal sent by the UART controller, and if the control device has completed receiving the data packet sent by the UART controller, send a data reception completion signal to the selection signal control module;

[0012] The selection signal control module is specifically configured to determine that a second preset condition is satisfied after receiving the data reception completion signal.

[0013] In some possible implementations, the control device further includes: a selector;

[0014] The strobe signal control module is specifically configured to send an RS485 receive enable signal to the selector;

[0015] The selector is used to determine that the UART receive signal sent to the UART controller is a high level if the RS485 receive enable signal is a low level; if the RS485 receive enable signal is a high level, determine that the UART receive signal sent to the UART controller is an RS485 receive signal, and send the UART receive signal to the UART controller.

[0016] In some possible implementations, the selection signal control module is further configured to send a signal via RS485 to transmit data received from the UART controller to the RS485 transceiver.

[0017] In some possible implementations, the strobe signal control module is specifically configured to determine that the RS485 strobe signal is at a low level, and send the low-level RS485 strobe signal to the RS485 transceiver;

[0018] The RS485 transceiver is used to start the data receiving mode according to the low-level RS485 selection signal.

[0019] In a second aspect, the present application provides a computing device, including a memory and a processor;

[0020] One or more computer programs are stored in the memory, and the one or more computer programs include instructions; when the instructions are executed by the processor, the computing device executes the method as described in any one of the first aspects.

[0021] It can be seen from the above technical solution that this application has at least the following beneficial effects:

[0022] The present application provides an RS485 bus automatic transceiver control device, which includes: a selection signal control module, which is used to cache preset UART transmission signals in a cache array, wherein the last UART transmission signal in the cache array is output; judging whether a first preset condition is met, if the first preset condition is met, entering the RS485 reception closed state, resetting the first counter, setting the RS485 reception enable signal to a low level, switching to the selection enable state, and then setting the selection signal in the RS485 transceiver to a high level to receive the data packet sent by the UART controller; then judging whether a second preset condition is met, if the second preset condition is met, entering the closed timing state; judging whether a third preset condition is met, if the third preset condition is met, setting the selection signal in the RS485 transceiver to a low level, entering the RS485 reception enable state, resetting the second counter, and in the RS485 reception enable state, if the second count of the second counter exceeds the second preset count threshold, returning to the initial idle state. In this application, a strobe signal control module is designed in the FPGA chip to automatically control the output of the strobe signal of the RS485 bus interface, thereby realizing automatic switching of data transmission and reception.

[0023] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution or beneficial effect is included in at least one embodiment. Therefore, the description of a technical feature, technical solution or beneficial effect in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be implemented without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in specific embodiments that do not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0025] Figure 2 A schematic diagram of an RS485 bus automatic transceiver control device provided in an embodiment of the present application;

[0026] Figure 3 A schematic diagram of state switching in a strobe signal control module provided in an embodiment of the present application;

[0027] Figure 4A schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The terms "first", "second" and "third" in this application specification and the accompanying drawings are used to distinguish different objects rather than to limit a specific order.

[0029] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0030] Currently, when sending and receiving data, it is necessary to pull the DE signal high when sending data and pull the DE signal low when receiving signals. That is, it is necessary to operate the DE signal before sending and receiving data, and it is not possible to send and receive data directly like other serial ports.

[0031] In view of this, an embodiment of the present application provides an RS485 bus automatic switching device for transmitting and receiving, which includes: a selection signal control module for caching a preset number of UART transmission signals in a cache array, wherein the last UART transmission signal in the cache array is output; judging whether a first preset condition is met, if the first preset condition is met, entering the RS485 reception closed state, resetting the first counter, setting the RS485 reception enable signal to a low level, switching to the selection enable state, and then setting the selection signal in the RS485 transceiver to a high level to receive the data packet sent by the UART controller; then judging whether a second preset condition is met, if the second preset condition is met, entering the closed timing state; judging whether a third preset condition is met, if the third preset condition is met, setting the selection signal in the RS485 transceiver to a low level, entering the RS485 reception enable state, resetting the second counter, and in the RS485 reception enable state, if the second count of the second counter exceeds the second preset count threshold, returning to the initial idle state. In this application, a strobe signal control module is designed in the FPGA chip to automatically control the output of the strobe signal of the RS485 bus interface, thereby realizing automatic switching of data transmission and reception.

[0032] In order to make the technical solution of this application clearer and easier to understand, the application scenarios of the technical solution of this application are introduced below with reference to the accompanying drawings. Figure 1 As shown in the figure, this figure is a schematic diagram of an application scenario provided by an embodiment of the present application.

[0033] As can be seen in the figure, in the application scenario, the first end of the control device 103 is connected to the second end of the UART controller 102, the second end of the control device 103 is connected to the first end of the RS485 transceiver 104, the first end of the UART controller 102 is connected to the host 101, and the second end of the RS485 transceiver 104 is connected to the RS485 cable 105; the UART controller 102 sends a UART send signal to the control device 103, the control device 103 sends an RS485 send signal and an RS485 selection signal to the RS485 transceiver 104, the RS485 transceiver 104 sends an RS485 receive signal to the control device 103, and the control device 103 sends a UART receive signal to the UART controller 102. The control device 103 also requires an external input baud rate, which can be input by the host 101 or in other ways.

[0034] Since in the prior art, when the host 101 transmits data through the UART controller 102 and the RS485 transceiver 104, it is necessary for the upper level to write code to control the high and low levels of the selection signal for sending and receiving data. Therefore, this application sets a control device 103 between the UART controller 102 and the RS485 transceiver 104 to replace the upper level writing code to control the high and low levels of the selection signal to ensure smooth transmission of data.

[0035] In order to make the technical solution of this application clearer and easier to understand, the following describes an RS485 bus automatic transceiver control device provided by the embodiment of this application in combination with the above application scenario. Figure 2 As shown in the figure, this figure is a schematic diagram of an RS485 bus automatic transceiver control device provided in an embodiment of the present application.

[0036] In an embodiment of the present application, the first end of the control device 103 is connected to the UART controller 102, and the second end of the control device 103 is connected to the RS485 transceiver 104. The control device 103 includes: a selection signal control module 201, a receiving timing control module 202 and a selector 203.

[0037] Wherein, strobe signal control module 201 major functions are to control RS485 strobe signal output high level when sending data, and to control RS485 strobe signal output low level when not sending data. Strobe signal control module 201 internal functions comprise that the buffer memory of UART transmit signal sends, RS485 starts to send detection and RS485 strobe signal control state machine.

[0038] The main function of the receiving timing control module 202 is to receive data sent by UART, process the received data according to the standard UART protocol based on the received baud rate, and send a data reception completion signal to the selection signal control module 201 when a packet of data is received.

[0039] The main function of the selector 203 is to select the RS485 receive signal as the UART receive signal output when the RS485 receive enable signal sent by the selection signal control module 201 is high; if the RS485 receive enable signal sent by the selection signal control module 201 is low, the selector 203 selects the high level "1" output.

[0040] The following is a detailed description of the implementation of the control device 103:

[0041] The UART controller 102 sends a UART transmit signal to the control device 103. The UART transmit signal is first buffered in a buffer array of the strobe signal control module 201. The buffer array can buffer a preset number of data. The last data in the buffer array is transmitted to the RS485 transceiver as the RS485 transmit signal of the control device 103. In the embodiment of the present application, the preset number is 10, and the last data in the buffer array is the 10th data. The purpose of buffering 10 data is to reserve sufficient time for the strobe signal control module 201 to receive the UART transmit signal and prevent data loss.

[0042] The strobe signal control module 201 determines whether a first preset condition is met, wherein the first preset condition is that the UART transmit signal sent by the UART controller 102 changes from a high level to a low level. If the first preset condition is met, the RS485 receive closed state is entered, and a high level RS485 strobe signal is sent to the RS485 transceiver 104. Then, the RS485 transceiver 104 enters a strobe enabled state. The RS485 transceiver 104 starts the transmit data mode according to the high level RS485 strobe signal.

[0043] The selection signal control module 201 then determines whether a second preset condition is met, where the second preset condition is that the control device 103 has completed receiving the data packet sent by the UART controller 102. If the second preset condition is met, the selection enable state enters the closed timing state and resets the first counter.

[0044] The selection signal control module 201 then determines whether a third preset condition is met. The third preset condition is that in the timing off state, the first count of the first counter exceeds a first preset count threshold. If the third preset condition is met, the RS485 reception enable state is entered, and a low-level RS485 selection signal is sent to the RS485 transceiver 104.

[0045] In an embodiment of the present application, the first preset counting threshold is set to 12. After the control device 103 sends data to the RS485 transceiver 104, in order to ensure that the data packet can be completely sent to the RS485 transceiver 104, the first counter starts counting when the timing state is turned off. When the first count exceeds the first preset counting threshold, it indicates that the data packet has been sent. Therefore, the selection signal control module 201 enters the RS485 receive enable state and sends a low-level RS485 selection signal to the RS485 transceiver 104.

[0046] After entering the RS485 receive enable state, resetting the second counter; judging whether a fourth preset condition is met, wherein the fourth preset condition is that in the RS485 receive enable state, the second count of the second counter exceeds the second preset count threshold; if the fourth preset condition is met, returning to the initial idle state.

[0047] In the embodiment of the present application, the second preset counting threshold is set to 100, because the RS485 transceiver 104 sends the received data packet to the RS485 cable 105. After the RS485 cable 105 receives the data packet, the selection signal control module 201 switches to the RS485 reception enable state. In this way, if the RS485 cable 105 has data to be sent to the UART controller 102, the RS485 transceiver 104 starts the data receiving mode according to the low-level RS485 selection signal, and can be sent through the control device 103. If the second count of the second counter exceeds the second preset counting threshold and the RS485 cable 105 has no data to be sent to the UART controller 102, the selection signal control module 201 returns to the initial idle state.

[0048] The strobe signal control module 201 is further configured to determine whether a first preset condition is satisfied after entering the closed timing state, and enter the RS485 receiving closed state if the first preset condition is satisfied.

[0049] The strobe signal control module 201 is further configured to determine whether a first preset condition is satisfied after entering the RS485 reception enabled state, and enter the RS485 reception disabled state if the first preset condition is satisfied.

[0050] The receiving timing control module 202 is used to determine whether the control device 103 has completed receiving the data packet sent by the UART controller 102 based on the baud rate and the UART sending signal sent by the UART controller 102, and if the control device 103 has completed receiving the data packet sent by the UART controller 102, it sends a data reception completion signal to the selection signal control module 201.

[0051] The receiving timing control module 202 processes the received data according to the standard UART protocol to determine the end time of a data packet.

[0052] After receiving the data reception completion signal, the strobe signal control module 201 determines whether a second preset condition is met. If the second preset condition is met, the strobe signal control module 201 sends an RS485 reception enable signal to the selector 203 .

[0053] The selector 203 is configured to: if the RS485 reception enable signal is low, the UART reception signal sent to the UART controller 102 is high; if the RS485 reception enable signal is high, the UART reception signal sent to the UART controller 102 is the RS485 reception signal.

[0054] In the embodiment of the present application, a schematic diagram is provided of the control device 103 switching different states in the strobe signal control module 201 according to different signal instructions, such as Figure 3 As shown in FIG, this figure is a schematic diagram of state switching in a selection signal control module provided in an embodiment of the present application.

[0055] As can be seen in the figure, the initial idle state switches to the RS485 receive closed state after the first preset condition is met, and the RS485 receive closed state switches to the strobe enabled state. When the second preset condition is met, the strobe enabled state switches to the closed timing state. If the first preset condition is met, the closed timing state switches to the RS485 receive closed state for a new round of data transmission.

[0056] If the third preset condition is met, the timing off state will be switched to the RS485 receive enabled state. After the fourth preset condition is met, the state will be switched to the initial idle state. If the first preset condition is met in the RS485 receive enabled state, the state will be switched to the RS485 receive off state for a new round of data transmission.

[0057] Among them, the first preset condition is that the UART transmission signal sent by the UART controller 102 changes from a high level to a low level; the second preset condition is that the control device 103 has completed receiving the data packet sent by the UART controller 102; the third preset condition is that in the timing off state, the first count of the first counter exceeds the first preset count threshold; the fourth preset condition is that in the RS485 reception enabled state, the second count of the second counter exceeds the second preset count threshold.

[0058] The present application also provides a computing device. Figure 4As shown, this figure is a schematic diagram of a computing device provided by an embodiment of the present application, wherein the computing device 400 includes a bus 401, a processor 402, a communication interface 403, and a memory 404. The processor 402, the memory 404, and the communication interface 403 communicate with each other via the bus 401.

[0059] The bus 401 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0060] The processor 402 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0061] The communication interface 403 is used for communicating with the outside.

[0062] Memory 404 may include volatile memory, such as random access memory (RAM). Memory 404 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0063] The present application also provides a computer program product comprising one or more computer instructions that, when loaded and executed on a computing device, fully or partially generate the process or function described in the present application.

[0064] The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer or data center to another website, computer or data center via wired (e.g., coaxial cable, optical fiber) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0065] The descriptions of the processes or structures corresponding to the above figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0066] The above description is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. An RS485 bus automatic transceiver control device, characterized in that: The first end of the control device is connected to the UART controller, and the second end of the control device is connected to the RS485 transceiver. The control device includes: a strobe signal control module; The strobe signal control module is configured to cache a preset number of UART transmit signals in a cache array, wherein the last UART transmit signal in the cache array is output; determine whether a first preset condition is met, the first preset condition being that the UART transmit signal sent by the UART controller changes from a high level to a low level; if so, enter an RS485 receive closed state, reset a first counter, set an RS485 receive enable signal to a low level, switch to a strobe enable state, and then set the strobe signal in the RS485 transceiver to a high level to receive a data packet sent by the UART controller; determine whether a second preset condition is met, the second preset condition being that the control device has completed receiving the data packet sent by the UART controller; if so, enter a closed timing state; determine whether a third preset condition is met, the third preset condition being that in the closed timing state, a first count of the first counter exceeds a first preset count threshold; if so, set the strobe signal in the RS485 transceiver to a low level, and enter an RS485 receive enable state.

2. The control device according to claim 1, characterized in that The selection signal control module is further used to reset the second counter after entering the RS485 reception enabled state; determine whether a fourth preset condition is met, wherein the fourth preset condition is that in the RS485 reception enabled state, the second count of the second counter exceeds a second preset count threshold; if the fourth preset condition is met, return to the initial idle state.

3. The control device according to claim 1, characterized in that The strobe signal control module is further configured to determine whether a first preset condition is satisfied after entering the closed timing state, and enter the RS485 receiving closed state if the first preset condition is satisfied.

4. The control device according to claim 1, characterized in that The strobe signal control module is further configured to determine whether a first preset condition is satisfied after entering the RS485 receiving enabled state, and enter the RS485 receiving disabled state if the first preset condition is satisfied.

5. The control device according to claim 1, characterized in that The control device also includes a receiving timing control module; The receiving timing control module is used to determine whether the control device has completed receiving the data packet sent by the UART controller based on the baud rate and the UART transmission signal sent by the UART controller, and if the control device has completed receiving the data packet sent by the UART controller, send a data reception completion signal to the selection signal control module; The selection signal control module is specifically configured to determine that a second preset condition is satisfied after receiving the data reception completion signal.

6. The control device according to claim 1, characterized in that The control device further includes: a selector; The strobe signal control module is specifically configured to send an RS485 receive enable signal to the selector; The selector is used to determine that the UART receive signal sent to the UART controller is a high level if the RS485 receive enable signal is a low level; if the RS485 receive enable signal is a high level, determine that the UART receive signal sent to the UART controller is an RS485 receive signal, and send the UART receive signal to the UART controller.

7. The control device according to claim 1, characterized in that The strobe signal control module is further configured to send a signal via RS485 to transmit the data received from the UART controller to the RS485 transceiver.

8. The control device according to claim 1, characterized in that Described strobe signal control module, is specifically used for determining that RS485 strobe signal is low level, sends low level RS485 strobe signal to described RS485 transceiver; The RS485 transceiver is used to start the data receiving mode according to the low-level RS485 selection signal.

9. The control device according to claim 1, characterized in that Described strobe signal control module, is specifically used for determining that RS485 strobe signal is high level, sends the RS485 strobe signal of high level to described RS485 transceiver; The RS485 transceiver is used to start the data transmission mode according to the high-level RS485 selection signal.

10. A computing device, characterized in that The computing device includes the control device according to any one of claims 1 to 9, and further includes a host; the host is connected to the control device.

Citation Information

Patent Citations

  • High-reliability RS485 bus interface control system, computing chip and industrial computer

    CN119449518A